Practical Computer Architecture Education with RISC-V Stefan Wallentowitz Professor Munich University of Applied Sciences @Wallento

Practical Computer Architecture Education with RISC-V Stefan Wallentowitz Professor Munich University of Applied Sciences @wallento

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ About Me

Professional

•Graduated from RWTH Aachen and TU Munich, EE/Computer Engineering •Research Interests: Manycore SoC, physical hardware security, verification •Professor at Munich University of Applied Sciences since March 2019

Hobbyist

•Long time user and contributor to OpenRISC, then RISC-V •Many open source projects (HDL, Tools, …)

Advocacy & Community

•Director at Free and Open Source Silicon Foundation

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Munich University of Applied Sciences

► 18400 Students, 14 Departments ► Characteristics • Primarily Bachelor and Masters Degrees • Strong Focus on Practice and Application • Application-oriented Research • Small Class Sizes (5-40 students) • Compulsory Industry Internship • Professors: Min. 5 years industry experience ► (Comparable) Strategic Partners: Cal Poly (San Luis Obispo), TAMK (Tampere, Finland), UAS Vienna and Zurich ► My Faculty: Computer Science & Mathematics #RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ My First Course: Computer Architecture

► 4th Semester Bachelor ► Classic Curriculum • Pipelining Basics • How we got to large IPCs (BP, Superscalar, OoO) • Memory, Interconnect, … ► Lecture & Integrated Laboratory ► … and all this cool open source stuff out there!

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/

How I see Computer Architecture

BY 4.0 BY

, CC

webalys © Wikimedia/ ©

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/

How my CS Students see Computer Architecture

SA 3.0 SA

, CC ,

Rijcke © Wikimedia/Ruben Wikimedia/Ruben © de #RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ The Lecture

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ The Laboratory

RISC-V Basics

• Refresher in Computer Systems, RISCV Instruction Set and Assembly • Tools: rv8, spike, Venus

Computer Architecture

• DLX Pipeline: Ripes Simulator • Simulators, Emulators, Levels of Abstraction • RTL Simulations of popular open source CPUs (ibex, SCR-1, Rocket, Ariane, BOOM)

FPGA Platform

• Nexys A7 FPGA board with different open source CPUs

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ RISC-V Basics

► Refresh Assembly Skills ► Small programs, calling conventions etc. ► Venus simulator (JavaScript in Browser)

Venus Simulator: https://www.kvakil.me/venus/

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Basic DLX Pipeline

► Move away from pure functional (instruction accurate) ► Understand basic (DLX) pipeline principle ► Ripes simulator (awesome project!)

Ripes Simulator: https://github.com/mortbopet/Ripes #RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Simulators, Emulators, Level of Abstraction

► Step from visual simulators to other types of simulation/emulation ► rv8: Different modes, understand user mode emulation etc. ► Understand levels of abstraction ► RTL simulation (Verilator) and gtkwave: Syntacore SCR-1

Syntacore SCR-1: https://github.com/syntacore/scr1

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Computer Architecture Insights

► Goal: Understand Computer Architecture concepts ► Insights into core implementations without waveforms etc. but with real processor cores! ► Example of existing tools: BOOM and gem5 O3 pipeline viewer

► THAT, but with much more µ-architectural details!

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Pipeline Viewer

► Python: pip install pipeline-viewer ► Re-implementation of basic pipeline viewer, but with extra modes ► Extensions of core simulation environment with DPI

► Example: Ariane 64-bit core CTF (binary trace) or text file

pipeline- Ariane

Trace File viewer

Tracer DPI µarch DPI

Testbench Minimal extensions Observe microarchitecture to ease tracking of and trace events instructions (may become obsolete) #RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Pipeline Viewer: Instruction Trace

► Assignment: Observe instructions in pipeline, determine IPC

Duration PC & Disassembly

Instruction lifecycle over time

Total retired instructions #RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Pipeline Viewer: Branch Predictor

► Assignment: Compare expected behavior, impact of difference sizes

Branch prediction and updates to the predictor

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Work-in-Progress: FPGA Integration

► Implement cores in FPGA and add micro-architecture trace ► Ran out of time in spring 2019, will be added in spring 2020

pipeline- Core Open SoC Debug CTF

µarch viewer Tracer

FPGA

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Outlook: Computer System Basics

► Course in Computer System Fundamentals ► Currently MMIX & VMB ► Switch to RISC-V ► Plan: Extend Venus simulator for example with I/O visualization ► ETA: Summer 2020

► Also: Benchmarking with Embench

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/ Summary

► Computer Architecture Teaching with Real Processor Cores ► Accessible to non-EE students, no need to touch HDL/waveforms ► Reusable infrastructure, WIP even for FPGA Cores: lowRISC Ibex, Syntacore SCR-1, ETH Ariane, Berkeley BOOM ► Laboratory Curriculum

► Soon available online: https://github.com/wallento/riscv-ca-teaching

► Get in touch!

[email protected] @wallento

#RISCVSUMMIT | tmt.knect365.com/risc-v-summit/