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The Pennsylvania State University the Graduate School DETECTING and MITIGATING CACHE-BASED SIDE-CHANNELS a Dissertation in Compu The Pennsylvania State University The Graduate School DETECTING AND MITIGATING CACHE-BASED SIDE-CHANNELS A Dissertation in Computer Science and Engineering by Robert Brotzman c 2021 Robert Brotzman Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy May 2021 The dissertation of Robert Brotzman was reviewed and approved by the following: Gang Tan Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Danfeng Zhang Assistant Professor of Computer Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Mahmut Kandemir Professor of Computer Science and Engineering Committee Member Dinghao Wu Associate Professor of Information Sciences and Technology Outside Committee Member Chita R. Das Professor of Computer Science and Engineering Department Head of Computer Science and Engineering Abstract Identifying cache-based side channels in software is a particularly daunting task even for highly trained professionals. This is a consequence of side channels manifesting in a very subtle manner due to the interaction between the software and hardware. To com- pound the issue, once these vulnerabilities are detected, there are not many approaches available to mitigate them on commodity hardware today with reasonable overhead. To make matters worse, new attack vectors are being uncovered seemingly all the time. This is a result of new features frequently being added to hardware to improve per- formance. This is most apparent with the revelation of Spectre and Meltdown, demon- strating that common optimizations found on nearly all modern CPUs can be used to construct new side-channel attacks that are costly to mitigate. With every new hardware feature and optimization brings new challenges to accurately model the relationship be- tween the software and how it interacts with hardware. Given these issues, this dissertation seeks to address two core problems of first the detection and second the mitigation of cache-based side channels. To address the issue of detecting cache-based side channels, we develop a tool called CaSym that automat- ically detects and pinpoints cache-based side channels in software or verifies their ab- iii sence. CaSym uses symbolic execution to reason about programs and introduces novel cache models to achieve a more robust modeling of the CPU cache. To address new vul- nerabilities discovered leveraging speculative execution, we extended CaSym in a new tool called SpecSafe to also detect leakage caused speculative execution. This is accom- plished by introducing program transformation to soundly capture program behavior manifesting from speculative execution while still being able to identify conventional cache based side channels. To address the issue of mitigating side-channels, we propose a novel user-space side channel mitigation targeting the CPU cache called Ghost Thread that is both reasonably efficient and works on virtually all commodity hardware. Ghost Thread uses threads to introduce noise into the CPU’s cache state making it drastically more difficult to successfully launch a cache-based side channel. Lastly, we survey existing user-space mitigations for Spectre attacks to provide a roadmap to developers to select the most appropriate mitigation given their circumstances. iv Table of Contents List of Figures ix List of Tables xii Acknowledgments xiv Chapter 1 Introduction1 Chapter 2 Background7 2.1 CPU Cache ................................ 7 2.2 Speculative Execution........................... 8 2.3 Attacks .................................. 9 2.3.1 Cache Side Channels....................... 9 2.3.2 Transient Execution Attacks ................... 13 Chapter 3 Related Work 18 3.1 Mitigation Techniques........................... 18 3.1.1 Software.............................. 18 3.1.2 Hardware............................. 20 3.2 Detection Techniques........................... 20 3.2.1 Conventional Cache Attacks Detection.............. 20 3.2.2 Spectre Side-Channel Detection ................. 21 3.2.3 Timing Channel Detection .................... 22 3.2.4 Other Attack Detection...................... 23 v Chapter 4 A User-Space Cache Side Channel Mitigation 24 4.1 Motivation................................. 24 4.2 Attack Model ............................... 26 4.3 System Design............................... 26 4.3.1 Why a User-Level Library .................... 27 4.3.2 System Overview......................... 28 4.3.3 Library Interface ......................... 29 4.3.4 Tuning Ghost Thread....................... 32 4.3.4.1 Multiple Protection Threads.............. 32 4.3.4.2 Ensuring Thread Scheduling.............. 32 4.3.4.3 Varying Noise Injection Rate ............. 35 4.3.4.4 Memory Access Randomization............ 36 4.3.5 Usability of Ghost Thread .................... 37 4.4 Security Analysis............................. 39 4.4.1 Normalized Samples ....................... 39 4.4.2 Empirical Study on Cryptography Libraries........... 42 4.4.2.1 AES Attack....................... 42 4.4.2.2 RSA Attack....................... 45 4.5 Evaluation................................. 46 4.5.1 Application Overhead....................... 47 4.5.2 Worst Case Analysis ....................... 50 4.5.2.1 Performance Results.................. 51 4.5.2.2 Security Results .................... 53 4.5.2.3 Adjusting Noise Frequency .............. 55 4.5.3 System Impact .......................... 56 4.6 Discussion................................. 58 4.7 Summary ................................. 59 Chapter 5 Cache-Aware Symbolic Execution 61 5.1 Motivation................................. 61 5.2 Threat model ............................... 62 5.3 System Overview............................. 64 5.4 Tracking Cache States........................... 66 5.4.1 Loop-free programs........................ 67 5.4.2 Compositional reasoning..................... 73 5.4.3 Transforming loops........................ 76 5.5 Cache Models............................... 77 5.5.1 Abstract vs. concrete cache models................ 77 vi 5.5.2 Infinite cache model ....................... 78 5.5.3 Age model ............................ 79 5.5.4 More concrete models ...................... 81 5.6 Localizing and Mitigating Side Channels................. 82 5.6.1 Localizing side channels ..................... 82 5.6.2 Fixing side channels ....................... 84 5.6.2.1 Preloading ....................... 84 5.6.2.2 Pinning......................... 85 5.6.2.3 Fixing side channels.................. 86 5.7 Implementation.............................. 87 5.8 Evaluation................................. 87 5.8.1 Evaluation for access-based attackers .............. 90 5.8.2 Evaluation for trace-based attackers ............... 92 5.8.3 Fixing side channels ....................... 96 5.8.4 Abstract vs. Concrete Cache Models............... 98 5.9 Limitations ................................ 99 5.10 Summary ................................. 99 Chapter 6 Detecting Cache Side Channels with Speculative Execution 102 6.1 Motivation.................................102 6.2 Threat Model ...............................104 6.3 New Speculative Side Channels......................105 6.3.1 Attack Code Snippets.......................106 6.3.2 Measuring Channel Throughput . 109 6.4 Attack Setup................................109 6.5 Speculative-Aware non-interference ...................111 6.5.1 Limitations of Existing Definitions . 114 6.5.1.1 Conventional Cache Side Channels . 114 6.5.1.2 Speculative Side Channels . 115 6.5.1.3 Limitations of Existing Security Definitions . 115 6.5.2 Speculative Aware Noninterference . 118 6.6 SpecSafe..................................119 6.6.1 Program transformation......................120 6.7 Implementation..............................125 6.8 Evaluation.................................127 6.8.1 Micro-benchmarks ........................128 6.8.2 Security Benchmarks.......................130 6.9 Summary .................................135 vii Chapter 7 A Systematic Comparison of User-Space Spectre Mitigations 137 7.1 Motivation.................................137 7.2 Attack Models...............................139 7.2.1 Memory Trace Granularity....................139 7.2.2 Attack Interaction Granularity ..................140 7.2.3 Attack Location..........................140 7.3 Defenses..................................142 7.3.1 Halt Speculation with Execution Barriers . 142 7.3.2 Halt Speculation with Data Dependence . 146 7.3.3 Prevent Speculation with Preemptive Data Caching (PDC) . 149 7.3.4 Speculative Control-Flow Capturing . 152 7.3.5 Partitioning............................155 7.3.6 Obfuscation............................157 7.4 Performance Impact............................158 7.4.1 Experimental Set Up .......................158 7.4.2 Performance Evaluation .....................159 7.5 Evaluation of binary size increase.....................164 7.6 Developer Guidance and Discussion ...................165 7.7 Summary .................................168 Chapter 8 Future Work 169 8.1 Program Analysis.............................169 8.2 Mitigations ................................170 Chapter 9 Conclusion 173 Appendix A Formalization 175 A.1 Formalizing Program Semantics with Speculation . 175 A.2 Soundness Proof..............................178 Bibliography 194 viii List of Figures 2.1 Illustration of how an adversary can learn secret data using a conven- tional cache side channel. We assume A is an array of 1-byte elements and the cache line
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