An Analysis of Speculative Type Confusion Vulnerabilities in the Wild
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Efficiently Mitigating Transient Execution Attacks Using the Unmapped Speculation Contract Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M
Efficiently Mitigating Transient Execution Attacks using the Unmapped Speculation Contract Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M. Frans Kaashoek, and Nickolai Zeldovich, MIT CSAIL https://www.usenix.org/conference/osdi20/presentation/behrens This paper is included in the Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation November 4–6, 2020 978-1-939133-19-9 Open access to the Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation is sponsored by USENIX Efficiently Mitigating Transient Execution Attacks using the Unmapped Speculation Contract Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL Abstract designers have implemented a range of mitigations to defeat transient execution attacks, including state flushing, selectively Today’s kernels pay a performance penalty for mitigations— preventing speculative execution, and removing observation such as KPTI, retpoline, return stack stuffing, speculation channels [5]. These mitigations impose performance over- barriers—to protect against transient execution side-channel heads (see §2): some of the mitigations must be applied at attacks such as Meltdown [21] and Spectre [16]. each privilege mode transition (e.g., system call entry and exit), To address this performance penalty, this paper articulates and some must be applied to all running code (e.g., retpolines the unmapped speculation contract, an observation that mem- for all indirect jumps). In some cases, they are so expensive ory that isn’t mapped in a page table cannot be leaked through that OS vendors have decided to leave them disabled by de- transient execution. To demonstrate the value of this contract, fault [2, 22]. -
Class-Action Lawsuit
Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys. -
LVI-LFB: Scenarios 3 & 4
WHITEPAPER Security Load Value Injection in the Line Fill Buffers: How to Hijack Control Flow without Spectre www.bitdefender.com Contents Abstract .............................................................................................................................3 Introduction .......................................................................................................................3 Recap – Meltdown, Spectre & MDS .................................................................................4 Meltdown .................................................................................................................................4 Spectre ..................................................................................................................................... 4 Microarchitectural Data Sampling .......................................................................................... 5 Load Value Injection in the Line Fill Buffers ....................................................................5 Exploiting LVI-LFB: scenarios 3 & 4..................................................................................7 Real-life exploit ..................................................................................................................7 Mitigations .........................................................................................................................8 Conclusions .......................................................................................................................9 -
Mitigation Overview for Potential Side- Channel Cache Exploits in Linux* White Paper
Mitigation Overview for Potential Side- Channel Cache Exploits in Linux* White Paper Revision 2.0 May, 2018 Any future revisions to this content can be found at https://software.intel.com/security-software- guidance/insights/deep-dive-mitigation-overview-side- channel-exploits-linux when new information is available. This archival document is no longer being updated. Document Number: 337034-002 Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at www.intel.com. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. Intel provides these materials as-is, with no express or implied warranties. Intel, the Intel logo, Intel Core, Intel Atom, Intel Xeon, Intel Xeon Phi, Intel® C Compiler, Intel Software Guard Extensions, and Intel® Trusted Execution Engine are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2018, Intel Corporation. All rights reserved. Mitigation Overview for Potential Side-Channel Cache Exploits in Linux* White Paper May 2018 -
Software-Based Power Side-Channel Attacks on X86
PLATYPUS: Software-based Power Side-Channel Attacks on x86 Moritz Lipp∗, Andreas Kogler∗, David Oswald†, Michael Schwarz‡, Catherine Easdon∗, Claudio Canella∗, and Daniel Gruss∗ ∗ Graz University of Technology †University of Birmingham, UK ‡CISPA Helmholtz Center for Information Security Abstract—Power side-channel attacks exploit variations in on an ARM TrustZone-M platform using an onboard ADC, power consumption to extract secrets from a device, e.g., crypto- and Mantel et al. [56] distinguished different RSA keys by graphic keys. Prior attacks typically required physical access to measuring the power consumption on Intel desktop machines. the target device and specialized equipment such as probes and a high-resolution oscilloscope. The experimental results of Mantel et al. on RSA demonstrated In this paper, we present PLATYPUS attacks, which are that certain multiply operations of the square-and-multiply novel software-based power side-channel attacks on Intel server, implementation can be detected, but no full key recovery was desktop, and laptop CPUs. We exploit unprivileged access to achieved. Similarly, Fusi [20] tried to recover RSA-16384 keys the Intel Running Average Power Limit (RAPL) interface that but concluded that the sampling rate of the interface is too low exposes values directly correlated with power consumption, forming a low-resolution side channel. to mount an attack. We show that with sufficient statistical evaluation, we can In this work, we present PLATYPUS1 attacks which are observe variations in power consumption, which distinguish novel software-based power side-channel attacks on Intel different instructions and different Hamming weights of operands servers, desktops, and laptops by abusing unprivileged access and memory loads. -
Speculative Dereferencing: Reviving Foreshadow (Extended Version)
Speculative Dereferencing: Reviving Foreshadow (Extended Version) Martin Schwarzl1, Thomas Schuster1, Michael Schwarz2, and Daniel Gruss1 1Graz University of Technology, Austria 2CISPA Helmholtz Center for Information Security, Germany Abstract. In this paper, we provide a systematic analysis of the root cause of the prefetching effect observed in previous works and show that its attribution to a prefetching mechanism is incorrect in all previous works, leading to incorrect conclusions and incomplete defenses. We show that the root cause is speculative dereferencing of user-space registers in the kernel. This new insight enables the first end-to-end Foreshadow (L1TF) exploit targeting non-L1 data, despite Foreshadow mitigations enabled, a novel technique to directly leak register values, and several side-channel attacks. While the L1TF effect is mitigated on the most re- cent Intel CPUs, all other attacks we present still work on all Intel CPUs and on CPUs by other vendors previously believed to be unaffected. 1 Introduction For security reasons, operating systems hide physical addresses from user pro- grams [34]. Hence, an attacker requiring this information has to leak it first, e.g., with the address-translation attack by Gruss et al. [17, §3.3 and §5]. It allows user programs to fetch arbitrary kernel addresses into the cache and thereby to resolve virtual to physical addresses. As a mitigation against e.g., the address- translation attack, Gruss et al. [17, 16] proposed the KAISER technique. Other attacks observed and exploited similar prefetching effects. Meltdown [41] practically leaks memory that is not in the L1 cache. Xiao et al. [72] show that this relies on a prefetching effect that fetches data from the L3 cache into the L1 cache. -
Managed Runtime Speculative Execution Side Channel Mitigations White Paper
Managed Runtime Speculative Execution Side Channel Mitigations White Paper Revision 001 June 2018 Document Number: 337313-001 No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document; however, the information reported herein is available for use in connection with the mitigation of the security vulnerabilities described. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.intel.com/design/literature.htm. Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others © Intel Corporation. Managed Runtime Speculative Execution Side Channel Mitigations -
Arxiv:1905.10311V4 [Cs.CR] 10 Mar 2020
SpecFuzz Bringing Spectre-type vulnerabilities to the surface Oleksii Oleksenko†, Bohdan Trach†, Mark Silberstein‡, and Christof Fetzer† †TU Dresden, ‡ Technion Abstract This observation led to the development of software tools SpecFuzz is the first tool that enables dynamic testing for for Spectre mitigation. They identify the code snippets pur- speculative execution vulnerabilities (e.g., Spectre). The key ported to be vulnerable to the Spectre attacks and instrument is a novel concept of speculation exposure: The program is them to prevent or eliminate unsafe speculation. Inherently, instrumented to simulate speculative execution in software by the instrumentation incurs runtime overheads, thereby leading forcefully executing the code paths that could be triggered due to the apparent tradeoff between security and performance. to mispredictions, thereby making the speculative memory Currently, all the existing tools exercise only the extreme accesses visible to integrity checkers (e.g., AddressSanitizer). points in this tradeoff, offering either poor performance with Combined with the conventional fuzzing techniques, specula- high security, or poor security with high performance. tion exposure enables more precise identification of potential Specifically, conservative techniques [3, 21, 28, 53] pes- vulnerabilities compared to state-of-the-art static analyzers. simistically harden every speculatable instruction (e.g., every Our prototype for detecting Spectre V1 vulnerabilities suc- conditional branch) to either prevent the speculation or make cessfully identifies all known variations of Spectre V1 and it provably benign. This approach is secure, but may signifi- decreases the mitigation overheads across the evaluated appli- cantly hurt program performance [44]. cations, reducing the amount of instrumented branches by up On the other hand, static analysis tools [17, 27, 41] reduce to 77% given a sufficient test coverage. -
Public Vulnerability Research Market in 2014
Public Vulnerability Research Market in 2014 The Evolving Threat Environment During the Internet of Things Era NFDF-74 November 2015 Research Team Lead Analyst Contributing Analyst Pamela Tufegdzic Chris Kissel Industry Analyst Industry Analyst ICT – Network Security ICT – Network Security (248) 259-2053 (623) 910-7986 [email protected] [email protected] Vice President of Research Research Director Michael Suby Frank Dickson VP of Research Research Director Stratecast/Frost & Sullivan ICT — Network Security (720) 344-4860 (469) 387-0256 [email protected] [email protected] NFDF-74 2 List of Exhibits Section Slide Number Executive Summary 8 Market Overview 10 • Market Overview – Research Objectives 11 • Market Overview (continued) 12 • Market Overview—Best Practices Public Vulnerability Disclosure 17 • Market Overview—The Evolving Attacker 18 • Market Overview—Terminology and Definitions 19 • Market Overview—Key Questions This Insight Answers 22 Research Methodology 23 Cyber Threat Analysis and Reporting 26 Introduction to Cyber Threat Analysis and Reporting 27 The Internet of Things 28 The Internet of Things—(continued) 29 NFDF-74 3 List of Exhibits (continued) Section Slide Number • SCADA 31 • Software―Java 33 • Malware 34 • Mobile Malware 37 Market Trends in Public Vulnerabilities 38 • Vulnerabilities Reported by Year 39 • Vulnerabilities Reported by Quarter 40 • Market Trends 41 • Vulnerability Disclosure 43 • Vulnerability Disclosure by Organization Type 46 • Analysis of Vulnerabilities by Severity 49 NFDF-74 -
SPECBOX: a Label-Based Transparent Speculation Scheme Against Transient Execution Attacks
SPECBOX: A Label-Based Transparent Speculation Scheme Against Transient Execution Attacks Bowen Tang1;2 , Chenggang Wu1;2, Zhe Wang1;2, Lichen Jia1;2, Pen-Chung Yew3, Yueqiang Cheng4, Yinqian Zhang5, Chenxi Wang6, Guoqing Harry Xu6 1State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, 2University of the Chinese Academy of Sciences, 3University of Minnesota at Twin Cities, 4NIO Security Research, 5Southern University of Science and Technology, 6University of California, Los Angeles 1{tangbowen, wucg, wangzhe12, jialichen}@ict.ac.cn, [email protected], [email protected], [email protected], 6{wangchenxi, harryxu}@cs.ucla.edu Abstract—Speculative execution techniques have been a cor- when the processor determines that it is a mis-prediction in nerstone of modern processors to improve instruction-level Line 5, it will squash the instructions of Lines 6-7 and follow parallelism. However, recent studies showed that this kind of the correct path. In the current design, the processor will not techniques could be exploited by attackers to leak secret data via transient execution attacks, such as Spectre. Many defenses clean up the side effects in the cache (i.e. the data brought in are proposed to address this problem, but they all face various during the mis-speculative execution). The attacker can scan challenges: (1) Tracking data flow in the instruction pipeline the dummy array in the cache, and measure the access time could comprehensively address this problem, but it could cause of each array element. According to the access latency, the pipeline stalls and incur high performance overhead; (2) Making attacker can decide which item has been loaded into the cache, side effect of speculative execution imperceptible to attackers, but it often needs additional storage components and complicated and thereby infer the secret value. -
Efficiently Mitigating Transient Execution Attacks Using the Unmapped Speculation Contract Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M
Efficiently Mitigating Transient Execution Attacks using the Unmapped Speculation Contract Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M. Frans Kaashoek, and Nickolai Zeldovich MIT CSAIL Abstract designers have implemented a range of mitigations to defeat transient execution attacks, including state flushing, selectively Today’s kernels pay a performance penalty for mitigations— preventing speculative execution, and removing observation such as KPTI, retpoline, return stack stuffing, speculation channels [5]. These mitigations impose performance over- barriers—to protect against transient execution side-channel heads (see §2): some of the mitigations must be applied at attacks such as Meltdown [21] and Spectre [16]. each privilege mode transition (e.g., system call entry and exit), To address this performance penalty, this paper articulates and some must be applied to all running code (e.g., retpolines the unmapped speculation contract, an observation that mem- for all indirect jumps). In some cases, they are so expensive ory that isn’t mapped in a page table cannot be leaked through that OS vendors have decided to leave them disabled by de- transient execution. To demonstrate the value of this contract, fault [2, 22]. Recent processor designs have also incorporated the paper presents WARD, a new kernel design that maintains mitigations into hardware, which also reduces performance a separate kernel page table for every process. This page table compared to earlier processor designs that do not perform such contains mappings for kernel memory that is safe to expose hardware mitigations. to that process. Because a process doesn’t map data of other To address the above challenge, this paper proposes a new processes, this design allows for many system calls to execute hardware/software contract, called the unmapped speculation without any mitigation overhead. -
Apple Iphones Hacked by Websites Exploiting Zero-Day Flaws Govinfosecurity.Com/Apple-Iphones-Hacked-By-Websites-Exploiting-Zero-Day-Flaws-A-13001
Apple iPhones Hacked by Websites Exploiting Zero-Day Flaws govinfosecurity.com/apple-iphones-hacked-by-websites-exploiting-zero-day-flaws-a-13001 See related story with an update on the latest developments. See Also: Live Webinar | Scaling Security at the Internet Edge with Stateless Technology Since at least 2016, hacked websites have targeted zero-day flaws in the latest versions of Apple iOS to surreptitiously hack iPhones, new research from Google shows. The attack campaign has been revealed by Google's Project Zero team, which searches for zero- day flaws. It says the attack campaign was used to infect iOS devices with an implant - aka malware - that could steal private data, including photos and messages in Telegram, iMessages and Gmail, as well as send GPS data to a command-and-control server for tracking users in real time, provided they're online. "Earlier this year Google's Threat Analysis Group discovered a small collection of hacked websites. The hacked sites were being used in indiscriminate watering hole attacks against their visitors, using iPhone 0-day," Ian Beer of the Project Zero team says in a blog post published Thursday. "There was no target discrimination; simply visiting the hacked site was enough for the exploit server to attack your device, and if it was successful, install a monitoring implant," he says. "We estimate that these sites receive thousands of visitors per week." Google's test of the implant - malware - installed by the websites found that it could exfiltrate numerous types of personal data, including iMessages (Source: Google Project Zero) Apple did not immediately respond to a request for comment.