WLAN System Analysis and System Design Flow

WLAN System Analysis and System Design Flow Andy Wallace and Joel Kirshman Email: [email protected] Applied Wave Research UK (Europe), 2 Huntingate, Hitchin, Herts, UK. SG4 0TJ

Abstract

This paper provides an introduction to IEEE 802.11a Wireless LAN specifications and illustrates through the use of AWR’s Visual System Simulator (VSS)®, an efficient means to do WLAN system level trade off studies. Orthogonal Frequency Division Multiplexing (OFDM) definition, along with its benefits, is discussed using practical analysis to clearly identify realistic scenarios.

With emphasis on the receiver, the link budget is calculated, providing exact specifications for the constituent parts of the chain. Simulation of Bit Error Rate (BER) to produce an operational system is also covered. Finally, by uniting these ideas, a possible amplifier is proposed along with the necessary error correction techniques. These proposals are demonstrated in a final design, again simulated within VSS®.

Although the presentation revolves around a WLAN application, the system analysis approach and methodology presented here is applicable to any wireless or wired application. AWR’s sampled time- domain, complex-envelope system simulator, VSS®, is used throughout the presentation.

Introduction – The WLAN (802.11a) Specification

This paper specifically addresses an 802.11a design. We must first review the physical layer of an 802.11a signal. Note that four different modulation schemes are used to accommodate data rates varying from 6 Mbps to 54 Mbps. BPSK is also used for the pilot signals which are used for detection and carrier recovery.

Table 1: 802.11a Modulation Detail

Table 1 shows various data rates and modulation schemes and the use of several convolutional encoding rates. Block interleaving is also incorporated. OFDM is used to “transport” the information symbols. The coding and interleaving are used to mitigate the impact of multipath. The occupied information bandwidth is 16.6 MHz .

Paper 9 : Page 1 of 12

OFDM – Orthogonal Frequency Division Multiplexing

OFDM originated in the late 50’s and finally gathered steam in 1966 at Bell Laboratories. It is used today because it accommodates high bit rates. OFDM is also used in DVB-S, for example. The spacing between each carrier is carefully chosen, such that one symbol does not interfere with its neighbour. A guard interval is applied to reduce inter-carrier interference (ICI) due to multipath. If analog technology were to be used to produce analog sinusoids for each symbol, a lot of chip “real estate” would be needed for the individual mixers and LO sources.

To minimize “real estate” requirements, digital signal processing in the form of the Fast Fourier Transform is used. In fact it is the inverse FFT (IFFT) that is used on the transmit end. The time domain signal of the transmitted signal is turned into an IFFT using modern DSP techniques. On the receive end an FFT transform is performed and effectively, the frequency content of the transmitted OFDM symbol is recovered. An example transmit/receive chain taken from IEEE specifications is shown in Figure 2.

Figure 2: IEEE Example WLAN Transmit/Receive Chain

For practical reasons, a 64-point FFT is used to implement an 802.11a system, although any size FFT could be used as long at the 48 symbols are accounted for. If a larger FFT size were used, more nulls would have to be transmitted. An 802.11a signal in the time domain as well as in the frequency domain (spectrum) would have the characteristics shown in Figure 3. The 8 pilot signals are seen starting at a time equal to zero and each data symbol is preceded by a guard interval of 0.8us.

Figure 3: 802.11a Time and Frequency Domain Waveforms from VSS® Paper 9 : Page 2 of 12

An 802.11a signal can use up to 12 channels with channel spacing of 20 MHz. The maximum output power levels for the channels are shown in Table 4. The null placed at DC in the OFDM symbol allows one to use direct conversion without being greatly affected by DC-offset – as could clearly seen in the AWR VSS® simulation software.

Frequency Band (GHz) Maximum output power up to 6dBi antenna gain (mW) 5.15 – 5.25 40 (2.5mW/MHz) ~ 16dBm 5.25 – 5.35 200 (12.5mW/MHz) ~ 23dBm 5.725 -5.825 800 (50mW/MHz) ~ 29dBm

Table 4: 802.11a Output Power Specification

WLAN– System Design Challenges

There are serious challenges to using OFDM. Relative to 64QAM, the 802.11a 54Mbps has a higher peak-to- average ratio (PAR). As an example, consider what would happen if all 52 sub-carries simultaneously lined up, the PAR would be 17dB, which is much greater than QAM. Considering the AM/AM and AM/PM characteristics of an amplifier compared to the instantaneous power and phase of the signal, it is obvious that the peak power of the OFDM symbol can go into the nonlinear region of the amplifier, even if it has the same average power of the 64QAM signal.

Added to the PAR, one must consider the impact of the frequency offset of a local oscillator (LO). If the LO on the receive end is set to the same value as the LO on the transmit end, the RX signal would not suffer from inter-carrier interference (ICI). That is, the spectral content of a received symbol would not mix with its neighbour. If there is a slight offset between clocks, one symbol will “smear” into its neighbour.

Both of these effects can be investigated using system simulation software. Phase noise can also be simulated in VSS® by spectrally shaping a Gaussian noise source with a data file providing noise at a given offset frequency.

Error Vector Magnitude (EVM) is a measure of the inaccuracy of the IQ symbol, given these effects. The EVM specification or “Relative Constellation Error” for the 802.11a 54Mbps signal is -25dB as shown in Table 5. (On the transmit end the EVM measurement shall not exceed -25dB.) Alongside, the spectral measurement of the transmitted signal with an RBW set to 100KHz and a VBW of 30KHz shall stay within the confines of the specification mask. Although a specific spectral shaping technique is not called upon in the specifications, engineers use this technique to keep the spectrum within the confines of the mask. In addition, backing off the signal power from the 1dB compression point plays a role in keeping the spectrum within the mask.

Table 5: 802.11a EVM and Spectral Specification Paper 9 : Page 3 of 12

VSS – System Design Simulation for the WLAN Transmitter

The VSS® design suite from AWR allows one an “up front” view of your system. Figure 6 shows the effect of these contributing factors against specification conformance.

VSA Measures ACPR vs. Pout

VSA A=sweep(stepped(0,18,1)) ID=M1 A = Swept variable in dB

used to sweep signal power SRC MEAS

PIN=-18 PIN = Average Signal Power in dBm TP TP TP ID=IN ID=OUT NL_F GAIN ID=S12 ID=S3 DATA="PA_AMPM_1111" I80211A_TX PRBS GAIN=A dB DFTYP=AM-PM

1 2

PRBS 15 3 802.11a Signal Gain in dB Amplifier Under Test VSA Transmitter ID=M2 36Mbps SRC MEAS

VSA To Measure AM/AM, AM/PM

Figure 6: 802.11a Transmit Chain in VSS®

By sweeping the input power and the phase distortion, one can find the limits of design specification in order to meet the requirement design criteria. Table 7 and Figure 8 show how this ultimately affects the design limits of the individual components of the chain. DB(PWR_SPECN(TP.IN,100,3,10,0,-1,0,-1,1,0,0)) DB(PWR_SPECN(TP.OUT,100,3,10,1,-1,0,-1,1,0,0)) PlotCol(1,2) 801_11a For ACPR 801_11a For ACPR 802_11a Tx Spectrum Mask 80211A Spectrum Before and After Amplifier 5 0 EVM versus Gain/ -5 0 dB 0.3 dB 0.4 dB 0.5 dB Phase error -10 -15 -20 0 Degrees -33.7 dB -29.2 dB -27.3 dB -25.6 dB -25 -30 1 Degrees -32.2 dB -28.6 dB -26.9 dB -25.3 dB -35 2 Degrees -29.2 dB -27.1 dB -25.7 dB -24.5 dB -40 -45 3 Degrees -26.5 dB -25.1 dB -24.3 dB -23.4 dB -50 -55 5160 5170 5180 5190 5200 5210 5220 5230 5240 Frequency (MHz)

Table 7: VSS® Simulated EVM Results Figure 8: VSS® Simulated Spectrum

This table can then be passed to circuit designers to help them understand the confines of their quadrature mixer design. The idea is to use VSS® to get a qualitative view of the system at a very early stage. VSS® can be used from the beginning of a new design, developing specifications and/or throughout the design cycle to root out a problem from a higher level of abstraction.

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WLAN– Receiver Bit Error Rate (BER)

IEEE 802.11a specifications require a packet error rate of less than 10% for all possible data rates. A packet consists of 8000 bits (1000 bytes). The bit error rate comes directly from PER:

P (1 P )8000 PER < 0.1 for 1000 bytes (8000 bits) PC = − BE 8000 Let PPC = Probability that a packet is received correctly PPE =1− PPC =1−(1− PBE ) 8000 Let PBE = Probability that a bit is received in error (1− PBE ) =1− PPE

Let PPE = Probability that a packet is received in error PPE < 0.1, Solve for PBE

PBE ≤1.32e − 5 Thus, we see that the receiver needs to maintain a maximum BER of 1e-5.

Receiver sensitivity: S = NF + No + S / N is dependent on modulation technique, coding, bandwidth of signal and the noise figure of the receiver. It is the required minimum signal power to achieve a particular BER.

Table 9: IEEE 802.11a Table for Receiver Sensitivity

According to specifications in Table 9, a receiver detecting a 54Mbps signal should be able to achieve a BER of 1e-5 with an input power of -65dBm. Thus, using the equation for S above one can see that there is an 18.5dB margin for NF.

S = NF + No + S / N

No = 10log10 (kTB/1e - 3) in dBm. (Note : for B = 1Hz, No = −174 dBm)

For 802.11a set B = 16.6 MHz, then No ≅ −101.8 dBm. A S/N = 18.3 dB for 54 Mb/s ensures a (coded) BER of 1e - 5 S = -101.8 + 18.3 = -83.5 dBm This is 18.5 dB above specification

How was the 18.3dB value for S/N obtained?

P P S / N = S = S , for B =16.6 MHz PN B ⋅ N0

S / N = Eb N0 + 6.3 dB E P ⋅T /(#bits) P T = 4µ sec b = S SYM = S ⋅ SYM N0 N0 N0 6⋅48

bits per subcarrier in 64-QAM data subcarriers per 4usec OFDM symbol Also, one can find (for example, Van Nee & Prasad, p. 65) that for 64-QAM with the rate-3/4 code in the standard, the required Eb/N0 = 12 dB @ BER = 1e-5. So, the required SNR for 802.11a-54Mb/s becomes:

S/N = 12 + 6.3 = 18.3 dB. Paper 9 : Page 5 of 12

If one reads papers on WLAN design, it is very difficult to find such equations. In general, the papers reference a BER of 1e-5 and a value for S/N without giving details. We clearly state that a signal-to-noise ratio of 18.3dB is needed for a 64QAM signal with ¾ rate convolutional encoding, soft decision on the receive end and a defined trace back length. A different modulation and coding rate would yield a different S/N. In theory, one can design a receiver that can detect an -83.5dBm signal and achieve a BER of 1e-5 as long as the NF is zero. Reality dictates, however, that the NF would not be zero, so we have an 18.5 dB margin to work with.

VSS – System Design Simulation for the WLAN Receiver

For simulation purposes in Figure 10., we have folded the complete RF link into one amplifier. This amplifier is representative of the receiver’s Gain, IIP3 and NF. Later, we place the complete RF link into a system analysis and use VSS® to ascertain at a very high level of abstraction the receiver sensitivity value for a BER of 1e-5.

Figure 10: 802.11a Receive Chain in VSS®

This VSS® project includes the scrambling, convolutional encoding and interleaving and shows the individual blocks needed to construct an 802.11a 54Mbps signal along with the receive chain. VSS® is sweeping the signal power seen just before the receiver and as we sweep the signal power, VSS® plots BER. Each amplifier in this design represents values obtained from the RF-link cascaded measurements for minimum, average and maximum extremes of parameters. A BER simulation for each amplifier is shown in Table 11.

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Table 11: Simulated BER versus RF Link Parameters in VSS® As the simulation is running, we generate a BER curve using the highest NF and lowest gain value obtained from the cascaded analysis. The configuration ultimately defines the receiver’s worst case sensitivity. The simulation is a raw or Monte Carlo simulation. Bits in are being compared with bits out and a BER calculation is performed. A Monte Carlo simulation is used because there is a nonlinear element in the diagram as well as a soft decision. One cannot use a quasi-analytical or importance sampling to do such BER simulations and this is true for all system simulation tools. These BER simulation methods are acceptable if one is using just encoding, but even then the methods have many constraints and are not easily set up. Nevertheless, a simulation on a 1.5GHz PC takes less than 10 minutes to get to a BER of 1e-5.

Using the amplifier with the lowest NF and OIP3 would have given a result 1dB off. The specification states that one should be able to detect a signal of -65dBm and get a BER of 1e-5. In this case we determined that the receiver sensitivity is -76.91dBm, which now leaves a 12dB margin. Thus, this eats into the original 18.5dB margin. From a system analysis perspective there is a 12dB margin to work with. This can be easily consumed depending on receiver performance. In the simulation we use an ideal receiver and the synchronization is handled automatically by VSS® (unlike other system tools where manual compensation is needed). Using engineering, one can design a receiver that has a phase recovery loop and pilot detection. From a systems perspective, however, it is imperative that designers understand up front what is achievable. After all, if something cannot be simulated (i.e. mathematically proven), there is no chance that it can be built in hardware. Initial design work saves time in the long run and it is important to consider this point. A simulation tool is used to show what does not work very early on and therefore reduce cycle times. Telling the receiver designers that they have a 12dB margin to work with aids in the design of the receiver and the selection of ADCs, for example.

As shown in Figure 12, even interference simulation can be undertaken in VSS®. We have created an 802.11a interfering signal at 5240MHz along with a 5220MHz CW interferer tone. When the combination of the interfering tone with the adjacent channel is down converted, the resulting third-order intermodulation product folds into the bandwidth of the desired signal at 5200MHz. In VSS®, the receiver will consider the primary signal as the one to detect because the second combiner has its primary input designated as node 1. This enables the receiver to detect the propagated parameters of the primary signal for auto gain, phase and delay compensation. The receiver considers the other signals as interference and the mixer produces the resulting third-order intermodulation product. As the signal power is lowered, the BER results improve. The pulse shaping used by the interfering channel also plays a role in the BER simulation. If the skirt of the interfering channel were not as steep, it would “roll” into the desired channel and affect BER simulations. The secondary OVERLAP parameter of the 802.11aTX block governs the pulse shaping of the signal.

802.11a Interferen ce Test Bench Oversample=8

AvgSigPWR=0 TraceBack=48 A=73 For 3 dB above Sensitivity

TP TP OFDM_MOD ID=TP2 TP ID=BitsIn ID=A27 ID=IQdemod OUTLVL=AvgSigPWR OLVLTYP=Avg. Total Power (dBm) Convolutional decoder and deinterleaver BER SUBCKT RND_D NC=64 AWGN AMP_B TP ID=BER2 ID=S1 SUBCKT ID=A29 I80211A_SCRM CS=0.3125 MHz ATTEN ID=A17 GAIN=11.42 dB I80211A_SCRM ID=TP1 SWPVAR=InterferencePWR OFDM_DMOD NET="Disassembler" ID=S2 M=2 ID=A28 TP GI=0.25 ID=S6 PWR=-174 IP3=7.10 dBm QAM_DET VIT_DEC ID=A15 SWPTYP=Auto NET="DLVR" CNV_ENC QAM_MAP ID=subc PWRTYP=Single-sided PSD (dBm/Hz) NF=5.33 dB RATE= SCRMBLR=bin("1110101") SUBCKT SUBCKT CTRFRQ=5200 MHz LOSS=A dB ID=A13 SCRMBLR=bin("1110101") OUTFL="" Gain = 11.75 1 2 2 1 1 2 1 2 1 2 1 2 BER 3 3 3 PRBS OFDM Path Thermal Gain = 11.42 OFDM Disassembler MNERR =100 Scrambler Convolutional encoder, interleaver, and mapper SUBCKT De-Scrambler Mod Loss Nosie OIP3 = 7.10 DeMod NET="Soft 64QAM To Viterbi" TBLKSZ = 5000 1 2 TP ID=Tx1 NF = 5.33 802.11 54Mbps RX 802.11 54Mbps TX Upper for HARD, lower for SOFT decoding

DB(PWR_SPEC(TP.TP3,1000,0,10,0,-1,0,-1,1,0,0,0)) (dBm) 80211a I80211A_TX COMB TP ID=A7 ID=S7 ID=TP3 OUTLVL=InterferencePWR-30 LOSS=0 dB OLVLTYP=Avg. Power (dBW) COMB CTRFRQ= RND_D DRATE=54 Mbits/s ID=S8 PRIMINP=Node 1 ID=A8 CH= LOSS=0 dB NIN=2 RX Signal M=2 IDLEINTV=0 us CTRFRQ=5200 MHz 1 3 RATE= TXLEN=1024 PRIMINP=Auto 0 NIN=2 1 2 1 3 2 -20 2 Interference 3 -40 TONE ID=A9 -60 FRQ=5220 MHz InterferencePWR=sweep(stepped(-30,-35,-1)) PWR=InterferencePWR-30 dBW PHS=0 Deg CTRFRQ= -80 SMPFRQ=20e6*Oversample Hz ZS=_Z0 Ohm InterferencePWR= -35.5 T=_TAMB DegK NOISE=Freq analysis only -100 Desired

TP -120 ID=TP4 -140 Interferers (tone + 802.11a source) -160 -180 -200 5120 5140 5160 5180 5200 5220 5240 5260 5280 Frequency (MHz) Figure 12: 802.11a Interference Simulation in VSS®

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VSS – Impact of the Power Amplifier and Digital Predistortion

Why is there interest in linearizing the Power Amplifier (PA)? The motivation is to increase its power added efficiency of this amplifier. Typically, one want’s to keep the signal’s instantaneous power as close as possible to the 1dB compression point to increase PAE. Today’s signals are more complex and have high peak-to-average ratios. As the signal’s instantaneous power approaches the nonlinear region of an amplifier it becomes distorted. A spectrum plot reveals the result of operating in the nonlinear region, with third-order intermodulation products that cause spectral regrowth and higher ACPR values as in Figure 13.

Figure 13: Distorting PA Simulation in VSS®

To avoid PA distortion (keep the operation of PA in the linear region), one could simply back off from the 1dB compression point and accept this as the solution. Since we are working with a quadrature signal, specifically QAM, mathematically one needs to make sure that the derivative of the gain and phase response of the PA are approximately zero. Simply backing off from the 1dB compression point might not be the best thing to do to avoid distortion. The further from the 1dB compression point, the less efficient the PA.

A better option is digital predistortion. The idea is to choose a function F such that H(F) is linear for all input values. Graphically, we want to create the inverse AM/AM curve and combine it with the original curve such that the overall effect after the amplifier is a linear response. The baseband signal (IQ signal) is pre distorted so as to generate the inverse AM/AM AM/PM curves. The predistorter applies zero gain to the signal in the linear region; in the nonlinear region it either amplifies or attenuates the signal. Note that the overall gain of the predistorter in series with the PA must be the same as the PA alone. VSS® includes all of the necessary components to build such mathematical digital predistortion.

Clearly, in the linear region of operation the predistorter applies little to no gain to the incoming signal. In the nonlinear region, however, the predistorter activates. After establishing the inverse characteristics one needs to derive the coefficients that will be used to pre distort the incoming IQ signal. One could use a lookup table of power points. Here, the lookup tables (I & Q) each consist of 26 coefficients used to apply the necessary gain and phase shift to the incoming IQ signal. We use the signal’s instantaneous power to index the lookup table. One must first construct a circuit to calculate the signal’s power. There are two LUTs, one for the inphase coefficients and the other for the quadrature phase coefficients. The instantaneous power is calculated and the appropriate coefficients are selected. The LUTs internally handle interpolation. Simultaneously, the IQ signal is being complex multiplied with the coefficients as shown in Figure 14.

Paper 9 : Page 8 of 12

Figure 14: LUT Simulation in VSS®

The effect of LUT access time can be simulated in system software such as VSS®. The top link in Figure 15. is the amplifier alone. The second link is the digital predistorter with a variable D (for delay). The variable D is swept from 0 to 3. Each step is equivalent to 4ns. Thus, when D=0 the access time is 0ns and when D=3 the access time is 12ns. The blue spectrum is the signal before amplification. The green spectrum is being updated during the sweep of D (or the LUT access time). The red spectrum has a fixed access time of 12ns. The black spectrum is without digital predistortion.

Delay (ns) ACPR (dB) < 4 -74 4 -73 8 -70 12 -68

Figure 15: Digital Predistortion Delay Simulation in VSS®

The digital predistorter can be placed in the TX chain, before the transmitter PA. Ultimately, the predistorter helped with the overall receiver sensitivity number. We did not have to “back off” the signal in order to meet specification and can conclude that we have suitably linearized the PA.

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AWR Design Environment – Implementing a Final Solution

Finally, to use all of these ideas in a complete WLAN card design, we start with the ideal circuit design. Using advanced library model components and the unique AWR XML libraries for electrical model, schematic symbol and physical footprint, the board design is quickly developed into a practical design, accounting for all RF affects. Consideration is given to the physical layout as the project is built providing a true simulation model for the card in Figures 16 and 17.

External EM tools such as Sonnet can be used to design the antenna. This block simply becomes another model available within the AWR Design Environment. The AWR 3D planar EM tool is also used to reduce the PA output harmonics with resonator rings buried in the PCB stack.

SUB CKT ID =S61 NET= "Ant ennaSonnet802_11b"

MC TRACE ID =TL2 W =0.3 mm Receive Chain L=16.42 mm R=2 mm

M3C LIN I D=TL6 W 1=0.25 mm MTR ACE2 W 2=0.25 mm ID =X20 W 3=0.25 mm Antenna S1=0. 6 m m W =0.2 mm L=1.86 mm S2=0. 6 m m BType=1 L=1 mm M=1 1 Acc=1 4 W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X 2 5

L L L L L L

L L L L L L L L W2

D D D D D D D D D D D D D D T/R Switch B AL2 5 M M M M M M M M M M M M M M Balun SUBCK T M TRAC E2 ID=S5 3 6 W3 M TRACE 2 M 6CLIN M CTRAC E I D=X13 M CTRA CE NET=" TR Swit ch Package" 3 BA L1 I D=X19 2 2 2 2 2 2 2 2 2 2 2 2 2 2 M_PR OBE W =0C.A3 mPm_Mur ata STATE=0 CAP_M urat a I D=TL7 I D=X9 ID=V P1 L=2.I 9D7= mC2m I D=X12 ID =C12 W =0.2 mm W 1=0. 2 m m MTRA CE2 W =0. 3 mm W =0. 3 m m L=1. 98 m m 5 6 5 5 54 53 52 51 50 49 48 47 46 W 24=50. 2 m 4m4 43 ID=X 1 MTRAC E2 L=11. 1 m m S UBCK6T BT ypCe==100 pF L=5. 546 m m C=100 pF BType=1 CAP _Mur ata M =1Par t=G RM 033R71C101KD01 Par t=G RM033R71C 101KD01 MD LX W 3=0. 2 m m W=0. 2 m m ID=X 6 R =2 mm I D=S2 R =2 m m UNBAL 1 M =1 1 2 W 4=0. 2 m m L=1.23 mm W=0. 2 mIDm=C3 N ET=" balun" 1 W 5=0. 2 m m 42 BType=1 L= 1. 497C m=1m00 pF 5 UNB AL SU BCKT W 6=0. 2 m m M=1 BType=P1ar t=G RM033R 71C 101KD01 MD LX 1 2 I D=S1 S1=0. 3 m m M=1 2 NE T="BC M 2050" S2=0. 3 m m 41 BAL2 2 SU BCKT S3=0. 4 m m MTR ACE2 I D=S6 MD LX 1 2 S4=0. 3 m m M TRACE 2 ID =X18 N ET="A ntenna Balun" 3 S5=0. 3 m m 40 I D=X2 W =0.2 mm BAL1 CNTL MCT RACE L=0. 2 m m W =0.2 mm L=4.01 mm MD LX M TRACE 2 ID =TL3 1 2 Acc=1 1 7L=0. 66 mm 4 39 BType=1 I D=X5 G ND IN BType=1 W =0.3 mm W 1 M=1 L=L@MCTR ACE. TL2 m m M =1 W =0.2 mm R=2 mm MD LX L=1. 54C5A mPm_Mur ata 1 2 5 38 O UT2 GND 2 8 BType=ID1 =C9 M =1 C=100 pF MD LX W2 S UBCKT 1 2 6 37 Par t=G RM033R 71C 101KD01 PORT I D=S25 PORT OUT1 P=2 PO RT_PS1 2 2 N ET=" Baseband CPh=i 4p" Z=50 O hm P=1 3 9 2 2 Diversity Switch Z=100 Ohm Z=50 Ohm 7 36 W 3 MOD rkoa0603001 ID=M DLX_R1 PS tar t=- 20 dBm R=51 O hm MCOTRDcAaCtcE06030M0O1 Dcatc0603001 PS top=10 dBm MO Dcatc0603001 MO Dcatc0603001 ID =MDLX_C 27ID =MDLX_C 28 MM CON V MSUB = ID=TL4 PS tep=2 dB PO RT 4 1 0 C AP_Mur at a ID =MD LX_C39 ID =MDLX _C40 C=12 pF C=100X 0 pF X ID=M M1 8 35 Sim _mode=0 W=0. 23 m m L L D P=3 W 4 I D=C 14 C=220 pF X C=2. 3 pF MX SU B= MSU B= D 1 3 L Toler ance=1 LL =2.919 m m M M + Z=50 Ohm C =100 pF MS UB= D MS UB= SD im _mode=0 Sim _mode=0 D iff R=2 m m 1 3 M M 9 34 P art =GRM 033R71C101KD 01 Si m_mode=0 MSimDL_Xmode=0 Toler ance=1 Toler an1ce=1 1 5 11 Toler ance=1 1 Toler ance=1 1 1 2 W 5 2 4 10 33 Com m - 6 1 2 2 4 1 MD LX 2 11 32 W 6 S UBCKT SU BCKT I D=S7 MD LX I D=S60 M TRACE 2 N ET=" Transm ist LPF" MTR ACE2 RES 1 2 12 31 NE T="PA Out put Padstack" I D=X21 ID =X11 GND Vcc1 Vcc2 ID=R 1 SU BCKT W =0.2 mm W =0.2 mm R=25 O hm MTR ACE2 MTR ACE2 L=1. 12 m m L=1.39 mm MD LX 1 2 ID =X3 ID =X8 I D=S4 BType=1 BType=1 13 30 CA P_Mur ata G ND N ET="P A Packaged" GND MTEE X$ W =0.2 mm I D=C21 W =0.2 mm ID= MT1 M =1 M=1 MD LX L=0.79 mm L=L@MTRA CE2. X7 m m 1 2 BType=1 C=100 pF BType=1 MSU B=Fred 14 29 Par t=G RM033R 71C101KD01 SUBCK T R Fin RFout 1 2 1 2 1 2 M=1 M=1 IDB=AS3L2 5 MCT RACE NET=" balun" CAP _Mur ata M LIN MTRA CE2 3 15 16 17 18 19 20 21 2 2 2 3 2 4 2 5 26 27 28 ID =X10 V B1 GND ID=X 22 W =0.3 m m ID =C1 I D=TL1 2 W=0. 2 m m 2 2 2 2 2 2 2 2 2 2 2 2 BAL1 6 C=51 pF W =0. 2 m m L=4.12 mm Par t=G RM033R 71C 101KD0L1=0. 64 m m M TRAC E2 L=0.21 mm R=2 mm I D=X23 BType=1 M TRACE 2 MTRA CE2CAP _Mur ata Vcc0 VB2 VB3 W =0. 2 m m M=1 I D=X4 ID=X 7 ID =C22 2 2 2 L=0. 26 m m W =0.2 mm W=0. 2 m mC=100 pF X B Type=1 L D X X X X X X X X X L=0. 9274 mm L=1.426 mPmar t=G RM033R 71C101KD01 2 UNBAL M =1 X X X L M L L L L L L L L L L L D BType=1 BType=1 D D D D D D D D D D D M M M M M M M M M M M M M =1 M=1 1 M SUB X X X 1 1 1 1 1 1 1 1 1 1 1 1 L L L E r=3. 8 D D D H =0.25 mm M M M T= 0. 025 m m 1 1 1 R ho=1 CCI ND Tand=0 ID =L2 E rNom =3.8 R1=29 Ohm N ame=Fr ed R2=0. 013 Ohm Balun C=0. 045 pF L=33 nH K=0. 00016

Baseband/Transceiver Chipset Power Amplifier

Transmit Chain

Figure 16: Final WLAN Card Design

Figure 17: Final WLAN Card Design Layout

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AWR Design Environment – Using Microwave Office (MWO) and VSS® Together

The biggest advantage of having circuit level simulation tools (with the layout integral with the tool) combined with a top-level system simulation tool such as VSS®, is the ability to use the final design within an extracted systems world. Passing a complex 802.11a signal though the complete MWO circuit level design is simply a case of using subcircuit hierarchy within the same design environment.

Ultimately, this confirms “proof of concept” for the designer before time and money are spent on prototyping, manufacturing, or purchasing any of the constituent parts. This provides a high level of confidence that the final system will conform to the required specification, as per Figure 18.

TP System Spectrum 10 ID=PAIn TP 2.4366 GHz ref SUBCKT ID=PAOut (dBm) -0.1396 dBm ref ID=S1 Real RF Approach 0 (dBm) NET="SRC80211b_55Mbps1" Theoretical Ideal avgPWRdBW=Pin-30 -10 CTRFRQ=2437e6 NL_S Spectrum Mask RRCalpha=0.86 ID=S2 2.4366 GHz NET="RF Signal Path Board" -20 -6.208 dBm NOISE=Freq analysis only PSWP="" -30 FSWP="" RCVR ID=A1 -40 1 2 R D -50 3 IQ -60 5 4 2.404 2.415 2.426 2.437 2.448 2.459 2.47 Frequency (GHz)

TP ID=IQ

Figure 18: Final WLAN Card Design Conformance Testing

Conclusion

This paper discussed the theory of WLAN 802.11a and how such a system may be implemented. Using the AWR Design Environment, many of the specifications have been worked out and explored. Some of the technical challenges facing design teams have been described and the importance of using the correct design environment has been demonstrated.

Integrating both a circuit and system level simulation tool into the same environment has allowed a design to been proven before the cost implications of time and money are taken into account. A suitable approach to analyzing the RF-aware board has been used to optimize the design and to provide high confidence on the measurements expected once the prototypes are manufactured.

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Footnotes: – [1] Masoud Zargari, et. al, “A 5-GHz CMOS Transceiver for IEEE 802.11a Wireless LAN Systems” IEEE Journal of Solid-State Circuits, Vol 37, No. 12, December 2002. – [2] S. Kusunoki, et. al, “Power Amplifier Module with Digital Adaptive Pre- distortion for Cellular Phone” IEEE MTT-S Digest 2002, page 765.

References – “Wideband Orthogonal Frequency Division Multiplexing (W-OFDM)” WiLAN Wireless Data Communications, © 2000. – Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications High-speed Physical Layer in the 5 GHz Band. IEEE Std 802.11a-1999 – Svetoslav Gueorguiev, Saska Lindfors, “Design considerations for IEEE 802.11a WLAN transmitter in CMOS Technology” RISC group, Institute of Electronic Systems, Aalborg University, Denmark. – Jung Yee and Hossain Pezeshki-Esfahani, “Understanding Wireless LAN Performance Trade-Offs” Communications System Design November 2002. – “Improving Receiver Sensitivity with External LNA” Maxim Application Note, December 27, 2002. – “OFDM For Wireless Multimedia Communications” Richard Van Nee and Ramjee Prasad, Artech House Publishers. – Maria Hofvendahl, “2.4GHz Power Amplifier with Cartesian Feedback for WLAN” LiTH-ISY-EX-3524-2002, Datum 2002-09-03. – Ali Behravan, et. Al, “Adaptive Predistorter Design for Nonlinear High Power Amplifiers” – Frederick B. Popovich, et. al, “RF and Microwave Power Amplifier and Transmitter Technologies – Part 4” High Frequency Electronics, November 2003. – Allen Katz, “Linearizing High Power Amplifiers” Linearizer Technologies, Inc. – Ali Behravan, et. al., “Adaptive Predistorter Design for Nonlinear High Power Amplifiers”. – Frederick B. Popovich, et. al., “RF and Microwave Power Amplifier and Transmitter Technologies – Part 4”, High Frequency Electronics, November 2003. – Allen Katz, Linearizer Technologies, Inc. , “Linearizing High Power Amplifiers”

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