Model Checking of Software for Microcontrollers

Total Page:16

File Type:pdf, Size:1020Kb

Model Checking of Software for Microcontrollers Aachen Department of Computer Science Technical Report Model Checking of Software for Microcontrollers Bastian Schlich ISSN 0935–3232 Aachener Informatik Berichte AIB-2008-14 · · RWTH Aachen Department of Computer Science June 2008 · · The publications of the Department of Computer Science of RWTH Aachen University are in general accessible through the World Wide Web. http://aib.informatik.rwth-aachen.de/ Model Checking of Software for Microcontrollers Von der Fakultät für Mathematik, Informatik und Naturwissenschaften der RWTH Aachen University zur Erlangung des akademischen Grades eines Doktors der Naturwissenschaften genehmigte Dissertation vorgelegt von Diplom-Informatiker Bastian Schlich aus Essen/Ruhr Berichter: Professor Dr.-Ing. Stefan Kowalewski Professor Dr. Jan Peleska Tag der mündlichen Prüfung: 04.06.2008 Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar. Abstract Software of microcontrollers is getting more and more complex. It is mandatory to extensively analyze their software as errors can lead to severe failures or cause high costs. Model checking is a formal method used to verify whether a system satisfies certain properties. This thesis describes a new approach for model checking software for microcon- trollers. In this approach, assembly code is used for model checking instead of an intermediate representation such as C code. The development of [mc]square, which is a microcontroller assembly code model checker implementing this approach, is detailed. [mc]square has a modular architecture to cope with the hardware dependency of this approach. The single steps of the model checking process are divided into separate packages. The creation of the states is conducted by a specific simulator, which is the only hardware-dependent package. Within the simulator, the different microcontrollers are modeled accurately. This work describes the modeling of the ATMEL ATmega16 microcontroller and details implemented abstraction techniques, which are used to tackle the state- explosion problem. These abstraction techniques include lazy interrupt evaluation, lazy stack evaluation, delayed nondeterminism, dead variable reduction, and path reduction. Delayed nondeterminism introduces symbolic states, which represent a set of states, into [mc]square while still explicit model checking techniques are used. Thus, we successfully combined explicit and symbolic model checking techniques. A formal model of the simulator, which we developed to prove the correctness of abstraction techniques, is described. In this work, the formal model is used to show the correctness of delayed nondeterminism. To show the applicability of the approach, two case studies are described. In these case studies, we used programs of different sizes. All these programs were created by students in lab courses, during diploma theses, or in exercises without the intention to use them for model checking. Acknowledgments First and foremost, I would like to thank Professor Dr.-Ing. Stefan Kowalewski for giving me the opportunity to join his group to write my Dissertation thesis. He provided me great degrees of freedom to find my own topic and assisted me making important decisions. He was always willing to listen to my problems and gave me many useful advices. I thank Professor Dr. Jan Peleska for his willingness to be part of my Promotions- komission. Moreover, I thank him for the invitations to Bremen during which we had many fruitful discussions. I sincerely thank all members of Informatik 11 for the friendly working atmosphere, which contributed a lot to this thesis. Particularly, I have to thank my friends and colleagues Daniel Klünder, Falk Salewski, and Dirk Wilking for many fruitful discussions and for answering a pledora of questions both related and unrelated to my Dissertation thesis. Furthermore, I thank Dr. Carsten Weise for many useful hints and advices during the final phase of my thesis. I thank my students Lucas Brutschy, Eduard Feicho, Dominique Gückel, Volker Kamin, Jann Löll, Michael Rohrbach, Florian Scheuer, and John Schommer for helping me to implement [mc]square. I gratefully thank Dr. Thomas Noll for his support during the last year. He helped me to get a more formal insight of delayed nondeterminism and gave me many useful advices for my thesis. He always took the time to answer my numerous questions. I thank Dr. Ralf Huuck for inviting me to Australia. We had many interesting discussions and his pragmatism helped me to solve some of the problems that arise when writing a Dissertation thesis. Furthermore, I thank all colleagues of the Managing Complexity program at the National ICT Australia in Sydney. Especially, I thank Timothy Bourke, Jörg Brauer, Dr. Ansgar Fehnker, Dr. Gerwin Klein, Rafal Kolanski, and Harvey Tuch for many discussions and their valuable comments about my thesis. I appreciate Dr. Michael Weber’s contribution in the initial phase of my Disserta- tion thesis. He helped me discovering the peculiarities of assembly code. Last but not least, I would like to thank my family. They always supported me and helped my to find my way. Without them, this thesis would not have been possible. Bastian Schlich Aachen, June 2008 Contents 1 Introduction1 1.1 Objectives.................................2 1.2 Contributions...............................3 1.3 Outline..................................4 1.4 Bibliographic Notes............................4 1.5 Notation..................................5 2 Preliminaries7 2.1 Computation Tree Logic.........................7 2.2 Model Checking..............................9 2.2.1 Explicit vs. Symbolic Model Checking............. 10 2.2.2 Global vs. Local Model Checking................ 11 2.2.3 Counterexamples & Witnesses................. 11 2.3 Static Analysis.............................. 11 3 Model Checking Software for Microcontrollers 13 3.1 Model Checking C Code......................... 13 3.2 Model Checking Assembly Code.................... 16 3.3 Requirements for an Assembly Code Model Checker......... 18 4 [mc]square 21 4.1 Features.................................. 21 4.2 Architecture................................ 23 4.3 Evaluation................................. 26 5 State Space Building in [mc]square 29 5.1 Simulator Overview........................... 30 5.2 Simulator State.............................. 31 5.3 Microcontroller.............................. 32 5.3.1 Core................................ 33 5.3.2 Memories............................. 34 5.3.3 Stack............................... 38 5.3.4 Interrupts............................. 39 5.3.5 I/O Ports............................. 40 i Contents 5.3.6 Timers............................... 44 5.4 Program.................................. 48 5.5 Instruction Simulator........................... 50 5.6 Determinizer............................... 53 5.6.1 Determinizer Overview...................... 53 5.6.2 Immediate Instantiation..................... 56 5.6.3 Delayed Nondeterminism.................... 58 5.7 Formal Model of the Simulator..................... 62 5.7.1 Handlers and Guarded Assignments.............. 63 5.7.2 Modeling the ATMEL ATmega16................ 65 5.7.3 Coping with Nondeterminism.................. 67 5.7.4 Establishing Correctness..................... 70 5.8 Related Work............................... 70 5.8.1 Model Checking Machine Code................. 71 5.8.2 Delayed Nondeterminism.................... 73 6 Static Analysis in [mc]square 75 6.1 Challenges in Static Analysis of Assembly Code............ 75 6.2 Static Analyzer Overview........................ 77 6.3 Static Analyses.............................. 79 6.3.1 Control Flow Analysis...................... 79 6.3.2 Live Variables Analysis..................... 81 6.3.3 Reaching Definitions Analysis.................. 84 6.3.4 Stack Analysis.......................... 86 6.3.5 Global Interrupt Flag Analysis................. 88 6.4 Abstraction Techniques......................... 90 6.4.1 Dead Variable Reduction.................... 90 6.4.2 Path Reduction.......................... 91 6.5 Related Work............................... 93 7 Model Checking in [mc]square 97 7.1 Model Checker.............................. 97 7.1.1 Local Model Checking...................... 99 7.1.2 Global Model Checking..................... 103 7.1.3 Invariant Checking........................ 106 7.1.4 Counterexample Generation................... 107 7.2 State Space................................ 109 7.3 Influence on Validity of Formulas.................... 112 7.4 Related Work............................... 113 8 Case Studies 115 ii Contents 8.1 Effects of Abstraction Techniques on Different Programs....... 115 8.1.1 Execution............................. 115 8.1.2 Evaluation............................ 120 8.2 An Automotive Microcontroller Application.............. 121 8.2.1 Application............................ 122 8.2.2 Execution............................. 122 8.2.3 Evaluation............................ 129 9 Conclusion 131 9.1 Discussion................................. 131 9.2 Future Work............................... 133 iii Contents iv 1 Introduction Embedded systems are widely used in our daily life. They are, for example, employed in airplanes, cars, mobile phones, and household appliances. Embedded systems consist of hardware and software. The importance of the software on these devices is increasing because more and more functionality is implemented within the software and no longer realized by the hardware. The software of embedded
Recommended publications
  • Formal Verification of Hardware Peripheral with Security Property
    EXAMENSARBETE INOM TEKNIK, GRUNDNIVÅ, 15 HP STOCKHOLM, SVERIGE 2017 Formal Verification of Hardware Peripheral with Security Property Formell verifikation av extern hårdvara med säkerhetskrav VT 2017 NIKLAS ROSENKRANTZ JONATHAN Y HÅKANSSON KTH SKOLAN FÖR DATAVETENSKAP OCH KOMMUNIKATION Formal Verification of Hardware Peripheral with Security Property Jonathan Yao Håkansson, Niklas Rosencrantz Supervisor: Roberto Guanciale Examiner: Örjan Ekeberg CSC, KTH 2017 Abstract One problem with computers is that the operating system automatically trusts any externally connected peripheral. This can result in abuse when a peripheral technically can violate the security model because the peripheral is trusted. Because of that the security is an important issue to look at. The aim of our project is to see in which cases hardware peripherals can be trusted. We built a model of the universal asynchronous transmitter/receiver (UART), a model of the main memory (RAM) and a model of a DMA controller. We analysed interaction between hardware peripherals, user processes and the main memory. One of our results is that connections with hardware peripherals are secure if the hardware is properly configured. A threat scenario could be an eavesdropper or man-in-the-middle trying to steal data or change a cryptographic key. We consider the use-cases of DMA and protecting a cryptographic key. We prove the well-behavior of the algorithm. Some error-traces resulted from incorrect modelling that was resolved by adjusting the models. Benchmarks were done for different memory sizes. The result is that a peripheral can be trusted provided a configuration is done. Our models consist of finite state machines and their corresponding SMV modules.
    [Show full text]
  • Advanced SPIN Tutorial
    Advanced SPIN Tutorial Theo C. Ruys1 and Gerard J. Holzmann2 1 Department of Computer Science, University of Twente. P.O. Box 217, 7500 AE Enschede, The Netherlands. http://www.cs.utwente.nl/~ruys/ 2 NASA/JPL, Laboratory for Reliable Software. 4800 Oak Grove Drive, Pasadena, CA 91109, USA. http://spinroot.com/gerard/ Abstract. Spin [9] is a model checker for the verification of distributed systems software. The tool is freely distributed, and often described as one of the most widely used verification systems. The Advanced Spin Tu- torial is a sequel to [7] and is targeted towards intermediate to advanced Spin users. 1 Introduction Spin [2{5, 9] supports the formal verification of distributed systems code. The software was developed at Bell Labs in the formal methods and verification group starting in 1980. Spin is freely distributed, and often described as one of the most widely used verification systems. It is estimated that between 5,000 and 10,000 people routinely use Spin. Spin was awarded the ACM Software System Award for 2001 [1]. The automata-theoretic foundation for Spin is laid by [10]. The very recent [5] describes Spin 4.0, the latest version of the tool. The Spin software is written in standard ANSI C, and is portable across all versions of the UNIX operating system, including Mac OS X. It can also be compiled to run on any standard PC running Linux or Microsoft Windows. 2 Tutorial The Advanced Spin Tutorial is a sequel to [7] and is targeted towards interme- diate to advanced Spin users. The objective of the Advanced Spin Tutorial is to (further) educate the Spin 2004 attendees on model checking technology in general and Spin in particular.
    [Show full text]
  • Experiences from Large-Scale Model Checking: Verification of a Vehicle Control System
    Experiences from Large-Scale Model Checking: Verification of a Vehicle Control System Jonas Fritzsch Tobias Schmid Stefan Wagner University of Stuttgart BMW AG University of Stuttgart Institute of Software Engineering Munich, Germany Institute of Software Engineering Stuttgart, Germany [email protected] Stuttgart, Germany [email protected] [email protected] Abstract—In the age of autonomously driving vehi- safety that depends on a system or equipment operating cles, functionality and complexity of embedded systems correctly in response to its inputs” [3] is associated with the are increasing tremendously. Safety aspects become involved electrical, electronic, and programmable systems. more important and require such systems to operate with the highest possible level of fault tolerance. Simu- Car manufacturers thus need to “prove that the designed lation and systematic testing techniques have reached system fulfills the functional safety requirements according their limits in this regard. Here, formal verification to ISO 26262” [4] which is mandatory for the certification as a long established technique can be an appropriate of automated driving systems [5]. complement. However, the necessary preparatory work Traditional testing and simulation techniques, or failure like adequately modeling a system and specifying prop- erties in temporal logic are anything but trivial. In this mode and effects analysis (FMEA) alone reach their limits paper, we report on our experiences applying model in this regard. An exhaustive verification with limited checking to verify the arbitration logic of a Vehicle resources and time is difficult to achieve or even im- Control System. We balance pros and cons of different possible.
    [Show full text]
  • Incremental Learning and Testing of Reactive Systems
    Incremental Learning and Testing of Reactive Systems MUDDASSAR AZAM SINDHU Licentiate Thesis Stockholm, Sweden 2011 TRITA-CSC-A 2011:14 ISSN 1653-5723 KTH CSC ISRN KTH/CSC/A–11/14-SE SE-100 44 Stockholm ISBN 978-91-7501-062-5 SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framläg- ges till offentlig granskning för avläggande av teknologie licentiatexamen i datalogi Fredagen den 30 September 2011 klockan 10.00 i K2, Kungl Tekniska högskolan, Teknikringen 28 , Stockholm. © Muddassar Azam Sindhu, September 2011 Tryck: Universitetsservice US AB iii Dedication To Ammi, Abbu and Fari Abstract This thesis concerns the design, implementation and evaluation of a spec- ification based testing architecture for reactive systems using the paradigm of learning-based testing. As part of this work we have designed, verified and implemented new incremental learning algorithms for DFA and Kripke struc- tures. These have been integrated with the NuSMV model checker to give a new learning-based testing architecture. We have evaluated our architecture on case studies and shown that the method is effective. Acknowledgements I owe my deepest gratitude to my supervisor Prof. Karl Meinke without whose support this thesis would not have been possible. His thorough understanding of the subject, deep insight into the field and expertise during his lectures and meetings was always a source of knowledge and inspiration for me. His apt comments and constructive criticism always helped me to improve my work. His patience and encouragement whenever I was down during the last two and a half years always enabled me to re-start with a new zeal.
    [Show full text]
  • Program Model Checking
    National Aeronautics and Space Administration Intelligent Systems Division NASA Ames Research Center Program Model Checking A Practitioner’s Guide Masoud Mansouri-Samani, Perot Systems Government Services Peter C. Mehlitz, Perot Systems Government Services Corina S. Pasareanu, Perot Systems Government Services John J. Penix, Google, Inc. Guillaume P. Brat, USRA/RIACS Lawrence Z. Markosian, Perot Systems Government Services Owen O’Malley, Yahoo, Inc. Thomas T. Pressburger, NASA Ames Research Center Willem C. Visser, Seven Networks, Inc. January 15, 2008 Version 1.1 Contents CONTENTS ..................................................................................................................... III FIGURES .........................................................................................................................IX PREFACE........................................................................................................................XI 1 INTRODUCTION......................................................................................................... 1 1.1 What is Model Checking?........................................................................................1 1.2 Hardware vs. Software Model Checking.................................................................1 1.3 What is Program Model Checking?.........................................................................2 1.4 Advantages of Model Checking...............................................................................3 1.5 Model-Checking
    [Show full text]
  • Tool Presentation: Teaching Concurrency and Model Checking
    Tool Presentation: Teaching Concurrency and Model Checking Mordechai (Moti) Ben-Ari Department of Science Teaching Weizmann Institute of Science Rehovot 76100 Israel [email protected], http://stwww.weizmann.ac.il/g-cs/benari/ Abstract. This paper describes a set of software tools developed for teaching concurrency and model checking. jSpin is an elementary de- velopment environment for Spin that formats and filters the output of a simulation according to the user's specification. SpinSpider uses debugging output from Spin to generate a diagram of the state space of a Promela model; the diagram can be incrementally displayed us- ing iDot. VN supports teaching nondeterministic finite automata. The Erigone model checker is a partial reimplementation of Spin designed to be easy to use, well structured and well documented. It produces a full trace of the execution of the model checker in a format that is both readable and amenable to postprocessing. 1 Introduction Concurrency is a notoriously difficult subject to learn because the indeterminate behavior of programs poses challenges for students used to debugging programs by trial and error. They must learn new concepts of specification and correctness, as well as formal methods such as state transition diagrams and temporal logic. Several years ago, I became convinced that the Spin model checker is appropriate for teaching concurrency. This led me to write a new edition of my concurrency textbook [1], followed by an introductory textbook on Spin [2]. During this period, I developed software tools for teaching with Spin: jSpin, a development environment; SpinSpider, which automatically generates the state space diagram of a Promela program that can be viewed incrementally with iDot; VN, a tool to support learning nondeterminism of finite automata (NDFA).
    [Show full text]
  • Establishing Flight Software Reliability: Testing, Model Checking, Constraint-Solving, Monitoring and Learning
    Establishing Flight Software Reliability: Testing, Model Checking, Constraint-Solving, Monitoring and Learning Groce, A., Havelund, K., Holzmann, G., Joshi, R., & Xu, R. G. (2014). Establishing flight software reliability: testing, model checking, constraint-solving, monitoring and learning. Annals of Mathematics and Artificial Intelligence, 70(4), 315-349. doi:10.1007/s10472-014-9408-8 10.1007/s10472-014-9408-8 Springer Accepted Manuscript http://cdss.library.oregonstate.edu/sa-termsofuse Annals of Mathematics and Artificial Intelligence manuscript No. (will be inserted by the editor) Establishing Flight Software Reliability: Testing, Model Checking, Constraint-Solving, Monitoring and Learning Alex Groce · Klaus Havelund · Gerard Holzmann · Rajeev Joshi · Ru-Gang Xu the date of receipt and acceptance should be inserted later Abstract In this paper we discuss the application of a range of techniques to the verification of mission-critical flight software at NASA’s Jet Propulsion Laboratory. For this type of application we want to achieve a higher level of confidence than can be achieved through standard software testing. Unfortunately, given the current state of the art, especially when efforts are constrained by the tight deadlines and resource limitations of a flight project, it is not feasible to produce a rigorous formal proof of correctness of even a well-specified stand-alone module such as a file system (much less more tightly coupled or difficult-to-specify modules). This means that we must look for a practical alternative in the area between traditional testing and proof, as we attempt to optimize rigor and coverage. The approaches we describe here are based on testing, model checking, constraint-solving, monitoring, and finite-state machine learning, in addition to static code analysis.
    [Show full text]
  • The Cprover User Manual
    The CProver User Manual SatAbs – Predicate Abstraction with SAT CBMC – Bounded Model Checking Contents 1 Introduction 4 1.1 Motivation ............................ 4 1.2 Bounded Model Checking with CBMC ............ 5 1.3 Automatic Program Verification with SatAbs ........ 5 1.4 AShortTutorial ......................... 5 1.5 Hardware/Software Co-Verification . 6 2 Installation 7 2.1 Installing CBMC ......................... 7 2.2 Installing SatAbs ........................ 7 2.3 Installing the Eclipse Plugin . 9 2.4 Installing goto-cc ........................ 10 3 CBMC: Bounded Model Checking for C/C++ 11 3.1 AShortTutorial ......................... 11 3.1.1 FirstSteps ........................ 11 3.1.2 Verifying Modules . 12 3.1.3 LoopUnwinding ..................... 12 3.1.4 Unbounded Loops . 13 3.1.5 A Note About Compilers and the ANSI-C Library . 14 3.2 Command Line Interface . 15 4 Verifying C/C++ Programs with SatAbs 16 4.1 Background............................ 16 4.1.1 Abstraction and Refinement . 16 4.1.2 Properties......................... 18 4.2 Using the Command Line Interface . 19 4.3 Tutorials.............................. 20 4.3.1 Example: Reference Counting in Linux Device Drivers 21 4.3.2 Example: Buffer Overflow in a Mail Transfer Agent . 23 4.3.3 Unit Testing with SatAbs ............... 26 1 5 The Eclipse User Interface 31 6 Build Systems and Libraries 36 6.1 Integration into Build Systems with goto-cc ......... 36 6.1.1 Example: Building wu-ftpd . 36 6.1.2 Important Notes . 36 6.2 Libraries.............................. 37 6.2.1 Linkinglibraries ..................... 37 6.2.2 Abstractions for Zero-Terminated Strings . 37 7 ANSI-C/C++ Language Features 39 7.1 BasicDatatypes ........................
    [Show full text]
  • A Primer on Model Checking
    extended papers A Primer on Model Checking Mordechai (Moti) Ben-Ari odel checking is a widely used formal method for the verifi cation of concurrent programs. MThis article starts with an introduction to the concepts of model checking, followed by a description of Spin, one of the foremost model checkers. Software tools for teaching concurrency and nondeterminism using model checking are described: Erigone, a model checker for teaching; jSpin, a development environment; VN, a visualization of nondeterminism. INTRODUCTION A BIT OF LOGIC The June 2009 issue of inroads contained a special Suppose that you want to know if ~p->(p->q) is a 1 section on Formal Methods in Education and Train- 2 valid formula of the propositional calculus. You could ing. Several of the papers described the central place do what every mathematician does for a living: prove it of model checking for verifi cation of programs, primarily concurrent using a deductive system consisting of axioms assumed to be valid and distributed programs [14,17]. Model checking verifi es a pro- and rules of inference that preserve validity. The same can be done gram by using software to analyze its state space, as opposed to for computer programs: Deductive systems pioneered by C.A.R. the mathematical deductive methods proposed by the pioneers of Hoare [8] can be used to prove that a program is correct, mean- verifi cation like C.A.R. Hoare. Edmund Clarke, Allen Emerson ing that the execution of the program gives an output that satisfi es and Joseph Sifakis received the 2008 Turing Award for their inven- a correctness property expressed as a formula in logic.
    [Show full text]
  • Formal Verification of Requirements Using SPIN: a Case Study on Web
    Formal Verification of Requirements using SPIN: A Case Study on Web Services∗ Raman Kazhamiakin Marco Pistore Marco Roveri DIT, University of Trento ITC-irst Via Sommarive 14, I-38050, Trento, Italy Via Sommarive 18, I-38050, Trento, Italy {raman,pistore}@dit.unitn.it [email protected] Abstract in software development. Despite its criticality, require- ments are often described only in natural language and re- In this paper we describe a novel approach for the for- quirements analysis techniques are rarely applied. mal specification and verification of distributed processes The Tropos project (http://www.troposproject.org/) in a Web service framework. The formal specification is aims to develop a requirements driven software engineer- provided at two different levels of abstraction. The strategic ing methodology for agent-oriented, distributed systems. level describes the requirements of the Web service domain, Tropos provides graphical notations for requirements mod- in terms of the different actors participating to it, with their els, based on concepts like actors, goals, and dependencies goals and needs and with their mutual dependencies and among actors. Moreover, it adopts a variety of tools and expectations. The process level shows how these require- techniques to support the analysis of the requirements mod- ments are operationalized into communicating processes els. In particular, Tropos provides a formal specification running on the different Web servers. We model the strate- language, called Formal Tropos (hereafter FT). FT supple- gic level exploiting Formal Tropos (FT), a language for the ments the graphical notations with a first-order Linear Tem- formal definition of the requirements of agent-oriented sys- poral Logic (LTL) suitable for automated verification.
    [Show full text]
  • An Approach for Automated Verification of Web Applications Using Model Checking and Replaying the Scenarios of Counterexamples
    AN APPROACH FOR AUTOMATED VERIFICATION OF WEB APPLICATIONS USING MODEL CHECKING AND REPLAYING THE SCENARIOS OF COUNTEREXAMPLES A THESIS SUBMITTED TO THE GRADUATE SCHOOL OF INFORMATICS OF THE MIDDLE EAST TECHNICAL UNIVERSITY BY YUDUM PAÇİN IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN THE DEPARTMENT OF INFORMATION SYSTEMS SEPTEMBER 2015 AN APPROACH FOR AUTOMATED VERIFICATION OF WEB APPLICATIONS USING MODEL CHECKING AND REPLAYING THE SCENARIOS OF COUNTEREXAMPLES Submitted by YUDUM PAÇİN in partial fulfillment of the requirements for the degree of Master of Science in Information Systems, Middle East Technical University by, Prof. Dr. Nazife Baykal Director, Graduate School of Informatics Prof. Dr. Yasemin Yardımcı Head of Department, Information Systems Assoc. Prof. Dr. Aysu Betin Can Supervisor, Information Systems Examining Committee Members: Assoc. Prof. Dr. Altan Koçyiğit Information Systems, METU Assoc. Prof. Dr. Aysu Betin Can Information Systems, METU Assoc. Prof. Dr. Banu Günel Kılıç Information Systems, METU Assoc. Prof. Dr. Halit Oğuztüzün Computer Engineering, METU Assoc. Prof. Dr. Vahid Garousi Yusifoğlu Software Engineering, Haccettepe University Date: 03/09/2015 I hereby declare that all information in this document has been obtained and presented in accordance with academic rules and ethical conduct. I also declare that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work. Name, Last Name : Yudum Paçin Signature : iii ABSTRACT AN APPROACH FOR AUTOMATED VERIFICATION OF WEB APPLICATIONS USING MODEL CHECKING AND REPLAYING THE SCENARIOS OF COUNTEREXAMPLES Paçin, Yudum M.S., Department of Information Systems Supervisor: Assoc.
    [Show full text]
  • Model-Based Design of Cyber-Physical Systems
    Model-based Design of Cyber-Physical Systems Christian Rinderknecht 28th November 2014 Abstract We survey existing tools and methods for the simulation, testing and verification of concurrent communicating systems, and their pertinence for model-driven design and programming of cyber-physical systems. We also cover workflows and tests and conclude with two proposals. 1 Formal methods In the context of our project, we define a cyber-physical system (CPS) as a wireless mobile network of embedded systems featuring environmental sensors and computational capability. Usually, an embedded system carries on specific control functions with real-time constraints, e.g., related to safety, on top of a real-time operating system (RTOS), but we will extend the notion to encompass general-purpose computers, for example, smartphones and Raspberry Pis running GNU/Linux. Depending on the scale and the nature of the software applications, different network topologies, routing and synchronisation protocols may be used, for example centralised architectures (client-server) or decentralised ones, like peer-to-peer (P2P) or mobile ad hoc networks (MANET), where nodes are also routers. At the application layer, real-time constraints might be expected, as well as code (a.k.a. location) migration and security guarantees. The model-driven design of CPS uses formal models, possibly including real-time features, which are checked with regards to some desired properties and tested through simulation, before implementations are derived. Model checking is a formal method whereby the truth of a logical formula (e.g., of a temporal nature) is checked on a finite model of a system. It is different from testing, which consists in interacting with an implementation, whose state space may be infinite, and observing whether its responses conform to its model (if no stimulation of the system is performed, we have an instance of passive testing).
    [Show full text]