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R4300 RISC Processor Specification a Subsidiary of Silicon Graphics Inc

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R4300 RISC Processor Specification a Subsidiary of Silicon Graphics Inc R4300 RISC Processor Specification Revision 2.2 July, 1995 MIPS Technologies Inc. 2011 N. Shoreline Blvd. Mountain View, Ca. 94039-7311 http://www.mips.com MTI CONFIDENTIAL This document contains information that is proprietary to MIPS Technologies Inc. and is authorized only to employees of MIPS Technologies Inc. and to those persons specifically designated by MIPS Technologies Inc. The information in this document is preliminary and is subject to change without notice. MIPS Technologies Inc. reserves the right to change any products described herein to improve function or design. MIPS does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under patent rights nor imply the rights of others. Copyright 1991 - 1995 by MIPS Technologies Inc. No part of this document may be copied by any means without writ- ten permission of MIPS Technologies Inc. mips MIPS Technologies Inc. A subsidiary of Silicon Graphics Inc. R4300 RISC Processor Specification v2.2 Table Of Contents 1.0 Introduction .............................................................................................................................1 1.1 Reference Documents .....................................................................................................................1 1.2 Data Formats and Addressing .........................................................................................................1 1.3 Registers..........................................................................................................................................1 1.4 Spec Objectives ...............................................................................................................................2 2.0 Overview.................................................................................................................................3 3.0 Operation Fundamentals ........................................................................................................6 3.1 Power management.........................................................................................................................6 3.2 Processor Pipeline...........................................................................................................................6 3.2.1 Pipeline Overview...................................................................................................................6 3.2.2 Pipeline Interlocks and Exceptions.........................................................................................7 3.2.3 Pipeline Operation................................................................................................................10 3.2.3.1 Add ADD rd,rs,rt..........................................................................................................10 3.2.3.2 Jump and Link Register JALR rd,rs ............................................................................10 3.2.3.3 Branch on Equal BEQ rs,rt,offset................................................................................10 3.2.3.4 Trap if Less Than TLT rs,rt .........................................................................................11 3.2.3.5 Load Word LW rt,offset(base).....................................................................................11 3.2.3.6 Store Word SW rt,offset(base)....................................................................................11 4.0 Execution Unit.......................................................................................................................13 4.1 Goals..............................................................................................................................................13 4.2 Overview........................................................................................................................................13 4.3 Functional Description ...................................................................................................................14 4.3.1 Instruction latencies..............................................................................................................14 4.3.2 Unit Organization..................................................................................................................17 4.3.2.1 Integer/Mantissa Data Path ........................................................................................17 4.3.2.2 Operand Bypass Network...........................................................................................18 4.3.2.3 Register File................................................................................................................18 4.3.2.4 Floating-Point Instruction Execution ...........................................................................18 4.3.2.5 Instruction Address Unit..............................................................................................19 5.0 Data and Instruction Caches ................................................................................................21 5.1 Cache Organization .......................................................................................................................21 5.2 Cache States .................................................................................................................................21 5.2.1 Instruction Cache .................................................................................................................21 5.2.2 Data Cache ..........................................................................................................................22 5.2.2.1 Data Cache State transition........................................................................................22 5.2.3 Cache state change during processor execution .................................................................22 5.2.4 Manipulation of the Caches by an External Agent ...............................................................22 5.2.5 Cache Line ...........................................................................................................................22 5.2.6 Instruction Cache line replacement ......................................................................................22 5.2.7 Data Cache line replacement ...............................................................................................22 5.3 Cache Access Time.......................................................................................................................23 5.4 Cache Miss Handling.....................................................................................................................23 5.5 Cache Operations..........................................................................................................................23 5.6 Reset Effects..................................................................................................................................24 5.7 Flush Buffer....................................................................................................................................25 6.0 Cache Test Mode. ................................................................................................................27 July, 1995 – 1 – MTI Confidential R4300 RISC Processor Specification v2.2 6.1 Cache Memory Description............................................................................................................27 6.2 Test Mode Description...................................................................................................................27 6.3 Test Mode Commands ..................................................................................................................28 6.4 Cache Memory Address ................................................................................................................28 6.5 Cache Read ...................................................................................................................................29 6.6 Cache Write ...................................................................................................................................30 6.7 Cache Organization .......................................................................................................................33 7.0 System Control Coprocessor (CP0) ...............................................................................................35 7.1 R4300 Control Coprocessor Registers ..........................................................................................35 7.1.1 Index Register (0).................................................................................................................36 7.1.2 Random Register (1) ............................................................................................................36 7.1.3 EntryLo0 Register (2) ...........................................................................................................36 7.1.4 EntryLo1 Register (3) ...........................................................................................................37 7.1.5 Context Register (4) .............................................................................................................37 7.1.6 PageMask Register (5).........................................................................................................38 7.1.7 Wired Register (6) ................................................................................................................39
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