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Study of the Impact of Variations of Fabrication Process on Digital Circuits Tarun Chawla

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Study of the Impact of Variations of Fabrication Process on Digital Circuits Tarun Chawla Study of the impact of variations of fabrication process on digital circuits Tarun Chawla To cite this version: Tarun Chawla. Study of the impact of variations of fabrication process on digital circuits. Micro and nanotechnologies/Microelectronics. Télécom ParisTech, 2010. English. NNT : -. pastel-00537050 HAL Id: pastel-00537050 https://pastel.archives-ouvertes.fr/pastel-00537050 Submitted on 17 Nov 2010 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Thèse Présentée pour obtenir le grade de Docteur du Télécom ParisTech Spécialité: Électronique et Communications Tarun CHAWLA Titre: Etude de l’impact des variations du procédé de fabrication sur les circuits numériques Soutenue le 30 Septembre 2010 devant le jury composé de: Prof. Lirida NAVINER Président de Jury Dr. Marc BELLEVILLE Rapporteurs Dr. Nadine AZEMARD Rapporteurs Prof. Amara AMARA Directeur de thèse Prof. Andrei VLADIMIRESCU Co-directeur de thèse M. Sebastien MARCHAL Tuteur industriel - 2 - Abstract Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on inter- die variations that form the bulk of process variations. Much work has been done to study their effects and to make circuits more robust by improvements in technology or design. In this work, we have focused on two particular kinds of variations- Inter-die NMOS to PMOS mismatch and Intra-die local random mismatch. Neither had a noticeable effect in industrial designs and has become a cause of worry only recently. The source of these variations lies in the basic process and is random in nature. Thus, their effect cannot be ameliorated without overhauling the complete process. The work in academia has mostly focused on process changes or architectural improvements. Our work is geared towards design improvements at gate and path level. We looked at the basic phenomena behind these variations and using simulations observed how they affect the different parameters in a digital design. The focus was on synchronous systems, i.e. clock distribution system that is highly impacted by these variations. We proposed some design methods and optimization strategies to make the circuits more robust. Most of these methods are exploitable within existing design flows that minimizes the cost and allows for quick adoption in the industry. We included the effect of voltage and temperature changes on these two variations to put together a comprehensive understanding. We also proposed methods to verify the basis of our work by comparing against silicon test results. The results of this work have helped to shape the policy of how to handle local mismatch in industrial designs. - 3 - - 4 - Acknowledgement I would like extend my sincere gratitude to my thesis advisors Dr. Amara AMARA and Dr. Andrei VLADIMIRESCU, for their continuous guidance during this research. I am also greatly indebted to Sebastien MARCHAL, my industrial advisor, whose guidance and support made this thesis possible. I wish to thank all my colleagues who helped to solve my queries and problems. I am thankful to all my friends in France who made my stay here a very pleasant one. I am especially grateful to my colleague and friend Nirmal PREGASSAME who has translated many a things for me as well as helped to improve my French. Any endeavor in my life is incomplete without mentioning my family, especially my mother, who has taken great pains to help me become what I am today. Finally, I would like to thank STMicroelectronics, Crolles that provided me an opportunity to pursue my dream and enabled me to work along and learn from some of the best people in the field. - 5 - - 6 - Table of Contents THESE .......................................................................................................................................................... 1 ABSTRACT .................................................................................................................................................. 3 ACKNOWLEDGEMENT ........................................................................................................................... 5 TABLE OF CONTENTS ............................................................................................................................ 7 RESUME (EN FRANÇAIS) ...................................................................................................................... 11 LIST OF SYMBOLS ................................................................................................................................. 37 1 INTRODUCTION TO VARIATIONS IN DIGITAL DESIGN ................................................... 39 1.1 PROCESS VARIATIONS..................................................................................................................... 41 1.1.1 Nature .................................................................................................................................. 41 1.1.2 Predictability ........................................................................................................................ 42 1.2 VOLTAGE VARIATIONS ................................................................................................................... 43 1.3 TEMPERATURE VARIATIONS ........................................................................................................... 44 1.4 PVT VARIATIONS IN DIGITAL CIRCUITS .......................................................................................... 45 1.4.1 Variations in digital clock networks..................................................................................... 45 1.4.2 Variations vs. defects ........................................................................................................... 48 1.4.3 Analog behavior of digital networks .................................................................................... 48 1.5 OBJECTIVES .................................................................................................................................... 48 1.5.1 Identification of process variations and their mechanisms .................................................. 48 1.5.2 Estimation of variation impact on performance of digital circuits ...................................... 49 1.5.3 Evaluation of design methods and techniques to limit variation impact .............................. 49 2 STATE OF THE ART IN ASIC DESIGN ..................................................................................... 51 2.1 VARIATION TAXONOMY ................................................................................................................. 52 2.1.1 Temporal .............................................................................................................................. 52 2.1.2 Spatial .................................................................................................................................. 53 2.2 MANUFACTURING STEPS CAUSING VARIATIONS ............................................................................. 56 2.2.1 Photolithography ................................................................................................................. 56 2.2.2 Etching ................................................................................................................................. 57 2.2.3 Doping ................................................................................................................................. 57 2.2.4 Deposition ............................................................................................................................ 57 2.2.5 Chemical Mechanical Polishing (CMP) .............................................................................. 57 2.2.6 Annealing, Oxidation, Resist development ........................................................................... 58 2.3 DESIGN PARAMETERS AT DIFFERENT LEVELS OF ABSTRACTION ................................................... 58 2.3.1 Manufacturing level ............................................................................................................. 58 2.3.2 Transistor level .................................................................................................................... 63 2.3.3 Logic gate level .................................................................................................................... 69 2.3.4 Path level ............................................................................................................................. 72 2.3.5 Circuit level .......................................................................................................................... 77 2.4 DYNAMIC VARIATIONS ................................................................................................................... 79 2.4.1 Supply voltage ...................................................................................................................... 79 2.4.2 Temperature
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