DOCSLIB.ORG

Study of the Impact of Variations of Fabrication Process on Digital Circuits Tarun Chawla

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

Study of the impact of variations of fabrication process on digital circuits Tarun Chawla To cite this version: Tarun Chawla. Study of the impact of variations of fabrication process on digital circuits. Micro and nanotechnologies/Microelectronics. Télécom ParisTech, 2010. English. NNT : -. pastel-00537050 HAL Id: pastel-00537050 https://pastel.archives-ouvertes.fr/pastel-00537050 Submitted on 17 Nov 2010 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Thèse Présentée pour obtenir le grade de Docteur du Télécom ParisTech Spécialité: Électronique et Communications Tarun CHAWLA Titre: Etude de l’impact des variations du procédé de fabrication sur les circuits numériques Soutenue le 30 Septembre 2010 devant le jury composé de: Prof. Lirida NAVINER Président de Jury Dr. Marc BELLEVILLE Rapporteurs Dr. Nadine AZEMARD Rapporteurs Prof. Amara AMARA Directeur de thèse Prof. Andrei VLADIMIRESCU Co-directeur de thèse M. Sebastien MARCHAL Tuteur industriel - 2 - Abstract Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on inter- die variations that form the bulk of process variations. Much work has been done to study their effects and to make circuits more robust by improvements in technology or design. In this work, we have focused on two particular kinds of variations- Inter-die NMOS to PMOS mismatch and Intra-die local random mismatch. Neither had a noticeable effect in industrial designs and has become a cause of worry only recently. The source of these variations lies in the basic process and is random in nature. Thus, their effect cannot be ameliorated without overhauling the complete process. The work in academia has mostly focused on process changes or architectural improvements. Our work is geared towards design improvements at gate and path level. We looked at the basic phenomena behind these variations and using simulations observed how they affect the different parameters in a digital design. The focus was on synchronous systems, i.e. clock distribution system that is highly impacted by these variations. We proposed some design methods and optimization strategies to make the circuits more robust. Most of these methods are exploitable within existing design flows that minimizes the cost and allows for quick adoption in the industry. We included the effect of voltage and temperature changes on these two variations to put together a comprehensive understanding. We also proposed methods to verify the basis of our work by comparing against silicon test results. The results of this work have helped to shape the policy of how to handle local mismatch in industrial designs. - 3 - - 4 - Acknowledgement I would like extend my sincere gratitude to my thesis advisors Dr. Amara AMARA and Dr. Andrei VLADIMIRESCU, for their continuous guidance during this research. I am also greatly indebted to Sebastien MARCHAL, my industrial advisor, whose guidance and support made this thesis possible. I wish to thank all my colleagues who helped to solve my queries and problems. I am thankful to all my friends in France who made my stay here a very pleasant one. I am especially grateful to my colleague and friend Nirmal PREGASSAME who has translated many a things for me as well as helped to improve my French. Any endeavor in my life is incomplete without mentioning my family, especially my mother, who has taken great pains to help me become what I am today. Finally, I would like to thank STMicroelectronics, Crolles that provided me an opportunity to pursue my dream and enabled me to work along and learn from some of the best people in the field. - 5 - - 6 - Table of Contents THESE .......................................................................................................................................................... 1 ABSTRACT .................................................................................................................................................. 3 ACKNOWLEDGEMENT ........................................................................................................................... 5 TABLE OF CONTENTS ............................................................................................................................ 7 RESUME (EN FRANÇAIS) ...................................................................................................................... 11 LIST OF SYMBOLS ................................................................................................................................. 37 1 INTRODUCTION TO VARIATIONS IN DIGITAL DESIGN ................................................... 39 1.1 PROCESS VARIATIONS..................................................................................................................... 41 1.1.1 Nature .................................................................................................................................. 41 1.1.2 Predictability ........................................................................................................................ 42 1.2 VOLTAGE VARIATIONS ................................................................................................................... 43 1.3 TEMPERATURE VARIATIONS ........................................................................................................... 44 1.4 PVT VARIATIONS IN DIGITAL CIRCUITS .......................................................................................... 45 1.4.1 Variations in digital clock networks..................................................................................... 45 1.4.2 Variations vs. defects ........................................................................................................... 48 1.4.3 Analog behavior of digital networks .................................................................................... 48 1.5 OBJECTIVES .................................................................................................................................... 48 1.5.1 Identification of process variations and their mechanisms .................................................. 48 1.5.2 Estimation of variation impact on performance of digital circuits ...................................... 49 1.5.3 Evaluation of design methods and techniques to limit variation impact .............................. 49 2 STATE OF THE ART IN ASIC DESIGN ..................................................................................... 51 2.1 VARIATION TAXONOMY ................................................................................................................. 52 2.1.1 Temporal .............................................................................................................................. 52 2.1.2 Spatial .................................................................................................................................. 53 2.2 MANUFACTURING STEPS CAUSING VARIATIONS ............................................................................. 56 2.2.1 Photolithography ................................................................................................................. 56 2.2.2 Etching ................................................................................................................................. 57 2.2.3 Doping ................................................................................................................................. 57 2.2.4 Deposition ............................................................................................................................ 57 2.2.5 Chemical Mechanical Polishing (CMP) .............................................................................. 57 2.2.6 Annealing, Oxidation, Resist development ........................................................................... 58 2.3 DESIGN PARAMETERS AT DIFFERENT LEVELS OF ABSTRACTION ................................................... 58 2.3.1 Manufacturing level ............................................................................................................. 58 2.3.2 Transistor level .................................................................................................................... 63 2.3.3 Logic gate level .................................................................................................................... 69 2.3.4 Path level ............................................................................................................................. 72 2.3.5 Circuit level .......................................................................................................................... 77 2.4 DYNAMIC VARIATIONS ................................................................................................................... 79 2.4.1 Supply voltage ...................................................................................................................... 79 2.4.2 Temperature
Recommended publications
  • Timing Analysis of Integrated Circuits Under Process Variations

    Timing Analysis of Integrated Circuits Under Process Variations

    UNIVERSIDADE TECNICA´ DE LISBOA INSTITUTO SUPERIOR TECNICO´ Timing Analysis of Integrated Circuits Under Process Variations Lu´ısJorge Br´asMonteiro Guerra e Silva (Mestre) Disserta¸c~aopara obten¸c~aodo Grau de Doutor em Engenharia Inform´aticae de Computadores Orientador: Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira J´uri Presidente: Reitor da Universidade T´ecnicade Lisboa Vogais: Doutor Jo~aoPaulo Marques da Silva Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira Doutor Jo~aoManuel Paiva Cardoso Doutor Jos´eCarlos Alves Pereira Monteiro Doutor Joel Reuben Phillips Doutor Nuno Filipe Valentim Roma Maio de 2009 Abstract As feature sizes in integrated circuit technology decrease into the nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Traditional, nominal case analysis and verification methodologies are no longer able to ensure silicon success. This dissertation addresses this problem, by developing key contributions for a variation-aware timing analysis methodology, capable of accurately model and predict circuit performance for the latest integrated circuit technologies. The proposed approach builds on reliable and established timing analysis paradigms by introducing a variation-aware extension, that can easily be implemented in currently used design flows. This dissertation presents several key contributions. One is a methodology for generating parametric delay models, tailored to the specific needs of delay calculation for pre-characterized standard cells. Unlike previous approaches based on numerical approximations, the proposed method is essentially analytical, and therefore capable of producing more accurate and robust results, at a fraction of the computational cost. Another contribution is a methodology that enables the automated computation of the critical timing conditions (corners) of a digital integrated circuit, given variation-aware parametric delay models.
  • Test and Characterization Methodologies for Advanced Technology Nodes Darayus Adil Patel

    Test and Characterization Methodologies for Advanced Technology Nodes Darayus Adil Patel

    Test and characterization methodologies for advanced technology nodes Darayus Adil Patel To cite this version: Darayus Adil Patel. Test and characterization methodologies for advanced technology nodes. Elec- tronics. Université Montpellier, 2016. English. NNT : 2016MONTT285. tel-01808874 HAL Id: tel-01808874 https://tel.archives-ouvertes.fr/tel-01808874 Submitted on 6 Jun 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par Université de Montpellier Préparée au sein de l’école doctorale I2S Et de l’unité de recherche LIRMM Spécialité : SYAM Présentée par DARAYUS ADIL PATEL TEST AND CHARACTERIZATION METHODOLOGIES FOR ADVANCED TECHNOLOGY NODES Soutenue le 5 Juillet 2016 devant le jury composé de M. Daniel CHILLET Professeur, Université de Président du Jury / Rennes Rapporteur M. Salvador MIR Directeur de Recherche Rapporteur CNRS, TIMA Mme. Sylvie NAUDET Team Leader, Examinateur STMicroelectronics M. Alberto BOSIO MCF HDR, Université de Examinateur Montpellier M. Patrick GIRARD Directeur de Recherche Directeur de Thèse CNRS, LIRMM M. Arnaud
  • Phd Dissertation

    Phd Dissertation

    ABSTRACT WIDIALAKSONO, RANDY HARI. Three-Dimensional Integration of Heterogeneous Multi-Core Processors. (Under the direction of Dr. Paul Franzon and Dr. W. Rhett Davis.) This dissertation will explore the advantages of and design methodology for 3D integration in the context of building heterogeneous multi-core processors. The processor features a fast thread migration and cache core decoupling scheme. First, we present empirical results in a commercial 130 nm process. We demonstrate that the 3D implementation of a heterogeneous multi-core processor consumes 31% less power and 22% shorter average wirelength compared to the 2D implementation. Second, this work presents the physical design methodology used for the tape-out of a die-stacked 3D-IC processor. Finally, we propose a new algorithm and methodology for timing-driven 3D-IC via assignment. Experiment results show up to 30% improvement in total negative slack compared to a via assignment algorithm with total wirelength objective function. © Copyright 2016 by Randy Hari Widialaksono All Rights Reserved Three-Dimensional Integration of Heterogeneous Multi-Core Processors by Randy Hari Widialaksono A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the Degree of Doctor of Philosophy Computer Engineering Raleigh, North Carolina 2016 APPROVED BY: Dr. Eric Rotenberg Dr. Agnes Szanto Dr. Paul Franzon Dr. W. Rhett Davis Co-chair of Advisory Committee Co-chair of Advisory Committee DEDICATION Dedicated to my wife and my parents who instilled the importance of pursuing and applying knowledge. ii BIOGRAPHY Randy Widialaksono was born in Jakarta, Indonesia. He completed Bachelors in Electrical Engineering at Institut Teknologi Bandung, Indonesia, in 2009.

  • Reliable Design of Three-Dimensional Integrated Circuits

    Reliable Design of Three-Dimensional Integrated Circuits For obtaining the academic degree of Doctor of Engineering Department of Informatics Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany Approved Dissertation by Master of Science Shengcheng Wang From Tianjin, China Date of Oral Examination: 04.05.2018 Supervisor: Prof. Dr. Mehdi Baradaran Tahoori, Karlsruhe Institute of Technology Co-supervisor: Prof. Dr. Said Hamdioui, Delft University of Technology ii Shengcheng Wang Haid-und-Neu Str. 62 76131 Karlsruhe Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbstständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel voll- ständig angegeben haben und dass ich die Stellen der Arbeit - einschließlich Tabellen, Karten und Abbildungen - die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. Karlsruhe, Mai 2018 ——————————— Shengcheng Wang iii This page would be intentionally left blank. Abstract Beginning with the invention of the first Integrated Circuit (IC) by Kilby and Noyce in 1959, performance growth inIC is realized primarily by geometrical scaling, which has resulted in a steady doubling of device density from one technology node to another. This observation was famously known as “Moore’s law”. However, the performance en- hancement due to traditional technology scaling has begun to slow down and present diminishing returns due to a number of imminent show-stoppers, including fundamen- tal physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a mismatch between transistors and interconnects regarding size, speed and power.
  • Measurement and Analysis of Variability in CMOS Circuits

    Measurement and Analysis of Variability in CMOS Circuits

    Measurement and Analysis of Variability in CMOS circuits Liang Teck Pang Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2008-108 http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-108.html August 29, 2008 Copyright 2008, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement I wish to acknowledge the contributions of the students, faculty and sponsors of the Berkeley Wireless Research Center, the National Science Foundation Infrastructure Grant No. 0403427, wafer fabrication donation of STMicroelectronics, and the support of the Center for Circuit & System Solutions (C2S2) Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. Measurement and Analysis of Variability in CMOS circuits by Liang Teck Pang Diplˆome D’Ing´enieur (Ecole Centrale de Paris, France) 1997 Master of Philosophy (University of Cambridge, United Kingdom) 1997 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Sciences in the GRADUATE