Phd Dissertation
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Timing Analysis of Integrated Circuits Under Process Variations
UNIVERSIDADE TECNICA´ DE LISBOA INSTITUTO SUPERIOR TECNICO´ Timing Analysis of Integrated Circuits Under Process Variations Lu´ısJorge Br´asMonteiro Guerra e Silva (Mestre) Disserta¸c~aopara obten¸c~aodo Grau de Doutor em Engenharia Inform´aticae de Computadores Orientador: Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira J´uri Presidente: Reitor da Universidade T´ecnicade Lisboa Vogais: Doutor Jo~aoPaulo Marques da Silva Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira Doutor Jo~aoManuel Paiva Cardoso Doutor Jos´eCarlos Alves Pereira Monteiro Doutor Joel Reuben Phillips Doutor Nuno Filipe Valentim Roma Maio de 2009 Abstract As feature sizes in integrated circuit technology decrease into the nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Traditional, nominal case analysis and verification methodologies are no longer able to ensure silicon success. This dissertation addresses this problem, by developing key contributions for a variation-aware timing analysis methodology, capable of accurately model and predict circuit performance for the latest integrated circuit technologies. The proposed approach builds on reliable and established timing analysis paradigms by introducing a variation-aware extension, that can easily be implemented in currently used design flows. This dissertation presents several key contributions. One is a methodology for generating parametric delay models, tailored to the specific needs of delay calculation for pre-characterized standard cells. Unlike previous approaches based on numerical approximations, the proposed method is essentially analytical, and therefore capable of producing more accurate and robust results, at a fraction of the computational cost. Another contribution is a methodology that enables the automated computation of the critical timing conditions (corners) of a digital integrated circuit, given variation-aware parametric delay models. -
Test and Characterization Methodologies for Advanced Technology Nodes Darayus Adil Patel
Test and characterization methodologies for advanced technology nodes Darayus Adil Patel To cite this version: Darayus Adil Patel. Test and characterization methodologies for advanced technology nodes. Elec- tronics. Université Montpellier, 2016. English. NNT : 2016MONTT285. tel-01808874 HAL Id: tel-01808874 https://tel.archives-ouvertes.fr/tel-01808874 Submitted on 6 Jun 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par Université de Montpellier Préparée au sein de l’école doctorale I2S Et de l’unité de recherche LIRMM Spécialité : SYAM Présentée par DARAYUS ADIL PATEL TEST AND CHARACTERIZATION METHODOLOGIES FOR ADVANCED TECHNOLOGY NODES Soutenue le 5 Juillet 2016 devant le jury composé de M. Daniel CHILLET Professeur, Université de Président du Jury / Rennes Rapporteur M. Salvador MIR Directeur de Recherche Rapporteur CNRS, TIMA Mme. Sylvie NAUDET Team Leader, Examinateur STMicroelectronics M. Alberto BOSIO MCF HDR, Université de Examinateur Montpellier M. Patrick GIRARD Directeur de Recherche Directeur de Thèse CNRS, LIRMM M. Arnaud -
Study of the Impact of Variations of Fabrication Process on Digital Circuits Tarun Chawla
Study of the impact of variations of fabrication process on digital circuits Tarun Chawla To cite this version: Tarun Chawla. Study of the impact of variations of fabrication process on digital circuits. Micro and nanotechnologies/Microelectronics. Télécom ParisTech, 2010. English. NNT : -. pastel-00537050 HAL Id: pastel-00537050 https://pastel.archives-ouvertes.fr/pastel-00537050 Submitted on 17 Nov 2010 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Thèse Présentée pour obtenir le grade de Docteur du Télécom ParisTech Spécialité: Électronique et Communications Tarun CHAWLA Titre: Etude de l’impact des variations du procédé de fabrication sur les circuits numériques Soutenue le 30 Septembre 2010 devant le jury composé de: Prof. Lirida NAVINER Président de Jury Dr. Marc BELLEVILLE Rapporteurs Dr. Nadine AZEMARD Rapporteurs Prof. Amara AMARA Directeur de thèse Prof. Andrei VLADIMIRESCU Co-directeur de thèse M. Sebastien MARCHAL Tuteur industriel - 2 - Abstract Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on inter- die variations that form the bulk of process variations. Much work has been done to study their effects and to make circuits more robust by improvements in technology or design. -
Reliable Design of Three-Dimensional Integrated Circuits
Reliable Design of Three-Dimensional Integrated Circuits For obtaining the academic degree of Doctor of Engineering Department of Informatics Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany Approved Dissertation by Master of Science Shengcheng Wang From Tianjin, China Date of Oral Examination: 04.05.2018 Supervisor: Prof. Dr. Mehdi Baradaran Tahoori, Karlsruhe Institute of Technology Co-supervisor: Prof. Dr. Said Hamdioui, Delft University of Technology ii Shengcheng Wang Haid-und-Neu Str. 62 76131 Karlsruhe Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbstständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel voll- ständig angegeben haben und dass ich die Stellen der Arbeit - einschließlich Tabellen, Karten und Abbildungen - die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. Karlsruhe, Mai 2018 ——————————— Shengcheng Wang iii This page would be intentionally left blank. Abstract Beginning with the invention of the first Integrated Circuit (IC) by Kilby and Noyce in 1959, performance growth inIC is realized primarily by geometrical scaling, which has resulted in a steady doubling of device density from one technology node to another. This observation was famously known as “Moore’s law”. However, the performance en- hancement due to traditional technology scaling has begun to slow down and present diminishing returns due to a number of imminent show-stoppers, including fundamen- tal physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a mismatch between transistors and interconnects regarding size, speed and power. -
Measurement and Analysis of Variability in CMOS Circuits
Measurement and Analysis of Variability in CMOS circuits Liang Teck Pang Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2008-108 http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-108.html August 29, 2008 Copyright 2008, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement I wish to acknowledge the contributions of the students, faculty and sponsors of the Berkeley Wireless Research Center, the National Science Foundation Infrastructure Grant No. 0403427, wafer fabrication donation of STMicroelectronics, and the support of the Center for Circuit & System Solutions (C2S2) Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. Measurement and Analysis of Variability in CMOS circuits by Liang Teck Pang Diplˆome D’Ing´enieur (Ecole Centrale de Paris, France) 1997 Master of Philosophy (University of Cambridge, United Kingdom) 1997 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Sciences in the GRADUATE