Timing Analysis of Integrated Circuits Under Process Variations
Total Page：16
File Type：pdf, Size：1020Kb
UNIVERSIDADE TECNICA´ DE LISBOA INSTITUTO SUPERIOR TECNICO´ Timing Analysis of Integrated Circuits Under Process Variations Lu´ısJorge Br´asMonteiro Guerra e Silva (Mestre) Disserta¸c~aopara obten¸c~aodo Grau de Doutor em Engenharia Inform´aticae de Computadores Orientador: Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira J´uri Presidente: Reitor da Universidade T´ecnicade Lisboa Vogais: Doutor Jo~aoPaulo Marques da Silva Doutor Lu´ısMiguel Teixeira d'Avila´ Pinto da Silveira Doutor Jo~aoManuel Paiva Cardoso Doutor Jos´eCarlos Alves Pereira Monteiro Doutor Joel Reuben Phillips Doutor Nuno Filipe Valentim Roma Maio de 2009 Abstract As feature sizes in integrated circuit technology decrease into the nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Traditional, nominal case analysis and verification methodologies are no longer able to ensure silicon success. This dissertation addresses this problem, by developing key contributions for a variation-aware timing analysis methodology, capable of accurately model and predict circuit performance for the latest integrated circuit technologies. The proposed approach builds on reliable and established timing analysis paradigms by introducing a variation-aware extension, that can easily be implemented in currently used design flows. This dissertation presents several key contributions. One is a methodology for generating parametric delay models, tailored to the specific needs of delay calculation for pre-characterized standard cells. Unlike previous approaches based on numerical approximations, the proposed method is essentially analytical, and therefore capable of producing more accurate and robust results, at a fraction of the computational cost. Another contribution is a methodology that enables the automated computation of the critical timing conditions (corners) of a digital integrated circuit, given variation-aware parametric delay models. This constitutes an automated replacement for a task that has been mostly performed manually, relying on the knowledge of designers and process engineers. Keywords timing analysis, delay modeling, process parameter variations, corner analysis, critical timing corners i ii Resumo A` medida que a tecnologia dos circuitos integrados atinge escalas nanom´etricas,o impacto de varia¸c~oesnos par^ametrosde processo no desempenho dos circuitos torna-se extremamente relevante. As metodologias tradicionais de an´alisee verifica¸c~ao,considerando valores nomi- nais, j´an~aogarantem o sucesso na fabrica¸c~ao.Esta disserta¸c~aotrata este problema, desenvol- vendo contribui¸c~oeschave para uma metodologia de an´alisetemporal considerando varia¸c~oes, capaz de modelar e prev^ercom precis~aoo desempenho nas tecnologias recentes de circuitos integrados. A abordagem proposta assenta em paradigmas de an´alisetemporal estabeleci- dos, atrav´esda introdu¸c~aode extens~oescapazes de tratar varia¸c~oes,que podem facilmente ser implementadas nos fluxos de projecto actualmente utilizados. Esta disserta¸c~aoapre- senta v´ariascontribui¸c~oeschave. Uma delas ´euma metodologia para gera¸c~aode modelos de atraso param´etricos,adaptados `asnecessidades espec´ıficas de c´alculode atrasos para c´elulas pr´e-caracterizadas. Contrariamente a abordagens baseadas em aproxima¸c~oesnum´ericas,o m´etodo proposto ´eessencialmente anal´ıtico,e portanto capaz de produzir resultados mais precisos numa frac¸c~aodo custo computacional. Outra contribui¸c~ao´euma metodologia que permite determinar automaticamente as condi¸c~oestemporais cr´ıticasde um circuito integrado digital, dados modelos param´etricosde atraso. Trata-se da automatiza¸c~aode uma tarefa nor- malmente realizada manualmente, recorrendo `aexperi^encia dos projectistas e engenheiros de processo. Palavras-Chave an´alisetemporal, modela¸c~aode atrasos, varia¸c~oesnos par^ametrosde processo, an´alisede condi¸c~oeslimite, condi¸c~oestemporais cr´ıticas iii iv Acknowledgments First, I would like to thank Miguel, my adviser, for his friendship, wisdom and persistence in supervising a nasty student like me, that many times would procrastinate more than he should, not to mention other things that should be kept unmentioned. He has taught me many useful things, but particularly how to distinguish between bad and good research, and how to conduct my research career in a honest a productive manner. Second, I would like to thank Joel, my informal co-adviser, for his teachings, for his support during my stay in Berkeley, and for his patience in explaining me things that were trivial for him but difficult for me. Our weekly meetings were the source for many of the nice original contributions produced in this work. I would also like to thank Jo~aoMarques-Silva, a friend that has always been able to provide the right advice when necessary, and that helped convince me to stay in academia when I had my mind set to leave to the real world and make some real money. I do not regret that decision and I am glad I followed his advice. In^es,Sofia, Jos´eCarlos and Vasco, my long time friends and co-workers, also deserve my gratitude, for their constant support and encouragement. Additionally, I would also like to thank all the current and past members of the ALGOS Group, particularly Ana de Jesus, Arlindo Oliveira and Jos´eMonteiro. I am also grateful to all the members of the Cadence Research Laboratories in Berkeley, which contributed to the great work environment that I was lucky to find there, during my stay. A special thanks goes to Deidre Murphy and Andreas Kuehlmann. I keep the fondest memories of that period. v Finally, I would like to thank my parents, Maria and Jorge. Throughout my life I have always found on them a source of support and encouragement in pursuing my own options. They did that even at times that were particularly difficult for me as well as for them. I love them very much. This work was carried out at the Optimization and Simulation Algorithms Research Group (ALGOS) of INESC-ID Lisboa, in Lisboa, Portugal and at the Cadence Research Labora- tories, in Berkeley, California. This work was partially supported by Instituto Superior T´ecnico,by the Portuguese Foundation for Science and Technology under the project Pow- erPlan (POSC/EEA-ESE/61528/2004) and by Cadence Design Systems, Inc. vi Contents 1 Introduction 1 1.1 Motivation . 1 1.2 Timing Verification Methodology . 4 1.3 Objectives . 6 1.4 Original Work . 7 1.5 Dissertation Layout . 8 2 Background 9 2.1 Timing Simulation . 9 2.2 Static Timing Analysis . 11 2.3 Variability . 13 2.4 Statistical Approaches . 14 2.5 Corner-Based Approaches . 18 3 Parametric Delay Modeling 21 3.1 Delay and Slew Definitions . 22 3.2 Affine Functions . 25 3.2.1 Definition . 25 3.2.2 Extreme Values . 25 3.2.3 Sum . 26 3.2.4 Exact Max . 27 3.2.5 Simplification of the Max . 28 3.2.6 Bounding the Max . 29 vii 3.2.7 Bounding Error . 30 3.3 Mechanics of Delay Computation . 32 3.4 Interconnect and Cell Characterization . 34 3.5 Timing Graph . 36 4 Parametric Delay Calculation 39 4.1 Nominal Delay Calculation . 40 4.1.1 Cell Delay and Cell Loading . 40 4.1.2 Interconnect Delay . 46 4.2 Variation-Aware Methodology . 48 4.2.1 General Perturbation Formulation . 48 4.2.2 Specialization to Interconnect . 50 4.2.3 Interconnect Sensitivity Calculation . 52 4.3 Cell Delay Sensitivity Calculation . 52 4.4 Practical Implementation . 55 4.4.1 Interconnect Delay . 55 4.4.2 Effective Capacitance and Cell Delay . 56 4.4.3 Interconnect Delay Sensitivity . 58 4.4.4 Cell Delay Sensitivity . 59 4.5 Conclusions . 59 5 Worst-Timing Corner 61 5.1 Worst-Delay Corner . 63 5.2 Exhaustive Methods . 65 5.3 Static Pruning . 65 5.4 Dynamic Pruning . 67 5.4.1 Branch-and-Bound . 68 5.4.2 Path Space Search . 69 5.4.3 Parameter Space Search . 74 5.4.4 Decision Heuristics . 79 viii 5.5 Worst-Slack Corner . 79 5.5.1 Sequential Timing Constraints . 80 5.5.2 Setup Time and Late Mode . 81 5.5.3 Hold Time and Early Mode . 82 5.5.4 Multi-Cycle Paths . 83 5.5.5 Transparent Latches . 84 5.6 Conclusions . 84 6 Applications and Extensions 87 6.1 Augmented Timing Graph . 88 6.2 Worst-Slack Corner of a Single Register . 89 6.3 Worst-Slack Corner Over All Registers . 89 6.4 Minimum Clock Period . 90 6.5 Slack Violations . 90 6.6 Clock Tree Analysis . 91 6.6.1 Clock Latency . 92 6.6.2 Clock Skew . 93 6.7 k Worst-Delay Paths and Corners . 94 6.8 Conclusions . 98 7 Experimental Results 99 7.1 Benchmarks . 99 7.2 Parametric Delay Calculation . 100 7.3 Worst-Delay Corner . 104 7.4 Worst-Slack Corner . 105 7.5 k Worst-Delay Paths and Corners . 108 8 Conclusions and Future Work 111 8.1 Delay Computation . 111 8.2 Timing Analysis . 112 8.3 Future Work . 112 ix x List of Figures 1-1 Simplified timing verification flow. 4 2-1 Example timing graph and sum/max operations. 11 2-2 Upper bound computation example. 19 3-1 Reference voltages for delay and slew calculation. 22 3-2 Corners of x, for p =3................................ 26 3-3 Maximum of affine functions and of piecewise-affine functions, for p = 1. 27 3-4 Redundant affine functions in the max, for p = 1. 28 3-5 Tightest single plane upper bound of a convex piecewise-affine function, for p =1. ........................................ 30 3-6 Maximum/minimum error between two convex piecewise-affine functions, for p =1. ........................................ 31 3-7 Typical partition of a digital circuit topology for delay computation. 33 3-8 Most relevant parasitic effects considered in interconnect extraction. 34 3-9 Illustration of the original circuit and the corresponding timing graph. 36 3-10 Illustration of the elements of a timing graph.