Memory Hierarchy

Virtual Memory, Address Translation

Slides contents from:

Hennessy & Patterson, 5ed. Appendix B and Chapter 2. David Wentzlaff, ELE 475 – Computer Architecture. MJT, High Performance Computing, NPTEL.

Process/Program Address Space

Byte Address 0 CODE ● Compiler assumes a . linear address space DATA . – Byte 0 to Byte 232-1 . HEAP ● Virtual Address space

● The entire process data structure is may not be present in MM at all times.

STACK 232-1

M

M

A

Paged Virtual Memory A

Page Number 0 I

N

I

N

M

M

Virtual Address Space E

Virtual Address Space E Byte M

M

O

O

0 Page Number 13 R

Virtual Page R

Y Number 0 Y . Virtual Page . Number 1 Page Number 1

H

. H

A

Physical A

Physical R

R

Address Space D Address Space D

. Page Number 2

D

D

I

S

I

S

K . . K . . .

Virtual Page Page Number N-1 2 32-1 Number N-1 The Memory Hierarchy

PhysicalPhysical Virtual Addresses Addresses memory VirtualVirtual AddressesAddresses Main memory

Cache Registers

Words Lines (transferred Pages explicitly (transferred via load/store) automatically (transferred upon cache miss) automatically upon page fault)

VirtualVirtual AddressesAddresses Address Translation Table

Physical Page Numbers Virtual Address VPN 0 PPN 0 VPN PO VPN 1 . . PPN

. PPN PO . Physical Address VPN N-1

Paged Virtual Memory

● 48 bit Virtual Addresses, 40 bit Physical Addresses. Page size = 16KB. How many entries in a process's Page Translation Table? What is the size of the Page Translation Table?

Virtual Memory

Address Translation Table

MAINMAIN MEMORY MEMORY HARDHARD DISK DISK Physical Page Numbers Disk Addresses V Virtual Address VPN 0 VPN PO VPN 1

PPN Disk Address

PPN PO

Physical Address VPN N

Implementation of Address Translation

● Process always uses virtual addresses

● Memory Management Unit (MMU): part of CPU; hardware that does address translation – Caches recently used translations in a Translation Lookaside Buffer (Page Table Cache) ● The page tables are stored in OS's virtual address space

● The page tables are (at best) present in the MM – One main memory reference per address translation! ● To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory

Virtual Memory – Page Faults

● Situation where virtual address generated by processor is not available in main memory

● Detected on attempt to translate address – Page Table entry is invalid ● Must be `handled’ by operating system – Identify slot in main memory to be used – Get page contents from disk – Update page table entry ● Data can then be provided to the processor

Caches and Address Translation

PhysicallyPhysically Addressed Addressed Cache Cache

Virtual Physical Address Address CPU MMU Cache

Virtual Cache Physical Address Miss Address Main CPU Cache MMU Memory

VirtuallyVirtually Addressed Addressed Cache Cache

Which is less preferable?

● Physical addressed cache – Hit time higher (cache access after translation) ● Virtual addressed cache – Data/instruction of different processes with same virtual address in cache at the same time ...

● Flush cache on context switch, or ● Include Process id as part of each cache directory entry ● Synonyms – Virtual addresses that translate to same physical address – More than one copy of a block in cache ...

Synonyms (Aliases)

VA-T1 VA-T2 P1 P2 t1 t2

Shared L2

● L2 uses virtual addresses ● T1 and T2 share data from page X X

22 copies copies of of one one physical physical

pagepage in in the the cache! cache! Overlapped Operation

MMU

Virtual Tag check Address using PA

CPU Cache Indexing using VA

VirtuallyVirtually Indexed Indexed Physically Physically Tagged Tagged Cache Cache (VIPT) (VIPT)

OtherOther options: options: PIPT, PIPT, VIVT VIVT

Direct mapped, 32 KB, 32B block, Recall – Cache Access 32b main memory address

3232 b b address address Tag is not needed until the cache line TagTag IndexIndex (15b) (15b) 3Offset3Offset22 has been read

WW 1 1 32B32BWW 2 2Block Block...... 7 7 WW 8 8

To WW 1 1 WW 2 2 ...... 7 7 WW 8 8 Processor =? . . .

No Yes Cache Miss Cache Hit 64 b VM address VM Example Virtual Page No. (50) Page Offset (14)

(43) (7) TLB Tag TLB Index Index (8) Offset (6)

(26) Cache Block PhysicalPhysical Address Address (Tag) (Tag) Cache Block

=? =? L1 Hit/Miss TLB Hit/ Page Fault Physical Address (40)

To L2 Tag Index Offset

L2L2 Cache Cache Block Block Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address =? (Physically tagged) Fast Translation

● Address translation is on the critical path

● Paging – 2 memory accesses! – Address Translation Table + Data ● Translation Lookaside Buffer (TLB): Part of MMU that caches address translations

Translation Lookaside Buffer

● Cache of page table mappings

● 32 – 4096 entries long – SA, FA, or DM ● Dirty flag – use during page write back

● Ref – used for LRU

VPN PPN Valid Ref Dirty Access (tag) (data) Rights

Size of a Page

● Page is the unit of Memory Management

● Too large vs. Too small.

● Page Offset field need not be translated

● What if the Page Offset field was 12 bits? (Page size = 4KB)