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Superlattice-Source Nanowire FET with Steep Mot Es Superlattice-Source Nanowire FET with Steep MOt Es Subthreshold Characteristics MASSACHUSETTS ENSTTU OF TECHNOLOGY JUL Xmn Zhao 012013 B.S. Physics Peking University (2010) .... Submitted to the Department of Materials Science and Engineering in Partial Fulfillment of the Requirements for the Degree of Master of Science in Materials Science and Engineering at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY September 2012 C2012 Massachusetts Institute of Technology All Rights Reserved. A u th or ............................................... ......... ........................................................ Department of Materials Science and Engineering August 30, 2012 C ertified by ............................................................................................................................ Jesn's A. del Alamo Professor of Electrical Engineering Thesis Supervisor A n d b y ................................................................................. ............................................... Silvija Grade'ak Associate Professor of Materials Science and Engineering Thesis Reader Accepted by ....................................... ....................... Gerbrand Ceder Chair, Department Committee on Graduate Students 2 Superlattice-Source Nanowire FET with Steep Subthreshold Characteristics by Xin Zhao Submitted to the Department of Materials Science and Engineering on August 30, 2012 in Partial Fulfillment of the Requirements for the Degree of Master of Science in Materials Science and Engineering Abstract The non-scalable room temperature 60 mV/dec subthreshold swing of a conventional MOSFET is a fundamental limit to the continuation of transistor power scaling. In order to further reduce transistor power consumption and transistor footprint, new subthreshold transport mechanisms other than thermionic emission over an energy barrier are required. In this thesis, we devote our efforts towards the analysis and demonstration of a superlattice- source nanowire FET which can potentially beat the 60 mV/dec limit. This key to this device concept is to engineer the density of states of electrons at the source via a superlattice. We have calculated the band structure of a superlattice using a self-consistent quantum-mechanical simulation environment. In particular, the effect of transversal confinement on the band structure of a superlattice that occurs in a nanowire has been studied. We show that in order to obtain single-subband conduction, semiconductor nanowires with sub-10 nm diameter have to be fabricated. An analytical expression of the subthreshold swing including the effect of band edges has been derived and good agreement with simulations was achieved. A process flow to fabricate III-V nanowire MOSFETs has been designed. We have developed several key aspects of this process and have demonstrated the capability of fabricating smooth high-aspect ratio sub-10 nm semiconductor pillars in the InGaAs/InAlAs system lattice matched to InP. Thesis Supervisor: Jesn's A. del Alamo Title: Professor of Electrical Engineering 3 4 Acknowledgments First and foremost, I would like to express my deepest gratitude to my thesis advisor, Prof. Jesn's A. del Alamo for offering me this great opportunity to work on this exciting project. His dedication to excellence, strong physical sense of device physics and brilliant vision of this research field have constantly inspired and motivated me. Besides the scientific knowledge and technical skills I have learned from him, I benefit a lot from his elegant yet strict way of conducting research. He is a role model for successful researchers. I am very grateful for this excellent supervision and persistent help. I also want to thank Prof. Dimitri Antoniadis for his sharp, smart comments and suggestions during the group meetings. I have greatly benefited from his expertise and thinking each time I interact with him. This thesis would have not been possible without support from my colleagues and friends. I would like to sincerely thank Jianqiang Lin, Ling Xia and Winston Chem, for getting me started with III-V processing, simulation and measurements. I also want to say thank you to Luke Guo and Tao Yu. Discussions with them really spark new ideas and thoughts. Many thanks to del Alamo group members: Donghyun Jin, Alex Guo, Shireen Warnock, Jungwoo Joh, Tae-woo Kim and Usha Gogheni. I also appreciate the help from Fitzgerald group students Adam Jandl, Ryan Iutzi and Palacios group student Bin Lu, Han Wang and Omar Saadat. I shouldn't forget other folks on the 6 th floor too. I am also indebted to students and professors affiliated with the Center for Energy Electronics Sciences. Especially, I would like to thank Sapan Agarwal for insightful discussions on problems in TFETs. I have also benefited a lot from Amit Lakhani's advice on processing. This research was sponsored by the Center for Energy Efficient Electronics Sciences, which receives supportfrom the National Science Foundation. 5 6 Contents L ist o f F ig u re s ............................................................................................................................................... 9 L ist o f T ab le s .............................................................................................................................................. 1 3 Chapter 1I Introduction ................................................................................................................................ 15 1.1 The Need for Low Power Electronics................................................................................... 15 1.2 The Limit of Current Transistors ......................................................................................... 16 1.3 Superlattice-Source Nanowire FETs with Steep Subthreshold Characteristics .................... 18 1.4 T h esis O u tlin e ........................................................................................................................... 19 Chapter 2 Device Concept of Superlattice-Source Nanowire FETs ........................................................ 21 2 .1 In tro du ctio n ............................................................................................................................... 2 1 2.2 Operation M echanism of Superlattice-Source Nanowire FETs ............................................. 21 2.2.1 Physics of the Subthreshold Current in M OSFETs...................................................... 21 2.2.2 The Concept of Engineering the DOS at the Source...................................................... 22 2.2.3 Superlattice as Energy Filter ......................................................................................... 24 2.3 Quantum Mechanical Simulations of the Band Structures of Nanowire Superlattice .......... 27 2.3.1 Nextnano Simulation of the Band Structure of Superlattice ........................................ 27 2.3.2 The Effect of Transversal Confinement on the Band Structure of Superlattice............. 29 2.4 Device Design Issues ................................................................................................................ 32 2.4.1 Possible Device Architectures ....................................................................................... 32 2.4.2 Number of Periods of Superlattices .............................................................................. 34 2.4.3 Superlattice Doping........................................................................................................... 37 7 2.4.4 M aterial System ................................................................................................................ 39 2.4.5 Non-idealities in the Subthreshold Regime................................................................... 42 2 .5 S u mm ary ................................................................................................................................... 4 3 Chapter 3 Technology for SLS nanowire FETs..................................................................................... 45 3.1 Introduction............................................................................................................................... 45 3.2 Overall Process Design............................................................................................................. 45 3.3 Process Technology .................................................................................................................. 47 3.3.1 Electron Beam Lithography......................................................................................... 47 3.3.2 Reactive Ion Etching..................................................................................................... 55 3.3.3 Digital Etch ....................................................................................................................... 63 3.3.4 Planarization ..................................................................................................................... 66 3 .4 S u m m ary ................................................................................................................................... 6 8 Chapter 4 Conclusions and Suggestions ................................................................................................ 69 4 .1 S u m m ary ................................................................................................................................... 6 9 4.2 Suggestions ..............................................................................................................................
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