Xeon Phi™ Processor X200 Product Family Datasheet, Volume One: Electrical
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Intel® Xeon Phi™ Processor x200 Product Family Datasheet, Volume One: Electrical Volume 1 of 2 Rev. 002 January 2017 Order No.: 334710-002 YouLegal Lines andmay Disclaimers not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. 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Intel® Xeon Phi™ Processor x200 Product Family Datasheet, Volume One: Electrical Volume 1 of 2 January 2017 2 Order No.: 334710-002 Contents Contents 1.0 Overview ...................................................................................................................7 1.1 Introduction......................................................................................................7 1.2 Related Documents............................................................................................8 1.3 Terminology .....................................................................................................9 1.4 Processor Feature Overview .............................................................................. 11 1.4.1 Tile and Core Feature Overview ............................................................ 11 1.5 Interface Feature Overview............................................................................... 12 1.5.1 System Memory.................................................................................. 12 1.5.2 PCI Express*...................................................................................... 12 1.5.3 Direct Media Interface Gen 2 (DMI2) ..................................................... 12 1.5.4 Platform Environment Control Interface (PECI) ....................................... 12 1.6 Socket and Package Summary .......................................................................... 12 1.7 Statement of Volatility (SOV) ............................................................................ 13 1.8 State of Data .................................................................................................. 13 2.0 Processor Land Listings ........................................................................................... 14 3.0 Processor Signal Descriptions................................................................................ 108 3.1 Processor Signal Buffer Types ......................................................................... 108 3.2 Internal Pull Ups/Pull Downs ........................................................................... 109 3.3 System Memory Interface............................................................................... 109 3.4 PCI Express Based Interface Signals ................................................................ 111 3.5 DMI2 Signals ................................................................................................ 112 3.6 Fabric Component Signals............................................................................... 112 3.7 PECI Signal................................................................................................... 113 3.8 System Reference Clock Signals ...................................................................... 114 3.9 JTAG and TAP Signals .................................................................................... 114 3.10 Serial VID Interface (SVID) Signals.................................................................. 115 3.11 Processor Asynchronous Sideband and Miscellaneous Signals .............................. 115 3.12 Processor Power and Ground Supplies .............................................................. 118 3.13 Reserved or Unused Pins ................................................................................ 120 4.0 Processor Power Supply Specifications.................................................................. 121 4.1 Serial Voltage Identification (SVID).................................................................. 121 4.1.1 SVID Commands .............................................................................. 121 4.1.2 SVID Voltage Rail Addressing ............................................................. 124 4.2 Power Limit Specifications............................................................................... 125 4.3 Power Supply Specifications............................................................................ 126 4.3.1 Voltage Specifications........................................................................ 126 4.3.2 Current Specifications........................................................................ 127 4.3.3 Static and Transient Loadlines ............................................................ 129 4.3.4 VCC Overshoot Specifications ............................................................. 132 4.4 Decoupling Guidelines .................................................................................... 133 4.5 Processor Power Sequencing ........................................................................... 133 4.6 Absolute Maximum and Minimum Ratings ......................................................... 135 5.0 Processor Signal Specifications ............................................................................. 137 5.1 DC Specifications........................................................................................... 137 5.1.1 DDR4 Signal DC Specifications............................................................ 137 5.1.2 SMBus DC Specifications.................................................................... 139 5.1.3 PCI Express DC Specifications............................................................. 139 5.1.4 DMI2 DC Specifications...................................................................... 139 5.1.5 Fabric Component Signals DC Specifications ......................................... 139 Intel® Xeon Phi™ Processor x200 Product Family Datasheet, Volume One: Electrical January 2017 Volume 1 of 2 Order No.: 334710-002 3 Contents 5.1.6 PECI DC Specifications ....................................................................... 141 5.1.7 System Reference Clock (BCLK) DC Specifications ................................. 142 5.1.8 JTAG and TAP Signals DC Specifications ............................................... 144 5.1.9 Serial VID Interface (SVID) DC Specifications........................................ 144 5.1.10 Processor Asynchronous Sideband DC Specifications .............................. 145 5.2 Signal Quality................................................................................................ 145 5.2.1 PCIe and DMI Signal Quality Specifications ........................................... 146 5.2.2 Overshoot/Undershoot Tolerance......................................................... 146 Figures 1-1 Intel® Xeon Phi™ Processor x200 Product Family Platform .........................................11 4-1 VR Power-State Transitions ................................................................................. 123 4-2 VCCP Static and Transient Tolerance Loadlines ........................................................ 130 4-3 VCCCLR Static and Transient Tolerance Loadlines ..................................................... 131 4-4 VCC Overshoot Example Waveform....................................................................... 132 4-5 Processor Voltage Sequence Timing Requirements - Power Up.................................. 134 4-6 Processor Voltage Sequence Timing Requirements - Power Down.............................. 135 5-1 CD_HFI_REFCLK Single-Ended Measurement Points for Median Crosspoint and Swing.. 140 5-2 PECI Input Device Hysteresis ............................................................................... 141 5-3 BCLK Differential Measurement Point for Ringback .................................................. 142 5-4 BCLK Single-Ended Crosspoint Specification........................................................... 143 5-5 BCLK Single-Ended Measurement Points for Absolute Crosspoint and Swing ............... 143 5-6 BCLK Single-Ended Measurement Points for Delta Crosspoint ................................... 143 5-7 Maximum Acceptable Overshoot/Undershoot Waveform........................................... 147 Tables 1-1 Processor