DOCSLIB.ORG

Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array electronics Article Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array Ian Grout 1,* and Lenore Mullin 2 1 Department of Electronic and Computer Engineering, University of Limerick, V94 T9PX Limerick, Ireland 2 Department of Computer Science, College of Engineering and Applied Sciences, University at Albany, State University of New York, Albany, NY 12222, USA; [email protected] * Correspondence: [email protected]; Tel.: +353-61-202-298 Received: 18 October 2018; Accepted: 8 November 2018; Published: 13 November 2018 Abstract: In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems. Keywords: Inner and outer product; tensor; FPGA; hardware 1. Introduction Embedded system applications are today demanding greater levels of digital signal processing (DSP) capabilities whilst providing low-power operation and with reduced processing times for complex signal processing operations found typically in machine learning [1] systems. For example, facial recognition [2] for safety and security conscious applications is a noticeable every day example, and many smartphones today incorporate facial recognition software applications for phone and software app access. Embedded environmental sensors, as an alternative application, can input multiple sensor data values over a period of time and, using DSP algorithms, can analyze the data and autonomously provide specific outcomes. Although these applications may differ, within the system hardware and software, these are simply algorithms accessing data values that need to be processed. The system does not need to know the context of the data it is obtaining. Data processing is rather concerned with how effectively and efficiently it can obtain, store, and process the data before transmitting a result to an external system. This requires not only an understanding of regular access patterns in important internet of things (IoT) algorithms, but also an ability to identify similarities Electronics 2018, 7, 320; doi:10.3390/electronics7110320 www.mdpi.com/journal/electronics Electronics 2018, 7, 320 2 of 24 amongst such algorithms. Research presented herein shows how scalar operations, such as plus and times, extended to all scalar operations, can be defined in a single circuit that implements all scalar Electronics 2018, 7, x FOR PEER REVIEW 2 of 24 operations extended to: (i) n-dimensional tensors (arrays); (ii) the inner product, (matrix multiply is a 2-dsimilaritiesinstance) amongst and the such outer algorithms. product, Research both on prnesented-dimensional herein shows arrays how (the scalar Kronecker operations, Product such is a 2-d instance);as plus and and times, (iii) compressions,extended to all scalar or reductions, operations, over can be arbitrary defined in dimensions. a single circuit However, that implements even more relationshipsall scalar exist. operatio Onens of extended the most to: compute (i) n-dimensional intensive tensors operations (arrays); in IoT(ii) isthe the inner Khatri-Rao, product, (matrix or parallel Kroneckermultiply Product, is a 2-d which, instance) from and the the perspective outer product, of this both research, on n-dimensional is an outer arrays product (the projectedKronecker to a matrix,Product enabling is a contiguous2-d instance);reads and (iii) and compressions, writes of data or reductions, values at machineover arbitrary speeds. dimensions. However, even more relationships exist. One of the most compute intensive operations in IoT is the Khatri-Rao, In terms of the data, when this data is obtained, it must be stored in the available memory. or parallel Kronecker Product, which, from the perspective of this research, is an outer product This will be a mixture of cache memory within a suitably selected software programmed processor projected to a matrix, enabling contiguous reads and writes of data values at machine speeds. µ µ (microcontrollerIn terms ( ofC), the microprocessor data, when this ( dataP), oris digitalobtained signal, it must processor be stored (DSP)), in the available locally connected memory. This external volatilewill or be non-volatile a mixture of memory cache memory connected within to the a suitably processor, selected memory software connected programmed to the processorprocessor via local area(microcontroller network (LAN), (µC), or microprocessor via some form (µP), of Cloud or digital based signal memory processor (Cloud (DSP)), storage). locally Identifying connected what to useexternal and when volatile is the or challenge. non-volatile Ideally, memory the conne datacted would to the be storedprocessor, in specificmemory memory connected locations to the so that theprocessor processor via local can optimallyarea network access (LAN), the or stored via some input form data, of Cloud process based the memory data, and (Cloud store storage). the result (the outputIdentifying data) what again to in use memory and when in suitable is the challenge. new locations, Ideally, orthe overwriting data would existingbe stored data in specific in already utilizedmemory memory. locations Knowing so that and the anticipating processor can cache optimally memory access misses, the stored for input example, data, enableprocess a the design data, that and store the result (the output data) again in memory in suitable new locations, or overwriting minimizes overhead(s), such as signal delays, energy, heat, and power. existing data in already utilized memory. Knowing and anticipating cache memory misses, for In many embedded systems implemented today, the software programmed processor is the example, enable a design that minimizes overhead(s), such as signal delays, energy, heat, and power. commonlyIn used many programmable embedded systems device implemented to perform today, complex the software tasks and programmed interface to processor input and is outputthe systems.commonly The software used programmable approach has device been to developed perform comp overlex the tasks last and number interface ofyears to input and and is supportedoutput throughsystems. tools (usuallyThe software available approach via anhas integrated been developed development over the last environment number of years (IDE)) and and is programmingsupported languagethrough constructs, tools (usually providing available the necessary via an syntax integrated and semanticsdevelopment to perform environment the required (IDE)) complexand tasks.programming However, increasingly, language constructs, the programmable providing the logic necessary device syntax (PLD) and [3] semantics that allows to forperform a hardware the configurationrequired tocomplex be downloaded tasks. However, into increasingly, the PLD interms the programmable of digital logic logic operations device (PLD) is utilized.[3] that allows Figure 1 showsfor the a targethardware device configuration choices available to be downloaded to the designer into the today. PLD in Alternatively, terms of digital an logic application operations specific is utilized. Figure 1 shows the target device choices available to the designer today. Alternatively, an integrated circuit (ASIC) solution whereby a custom integrated circuit is designed and fabricated could application specific integrated circuit (ASIC) solution whereby a custom integrated circuit is designed be considered. Design goals include not only semantic, denotational, and functional descriptions of a and fabricated could be considered. Design goals include not only semantic, denotational, and circuit,functional but also andescriptions operational of a description circuit, but also (how anto operational build the description circuit and (how associated to build memory the circuit relative and to accessassociated patterns ofmemory important relative algorithms). to access patterns of important algorithms). Algorithm to be implemented Software programmed Hardware configured ASIC processor programmable logic device Microcontroller (µC) Field programmable gate array (FPGA) Microprocessor (µP) Complex programmable logic device (CPLD) Digital signal processor (DSP) Simple programmable logic device (SPLD) FigureFigure
Load more

Recommended publications
  • Fault Tolerance and Re-Training Analysis on Neural Networks
    FAULT TOLERANCE AND RE-TRAINING ANALYSIS ON NEURAL NETWORKS by ABHINAV KURIAN GEORGE B.Tech Electronics and Communication Engineering Amrita Vishwa Vidhyapeetham, Kerala, 2012 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science, Computer Engineering, College of Engineering and Applied Science, University of Cincinnati, Ohio 2019 Thesis Committee: Chair: Wen-Ben Jone, Ph.D. Member: Carla Purdy, Ph.D. Member: Ranganadha Vemuri, Ph.D. ABSTRACT In the current age of big data, artificial intelligence and machine learning technologies have gained much popularity. Due to the increasing demand for such applications, neural networks are being targeted toward hardware solutions. Owing to the shrinking feature size, number of physical defects are on the rise. These growing number of defects are preventing designers from realizing the full potential of the on-chip design. The challenge now is not only to find solutions that balance high-performance and energy-efficiency but also, to achieve fault-tolerance of a computational model. Neural computing, due to its inherent fault tolerant capabilities, can provide promising solutions to this issue. The primary focus of this thesis is to gain deeper understanding of fault tolerance in neural network hardware. As a part of this work, we present a comprehensive analysis of fault tolerance by exploring effects of faults on popular neural models: multi-layer perceptron model and convolution neural network. We built the models based on conventional 64-bit floating point representation. In addition to this, we also explore the recent 8-bit integer quantized representation. A fault injector model is designed to inject stuck-at faults at random locations in the network.
    [Show full text]
  • In-Datacenter Performance Analysis of a Tensor Processing Unit
    In-Datacenter Performance Analysis of a Tensor Processing Unit Presented by Josh Fried Background: Machine Learning Neural Networks: ● Multi Layer Perceptrons ● Recurrent Neural Networks (mostly LSTMs) ● Convolutional Neural Networks Synapse - each edge, has a weight Neuron - each node, sums weights and uses non-linear activation function over sum Propagating inputs through a layer of the NN is a matrix multiplication followed by an activation Background: Machine Learning Two phases: ● Training (offline) ○ relaxed deadlines ○ large batches to amortize costs of loading weights from DRAM ○ well suited to GPUs ○ Usually uses floating points ● Inference (online) ○ strict deadlines: 7-10ms at Google for some workloads ■ limited possibility for batching because of deadlines ○ Facebook uses CPUs for inference (last class) ○ Can use lower precision integers (faster/smaller/more efficient) ML Workloads @ Google 90% of ML workload time at Google spent on MLPs and LSTMs, despite broader focus on CNNs RankBrain (search) Inception (image classification), Google Translate AlphaGo (and others) Background: Hardware Trends End of Moore’s Law & Dennard Scaling ● Moore - transistor density is doubling every two years ● Dennard - power stays proportional to chip area as transistors shrink Machine Learning causing a huge growth in demand for compute ● 2006: Excess CPU capacity in datacenters is enough ● 2013: Projected 3 minutes per-day per-user of speech recognition ○ will require doubling datacenter compute capacity! Google’s Answer: Custom ASIC Goal: Build a chip that improves cost-performance for NN inference What are the main costs? Capital Costs Operational Costs (power bill!) TPU (V1) Design Goals Short design-deployment cycle: ~15 months! Plugs in to PCIe slot on existing servers Accelerates matrix multiplication operations Uses 8-bit integer operations instead of floating point How does the TPU work? CISC instructions, issued by host.
    [Show full text]
  • Abstractions for Programming Graphics Processors in High-Level Programming Languages
    Abstracties voor het programmeren van grafische processoren in hoogniveau-programmeertalen Abstractions for Programming Graphics Processors in High-Level Programming Languages Tim Besard Promotor: prof. dr. ir. B. De Sutter Proefschrift ingediend tot het behalen van de graad van Doctor in de ingenieurswetenschappen: computerwetenschappen Vakgroep Elektronica en Informatiesystemen Voorzitter: prof. dr. ir. K. De Bosschere Faculteit Ingenieurswetenschappen en Architectuur Academiejaar 2018 - 2019 ISBN 978-94-6355-244-8 NUR 980 Wettelijk depot: D/2019/10.500/52 Examination Committee Prof. Filip De Turck, chair Department of Information Technology Faculty of Engineering and Architecture Ghent University Prof. Koen De Bosschere, secretary Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Bjorn De Sutter, supervisor Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Jutho Haegeman Department of Physics and Astronomy Faculty of Sciences Ghent University Prof. Jan Lemeire Department of Electronics and Informatics Faculty of Engineering Vrije Universiteit Brussel Prof. Christophe Dubach School of Informatics College of Science & Engineering The University of Edinburgh Prof. Alan Edelman Computer Science & Artificial Intelligence Laboratory Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology ii Dankwoord Ik wist eigenlijk niet waar ik aan begon, toen ik in 2012 in de cata- comben van het Technicum op gesprek ging over een doctoraat. Of ik al eens met LLVM gewerkt had. Ondertussen zijn we vele jaren verder, werk ik op een bureau waar er wel daglicht is, en is het eindpunt van deze studie zowaar in zicht. Dat mag natuurlijk wel, zo vertelt men mij, na 7 jaar.
    [Show full text]
  • P1360R0: Towards Machine Learning for C++: Study Group 19
    P1360R0: Towards Machine Learning for C++: Study Group 19 Date: 2018-11-26(Post-SAN mailing): 10 AM ET Project: ISO JTC1/SC22/WG21: Programming Language C++ Audience SG19, WG21 Authors : Michael Wong (Codeplay), Vincent Reverdy (University of Illinois at Urbana-Champaign, Paris Observatory), Robert Douglas (Epsilon), Emad Barsoum (Microsoft), Sarthak Pati (University of Pennsylvania) Peter Goldsborough (Facebook) Franke Seide (MS) Contributors Emails: [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] Reply to: [email protected] Introduction 2 Motivation 2 Scope 5 Meeting frequency and means 6 Outreach to ML/AI/Data Science community 7 Liaison with other groups 7 Future meetings 7 Conclusion 8 Acknowledgements 8 References 8 Introduction This paper proposes a WG21 SG for Machine Learning with the goal of: ● Making Machine Learning a first-class citizen in ISO C++ It is the collaboration of a number of key industry, academic, and research groups, through several connections in CPPCON BoF[reference], LLVM 2018 discussions, and C++ San Diego meeting. The intention is to support such an SG, and describe the scope of such an SG. This is in terms of potential work resulting in papers submitted for future C++ Standards, or collaboration with other SGs. We will also propose ongoing teleconferences, meeting frequency and locations, as well as outreach to ML data scientists, conferences, and liaison with other Machine Learning groups such as at Khronos, and ISO. As of the SAN meeting, this group has been officially created as SG19, and we will begin teleconferences immediately, after the US thanksgiving, and after NIPS.
    [Show full text]
  • AI Chips: What They Are and Why They Matter
    APRIL 2020 AI Chips: What They Are and Why They Matter An AI Chips Reference AUTHORS Saif M. Khan Alexander Mann Table of Contents Introduction and Summary 3 The Laws of Chip Innovation 7 Transistor Shrinkage: Moore’s Law 7 Efficiency and Speed Improvements 8 Increasing Transistor Density Unlocks Improved Designs for Efficiency and Speed 9 Transistor Design is Reaching Fundamental Size Limits 10 The Slowing of Moore’s Law and the Decline of General-Purpose Chips 10 The Economies of Scale of General-Purpose Chips 10 Costs are Increasing Faster than the Semiconductor Market 11 The Semiconductor Industry’s Growth Rate is Unlikely to Increase 14 Chip Improvements as Moore’s Law Slows 15 Transistor Improvements Continue, but are Slowing 16 Improved Transistor Density Enables Specialization 18 The AI Chip Zoo 19 AI Chip Types 20 AI Chip Benchmarks 22 The Value of State-of-the-Art AI Chips 23 The Efficiency of State-of-the-Art AI Chips Translates into Cost-Effectiveness 23 Compute-Intensive AI Algorithms are Bottlenecked by Chip Costs and Speed 26 U.S. and Chinese AI Chips and Implications for National Competitiveness 27 Appendix A: Basics of Semiconductors and Chips 31 Appendix B: How AI Chips Work 33 Parallel Computing 33 Low-Precision Computing 34 Memory Optimization 35 Domain-Specific Languages 36 Appendix C: AI Chip Benchmarking Studies 37 Appendix D: Chip Economics Model 39 Chip Transistor Density, Design Costs, and Energy Costs 40 Foundry, Assembly, Test and Packaging Costs 41 Acknowledgments 44 Center for Security and Emerging Technology | 2 Introduction and Summary Artificial intelligence will play an important role in national and international security in the years to come.
    [Show full text]
  • Shinjae Yoo Computational Science Initiative Outline
    Lightning Overview of Machine Learning Shinjae Yoo Computational Science Initiative Outline • Why is Machine Learning important? • Machine Learning Concepts • Big Data and Machine Learning • Potential Research Areas 2 Why is Machine Learning important? 3 ML Application to Physics 4 ML Application to Biology 5 Machine Learning Concepts 6 What is Machine Learning (ML) • One of Machine Learning definitions • “How can we build computer systems that automatically improve with experience, and what are the fundamental laws that govern all learning processes?” Tom Mitchell, 2006 • Statistics: What conclusions can be inferred from data • ML incorporates additionally • What architectures and algorithms can be used to effectively handle data • How multiple learning subtasks can be orchestrated in a larger system, and questions of computational tractability 7 Machine Learning Components Algorithm Machine Learning HW+SW Data 8 Brief History of Machine Learning Speech Web Deep Blue N-gram Hadoop ENIAC Perceptron Recognition Browser Chess based MT 0.1.0 K-Means KNN 1950 1960 1970 1980 1990 2000 2010 1ST Chess WWW Data Driven Softmargin Image HMM GPGPU Learning Prog. invented ML SVM Net 2010 2011 2012 2013 2014 2015 2016 NN won ImageNet NN outperform IBM Watson AlphaGo with large margin human on ImageNet 9 Supervised Learning Pipeline Training Labeling Preprocessing Validate Data Cleansing Feature Engineering Normalization Testing Preprocessing Predict 10 Unsupervised Learning Pipeline Preprocessing Data Cleansing Feature Engineering Normalization Predict 11 Types of Learning 12 Types of Learning • Generative Learning 13 Types of Learning • Discriminative Learning 14 Types of Learning • Active Learning • How to select training data? 15 Types of Learning • Multi-task Learning 16 Types of Learning • Transfer Learning 17 Types of Learning • Kernel Learning • Metric Learning 18 Types of Learning • Kernel Learning • Metric Learning 19 Types of Learning • Kernel Learning • Metric Learning • Dimensionality Reduction 20 Types of Learning • Feature Learning 21 • Lee, et al.
    [Show full text]
  • Podracer Architectures for Scalable Reinforcement Learning
    2021-4-14 Podracer architectures for scalable Reinforcement Learning Matteo Hessel*,1, Manuel Kroiss*,1, Aidan Clark1, Iurii Kemaev1, John Quan1, Thomas Keck1, Fabio Viola1 and Hado van Hasselt*,1 *Equal contributions, 1DeepMind Supporting state-of-the-art AI research requires balancing rapid prototyping, ease of use, and quick iter- ation, with the ability to deploy experiments at a scale traditionally associated with production systems. Deep learning frameworks such as TensorFlow, PyTorch and JAX allow users to transparently make use of accelerators, such as TPUs and GPUs, to offload the more computationally intensive parts of training and inference in modern deep learning systems. Popular training pipelines that use these frameworks for deep learning typically focus on (un-)supervised learning. How to best train reinforcement learning (RL) agents at scale is still an active research area. In this report we argue that TPUs are particularly well suited for training RL agents in a scalable, efficient and reproducible way. Specifically we describe two architectures designed to make the best use of the resources available on a TPU Pod (a special configuration in a Google data center that features multiple TPU devices connected to each other by extremely low latency communication channels). Introduction Reinforcement learning (RL) algorithms have been shown to be capable of performing well on challenging sequential decision problems, ranging from board games (Silver et al., 2016) to video games (Mnih et al., 2015) and continuous control (Lillicrap et al., 2016; Van Hasselt, 2012). Many of these advances were powered by the adoption of deep learning (Krizhevsky et al., 2012) in RL.
    [Show full text]
  • Patent Claim Generation by Fine-Tuning Openai GPT-2
    Patent Claim Generation by Fine-Tuning OpenAI GPT-2 Jieh-Sheng Lee and Jieh Hsiang Department of Computer Science and Information Engineering National Taiwan University {d04922013, jhsiang}@ntu.edu.tw Abstract (Bidirectional Encoder Representations from Transformers) [4] has become the best practice In this work, we focus on fine-tuning an for state-of-the-art results. GPT-2 is the successor OpenAI GPT-2 pre-trained model for to GPT. Although both GPT-2 and BERT are generating patent claims. GPT-2 has capable of text generation, Wang and Cho [5] demonstrated impressive efficacy of pre- trained language models on various tasks, found that GPT-2 generations are of better particularly coherent text generation. quality. In fact, GPT-2 is claimed to be so Patent claim language itself has rarely powerful that the risk of its malicious use is high. been explored in the past and poses a For this reason, OpenAI decided to keep its unique challenge. We are motivated to largest model (1.5B parameters) closed so that generate coherent patent claims there is more time to discuss its ramifications. automatically so that augmented inventing In this work, we generated patent claims by might be viable someday. In our fine-tuning the released 345M medium version implementation, we identified a unique [6]. Overall we are impressed by how coherent language structure in patent claims and and complicate the generated patent claims could leveraged its implicit human annotations. We investigated the fine-tuning process by be, although not all text are generated equally in probing the first 100 steps and observing terms of quality.
    [Show full text]
  • Automatic Full Compilation of Julia Programs and ML Models to Cloud
    AUTOMATIC FULL COMPILATION OF JULIA PROGRAMS AND ML MODELS TO CLOUD TPUS Keno Fischer 1 Elliot Saba 1 ABSTRACT Google’s Cloud TPUs are a promising new hardware architecture for machine learning workloads. They have powered many of Google’s milestone machine learning achievements in recent years. Google has now made TPUs available for general use on their cloud platform and as of very recently has opened them up further to allow use by non-TensorFlow frontends. We describe a method and implementation for offloading suitable sections of Julia programs to TPUs via this new API and the Google XLA compiler. Our method is able to completely fuse the forward pass of a VGG19 model expressed as a Julia program into a single TPU executable to be offloaded to the device. Our method composes well with existing compiler-based automatic differentiation techniques on Julia code, and we are thus able to also automatically obtain the VGG19 backwards pass and similarly offload it to the TPU. Targeting TPUs using our compiler, we are able to evaluate the VGG19 forward pass on a batch of 100 images in 0.23s which compares favorably to the 52.4s required for the original model on the CPU. Our implementation is less than 1000 lines of Julia, with no TPU specific changes made to the core Julia compiler or any other Julia packages. 1 INTRODUCTION accelerator available to the public via their cloud offering. Originally, the use of TPUs was restricted to applications One of the fundamental changes that has enabled the steady written using Google’s TensorFlow machine learning frame- progress of machine learning techniques over the past sev- work.
    [Show full text]
  • Interoperating Deep Learning Models with ONNX.Jl
    Interoperating Deep Learning models with ONNX.jl Ayush Shridhar1, Phil Tomson2, and Mike Innes3 1International Institute of Information Technology, Bhubaneswar, India 2Unaffiliated 3Julia Computing, Inc ABSTRACT network, with complete support for control flow, recursion, clo- sures and data structures. Implementing models in Flux.jl is as sim- Flux [17] is a machine learning framework, written using the nu- ple as writing regular Julia code. Implementing models is as simple merical computing language Julia[4]. The framework makes writ- as writing the formulae for those, and Zygote.jl will compute the ing layers as simple as writing mathematical formulae, and it’s ad- derivatives seamlessly. vanced AD, Zygote [11] , applies automatic differentiation (AD) to Flux.jl also provides support for other hardware options using ex- calculate derivatives and train the model. It makes heavy use of Ju- ternal packages such as CuArrays.jl and CLArrays.jl. CuArrays lia’s language and compiler features to carry out code analysis and is written completely in Julia, making implementing GPU kernels make optimisations. For example, Julia’s GPU compilation support very simple. Making a model run on GPU can be done in a hassle- [3] can be used to JIT-compile custom GPU kernels for model lay- free manner: It is as simple as calling a few functions to trans- ers [19]. Flux also supports a number of a hardware options, from fer data to GPU. Flux.jl also has support for running models on CPUs, GPUs and even TPUs via XLA.jl, that compiles Julia code Google’s Tensor Processing Unit (TPU). TPUs help in very fast to XLA: an advanced compiler for linear algebra that is capable of linear algebra computation.
    [Show full text]
  • Data Movement Is All You Need: a Case Study on Optimizing Transformers
    Data Movement Is All You Need: A Case Study on Optimizing Transformers Andrei Ivanov∗, Nikoli Dryden∗, Tal Ben-Nun, Shigang Li, Torsten Hoefler ETH Zürich [email protected] ∗ Equal contribution Abstract—Transformers have become widely used for language challenges such as artificial general intelligence [27]. Thus, modeling and sequence learning tasks, and are one of the most improving transformer performance has been in the focus of important machine learning workloads today. Training one is a numerous research and industrial groups. very compute-intensive task, often taking days or weeks, and significant attention has been given to optimizing transformers. Significant attention has been given to optimizing transform- Despite this, existing implementations do not efficiently utilize ers: local and fixed-window attention [28]–[32], more general GPUs. We find that data movement is the key bottleneck when structured sparsity [33], learned sparsity [34]–[36], and other training. Due to Amdahl’s Law and massive improvements in algorithmic techniques [19], [37] improve the performance of compute performance, training has now become memory-bound. transformers. Major hardware efforts, such as Tensor Cores Further, existing frameworks use suboptimal data layouts. Using these insights, we present a recipe for globally optimizing data and TPUs [38] have accelerated tensor operations like matrix- movement in transformers. We reduce data movement by up matrix multiplication (MMM), a core transformer operation. to 22.91% and overall achieve a 1.30× performance improve- Despite this, existing implementations do not efficiently ment over state-of-the-art frameworks when training BERT. utilize GPUs. Even optimized implementations such as Mega- Our approach is applicable more broadly to optimizing deep tron [18] report achieving only 30% of peak GPU flop/s.
    [Show full text]
  • Accelerators for Cyber-Physical Systems Sam Green, İhsan Çiçek and Çetin Kaya Koç University of California, Santa Barbara Introduction Capabilities Desired in CPS?
    Accelerators for Cyber-Physical Systems Sam Green, İhsan Çiçek and Çetin Kaya Koç University of California, Santa Barbara Introduction Capabilities desired in CPS? • Interact with physical world • Networked • Potentially low-power • Resistant to environment • Perform safety-critical tasks • Cryptographically secure • Autonomous • Inexpensive Benefits from Moore’s Law are over • Since about 1970, could safely assume the number of transistors/$ would exponentially increase every 2 years • What can be done today for $X will be doable in 2 years for $X/2 dollars • Accelerators (aka ASICs) existed during this time, but CPU/µcontroller/DSP-based approaches dominated • No longer the case… [http://www.economist.com/node/21693710/sites/all/modules/custom/ec_essay] Other methods to increase performance/$? • Approximate computing • Analog computing • Neuromorphic computing Approximate Computing • Selective approximation can bring disproportionate gains in efficiency • 5% accuracy loss gives • 50x less energy for k-means clustering • 26x less energy for neural network evaluation [S. Mittal. A Survey of Techniques for Approximate Computing. ACM Comput. Surv., vol. 48, no. 4, p. 62:1–62:33, Mar. 2016.] [https://upload.wikimedia.org/wikipedia/commons/b/b7/3-bit_resolution_analog_comparison.png] Analog Computing • Physical world is a computational device • E.g. Use KVL and KCL to approximate activation function for analog neuron • 4X speedup, 20X less energy, 2.4% higher error across benchmarks vs. approximate digital neuron [St. Amant et al. General-purpose Code Acceleration with Limited-precision Analog Computation. ISCA, 2014] Neuromorphic Computing • Non-von Neumann, neuro-bio inspired architectures • Community sees biological circuits as the ultimate in efficiency [https://upload.wikimedia.org/wikipedia/commons/4/4a/Action_potential.svg] Accelerators for Deep Learning Inference [A.
    [Show full text]