This Thesis Has Been Submitted in Fulfilment of the Requirements for a Postgraduate Degree (E.G

This thesis has been submitted in fulfilment of the requirements for a postgraduate degree (e.g. PhD, MPhil, DClinPsychol) at the University of Edinburgh. Please note the following terms and conditions of use: This work is protected by copyright and other intellectual property rights, which are retained by the thesis author, unless otherwise stated. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the author. The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the author. When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given. Towards the Development of Flexible, Reliable, Reconfigurable, and High- Performance Imaging Systems by Jalal Khalifat A thesis submitted in partial fulfilment of the requirements for the degree of DOCTOR OF PHILOSOPHY The University of Edinburgh May 2016 Declaration I hereby declare that this thesis was composed and originated entirely by myself except where explicitly stated in the text, and that this work has not been submitted for any other degree or professional qualifications. Jalal Khalifat May 2016 Edinburgh, U.K. I Acknowledgements All praises are due to Allah, the most gracious, the most merciful, after three and a half years of continuous work, this work comes to end and it is the moment that I have to thank all the people who have supported me throughout my PhD study and who have contributed to the completion of this thesis. First and foremost, I would like to express my sincere appreciation to my supervisor, Professor Tughrul Arslan, who added a lot to my research work through his superb supervision and illimitable knowledge. I deeply appreciate his kindness, patience, and continuous guidance extended to me throughout these years. In addition, I would like also to express my gratitude to my second supervisor, Dr. Alistor Hamilton, who helped me a lot in different stages of my research work. Special thanks to my financial sponsor, the University of Bahrain (UoB) for providing me with the opportunity to conduct my research work in the UK. I would like to thank all my colleagues at the UoB for their support and encouragements during my study. I would like to thank all members of the System Level Integration Group (SLIG) at the University of Edinburgh. In particular, my senior colleague Dr. Ali Ebrahim, who supported me so much during my study through his suggestions and guidance. I also acknowledge the contributions of Mr. Adewale Adetomi and Mr. Godwin Enemali who have been closely involved in my research work. Last but not least, I would like to express my deepest gratitude and best wishes to all members of my family. Special thanks go to my wonderful wife and my parents for their love and support. II Lay Summary of Thesis The strength of Field-Programmable Gate Arrays (FPGAs) lies in the reconfigurable hardware resources that allow implementation of different hardware functions on the FPGA plane by loading various binary files. Modern FPGAs consist of a large number of these resources that allow building System on Chips (SoCs). Unlike software solutions, FPGA functions are composed using Hardware Description Language (HDL) and then synthesised to produce the function’s binary file. This method is more complex than the software designing flow, but with the evolution of FPGAs, automated high-level synthesis tools have been developed to accelerate and simplify this process. In addition to the flexibility of FPGA devices, hardware functions on FPGAs can be executed in parallel to achieve a higher performance compared to the sequential software solutions. A Dynamic Partial Reconfiguration (DPR) feature enhances the flexibility further by allowing the functionality of part of the system to be changed at run-time while the other parts are functioning normally. For the aforementioned reasons, FPGAs are becoming a suitable platform for many applications in different fields. This thesis presents the use of FPGAs in image processing and discusses the advantages of FPGAs over current solutions such as Application Specific Integrated Circuits (ASICs) and Graphics Processing Units (GPUs). These advantages of FPGAs have been obtained by implementing a number of imaging algorithms for different stages of the Image Processing Pipeline (IPP) on FPGA devices. Moreover, it presents a novel reliable imaging system that uses DPR to swap tasks over time. This practice increases system performance, reliability, and flexibility and reduces the area utilisation and power consumption. The system can be easily integrated into reconfigurable operating systems due to its unbounded flexibility resulting from the use of FPGA III Abstract Current FPGAs can implement large systems because of the high density of reconfigurable logic resources in a single chip. FPGAs are comprehensive devices that combine flexibility and high performance in the same platform compared to other platform such as General-Purpose Processors (GPPs) and Application Specific Integrated Circuits (ASICs). The flexibility of modern FPGAs is further enhanced by introducing Dynamic Partial Reconfiguration (DPR) feature, which allows for changing the functionality of part of the system while other parts are functioning. FPGAs became an important platform for digital image processing applications because of the aforementioned features. They can fulfil the need of efficient and flexible platforms that execute imaging tasks efficiently as well as the reliably with low power, high performance and high flexibility. The use of FPGAs as accelerators for image processing outperforms most of the current solutions. Current FPGA solutions can to load part of the imaging application that needs high computational power on dedicated reconfigurable hardware accelerators while other parts are working on the traditional solution to increase the system performance. Moreover, the use of the DPR feature enhances the flexibility of image processing further by swapping accelerators in and out at run-time. The use of fault mitigation techniques in FPGAs enables imaging applications to operate in harsh environments following the fact that FPGAs are sensitive to radiation and extreme conditions. The aim of this thesis is to present a platform for efficient implementations of imaging tasks. The research uses FPGAs as the key component of this platform and uses the concept of DPR to increase the performance, flexibility, to reduce the power dissipation and to expand the cycle of possible imaging applications. In this context, it proposes the use of FPGAs to accelerate the Image Processing Pipeline (IPP) stages, the core part of most imaging devices. The thesis has a number of novel concepts. The first novel concept is the use of FPGA hardware environment and DPR feature to increase the parallelism and achieve high flexibility. The concept also increases the performance and reduces the power consumption and area utilisation. Based on this concept, the following implementations are presented in this thesis: An IV implementation of Adams Hamilton Demosaicing algorithm for camera colour interpolation, which exploits the FPGA parallelism to outperform other equivalents. In addition, an implementation of Automatic White Balance (AWB), another IPP stage that employs DPR feature to prove the mentioned novelty aspects. Another novel concept in this thesis is presented in chapter 6, which uses DPR feature to develop a novel flexible imaging system that requires less logic and can be implemented in small FPGAs. The system can be employed as a template for any imaging application with no limitation. Moreover, discussed in this thesis is a novel reliable version of the imaging system that adopts novel techniques including scrubbing, Built-In Self Test (BIST), and Triple Modular Redundancy (TMR) to detect and correct errors using the Internal Configuration Access Port (ICAP) primitive. These techniques exploit the datapath-based nature of the implemented imaging system to improve the system's overall reliability. The thesis presents a proposal for integrating the imaging system with the Robust Reliable Reconfigurable Real-Time Heterogeneous Operating System (R4THOS) to get the best out of the system. The proposal shows the suitability of the proposed DPR imaging system to be used as part of the core system of autonomous cars because of its unbounded flexibility. These novel works are presented in a number of publications as shown in section 1.3 later in this thesis. V Contents Declaration ......................................................................................................................... I Acknowledgements ........................................................................................................... II Lay Summary of Thesis .................................................................................................. III Abstract ........................................................................................................................... IV Contents........................................................................................................................... VI List of Figures ................................................................................................................. IX List of Tables

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