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Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory

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Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory TIIIIIHINII US005630096A United States Patent [191 [11] Patent Number: 5 ,630,096 Zuravletf et al. [45] Date of Patent: May 13,1997 [54] CONTROLLER FOR A SYNCHRONOUS FOREIGN PATENT DOCUMENTS DRAM THAT MAXIMIZES THROUGHPUT BY ALLOWING MEMORY REQUESTS AND 549139 6/1993 European Pat. Off. COMMANDS TO BE ISSUED OUT OF OTHER PUBLICATIONS ORDER IBM Technical Disclosure Bulletin, vol. 33, No. 6A, pp. [75] Inventors: William K. Zuravlelf, Mountajnview; 269-272, Nov. 1990. Timothy RObillSOll, BOuld6I Creek, IBM Technical Disclosure Bulletin, vol. 33, No. 6A, pp. both of Calif. 265-266, Nov. 1990. _ _ _ _ IBM Technical Disclosure Bulletin, vol. 31, No. 9, pp. [73] Assrgnee: Microunity Systems Engineering, Inc., 351454, Feb 1989 Sunnyvale’ Cahf' IBM Technical Disclosure Bulletin, vol. 33, No. 3A, pp. 441-442, Aug. 1990. [21] APPI' NO‘: 43737 5 Micron Semiconductor, Inc., Spec Sheet. MT48LC2M8S1 [22] Filed: May 10’ 1995 S, cover page and pp. 33 and 37, 1993. [5 1] Int. Cl.6 . .. G06F 13/00 Primary Examiner—Frank J . Asta [52] US. Cl. ................................... .. 395/481; 364/DIG. 1; A?vmey, Agent vrFim1—B11n1S,D0ane,Sw¢cker & Mathis 365/233; 395/432; 395/477; 395/478; 395/485; 395/494; 395/496 [57] ABSTRACT [58] Field of Search ........................... .. 365/233; 395/432, A controller for a synchronous DRAM is provided for 395/477, 478, 481, 485, 494, 496 maximizing throughput of memory requests to the synchro . nous DRAM. The controller maintains the spacing between ~ [56] References cued the cormnands to conform with the speci?cations for the 5TB CU} [E synchronous DRAMs while preventing gaps from occurring U'S' P NT DO NTS in the data slots to the synchronous DRAM. Furthermore, 4,685,088 8/1987 Iannucci . the controller allows memory requests and commands to be 4,691,302 9/ 1937 Mawmusch - issued out of order so that the throughput may be maximized 4,734,833 3/1933 Tide" 3 by overlapping required operations which do not speci?cally 4740924 4/192: 361m ' involve data transfer. To achieve this maximized throughput, Hgsdtemon ‘ memory requests are tagged for indicating a sending order. , , ee et a1. 5,179,667 V1993 Iyer_ Thereafter, the memory requests may be arbrtrated when 5,193,193 3,1993 Iyer _ con?icting memory requests are queued and this arbltratlon 5 253 ,214 10/1993 Henmm . process is then decoded for simultaneously updating sched 5,253,357 10/1993 Allen eta1.. uling constraints. The memory requests may be further 5,276,856 1/1994 Norsworthy et all . quali?ed based on the scheduling constraints and a com 5278967 1/ 1994 . mand stack of memory request is then developed for modi 5233377 2/ 1994 G?smlelet 31- - fying update queues. The controller also functions by receiv gtliiai‘tlfe't a1 ing a controller clock signal and generating an SDRAM 5,311,483 5/1994 Takasugi . ' ' clock s1gnal by d1v1d1ng tl'ns controller clock signal. 5,381,536 l/l995 Phelps et al. ......................... .. 395/375 5,513,148 4/1996 Zagar .................................... .. 365/233 20 Claims, 6 Drawing Sheets -100 f 10 f 2Q 40 / 50 K BANK DATA PATH 111%’ DRIVER sum BANK DATA PATH RETURN DATA OUT <,.._‘—..__ DATA PATH <3: CONTROLLER CONTROL CLOCK BLOCK US. Patent May 13, 1997 Sheet 1 0f 6 5,630,096 [10 [2Q 40 [so [100 BANK DATA PATH | ( m 5%» ' DRIVER SDRAM DATABANK PATH I / OUT : REIURNDATA PATHDATA <:" coumoum , CONTROL CLOCK —" BLOCK W 210 W 220 K 23 O / 240 COMMAND BANK BANK C-SWE CONSTANT — UPDAIE QUAUHCATION ARBITRAHON UPDATE UNIT UNAT UNIT UNAT A '. I '. L -_ ' _ -_ B—STATE(n) ' -_ FIG. 2 US. Patent May 13, 1997 Sheet 2 0f 6 5,630,096 310 314 f 300 16MB sumf f 300 6 4“ 8 SigAM D 3 2/ 16/ A CLK D 3/2 161/ D A‘ m PROCESSORMICRO- ‘X; PROCESSORMICRO- f 316 16 64MB sum 0 A cu< FIG. 3(a) FIG. 3(b) / 300 [- 320 / 300 /- 322 D -E/-X 16MB SDRAM D ?f-X 64MB SDRAM mm / ‘ D A CU‘ MICRO- H“ A CLK PROCESSOR A/@ __—J PROCESSOR A/C _—f cu< CLK FIG. 3(0) FIG. 3(d) U.S. Patent May 13, 1997 Sheet 3 of 6 5,630,096 300 / 300 f 52, 8 0 n mm MICRO PROCESSOR A/C PROCESSOR A/C cu< CLK FIG. 3(e) FIG. / 300 300 354 [-350 16 16MB SDRAM X D a MiCRO D A (1K MICRO PROCESSOR A/c PROCESSOR A/(j 352\Ll CLK 16MB SDRAM D A (1K FIG. 3(9) FIG. 3(h) U.S. Patent May 13, 1997 Sheet 6 0f 6 5,630,096 Q=Zz .rJ.\L.J A_ __z= 53222231g@880;8888 ImILJNNENNNx.x.H..x.E28 xx;OiXXX \Q..w15.c= xxxxxxxxxmfWm@20880 E;2:2;lgzigfoi2%:955Eggnazfi2102 xgwiEggragga:08“82x3::8:g#22iE as;22;@023205222xxx; E8;XXX c_|_ XXXXXXXXZxxxxxxxxixxxxxxé hikigégkg::_C 1.1.? o Emma 25m V620$358 8E581 mam5%.156E200 60.6235w $2,528 GE2.5&8 SE65Sm21:51156528 E56mam21351$50528 mam£55m156E200 82: 5,630,096 1 2 CONTROLLER FOR A SYNCHRONOUS and meeting JEDEC standards for synchronous DRAMs so DRAM THAT MAXIMIZES THROUGHPUT that versatile synchronous DRAMs may be provided and BY ALLOWING MEMORY REQUESTS AND applied in many design applications. COMMANDS TO BE ISSUED OUT OF ORDER SUMMARY BACKGROUND An object of the present invention is to control a syn chronous DRAM by interfacing an external device, such as The present invention is directed to a controller for a microprocessor. for reading and writing to the synchronous maximizing throughput of memory requests from an exter DRAM. nal device to a synchronous DRAM. More particularly, the Another object of the present invention is to provide a present invention is directed to a controller which prioritizes controller for a synchronous DRAM which can buffer and multiple memory requests from the external device and process multiple memory requests so that greater issues reordered memory requests to the synchronous throughput, or an equivalent throughput at less latency, can DRAM so that the throughput from the external device to the be achieved by the synchronous DRAM. synchronous DRAM is maximized. A still further object of the present invention is to provide Synchronous DRAMs are relatively new devices which a controller for is suing and completing requests out of order are similar to conventional DRAMs but the synchronous with respect to the received or issued order so that the DRAMs have some important differences. The architecture throughput of the synchronous DRAM is improved by of the synchronous DRAMs is similar to conventional 20 overlapping required operations, which do not speci?cally DRAMs. For instance, the synchronous DRAMs have mul involve data transfer, with operations involving data trans tiplexed address pins, control pins such as RAS, CAS, CS. fer. WE. and bidirectional data pins. Also, the synchronous DRAMs activate a page as does the conventional DRAM A still further object of the present invention is to provide a controller for a synchronous DRAM that schedules and then subsequent accesses to that page occur faster. Accordingly, a precharge operation must be performed 25 memory request commands as closely together as possible before another page is activated. within the timing constraints of the synchronous DRAM so that the throughput of the memory requests is maximized. One di?erence between synchronous DRAMs and con ventional DRAMs is that all input signals are required to These objects of the present invention are ful?lled by have a set-up and hold time with respect to the clock input providing a controller for a synchronous DRAM comprising in synchronous DRAMs. The hold time is referenced to the a sorting unit for receiving memory requests and sorting said same clock input. The outputs also have a clock to output memory requests based on their addresses and a throughput delay referenced to the same clock. Thereby, the synchro maximizing unit for processing said memory requests to the nous characteristics are provided. Furthermore, the synchro synchronous DRAM in response to scheduling which maxi mizes the use of data slots by the synchronous DRAM. The nous DRAMs are pipelined which means that the latency is 35 generally greater than one clock cycle. As a result, second controller is able to prioritize and issue multiple requests to and third synchronous DRAM commands can be sent before the synchronous DRAM in a different order than was the data from the original write request arrives at the received or issued such that the out of order memory synchronous DRAM. Also, the synchronous DRAMs have requests improve the throughput to the synchronous DRAM. two internal banks of data paths which generally correspond In particular, the controller issues memory requests as to separate memory arrays sharing I/O pins. The two internal closely together as possible while maintaining the timing banks of memory paths are a JEDEC standard for synchro constraints of the synchronous DRAM based on its speci nous DRAMs. An example of a known synchronous DRAM ?cations. is a 2 MEG><8 SDRAM from Micron Semiconductor, Inc._. The objects of the present invention are also ful?lled by providing a method for controlling a synchronous DRAM model no. MT48LC2M8SS1S. 45 In the synchronous DRAMs, almost all I/O timings are comprising the steps of receiving memory requests and referenced to the input clock. Minimum parameters such as sorting said memory requests based on their addresses, and CAS latency remain but are transformed from electrical maximizing throughput of said memory requests to the timing requirements to logical requirements so that they are synchronous DRAM so that use of data slots by the syn chronous DRAM is maximized.
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