Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory
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This Thesis Has Been Submitted in Fulfilment of the Requirements for a Postgraduate Degree (E.G
This thesis has been submitted in fulfilment of the requirements for a postgraduate degree (e.g. PhD, MPhil, DClinPsychol) at the University of Edinburgh. Please note the following terms and conditions of use: This work is protected by copyright and other intellectual property rights, which are retained by the thesis author, unless otherwise stated. A copy can be downloaded for personal non-commercial research or study, without prior permission or charge. This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the author. The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the author. When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given. Towards the Development of Flexible, Reliable, Reconfigurable, and High- Performance Imaging Systems by Jalal Khalifat A thesis submitted in partial fulfilment of the requirements for the degree of DOCTOR OF PHILOSOPHY The University of Edinburgh May 2016 Declaration I hereby declare that this thesis was composed and originated entirely by myself except where explicitly stated in the text, and that this work has not been submitted for any other degree or professional qualifications. Jalal Khalifat May 2016 Edinburgh, U.K. I Acknowledgements All praises are due to Allah, the most gracious, the most merciful, after three and a half years of continuous work, this work comes to end and it is the moment that I have to thank all the people who have supported me throughout my PhD study and who have contributed to the completion of this thesis. -
Performance of Image and Video Processing with General-Purpose
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions y Parthasarathy Ranganathan , Sarita Adve , and Norman P. Jouppi Electrical and Computer Engineering y Western Research Laboratory Rice University Compaq Computer Corporation g fparthas,sarita @rice.edu [email protected] Abstract Media processing refers to the computing required for the creation, encoding/decoding, processing, display, and com- This paper aims to provide a quantitative understanding munication of digital multimedia information such as im- of the performance of image and video processing applica- ages, audio, video, and graphics. The last few years tions on general-purpose processors, without and with me- have seen significant advances in this area, but the true dia ISA extensions. We use detailed simulation of 12 bench- promise of media processing will be seen only when ap- marks to study the effectiveness of current architectural fea- plications such as collaborative teleconferencing, distance tures and identify future challenges for these workloads. learning, and high-quality media-rich content channels ap- Our results show that conventional techniques in current pear in ubiquitously available commodity systems. Fur- processors to enhance instruction-level parallelism (ILP) ther out, advanced human-computer interfaces, telepres- provide a factor of 2.3X to 4.2X performance improve- ence, and immersive and interactive virtual environments ment. The Sun VIS media ISA extensions provide an ad- hold even greater promise. ditional 1.1X to 4.2X performance improvement. The ILP One obstacle in achieving this promise is the high com- features and media ISA extensions significantly reduce the putational demands imposed by these applications. -
On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP Soc Cradle Architecture
On Implementation of MPEG-2 like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture Ganesh Yadav1, R. K. Singh2, and Vipin Chaudhary1 1 Dept. of Computer Science, Wayne State University fganesh@cs.,[email protected] 2 Cradle Technologies, [email protected] Abstract. In this paper we highlight the suitability of MDSP 3 architec- ture to exploit the data, algorithmic, and pipeline parallelism o®ered by video processing algorithms like the MPEG-2 for real-time performance. Most existing implementations extract either data or pipeline parallelism along with Instruction Level Parallelism (ILP) in their implementations. We discuss the design of MP@ML decoding system on shared memory MDSP platform and give insights on building larger systems like HDTV. We also highlight how the processor scalability is exploited. Software implementation of video decompression algorithms provides flexibility, but at the cost of being CPU intensive. Hardware implementations have a large development cycle and current VLIW dsp architectures are less flexible. MDSP platform o®ered us the flexibilty to design a system which could scale from four MSPs (Media Stream Processor is a logical clus- ter of one RISC and two DSP processors) to eight MSPs and build a single-chip solution including the IO interfaces for video/audio output. The system has been tested on CRA2003 board. Speci¯c contributions include the multiple VLD algorithm and other heuristic approaches like early-termination IDCT for fast video decoding. 1 Introduction Software programmable SoC architectures eliminate the need for designing ded- icated hardware accelerators for each standard we want to work with. With the rapid evolution of standards like MPEG-2, MPEG-4, H.264, etc. -
XOS Advanced Media Processor
XOS Advanced Media Processor The XOS Advanced Media Processor is a high performance live media processor for broadcast and streaming applications. Key Business Benefits Application versatility The XOS Advanced Media Processor is the latest generation of Harmonic software-based video appliances. XOS can be used for either broadcast or streaming applications, and is adapted to multiple deployment environments. Classic infrastructures are supported with SDI, ASI, and satellite RF interfaces. Full-IP architectures are also supported: XOS handles MPEG compressed formats, as well as the latest SMPTE ST 2022-6 and SMPTE ST 2110 standards. GRAPHICS TRANSCODE STATMUX MULTIPLEXING ENCRYPT SDI TS over IP PACKAGING SAT RECEPTION OTT INGEST DECRYPT 2022-6 BROADCAST 2110 DVB-S2X XOS HLS STREAMING XOS Advanced Media Processor Inputs and Functionality XOS is packed with features to address any kind of video processing application. In addition to its market-leading compression engine, XOS integrates a broad range of audio codecs, including Dolby AC-4, an advanced video pre-processing engine, a broadcast multiplexer with statmux support, and a state-of-the-art packager for streaming applications. From decoding to encoding, from HDR processing to audio loudness management, Harmonic has you covered. Improved cost of ownership XOS Advanced Media Processor’s unparalleled function integration and performance dramatically reduce the number of appliances required for a given application, significantly improving your cost of ownership. As a software solution, XOS -
A Bibliography of Publications in IEEE Micro
A Bibliography of Publications in IEEE Micro Nelson H. F. Beebe University of Utah Department of Mathematics, 110 LCB 155 S 1400 E RM 233 Salt Lake City, UT 84112-0090 USA Tel: +1 801 581 5254 FAX: +1 801 581 4148 E-mail: [email protected], [email protected], [email protected] (Internet) WWW URL: http://www.math.utah.edu/~beebe/ 16 September 2021 Version 2.108 Title word cross-reference -Core [MAT+18]. -Cubes [YW94]. -D [ASX19, BWMS19, DDG+19, Joh19c, PZB+19, ZSS+19]. -nm [ABG+16, KBN16, TKI+14]. #1 [Kah93i]. 0.18-Micron [HBd+99]. 0.9-micron + [Ano02d]. 000-fps [KII09]. 000-Processor $1 [Ano17-58, Ano17-59]. 12 [MAT 18]. 16 + + [ABG+16]. 2 [DTH+95]. 21=2 [Ste00a]. 28 [BSP 17]. 024-Core [JJK 11]. [KBN16]. 3 [ASX19, Alt14e, Ano96o, + AOYS95, BWMS19, CMAS11, DDG+19, 1 [Ano98s, BH15, Bre10, PFC 02a, Ste02a, + + Ste14a]. 1-GHz [Ano98s]. 1-terabits DFG 13, Joh19c, LXB07, LX10, MKT 13, + MAS+07, PMM15, PZB+19, SYW+14, [MIM 97]. 10 [Loc03]. 10-Gigabit SCSR93, VPV12, WLF+08, ZSS+19]. 60 [Gad07, HcF04]. 100 [TKI+14]. < [BMM15]. > [BMM15]. 2 [Kir84a, Pat84, PSW91, YSMH91, ZACM14]. [WHCK18]. 3 [KBW95]. II [BAH+05]. ∆ 100-Mops [PSW91]. 1000 [ES84]. 11- + [Lyl04]. 11/780 [Abr83]. 115 [JBF94]. [MKG 20]. k [Eng00j]. µ + [AT93, Dia95c, TS95]. N [YW94]. x 11FO4 [ASD 05]. 12 [And82a]. [DTB01, Dur96, SS05]. 12-DSP [Dur96]. 1284 [Dia94b]. 1284-1994 [Dia94b]. 13 * [CCD+82]. [KW02]. 1394 [SB00]. 1394-1955 [Dia96d]. 1 2 14 [WD03]. 15 [FD04]. 15-Billion-Dollar [KR19a]. -
The Bus Interface for 32-Bit Microprocessors That
Freescale Semiconductor, Inc. MPC60XBUSRM 1/2004 Rev. 0.1 . c n I , r o t c u d n o c i PowerPC™ Microprocessor m e S Family: e l a c The Bus Interface for 32-Bit s e Microprocessors e r F For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. Overview 1 Signal Descriptions 2 Memory Access Protocol 3 Memory Coherency 4 . System Status Signals 5 . c n I Additional Bus Configurations 6 , r o t Direct-Store Interface 7 c u d n System Considerations 8 o c i m Processor Summary A e S e Processor Clocking Overview B l a c s Processor Upgrade Suggestions C e e r F L2 Considerations for the PowerPC 604 Processor D Coherency Action Tables E Glossary of Terms and Abbreviations GLO Index IND For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 Overview 2 Signal Descriptions 3 Memory Access Protocol 4 Memory Coherency . 5 System Status Signals . c n I 6 Additional Bus Configurations , r o t 7 Direct-Store Interface c u d n 8 System Considerations o c i m A Processor Summary e S e B Processor Clocking Overview l a c s C Processor Upgrade Suggestions e e r F D L2 Considerations for the PowerPC 604 Processor E Coherency Action Tables GLO Glossary of Terms and Abbreviations IND Index For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. -
Architectural Trade-Offs in a Latency Tolerant Gallium Arsenide Microprocessor
Architectural Trade-offs in a Latency Tolerant Gallium Arsenide Microprocessor by Michael D. Upton A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in The University of Michigan 1996 Doctoral Committee: Associate Professor Richard B. Brown, CoChairperson Professor Trevor N. Mudge, CoChairperson Associate Professor Myron Campbell Professor Edward S. Davidson Professor Yale N. Patt © Michael D. Upton 1996 All Rights Reserved DEDICATION To Kelly, Without whose support this work may not have been started, would not have been enjoyed, and could not have been completed. Thank you for your continual support and encouragement. ii ACKNOWLEDGEMENTS Many people, both at Michigan and elsewhere, were instrumental in the completion of this work. I would like to thank my co-chairs, Richard Brown and Trevor Mudge, first for attracting me to Michigan, and then for allowing our group the freedom to explore many different ideas in architecture and circuit design. Their guidance and motivation combined to make this a truly memorable experience. I am also grateful to each of my other dissertation committee members: Ed Davidson, Yale Patt, and Myron Campbell. The support and encouragement of the other faculty on the project, Karem Sakallah and Ron Lomax, is also gratefully acknowledged. My friends and former colleagues Mark Rossman, Steve Sugiyama, Ray Farbarik, Tom Rossman and Kendall Russell were always willing to lend their assistance. Richard Oettel continually reminded me of the valuable support of friends and family, and the importance of having fun in your work. Our corporate sponsors: Cascade Design Automation, Chronologic, Cadence, and Metasoft, provided software and support that made this work possible. -
A Media Enhanced Vector Architecture for Embedded Memory Systems
A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis Report No. UCB/CSD-99-1059 July 1999 Computer Science Division (EECS) University of California Berkeley, California 94720 A Media-Enhanced Vector Architecture for Embedded Memory Systems by Christoforos Kozyrakis Research Project Submitted to the Department of Electrical Engineering and Computer Sciences, Uni- versity of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II. Approval for the Report and Comprehensive Examination: Committee: Professor David A. Patterson Research Advisor (Date) ******* Professor Katherine Yelick Second Reader (Date) A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis M.S. Report Abstract Next generation portable devices will require processors with both low energy consump- tion and high performance for media functions. At the same time, modern CMOS technology creates the need for highly scalable VLSI architectures. Conventional processor architec- tures fail to meet these requirements. This paper presents the architecture of Vector IRAM (VIRAM), a processor that combines vector processing with embedded DRAM technology. Vector processing achieves high multimedia performance with simple hardware, while em- bedded DRAM provides high memory bandwidth at low energy consumption. VIRAM pro- vides ¯exible support for media data types, short vectors, and DSP features. The vector pipeline is enhanced to hide DRAM latency without using caches. The peak performance is 3.2 GFLOPS (single precision) and maximum memory bandwidth is 25.6 GBytes/s. With a target power consumption of 2 Watts for the vector pipeline and the memory system, VIRAM supports 1.6 GFLOPS/Watt. For a set of representative media kernels, VIRAM sustains on average 88% of its peak performance, outperforming conventional SIMD media extensions and DSP processors by factors of 4.5 to 17. -
Ilore: Discovering a Lineage of Microprocessors
iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Science & Applications Kirk Cameron, Chair Godmar Back Margaret Ellis May 24, 2021 Blacksburg, Virginia Keywords: Computer history, systems, computer architecture, microprocessors Copyright 2021, Samuel Lewis Furman iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman (ABSTRACT) Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org. iLORE: Discovering a Lineage of Microprocessors Samuel Lewis Furman (GENERAL AUDIENCE ABSTRACT) Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. -
Scalable Vector Media-Processors for Embedded Systems
Scalable Vector Media-processors for Embedded Systems Christoforos Kozyrakis Report No. UCB/CSD-02-1183 May 2002 Computer Science Division (EECS) University of California Berkeley, California 94720 Scalable Vector Media-processors for Embedded Systems by Christoforos Kozyrakis Grad. (University of Crete, Greece) 1996 M.S. (University of California at Berkeley) 1999 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the GRADUATE DIVISION of the UNIVERSITY of CALIFORNIA at BERKELEY Committee in charge: Professor David A. Patterson, Chair Professor Katherine Yelick Professor John Chuang Spring 2002 Scalable Vector Media-processors for Embedded Systems Copyright Spring 2002 by Christoforos Kozyrakis Abstract Scalable Vector Media-processors for Embedded Systems by Christoforos Kozyrakis Doctor of Philosophy in Computer Science University of California at Berkeley Professor David A. Patterson, Chair Over the past twenty years, processor designers have concentrated on superscalar and VLIW architectures that exploit the instruction-level parallelism (ILP) available in engineering applications for workstation systems. Recently, however, the focus in computing has shifted from engineering to multimedia applications and from workstations to embedded systems. In this new computing environment, the performance, energy consumption, and development cost of ILP processors renders them ineffective despite their theoretical generality. This thesis focuses on the development of efficient architectures for embedded multimedia systems. We argue that it is possible to design processors that deliver high performance, have low energy consumption, and are simple to implement. The basis for the argument is the ability of vector architectures to exploit efficiently the data-level parallelism in multimedia applications. -
Mpact R Media Processor
Mpact TM R Media Processor by Chromatic Research Preliminary Data Sheet Features Description The new Mpact R media processor with a higher clock An Mpact media processor is a high performance copro- rate and an integrated display RAMDAC, continues to cessor for Windows 95 based PCs. Loaded with Mpact keep the Mpact product line the complete PC multimedia mediaware modules, the media processor adds or en- solution with the highest performance, integration and hances support for all seven multimedia functions: flexibility, and the lowest total cost. • Video: MPEG-1 & -2 decode, MPEG-1 encode • Complete • 2D graphics: Full VGA, SVGA support, acceleration of video • A total hardware solution for all multimedia ports: display playback and GUI through GDI and DirectDraw monitor, audio, telephone, video and joystick/MIDI • 3D graphics: Full 3D acceleration through Direct3D • Integrated software for all major multimedia functions on an • Digital Audio: Industry-standard Sound Card compatibility, x86 Windows 95 PC 3D Audio (SRS) and 3D positional audio effects • High Performance (DirectSound), Dolby AC-3Ô and MPEG-1 decode and • Very Long Instruction Word (VLIW) processor with 3.6 billion Wave Table and Waveguide synthesis operations per second peak in the Mpact R/3600 version • Fax/modem: Data up to 33.6 kb/s, fax up to 14.4 kb/s and • 5 concurrent I/O and memory controllers DSVD (Digital Simultaneous Voice and Data) • 132 MB/s PCI bus mastering interface • Telephony: Full-duplex speakerphone, Voicemail and caller • Concurrent operation with MRK multitasking real-time kernel ID • Dynamically shared processing with x86 host for highest • Videophone: H.324 over POTS and H.320 over ISDN total system efficiency using the MRM resource manager An Mpact media processor uses an optimized real-time • Flexible multitasking kernel to simultaneously execute these • Loadable mediaware modules provide the latest multimedia functionality using evolving APIs and operating system Mpact mediaware modules. -
Organization of the Motorola 88110 Superscalar RISC Microprocessor
Organization of the Motorola 88110 Superscalar RISC Microprocessor Motorola’s second-generation RISC microprocessor employs advanced techniques for exploit- ing instruction-level parallelism, including superscak instruction issue, out-of-order instruc- tion completion, speculative execution, dynamic hx&ruction rescheduling, and two parallel, high-bandwidth, on-chip caches. Designed to serve as the central processor in low-cost per- sonal computers and workstations, the 88110 supports demanding graphics and digital signal processing applications. Keith Diefendorff otorola designers conceived of the puters and workstation systems. Thus, our de- 88000 RISC (reduced instruction- sign objective was good performance at a given Michael Allen set computer) architecture to cost, rather than ultimate performance at any cost. Dl simplify construction of micropro- We recognized that the personal computer envi- Motorola cessors capable of exploiting high degrees of in- ronment is moving toward highly interactive soft- struction-level parallelism without sacrificing clock ware, user-oriented interfaces, voice and image speed. The designers held architectural complexity processing, and advanced graphics and video, to a minimum to eliminate pipeline bottlenecks all of which would place extremely high demands and remove limitations on concurrent instruction on integer, floating-point, and graphics process- execution. ing capabilities. At the same time, we realized The 88100/200 is the first implementation of the 88110 would have to meet these performance the 88000 architecture. It is a three-chip set, re- demands while operating with the inexpensive quiring one CPU (88100) chip and two (or more> DRAM systems typically found in low-cost per- cache (88200) chips. The CPU’s simple scalar sonal computers.