IEEE Std 1394-1995 IEEE Standard for a High Performance Serial Bus Sponsor Microprocessor and Microcomputer Standards Committee of the IEEE Computer Society Approved 12 December 1995 IEEE Standards Board Approved 22 July 1996 American National Standards Institute Abstract: A high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses, as well as such nonbus interconnects as the IEEE Std 1596-1992, Scalable Coherent Interface, is specified. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. This standard follows the IEEE Std 1212-1991 Command and Status Register (CSR) architecture. Keywords: backplane, bus, computers, high-speed serial bus, interconnect, parallel buses The Institute of Electrical And Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Copyright © 1996 by the Institute of Electrical and Electronics Engineers, Inc. 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Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. ii Introduction (This introduction is not a part of IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus.) This standard describes a serial bus that provides the same services as modern IEEE-standard parallel buses, but at a much lower cost. It has a 64-bit address space, control registers, and a read/write/lock operation set that conforms to the IEEE Std 1212-1991, Command and Status Register (CSR) standard. This simplifies bridging between the Serial Bus and the other interconnects using the IEEE 1212 architecture: IEEE Std 896-1991, FutureBus+ ® and IEEE Std 1596-1992, Scalable Coherent Interface (SCI). There are two physical environments for the Serial Bus: backplane and cable. The backplane environment uses two single-ended signals on a broadcast multitapped bus using backplane transceiver logic (BTL) or emitter coupled logic (ECL) transceiver technology at 49.152 Mbit/s or enhanced transistor-transistor logic (TTL) transceiver technology at 24.576 Mbit/s. In all cases, bus arbitration on the backplane is done using a dominant-mode-logic bit serial approach. The cable environment uses two low-voltage differential signals to connect devices in a noncyclic topology at 98.304 Mbit/s, 196.608 Mbit/s, and 393.216 Mbit/s data rates. The cable arbitration system uses a self-configuring hierachical request/grant protocol that supports hot plugging and widely varying physical topologies. In addition to standard read/write/lock transactions, the Serial Bus provides extensive time-based services, including isochronous data transport (guaranteed latency and bandwidth) and an accurate submicrosecond global timebase for synchronizing events and data. This standards effort started in 1986 at the request of the membership of the IEEE Microcomputer Standards Committee as an attempt to unify the different serial busses originally proposed as parts of the IEEE 1014 VME, IEEE 1296 Multibus II, and IEEE 896 FutureBus+® efforts. The original chair was Michael Teener, and much of the original architecture of this standard was invented by Mr. Teener, David James, and David Gustavson. In particular, the fairness and retry algorithms were originally proposed by David James during this early period. As the proposed standard was developed, it attracted more interest from those that needed a much improved external I/O interconnect for multimedia information and for mass storage. This added the requirements for isochronous transport, much higher data rates, and a more rugged cable and connector system. To answer these needs a) David James and Michael Teener developed a isochronous access protocol that was compatible with the existing fairness scheme. This protocol was simplified and enhanced based on proposals by Ed Gardner. b) Roger Van Brunt and Florin Oprescu developed a much improved physical layer for the cable environment, which was capable of 400 Mbit/s peak rates using low-cost digital complimentary-symmetry metal-oxide semiconductor (CMOS) technology. Forrest Crowell further reduced the complexity of the cable physical layer proposing the data-strobe encoding from INMOS. Florin Oprescu's self-configuring hierarchical arbitration protocol was also adopted at this time, with simplifications developed by Willam Duckwall. c) Andy Carter proposed the connector and cable system for the cable environment, based on original work done by Hosiden Corporation. The connector task group under the leadership of David Hatch refined that proposal to meet the requirements of all concerned. d) Greg Floryance, Bill Ham, and Max Bassler led the specification for the internal connection system for the cable environment. Bill Ham also worked to ensure that system level grounding and power issues were handled correctly. e) Thom Potyraj coordinated the development of the backplane environment and contributed much of its technical content. f) Gerald Marazas defined the bus management protocols with extensive help from David James, Peter Johansson, Hisato Shima, Scott Smyers, and Michael Teener. Peter Johansson rewrote the bus management text during the ballot resolution process as the best way to respond to extensive ballot comments on this topic. Gerald Marazas took over as chair of the working group in 1993, while Michael Teener continued as editor of the standard. Additional editing was done by Thom Potyraj for the backplane environment physical layer, Jeff Stai for the link and transaction layers, Gerald Marazas for the bus management layer, Bill Ham for the cable environment system iii properties, Max Bassler and Greg Floryance for the internal device physical interface, Jim Baldwin for the PHY-Link interface definition, Florin Oprescu for the cable test procedures, and Steven Dunwoody for the shielding