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Analog Signal Processing Solutions and Design of Memristor-Cmos Analog Co-Processor for Acceleration of High-Performance Computing Applications

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Analog Signal Processing Solutions and Design of Memristor-Cmos Analog Co-Processor for Acceleration of High-Performance Computing Applications University of Massachusetts Amherst ScholarWorks@UMass Amherst Doctoral Dissertations Dissertations and Theses July 2018 ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO-PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS Nihar Athreyas University of Massachusetts Amherst Follow this and additional works at: https://scholarworks.umass.edu/dissertations_2 Part of the Electronic Devices and Semiconductor Manufacturing Commons, Hardware Systems Commons, Signal Processing Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons Recommended Citation Athreyas, Nihar, "ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO-PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS" (2018). Doctoral Dissertations. 1215. https://doi.org/10.7275/11884361.0 https://scholarworks.umass.edu/dissertations_2/1215 This Open Access Dissertation is brought to you for free and open access by the Dissertations and Theses at ScholarWorks@UMass Amherst. It has been accepted for inclusion in Doctoral Dissertations by an authorized administrator of ScholarWorks@UMass Amherst. For more information, please contact [email protected]. ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO- PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS A Dissertation Presented by NIHAR ATHREYAS Submitted to the Graduate School of the University of Massachusetts Amherst in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY May 2018 ELECTRICAL AND COMPUTER ENGINEERING © Copyright by Nihar Athreyas 2018 All Rights Reserved ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO- PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS A Dissertation Presented by NIHAR ATHREYAS Approved as to style and content by: ______________________________________________ Dev Gupta, Co-Chair ______________________________________________ J. Joshua Yang, Co-Chair ______________________________________________ Patrick Kelly, Member ______________________________________________ Blair Perot, Member ____________________________________________ Christopher V. Hollot, Department Head Electrical and Computer Engineering DEDICATION To Mom, Dad, Lakshmi, My family and My Dearest Friends (too many to mention by name but, they know who they are) who have been a constant source of motivation and support, at times when I needed it (or not) And To Tom Brady and the Patriots for the never give up attitude, and without whom Sundays would be very boring. ACKNOWLEDGMENTS It gives me immense pleasure to thank those who have made this work possible. I would like to start by thanking Dr. Dev Gupta for believing in me and hiring me as his research assistant 5 years ago. He has had a strong influence on my professional life and he has always pointed me in the right direction, every time I needed it. I’m lucky to have him as my advisor and mentor. I would like to thank Dr. Joshua Yang who co-advised me on this thesis. He always offered valuable suggestions and encouragement. I would like to extend my gratitude to Dr. Patrick Kelly who has always been a constant source of motivation and support. I would like to express my gratitude to Dr. Blair Perot for his valuable time, suggestions and advice and for getting me interested in partial differential equations. I want to thank Dr. Qiangfei Xia for all his support and guidance. I would also like to thank Jai Gupta and Abbie Mathew of Spero Devices for accommodating me and supporting me in every possible way. It’s always a pleasure working with you guys. I would like to thank the University of Massachusetts, Amherst for providing a wonderful environment and resources for the completion of this project. A special thank you to my family and all my friends for the support they provided me with when the going got tough and everything else that they have done. v ABSTRACT ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO- PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS MAY 2018 NIHAR ATHREYAS B.E., VISVESVARAYA TECHNOLOGICAL UNIVERSITY M.S., UNIVERSITY OF MASSACHUSETTS, AMHERST Ph.D., UNIVERSITY OF MASSACHUSETTS, AMHERST Directed by: Professor Dev Gupta and Professor Joshua Yang Emerging applications in the field of machine vision, deep learning and scientific simulation require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet these ever-increasing demands. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. The major contribution of this work is to show that analog processing can be a viable solution to this problem. This is demonstrated in the three parts of the dissertation. In the first part of the dissertation, we demonstrate that analog processing can be used to solve the problem of stereo correspondence. Novel modifications to the algorithms are proposed which improves the computational speed and makes them efficiently implementable in analog hardware. The analog domain implementation provides further speedup in computation and has lower power consumption than a digital implementation. In the second part of the dissertation, a prototype of an analog processor was developed using commercially available off-the-shelf components. The focus was on providing experimental vi results that demonstrate functionality and to show that the performance of the prototype for low-level and mid-level image processing tasks is equivalent to a digital implementation. To demonstrate improvement in speed and power consumption, an integrated circuit design of the analog processor was proposed, and it was shown that such an analog processor would be faster than state-of-the-art digital and other analog processors. In the third part of the dissertation, a memristor-CMOS analog co-processor that can perform floating point vector matrix multiplication (VMM) is proposed. VMM computation underlies some of the major applications. To demonstrate the working of the analog co-processor at a system level, a new tool called PSpice Systems Option is used. It is shown that the analog co- processor has a superior performance when compared to the projected performances of digital and analog processors. Using the new tool, various application simulations for image processing and solution to partial differential equations are performed on the co-processor model. vii TABLE OF CONTENTS Page ACKNOWLEDGMENTS ...................................................................................................................... v ABSTRACT ........................................................................................................................................ vi LIST OF TABLES ................................................................................................................................ xii LIST OF FIGURES ............................................................................................................................. xiii CHAPTER 1. INTRODUCTION ................................................................................................................... 1 1.1. Analog signal processing solution for image alignment ........................................ 3 1.2. Analog Signal Processing Solution for Machine Vision Applications ..................... 5 1.3. Memristor-CMOS Analog Co-Processor for Acceleration of High- Performance Computing Applications ................................................................... 6 2. ANALOG SIGNAL PROCESSING FOR IMAGE ALIGNMENT ................................................... 8 2.1. Patch Based Stereo Correspondence Algorithm.................................................... 8 2.2. Review of Related Work ........................................................................................ 9 2.3. Reasons for Choosing Normalized Cross-correlation .......................................... 10 2.4. The Normalized Cross-correlation Algorithm ...................................................... 10 2.4.1. Fast NCC Algorithm: Sum Table Method for Calculating Denominator ........................................................................................... 12 2.4.2. Fast NCC Algorithm: Calculating the numerator .................................... 13 2.4.3. Modifications to the NCC algorithm ....................................................... 14 2.4.4. Reducing the number of shifts ............................................................... 14 2.4.5. Using diagonal elements ......................................................................... 15 2.5. Per-Pixel Stereo Correspondence Algorithm ....................................................... 17 2.5.1. Review of related work ........................................................................... 17 2.5.2. Disparity Estimation using overlapping blocks ....................................... 17 2.6. Hardware Architecture ........................................................................................ 18 2.6.1. Implementing the modified NCC algorithm in hardware ....................... 20 2.6.2. Implementing the SAD algorithm in hardware ....................................... 21 viii 2.7. Stereo Correspondence Algorithm Results .........................................................
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