Semester 1 Presentation

Total Page:16

File Type:pdf, Size:1020Kb

Semester 1 Presentation E-Clerk Team: SDMAY18-01 Website: https://sdmay18-01.sd.ece.iastate.edu Advisor & Client: Lee Harker Team Members Rex Borseth Annie Steenson DeQuan Burnside Major: Software Engineering Major: Software Engineering Major: Software Engineering Team Role: Client Liaison Team Role: Project Manager Team Role: Software Reporter Technical Role: Embedded Technical Role: Software Architect Technical Role: Backend Systems Developer Developer Nick Parsons George Zachariades Sandra Sebastian Major: Computer Engineering Major: Computer Engineering Major: Computer Engineering Team Role: Secretary Team Role: Treasurer Team Role: Hardware Reporter Technical Role: Hardware Technical Role: Systems Technical Role: Hardware Architect Administrator Engineer Project Plan Problem Statement ● ETG small equipment checkout ● Sub-optimal business hours ● Waste of precious faculty time ● Inefficient bookkeeping ● Low accountability Functional Requirements - Students ● Log in and out ● View available equipment ● Select an equipment item to checkout ● Determine checkout duration ● View currently checked out equipment (personal) ● Return equipment, close checkout record ● Report system misuse or broken items Functional Requirements - Admin ● Log in and out ● C.R.U.D. available equipment ● Determine max checkout durations for items ● C.R.U.D. student users, records, and user privileges ● Create, update, remove lockers ● Add new Administrators Non-Functional Requirements ● Scalability ● Availability ● Reliability / Recoverability ● Maintainability ● Security ● Data Integrity ● Usability Conceptual Sketch ● Metal Lockers ● Dallas 1-Wire® System ● Raspberry Pi ● Linux Virtual Machine ○ Website ○ MySQL ● Monitor ● Keyboard Technical Constraints and Considerations ● How much current we can deliver to the 12-volt locks ● Sanitize database every semester ○ Graduating students/ Leaving students ● Misuse: Item return validation ● Website must be maintainable by ETG Market Survey ● Send out Survey to ECpE students Market Survey ● Send out Survey to ECpE students Potential Risks & Mitigation ● Learning Curves ● Failing to manage time wisely ● Malicious users, system abuse ● Concurrency Issues ○ Opening two sessions of the website on the Raspberry Pi Resource & Cost Estimate ● Total Estimated Cost: $627.82 Resource & Cost Estimate ● Total Estimated Cost: $627.82 Alternatives: Amazon - Hubs ● Up to $6K-$20K in cost plus monthly maintenance fees ● Similar misuse risks https://amazon29.au1.qualtrics.com/jfe/form /SV_dcgOjgJfneXEG45 System Design Functional Decomposition ● Two major components: ○ Hardware ■ Lockers ■ 1-Wire® System ■ Raspberry Pi ○ Software ■ Virtual Machine ■ Website ■ Database ■ OWFS (1-Wire Filesystem) Macro-level System Design Software - OWFS (1-Wire Filesystem) ● Will run on the Raspberry Pi ● I2C connection is used to connect to one wire system ● Runs a virtual filesystem ● Each device on discovered is automatically added as a file ● Runs two servers ○ OW server runs filesystem ○ HTTP server Hardware Design ● System ○ Raspberry Pi ○ One-Wire Master Device ○ Logic Level Converter (3.3V to 5V) ● Per Locker items ○ One-Wire Slave Devices ○ LM 660 Operational Amplifier ○ IRF 540 Mosfet Device ○ 12V Electric Lock Hardware Design - Master Circuit Diagram ● Hardware Design - Slave Circuit Diagram ● Hardware Design - Circuit Equations 12V limit to MOSFET If Vt is never reached, the MOSFET will be in an “OFF” state. (Vgs = 0) Software - Platforms Software - Database Schema Security - Authentication - Shibboleth ● Version - Shibboleth 2.6.0 ● Redirecting /secure to the Shibboleth authentication page. ● Returning header with successful login. ● User now authenticated and can checkout equipment. ● Logging authenticated users with login time. Prototype Demo Prototype Demo Authentication - Shibboleth - Demo Test Plan ● Unit tests ● Code Coverage ● Functionality Testing ○ Proper navigation (links) ○ Form validation ● Database testing ○ Data consistency ● Content checking ○ Disability Accommodations Test Plan ● Compatibility Testing ○ Browsers ○ Print Options ● Security Tests ○ Unauthorized requests ○ SSL is working properly ○ Securing Raspberry Pi ● Hardware ○ Circuit validation ○ Operational validation Conclusion Project Milestones (First Semester) ● Prototype - 12/06/2017 ○ User clicks on button to signal they want to checkout something ○ Frontend sends HTTP request to backend ○ Backend sends a TCP request to OWFS server ○ OWFS turns slave device port assigned to the lock off Project Milestones (Second Semester) ● Minimal Viable Product (MVP) - 03/09/2018 ○ Check out/in and retrieve/return equipment to designated locker box. ○ 40% unit test code coverage ● Alpha Testing ○ Team and ETG tests the MVP ● Staging ○ Product has pristine user interface ○ Fully functional student and admin features ○ 60% unit test code coverage Project Milestones (Second Semester) ● Beta Testing ○ Team will ask a group of students and ETG staff to trial the system ● Final Product - 04/27/2018 ○ Final product should have any modification requirements found from testing ○ Over 95% unit test code coverage ○ Logging and error handling ○ Backup script ○ Software and hardware manuals Current Project Status ● Prototype is complete ● Work on MVP over break ● Implement checkout functionality ● Make website look professional ● Have master device differentiate which slave devices to signal ● Securing OWFS server Plan for Next Semester ● Make more specific goals ● Work on personal accountability ● Build out MVP first month ● Finalize circuit design ● Add LED and Locker functionality to one-wire system ● Build out the staging product ● Test, test, test Contributions of Each Project Member ● Team Total: 387 hours Task Responsibility ● Annie: Software Architect, Full stack dev ○ Design software architecture ○ Front-end components ○ Back-end implementation ● Quan: Backend Dev ○ REST API endpoints ○ Document software processes ● Rex: Embedded Systems Dev ○ REST API endpoints ○ OWFS integration Task Responsibility ● George: Systems Administrator ○ Shibboleth integration ○ OWFS and locker integration/testing ● Sandra: Hardware Engineer, Front-end Dev ○ OWFS and locker integration/testing ○ Front-end styling ● Nick: Hardware Architect ○ Design circuits ○ 1-wire® system ○ Locker integration ○ Document hardware processes Thanks! ANY QUESTIONS? Appendix: In Depth Slides Market Survey ● Send out Survey to ECpE students Market Survey ● Send out Survey to ECpE students 1-Wire Technology https://www.maximintegrated.com/en/app-notes/index.mvp/id/1796 1-Wire Block Diagram https://www.maximintegrated.com/en/products/digital/one-wire.html Plan for Next Semester ● Annie: ● Quan: ● Rex: ● George: ● Sandra: ● Nick:.
Recommended publications
  • Is Parallel Programming Hard, And, If So, What Can You Do About It?
    Is Parallel Programming Hard, And, If So, What Can You Do About It? Edited by: Paul E. McKenney Linux Technology Center IBM Beaverton [email protected] December 16, 2011 ii Legal Statement This work represents the views of the authors and does not necessarily represent the view of their employers. IBM, zSeries, and Power PC are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. Linux is a registered trademark of Linus Torvalds. i386 is a trademarks of Intel Corporation or its subsidiaries in the United States, other countries, or both. Other company, product, and service names may be trademarks or service marks of such companies. The non-source-code text and images in this doc- ument are provided under the terms of the Creative Commons Attribution-Share Alike 3.0 United States li- cense (http://creativecommons.org/licenses/ by-sa/3.0/us/). In brief, you may use the contents of this document for any purpose, personal, commercial, or otherwise, so long as attribution to the authors is maintained. Likewise, the document may be modified, and derivative works and translations made available, so long as such modifications and derivations are offered to the public on equal terms as the non-source-code text and images in the original document. Source code is covered by various versions of the GPL (http://www.gnu.org/licenses/gpl-2.0.html). Some of this code is GPLv2-only, as it derives from the Linux kernel, while other code is GPLv2-or-later.
    [Show full text]
  • Antipatterns Refactoring Software, Architectures, and Projects in Crisis
    AntiPatterns Refactoring Software, Architectures, and Projects in Crisis William J. Brown Raphael C. Malveau Hays W. McCormick III Thomas J. Mowbray John Wiley & Sons, Inc. Publisher: Robert Ipsen Editor: Theresa Hudson Managing Editor: Micheline Frederick Text Design & Composition: North Market Street Graphics Copyright © 1998 by William J. Brown, Raphael C. Malveau, Hays W. McCormick III, and Thomas J. Mowbray. All rights reserved. Published by John Wiley & Sons, Inc. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per−copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750−8400, fax (978) 750−. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY 10158−, (212) 850−, fax (212) 850−, E−Mail: PERMREQ @ WILEY.COM. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold with the understanding that the publisher is not engaged in professional services. If professional advice or other expert assistance is required, the services of a competent professional person should be sought. Designations used by companies to distinguish their products are often claimed as trademarks. In all instances where John Wiley & Sons, Inc., is aware of a claim, the product names appear in initial capital or all capital letters.
    [Show full text]
  • Performance Analyses and Code Transformations for MATLAB Applications Patryk Kiepas
    Performance analyses and code transformations for MATLAB applications Patryk Kiepas To cite this version: Patryk Kiepas. Performance analyses and code transformations for MATLAB applications. Computa- tion and Language [cs.CL]. Université Paris sciences et lettres, 2019. English. NNT : 2019PSLEM063. tel-02516727 HAL Id: tel-02516727 https://pastel.archives-ouvertes.fr/tel-02516727 Submitted on 24 Mar 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Préparée à MINES ParisTech Analyses de performances et transformations de code pour les applications MATLAB Performance analyses and code transformations for MATLAB applications Soutenue par Composition du jury : Patryk KIEPAS Christine EISENBEIS Le 19 decembre 2019 Directrice de recherche, Inria / Paris 11 Présidente du jury João Manuel Paiva CARDOSO Professeur, University of Porto Rapporteur Ecole doctorale n° 621 Erven ROHOU Ingénierie des Systèmes, Directeur de recherche, Inria Rennes Rapporteur Matériaux, Mécanique, Michel BARRETEAU Ingénieur de recherche, THALES Examinateur Énergétique Francois GIERSCH Ingénieur de recherche, THALES Invité Spécialité Claude TADONKI Informatique temps-réel, Chargé de recherche, MINES ParisTech Directeur de thèse robotique et automatique Corinne ANCOURT Maître de recherche, MINES ParisTech Co-directrice de thèse Jarosław KOŹLAK Professeur, AGH UST Co-directeur de thèse 2 Abstract MATLAB is an interactive computing environment with an easy programming language and a vast library of built-in functions.
    [Show full text]
  • Large-Scale Software Architecture
    Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Large-Scale Software Architecture Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Copyright # 2003 by John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) 1243 779777 Email (for orders and customer service enquiries): [email protected] Visit our Home Page on www.wileyeurope.com or www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the publication. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to [email protected], or faxed to (+44) 1243 770571. Neither the authors nor John Wiley & Sons, Ltd accept any responsibility or liability for loss or damage occasioned to any person or property through using the material, instructions, methods or ideas contained herein, or acting or freraining from acting as a result of such use.
    [Show full text]
  • [0470848499]Large-Scale Software Architecture.Pdf
    Y L F M A E T Team-Fly® Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Large-Scale Software Architecture Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Copyright # 2003 by John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) 1243 779777 Email (for orders and customer service enquiries): [email protected] Visit our Home Page on www.wileyeurope.com or www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the publication. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to [email protected], or faxed to (+44) 1243 770571. Neither the authors nor John Wiley & Sons, Ltd accept any responsibility or liability for loss or damage occasioned to any person or property through using the material, instructions, methods or ideas contained herein, or acting or freraining from acting as a result of such use.
    [Show full text]
  • A Development Process Generative Pattern Language
    Proceedings of PLoP/94, Monticello, Il., August 1994 AT&T Bell Laboratories A Development Process Generative Pattern Language James O. Coplien – AT&T Bell Laboratories (708) 713-5384 [email protected] 1. Introduction This paper introduces a family of patterns that can be used to shape a new organization and its development processes. Patterns support emerging techniques in the software design community, where they are finding a new home as a way of understanding and creating computer programs. There is an increasing awareness that new program structuring techniques must be supported by suitable management techniques, and by appropriate organization structures; orga- nizational patterns are one powerful way to capture these. We believe that patterns are particularly suitable to organizational construction and evolution. Patterns form the basis of much of modern cultural anthropology: a culture is defined by its patterns of relationships. Also, while the works of Christopher Alexander1 deal with town planning and building architecture to support human enterprise and inter- action, it can be said that organization is the modern analogue to architecture in contemporary professional organiza- tions. Organizational patterns have a first-order effect on the ability of people to carry on. We believe that the physical architecture of the buildings supporting such work are the dual of the organizational patterns; these two worlds cross in the work of Thomas Allen at MIT.2 There is nothing new in taking a pattern perspective to organizational analysis. What is novel about the work here is its attempt to use patterns in a generative way. All architecture fundamentally concerns itself with control;3 here we use architecture to supplant process as the (indirect) means to controlling people in an organization.
    [Show full text]
  • Precise Measurement-Based Worst-Case Execution Time Estimation
    Precise Measurement-Based Worst-Case Execution Time Estimation DISSERTATION submitted in partial fulfillment of the requirements for the degree of Doktor der technischen Wissenschaften (Dr. techn.) by Michael Zolda to the Faculty of Informatics at Vienna University of Technology Advisor:: Priv.-Doz. Dipl.-Ing. Dr. techn. Raimund Kirner This dissertation has been reviewed by: (Priv.-Doz. Dipl.-Ing. (ao.Univ.-Prof. Dipl.-Ing. Dr. Raimund Kirner) Dr. techn. Peter Puschner) Vienna, September 2012 (Michael Zolda) Technische Universität Wien A-1040 Wien Karlsplatz 13 Tel. +43-1-58801-0 www.tuwien.ac.at Erklärung zur Verfassung der Arbeit Michael Zolda Rögergasse 22 / TOP 2, A-1090 Wien Hiermit erkläre ich, dass ich diese Arbeit selbständig verfasst habe, dass ich die verwendeten Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit – einschließlich Tabellen, Karten und Abbildungen – die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. (Ort, Datum) (Michael Zolda) i Abstract A real-time computer system is a computer system in which the correctness of the sys- tem behavior depends not only on the logic results of the computations, but also on the physical instant at which these results are produced. Today, most real-time computer systems are implemented as collections of software tasks that are executed concurrently on a suitable hardware platform consisting of one or multiple microprocessors or micro- processor cores. Obtaining the worst-case execution time (WCET) of each real-time task is an essential step in ensuring the correctness of such a system.
    [Show full text]
  • COMPUTER SYSTEM ARCHITECTURE Reviewer
    ALAGAPPA UNIVERSITY [Accredited with ‘A+’ Grade by NAAC (CGPA:3.64) in the Third Cycle and Graded as Category–I University by MHRD-UGC] (A State University Established by the Government of Tamil Nadu) KARAIKUDI – 630 003 Directorate of Distance Education M.Sc. [Computer Science] II - Semester 341 21 COMPUTER SYSTEM ARCHITECTURE Reviewer Assistant Professor, Dr. M. Vanitha Department of Computer Applications, Alagappa University, Karaikudi Authors Dr. Vivek Jaglan, Associate Professor, Amity University, Haryana Pavan Raju, Member of Institute of Institutional Industrial Research (IIIR), Sonepat, Haryana Units (1, 2, 3, 4, 5, 6) Dr. Arun Kumar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Kuldeep Singh Kaswan, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Shrddha Sagar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Units (7, 8, 9, 10.9, 11.6, 12, 13, 14) Vivek Kesari, Assistant Professor, Galgotia's GIMT Institute of Management & Technology, Greater Noida, Distt. Gautam Budh Nagar Units (10.0-10.8.4, 10.10-10.14, 11.0-11.5, 11.7-11.11) "The copyright shall be vested with Alagappa University" All rights reserved. No part of this publication which is material protected by this copyright notice may be reproduced or transmitted or utilized or stored in any form or by any means now known or hereinafter invented, electronic, digital or mechanical, including photocopying, scanning, recording or by any information storage or retrieval system, without prior written permission from the Alagappa University, Karaikudi, Tamil Nadu.
    [Show full text]
  • Software Architect Certification As Part of the Lockheed Martin Integrated
    LM ADQP: Development & Qualification Program for Architects and Technical Leaders SEI SATURN Conference St. Petersburg, FL 9 May 12 Dr. Jeffrey S. Poulin LM Advanced Architect LM Fellow Chair, LM ADQP 1 © 2012 Lockheed Martin Corporation Agenda 1. Background – Why an Architect Development & Qualification Program (ADQP)? – How ADQP fits into LM Architecture activities – Program history 2. Architect Development – Focus items – University partnerships – Technical leadership career path 3. Architect Qualification – Levels of recognition – Criteria – Governance and administration 2 © 2012 Lockheed Martin Corporation Why this program? To have an orderly and understood process to: 1. identify, 2. grow, and 3. recognize technical leaders that can deliver complete technical solutions/programs to LM Customers. 3 © 2012 Lockheed Martin Corporation Part 1: Background 4 © 2012 Lockheed Martin Corporation Why Qualify Our Architects? USC Code 44 (Public Law 104-106, Clinger-Cohen Act of 1996) – CIO is responsible for developing, maintaining, and facilitating the implementation of an integrated IT architecture. OMB Circular A-130 - Agencies must use or create an Enterprise Architecture Framework and document linkages between mission needs, information content, and IT capabilities. DODD 8320.2, DOD 8320.02G, SECNAVINST 5000.36 – Guidance to DOD/DON for implementation of a supporting Data Strategy. DON N61/7U160503 6 APR 2007 – Announcement of DON Navy Enterprise Architecture and Data Strategy (NEADS) Policy, with implementation guidance for all legacy
    [Show full text]
  • Senior Deep Learning Hardware Architect
    Hero Meets Hero! Reexen Technology is a rising startup specialized in energy-efficient integrated electronics that help enable ubiquitous intelligence. Our end-to- end solutions, from sensing to local decision making, find a vast range of applications in audio, vision, and biomedical products. Our ambition and success heavily rely on our core competence in low-power analog/mixed- signal and digital integrated circuit design, as well as holistic considerations at the system, architecture, and algorithm levels. Imagine what you could do here. At Reexen, new ideas have a way of becoming innovative products, services, and customer experiences. Bring passion and dedication to your job, and there is no telling what you could accomplish. Would you like to work in a rapidly changing environment where your technical abilities will be challenged on a day-to-day basis? Reexen is searching for a world-class architect in deep learning and its application to vision, speech, and other domains, with the goal of solving specific problems encountered in Reexen’s product development. Reexen is working on the next-generation architecture for NPU to be used in wearable and IoT devices. What we are looking for: Senior Deep Learning Hardware Architect Main responsibilities • Research and develop high-level architecture and micro-architecture for neural processor hardware. • To optimize execution of neural network models on neural processor hardware. • Expertise in deep learning-related algorithms, such as Convolutional Neural Networks, Long Short-Term Memory, classification/detection, and their applications. • Familiarity with computer vision algorithms such as object detection, tracking, and recognition. • Understand the hardware implications of the aforementioned algorithms in terms of performance and power.
    [Show full text]
  • Hardware Architecture - Wikipedia, the Free Encyclopedia Hardware Architecture from Wikipedia, the Free Encyclopedia
    Navigation menu Hardware architecture - Wikipedia, the free encyclopedia Hardware architecture From Wikipedia, the free encyclopedia In engineering, hardware architecture refers to the identification of a system's physical components and their interrelationships. This An F-117 conducts a live exercise bombing run using An orthographically projected diagram of the F-117A description, often GBU-27 laser-guided bombs. Nighthawk. called a hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides software component designers important information needed for software development and integration. Clear definition of a hardware architecture allows the various traditional engineering disciplines (e.g., electrical and mechanical engineering) to work more effectively together to [ ] develop and manufacture new machines, devices and components. 1 Hardware is also an expression used within the computer engineering industry to explicitly distinguish the (electronic computer) hardware from the software that runs on it. But hardware, within the automation and software engineering disciplines, need not simply be a computer of some sort. A modern automobile runs vastly more software than the Apollo spacecraft. Also, modern aircraft cannot function without running tens of millions of computer instructions embedded and distributed throughout the aircraft and resident in both standard computer hardware and in specialized hardward components such as IC wired logic gates, analog and hybrid devices, and other digital components. The need to effectively model how separate physical components combine to form complex systems is important over a wide range of applications, including computers, personal digital assistants (PDAs), cell phones, surgical instrumentation, satellites, and submarines. Hardware architecture is the representation of an engineered (or to be engineered) electronic or electromechanical hardware system, and the process and discipline for effectively implementing the design(s) for such a system.
    [Show full text]
  • 0321357485 Sample.Pdf
    Many of the designations used by manufacturers and sellers to distinguish their prod- ucts are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed with ini- tial capital letters or in all capitals. The authors and publisher have taken care in the preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec- tion with or arising out of the use of the information or programs contained herein. The publisher offers excellent discounts on this book when ordered in quantity for bulk purchases or special sales, which may include electronic versions and/or custom covers and content particular to your business, training goals, marketing focus, and branding interests. For more information, please contact: U.S. Corporate and Government Sales (800) 382-3419 [email protected] For sales outside the United States, please contact: International Sales [email protected] Visit us on the Web: informit.com/aw Library of Congress Cataloging-in-Publication Data Eeles, Peter, 1962– The process of software architecting / Peter Eeles, Peter Cripps. p. cm. Includes bibliographical references and index. ISBN 0-321-35748-5 (pbk. : alk. paper) 1. Software architecture. 2. System design. I. Cripps, Peter, 1958– II. Title. QA76.754.E35 2009 005.1'2—dc22 2009013890 Copyright © 2010 Pearson Education, Inc. All rights reserved. Printed in the United States of America. This publication is pro- tected by copyright, and permission must be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise.
    [Show full text]