DOCSLIB.ORG

COMPUTER SYSTEM ARCHITECTURE Reviewer

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
COMPUTER SYSTEM ARCHITECTURE Reviewer ALAGAPPA UNIVERSITY [Accredited with ‘A+’ Grade by NAAC (CGPA:3.64) in the Third Cycle and Graded as Category–I University by MHRD-UGC] (A State University Established by the Government of Tamil Nadu) KARAIKUDI – 630 003 Directorate of Distance Education M.Sc. [Computer Science] II - Semester 341 21 COMPUTER SYSTEM ARCHITECTURE Reviewer Assistant Professor, Dr. M. Vanitha Department of Computer Applications, Alagappa University, Karaikudi Authors Dr. Vivek Jaglan, Associate Professor, Amity University, Haryana Pavan Raju, Member of Institute of Institutional Industrial Research (IIIR), Sonepat, Haryana Units (1, 2, 3, 4, 5, 6) Dr. Arun Kumar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Kuldeep Singh Kaswan, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Shrddha Sagar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Units (7, 8, 9, 10.9, 11.6, 12, 13, 14) Vivek Kesari, Assistant Professor, Galgotia's GIMT Institute of Management & Technology, Greater Noida, Distt. Gautam Budh Nagar Units (10.0-10.8.4, 10.10-10.14, 11.0-11.5, 11.7-11.11) "The copyright shall be vested with Alagappa University" All rights reserved. No part of this publication which is material protected by this copyright notice may be reproduced or transmitted or utilized or stored in any form or by any means now known or hereinafter invented, electronic, digital or mechanical, including photocopying, scanning, recording or by any information storage or retrieval system, without prior written permission from the Alagappa University, Karaikudi, Tamil Nadu. Information contained in this book has been published by VIKAS® Publishing House Pvt. Ltd. and has been obtained by its Authors from sources believed to be reliable and are correct to the best of their knowledge. However, the Alagappa University, Publisher and its Authors shall in no event be liable for any errors, omissions or damages arising out of use of this information and specifically disclaim any implied warranties or merchantability or fitness for any particular use. Vikas® is the registered trademark of Vikas® Publishing House Pvt. Ltd. VIKAS® PUBLISHING HOUSE PVT. LTD. E-28, Sector-8, Noida - 201301 (UP) Phone: 0120-4078900 Fax: 0120-4078999 Regd. Office: A-27, 2nd Floor, Mohan Co-operative Industrial Estate, New Delhi 1100 44 Website: www.vikaspublishing.com Email: [email protected] Work Order No. AU/DDE/DE1-15/Printing of Course Materials/2020 Dated 05.02.2020 Copies-200 SYLLABI-BOOK MAPPING TABLE Computer System Architecture BLOCK I: Fundamentals Unit 1: Introduction Unit 1: Introduction : Definition, trends, power in IC, cost (Pages 1-18) Unit 2: Performance : Dependability, measuring, reporting and Unit 2: Performance summarizing performance (Pages 19-34) Unit 3: Quality: Quality principles of computer design, performance Unit 3: Quality of Computer Design (Pages 35-42) BLOCK II : ILP Concepts Unit 4: Introduction: concepts and challenges, Basic computer Unit 4: Instruction Level Parallelism techniques for exposing ILP, reducing branch costs with prediction, (Pages 43-52) data hazards Unit 5: Scheduling Unit 5: Scheduling : dynamic scheduling, hardware based speculation, (Pages 53-70) multiple issue and static scheduling, advanced techniques for instruction Unit 6: Limitations of ILP delivery and speculation (Pages 71-78) Unit 6: Limitations of ILP: hardware and software speculation, multithreading BLOCK III : Thread Level Parallelism Unit 7: Multiprocessor and thread level parallelism: Introduction, Unit 7: Multiprocessor and Thread symmetric shared memory architecture Level Parallelism Unit 8: Performance and architectures: performance of symmetric (Pages 79-94) shared memory multiprocessors, Distributed shared memory Unit 8: Performance and Architectures architectures (Pages 95-102) Unit 9: Synchronization models: synchronization, model of memory Unit 9: Synchronization Models consistency, cross cutting issues (Pages 103-108) BLOCK IV : Memory Hierarchy Design Unit 10: Introduction to Memory Unit 10: Introduction : Optimization of cache performance, memory Organization technologyand optimizations (Pages 109-140) Unit 11: Protection: virtual memory and virtual machines Unit 11: Protection Unit 12: Issues : crosscutting issues in the design of memory hierarchies (Pages 141-162) Unit 12: Issues (Pages 163-166) BLOCK V : Storage Systems Unit 13: Introduction : advanced topics in Disk storage, real faults and Unit 13: Introduction to Storage failures, I/O performance, reliability measures and benchmarks Systems Unit 14: Issues : a little queuing theory, crosscutting issues, designing (Pages 167-180) and evaluating and I/O system, the Internet Archive Cluster Unit 14: Issues (Pages 181-192) CONTENTS BLOCK I: FUNDAMENTALS UNIT 1 INTRODUCTION 1-18 1.0 Introduction 1.1 Objectives 1.2 History of Computers 1.3 Computer Architecture 1.4 Answers to Check Your Progress Questions 1.5 Summary 1.6 Key Words 1.7 Self Assessment Questions and Exercises 1.8 Further Readings UNIT 2 PERFORMANCE 19-34 2.0 Introduction 2.1 Objectives 2.2 Factors for Measuring Performance 2.3 Dependability and Measuring Performance 2.4 Summarizing Performances 2.5 Answers to Check Your Progress Questions 2.6 Summary 2.7 Key Words 2.8 Self Assessment Questions and Exercises 2.9 Further Readings UNIT 3 QUALITY OF COMPUTER DESIGN 35-42 3.0 Introduction 3.1 Objectives 3.2 Quality Principles and Performance 3.3 Answers to Check Your Progress Questions 3.4 Summary 3.5 Key Words 3.6 Self Assessment Questions and Exercises 3.7 Further Readings BLOCK II: ILP CONCEPTS UNIT 4 INSTRUCTION LEVEL PARALLELISM 43-52 4.0 Introduction 4.1 Objectives 4.2 Concepts and Challenges 4.3 Compiler Techniques 4.4 Reducing Branch Costs 4.5 Data Hazards 4.6 Answers to Check Your Progress Questions 4.7 Summary 4.8 Key Words 4.9 Self Assessment Questions and Exercises 4.10 Further Readings UNIT 5 SCHEDULING 53-70 5.0 Introduction 5.1 Objectives 5.2 Dynamic Scheduling 5.2.1 Scoreboard 5.2.2 Tomasulo Algorithm 5.2.3 Difference Between Scoreboard and Tomasulo Algorithm 5.3 Hardware Based Speculation 5.4 Multiple Issue and Static Scheduling 5.5 Advanced Techniques for Instruction Delivery and Speculation 5.5.1 Increasing Instruction Fetch Bandwidth 5.5.2 Branch-target Buffers 5.5.3 Integrated Instruction Fetch Units 5.5.4 Value Prediction 5.5.5 Address Aliasing Prediction 5.6 Answers to Check Your Progress Questions 5.7 Summary 5.8 Key Words 5.9 Self Assessment Questions and Exercises 5.10 Further Readings UNIT 6 LIMITATIONS OF ILP 71-78 6.0 Introduction 6.1 Objectives 6.2 Hardware and Software Speculation 6.3 Multithreading 6.4 Answers to Check Your Progress Questions 6.5 Summary 6.6 Key words 6.7 Self Assessment Questions and exercises 6.8 Further Readings BLOCK III: THREAD LEVEL PARALLELISM UNIT 7 MULTIPROCESSOR AND THREAD LEVEL PARALLELISM 79-94 7.0 Introduction 7.1 Objectives 7.2 Multiprocessors 7.3 Thread Level Parallelism (Task Parallelism, Function Parallelism, Control Parallelism) 7.3.1 Parallel Architectures 7.4 Symmetric Shared Memory Architecture 7.5 Answers to Check Your Progress Questions 7.6 Summary 7.7 Key Words 7.8 Self Assessment Questions and Exercises 7.9 Further Readings UNIT 8 PERFORMANCE AND ARCHITECTURES 95-102 8.0 Introduction 8.1 Objectives 8.2 Performance of Symmetric Shared Memory Architectures 8.3 Distributed Shared Memory Architectures 8.4 Answers to Check Your Progress Questions 8.5 Summary 8.6 Key words 8.7 Self Assessment Questions and Exercises 8.8 Further Readings UNIT 9 SYNCHRONIZATION MODELS 103-108 9.0 Introduction 9.1 Objectives 9.2 Synchronization 9.3 Memory Consistency Models 9.4 Cross Cutting Issues 9.5 Answers to Check Your Progress Questions 9.6 Summary 9.7 Key Words 9.8 Self Assessment Questions and Exercises 9.9 Further Readings BLOCK IV: MEMORY HIERARCHY DESIGN UNIT 10 INTRODUCTION TO MEMORY ORGANIZATION 109-140 10.0 Introduction 10.1 Objectives 10.2 Memory Hierarchy Organization 10.3 Main Memory 10.3.1 Random Access Memory (RAM); 10.3.2 Read Only Memory (ROM) 10.4 Organization of Ram and Rom Chips 10.4.1 Memory Address Map; 10.4.2 Memory Connection to CPU 10.5 Auxiliary Memory 10.6 Associative Memory 10.7 Cache Memory 10.7.1 Basic Operation; 10.7.2 Performance 10.8 Mapping Process 10.8.1 Associative Mapping; 10.8.2 Direct Mapping 10.8.3 Set Associative Mapping; 10.8.4 Writing into Cache 10.9 Optimization of Cache Performance, Memory Technology and Optimization 10.10 Answers to Check Your Progress Questions 10.11 Summary 10.12 Key Words 10.13 Self Assessment Questions and Exercises 10.14 Further Readings UNIT 11 PROTECTION 141-162 11.0 Introduction 11.1 Objectives 11.2 Virtual Memory 11.2.1 Page Replacement 11.3 Memory Management Hardware 11.4 Direct Memory Access 11.5 Memory Management and System Performance 11.6 Virtual Machines 11.7 Answers to Check Your Progress Questions 11.8 Summary 11.9 Key Words 11.10 Self Assessment Questions and Exercises 11.11 Further Readings UNIT 12 ISSUES 163-166 12.0 Introduction 12.1 Objectives 12.2 Crosscutting Issues in the Design of Memory Hierarchy 12.3 Answers to Check Your Progress Questions 12.4 Summary 12.5 Key Words 12.6 Self Assessment Questions and Exercises 12.7 Further Readings BLOCK V: STORAGE SYSTEMS UNIT 13 INTRODUCTION TO STORAGE SYSTEMS 167-180 13.0 Introduction 13.1 Objectives 13.2 Storage Devices 13.2.1 Unit
Load more

Recommended publications
  • Is Parallel Programming Hard, And, If So, What Can You Do About It?
    Is Parallel Programming Hard, And, If So, What Can You Do About It? Edited by: Paul E. McKenney Linux Technology Center IBM Beaverton [email protected] December 16, 2011 ii Legal Statement This work represents the views of the authors and does not necessarily represent the view of their employers. IBM, zSeries, and Power PC are trademarks or registered trademarks of International Business Machines Corporation in the United States, other countries, or both. Linux is a registered trademark of Linus Torvalds. i386 is a trademarks of Intel Corporation or its subsidiaries in the United States, other countries, or both. Other company, product, and service names may be trademarks or service marks of such companies. The non-source-code text and images in this doc- ument are provided under the terms of the Creative Commons Attribution-Share Alike 3.0 United States li- cense (http://creativecommons.org/licenses/ by-sa/3.0/us/). In brief, you may use the contents of this document for any purpose, personal, commercial, or otherwise, so long as attribution to the authors is maintained. Likewise, the document may be modified, and derivative works and translations made available, so long as such modifications and derivations are offered to the public on equal terms as the non-source-code text and images in the original document. Source code is covered by various versions of the GPL (http://www.gnu.org/licenses/gpl-2.0.html). Some of this code is GPLv2-only, as it derives from the Linux kernel, while other code is GPLv2-or-later.
    [Show full text]
  • Management of Data Elements in Information Processing
    PB-249-530 MANAGEMENT OF DATA ELEMENTS IN INFORMATION PROCESSING U.S. DEPARTMENT OF COMMERCE / National Bureau of Standards SECOND NATIONAL SYMPOSIUM NATIONAL BUREAU OF STANDARDS GAITHERSBURG, MARYLAND 1975 OCTOBER 23-24 Available by purchase from the National Technical Information Service, 5285 Port Royal Road, Springfield, Va. 221 Price: $9.25 hardcopy; $2.25 microfiche. National Technical Information Service U. S. DEPARTMENT OF COMMERCE PB-249-530 Management of Data Elements in Information Processing Proceedings of a Second Symposium Sponsored by the American National Standards Institute and by The National Bureau of Standards 1975 October 23-24 NBS, Gaithersburg, Maryland Hazel E. McEwen, Editor Institute for Computer Sciences and Technology National Bureau of Standards Washington, D.C. 20234 U.S. DEPARTMENT OF COMMERCE, Elliot L. Richardson, Secrefary NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acfing Direc/or Table of Contents Page Introduction to the Program of the Second National Symposium on The Management of Data Elements in Information Processing ix David V. Savidge, Program Chairman On-Line Tactical Data Inputting: Research in Operator Training and Performance 1 Irving Alderman, Ph.D. "Turning the Corner" on MIS, A Proposed Program of Data Standards in Post-Secondary Education 9 Donald R. Arnold, Ph.D. ASCII - The Data Alphabet That Will Endure 17 Robert W. Bemer Techniques in Developing Standard Procedures for Data Editing 23 George W. Covill An Adaptive File Management Systems 45 Dennis L. Dance and Udo W. Pooch (Given by Dance) A Focus on the Role of the Data Manager 57 Ruth M, Davis, Ph.D. A Proposed Standard Routine for Generating Proposed Standard Check Characters 61 Paul -Andre Desjardins Methodology for Development of Standard Data Elements within Multiple Public Agencies 69 L.
    [Show full text]
  • Antipatterns Refactoring Software, Architectures, and Projects in Crisis
    AntiPatterns Refactoring Software, Architectures, and Projects in Crisis William J. Brown Raphael C. Malveau Hays W. McCormick III Thomas J. Mowbray John Wiley & Sons, Inc. Publisher: Robert Ipsen Editor: Theresa Hudson Managing Editor: Micheline Frederick Text Design & Composition: North Market Street Graphics Copyright © 1998 by William J. Brown, Raphael C. Malveau, Hays W. McCormick III, and Thomas J. Mowbray. All rights reserved. Published by John Wiley & Sons, Inc. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per−copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750−8400, fax (978) 750−. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY 10158−, (212) 850−, fax (212) 850−, E−Mail: PERMREQ @ WILEY.COM. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold with the understanding that the publisher is not engaged in professional services. If professional advice or other expert assistance is required, the services of a competent professional person should be sought. Designations used by companies to distinguish their products are often claimed as trademarks. In all instances where John Wiley & Sons, Inc., is aware of a claim, the product names appear in initial capital or all capital letters.
    [Show full text]
  • H/W3 Binary to Denary
    Name ___________________________________ Form ________ H/W Year 8 Homework Booklet Theme 1 Data Representation Computers themselves, and “ software yet to be developed, will revolutionize “ the way we learn. - Steve Jobs Founder of Apple Introduction What language does a computer understand? How does a computer represent data, information and images? Soon, you will be able to answer the questions above! In this theme we will explore the different ways in which data is represented by the computer, ranging from numbers to images. We will learn and understand the number bases and conversions between denary and binary. We will also be looking at units of information, binary addition and how we can convert binary data into a black and white image! See the key below to find out what the icons below mean: Self Assessment: You will mark your work at the start of next lesson. ENSURE YOU COMPELTE HOMEWORK AS MARKS WILL BE COLLECTED IN! Edmodo Quiz: The will be a quiz the start of next lesson based on your homework. SO MAKE SURE YOU REVISE! Peer Assessment: Homework marked by your class mate at the start of next lesson. MAKE SURE YOU HAVE YOUR HOMEWORK DONE SO YOU CAN SWAP WITH ANOTHER PUPIL! Stuck? Got a question? Email your teacher. Mr Rifai (Head of Computing) [email protected] Miss Davison [email protected] Miss Pascoe [email protected] 2 Due Date: H/W1 Data & Number Bases Read and digest the information below. You will be quizzed next lesson! Any set of characters gathered and translated for What is Data? some purpose.
    [Show full text]
  • Performance Analyses and Code Transformations for MATLAB Applications Patryk Kiepas
    Performance analyses and code transformations for MATLAB applications Patryk Kiepas To cite this version: Patryk Kiepas. Performance analyses and code transformations for MATLAB applications. Computa- tion and Language [cs.CL]. Université Paris sciences et lettres, 2019. English. NNT : 2019PSLEM063. tel-02516727 HAL Id: tel-02516727 https://pastel.archives-ouvertes.fr/tel-02516727 Submitted on 24 Mar 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Préparée à MINES ParisTech Analyses de performances et transformations de code pour les applications MATLAB Performance analyses and code transformations for MATLAB applications Soutenue par Composition du jury : Patryk KIEPAS Christine EISENBEIS Le 19 decembre 2019 Directrice de recherche, Inria / Paris 11 Présidente du jury João Manuel Paiva CARDOSO Professeur, University of Porto Rapporteur Ecole doctorale n° 621 Erven ROHOU Ingénierie des Systèmes, Directeur de recherche, Inria Rennes Rapporteur Matériaux, Mécanique, Michel BARRETEAU Ingénieur de recherche, THALES Examinateur Énergétique Francois GIERSCH Ingénieur de recherche, THALES Invité Spécialité Claude TADONKI Informatique temps-réel, Chargé de recherche, MINES ParisTech Directeur de thèse robotique et automatique Corinne ANCOURT Maître de recherche, MINES ParisTech Co-directrice de thèse Jarosław KOŹLAK Professeur, AGH UST Co-directeur de thèse 2 Abstract MATLAB is an interactive computing environment with an easy programming language and a vast library of built-in functions.
    [Show full text]
  • Large-Scale Software Architecture
    Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Large-Scale Software Architecture Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Copyright # 2003 by John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) 1243 779777 Email (for orders and customer service enquiries): [email protected] Visit our Home Page on www.wileyeurope.com or www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the publication. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to [email protected], or faxed to (+44) 1243 770571. Neither the authors nor John Wiley & Sons, Ltd accept any responsibility or liability for loss or damage occasioned to any person or property through using the material, instructions, methods or ideas contained herein, or acting or freraining from acting as a result of such use.
    [Show full text]
  • On Identifying Basic Discourse Units in Speech: Theoretical and Empirical Issues
    Discours Revue de linguistique, psycholinguistique et informatique. A journal of linguistics, psycholinguistics and computational linguistics 4 | 2009 Linearization and Segmentation in Discourse On identifying basic discourse units in speech: theoretical and empirical issues Liesbeth Degand and Anne Catherine Simon Electronic version URL: http://journals.openedition.org/discours/5852 DOI: 10.4000/discours.5852 ISSN: 1963-1723 Publisher: Laboratoire LATTICE, Presses universitaires de Caen Electronic reference Liesbeth Degand and Anne Catherine Simon, « On identifying basic discourse units in speech: theoretical and empirical issues », Discours [Online], 4 | 2009, Online since 30 June 2009, connection on 10 December 2020. URL : http://journals.openedition.org/discours/5852 ; DOI : https://doi.org/ 10.4000/discours.5852 Discours est mis à disposition selon les termes de la licence Creative Commons Attribution - Pas d'Utilisation Commerciale - Pas de Modification 4.0 International. Discours 4 | 2009, Linearization and Segmentation in Discourse (Special issue) On identifying basic discourse units in speech: theoretical and empirical issues Liesbeth Degand1,2, Anne Catherine Simon2 1FNRS, 2Université catholique de Louvain Abstract: In spite of its crucial role in discourse segmentation and discourse interpretation, there is no consensus in the literature on what a discourse unit is and how it should be identified. Working with spoken data, we claim that the basic discourse unit (BDU) is a multi-dimensional unit that should be defined in terms of two linguistic criteria: prosody and syntax. In this paper, we explain which criteria are used to perform the prosodic and syntactic segmentation, and how these levels are mapped onto one another. We discuss three types BDUs (one-to-one, syntax-bound, prosody- bound) and open up a number of theoretical issues with respect to their function in discourse interpretation.
    [Show full text]
  • Lecture Notes
    CSCI E-84 A Practical Approach to Data Science Ramon A. Mata-Toledo, Ph.D. Professor of Computer Science Harvard University Unit 1 - Lecture 1 January, Wednesday 27, 2016 Required Textbooks Main Objectives of the Course This course is an introduction to the field of data science and its applicability to the business world. At the end of the semester you should be able to: • Understand how data science fits in an organization and gather, select, and model large amounts of data. • Identify the appropriate data and the methods that will allow you to extract knowledge from this data using the programming language R. What This Course is NOT is an in-depth calculus based statistic research environment . What is this course all about? It IS is a practical “hands-on approach” to understanding the methodology and tools of Data Science from a business prospective. Some of the technical we will briefly consider are: • Statistics • Database Querying • SQL • Data Warehousing • Regression Analysis • Explanatory versus Predictive Modeling Brief History of Data Science/Big Data The term data science can be considered the result of three main factors: • Evolution of data processing methods • Internet – particularly the Web 2.0 • Technological Advancements in computer processing speed/storage and development of algorithms for extracting useful information and knowledge from big data Brief History of Data Science/Big Data (continuation) However, “…Already seventy years ago we encounter the first attempts to quantify the growth rate in the volume of data or what has popularly been known as the “information explosion” (a term first used in 1941, according to the Oxford English Dictionary).
    [Show full text]
  • [0470848499]Large-Scale Software Architecture.Pdf
    Y L F M A E T Team-Fly® Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Large-Scale Software Architecture Large-Scale Software Architecture A Practical Guide using UML Jeff Garland CrystalClear Software Inc. Richard Anthony Object Computing Inc. Copyright # 2003 by John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) 1243 779777 Email (for orders and customer service enquiries): [email protected] Visit our Home Page on www.wileyeurope.com or www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the publication. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to [email protected], or faxed to (+44) 1243 770571. Neither the authors nor John Wiley & Sons, Ltd accept any responsibility or liability for loss or damage occasioned to any person or property through using the material, instructions, methods or ideas contained herein, or acting or freraining from acting as a result of such use.
    [Show full text]
  • Download Full Book
    Introduction to Computing Explorations in Language, Logic, and Machines David Evans University of Virginia For the latest version of this book and supplementary materials, visit: http://computingbook.org Version: August 19, 2011 Attribution-Noncommercial-Share Alike 3.0 United States License Contents 1 Computing 1 1.1 Processes, Procedures, and Computers . 2 1.2 Measuring Computing Power . 3 1.2.1 Information . 3 1.2.2 Representing Data . 8 1.2.3 Growth of Computing Power . 12 1.3 Science, Engineering, and the Liberal Arts . 13 1.4 Summary and Roadmap . 16 Part I: Defining Procedures 2 Language 19 2.1 Surface Forms and Meanings . 19 2.2 Language Construction . 20 2.3 Recursive Transition Networks . 22 2.4 Replacement Grammars . 26 2.5 Summary . 32 3 Programming 35 3.1 Problems with Natural Languages . 36 3.2 Programming Languages . 37 3.3 Scheme . 39 3.4 Expressions . 40 3.4.1 Primitives . 40 3.4.2 Application Expressions . 41 3.5 Definitions . 44 3.6 Procedures . 45 3.6.1 Making Procedures . 45 3.6.2 Substitution Model of Evaluation . 46 3.7 Decisions . 48 3.8 Evaluation Rules . 50 3.9 Summary . 52 4 Problems and Procedures 53 4.1 Solving Problems . 53 4.2 Composing Procedures . 54 4.2.1 Procedures as Inputs and Outputs . 55 4.3 Recursive Problem Solving . 56 4.4 Evaluating Recursive Applications . 64 4.5 Developing Complex Programs . 67 4.5.1 Printing . 68 4.5.2 Tracing . 69 4.6 Summary . 73 5 Data 75 5.1 Types . 75 5.2 Pairs .
    [Show full text]
  • Storage: Association Networks Association Networks: a Model That
    LP 8C retrieval 1 3/7/2017 Storage: Association Networks Association networks: A model that describes units of information in long term memory as being organized in a complex network of associations. Notice the relation to elaborative rehearsal. LP 8C retrieval 2 3/7/2017 Broken Associations Make Retrieval Difficult LP 8C retrieval 3 3/7/2017 Schemas and Encoding Schemas: Cognitive structures that help us perceive, organize, process and use information ( page 280). In the following example, a schema helps organize the seemingly random and obscure statements. Instructions: Take a minute to read through this paragraph. After a minute, try to recall as much information about the paragraph as you can. Do the best you can, exact word for word recall is not required as long as it is close. The procedure is actually quite simple. First arrange things into different groups. Of course, one pile may be sufficient depending on how much there is to do. If you have to go somewhere else due to lack of facilities that is the next step, otherwise you are pretty well set. It is important not to overdo things. That is, it is better to do too few things at once than too many. In the short run this may not seem important but complications can easily arise. A mistake can be expensive as well. At first, the whole procedure will seem complicated. Soon, however, it will become just another facet of life. It is difficult to foresee any end of the necessity for this task in the immediate future, but then one never can tell.
    [Show full text]
  • Megabyte from Wikipedia, the Free Encyclopedia
    Megabyte From Wikipedia, the free encyclopedia The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: 1 048 576 bytes (220) generally for computer memory;[1][2] and one million bytes (106, see prefix mega-) generally for computer storage.[1][3] The IEEE Standards Board has decided that "Mega will mean 1 000 000", with exceptions allowed for the base-two meaning.[3] In rare cases, it is used to mean 1000×1024 (1 024 000) bytes.[3] It is commonly abbreviated as Mbyte or MB (compare Mb, for the megabit). Multiples of bytes Contents SI decimal prefixes Binary IEC binary prefixes Name Value usage Name Value 1 Definition (Symbol) (Symbol) 2 Examples of use 3 10 10 3 See also kilobyte (kB) 10 2 kibibyte (KiB) 2 4 References megabyte (MB) 106 220 mebibyte (MiB) 220 5 External links gigabyte (GB) 109 230 gibibyte (GiB) 230 terabyte (TB) 1012 240 tebibyte (TiB) 240 Definition petabyte (PB) 1015 250 pebibyte (PiB) 250 exabyte (EB) 1018 260 exbibyte (EiB) 260 The term "megabyte" is commonly used to mean either zettabyte (ZB) 1021 270 zebibyte (ZiB) 270 10002 bytes or 10242 bytes. This originated as yottabyte (YB) 1024 280 yobibyte (YiB) 280 compromise technical jargon for the byte multiples that needed to be expressed by the powers of 2 but lacked See also: Multiples of bits · Orders of magnitude of data a convenient name. As 1024 (210) approximates 1000 (103), roughly corresponding SI multiples began to be used for binary multiples.
    [Show full text]