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ALAGAPPA UNIVERSITY [Accredited with ‘A+’ Grade by NAAC (CGPA:3.64) in the Third Cycle and Graded as Category–I University by MHRD-UGC] (A State University Established by the Government of Tamil Nadu) KARAIKUDI – 630 003 Directorate of Distance Education M.Sc. [Computer Science] II - Semester 341 21 COMPUTER SYSTEM ARCHITECTURE Reviewer Assistant Professor, Dr. M. Vanitha Department of Computer Applications, Alagappa University, Karaikudi Authors Dr. Vivek Jaglan, Associate Professor, Amity University, Haryana Pavan Raju, Member of Institute of Institutional Industrial Research (IIIR), Sonepat, Haryana Units (1, 2, 3, 4, 5, 6) Dr. Arun Kumar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Kuldeep Singh Kaswan, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Dr. Shrddha Sagar, Associate Professor, School of Computing Science & Engineering, Galgotias University, Greater Noida, Distt. Gautam Budh Nagar Units (7, 8, 9, 10.9, 11.6, 12, 13, 14) Vivek Kesari, Assistant Professor, Galgotia's GIMT Institute of Management & Technology, Greater Noida, Distt. Gautam Budh Nagar Units (10.0-10.8.4, 10.10-10.14, 11.0-11.5, 11.7-11.11) "The copyright shall be vested with Alagappa University" All rights reserved. No part of this publication which is material protected by this copyright notice may be reproduced or transmitted or utilized or stored in any form or by any means now known or hereinafter invented, electronic, digital or mechanical, including photocopying, scanning, recording or by any information storage or retrieval system, without prior written permission from the Alagappa University, Karaikudi, Tamil Nadu. Information contained in this book has been published by VIKAS® Publishing House Pvt. Ltd. and has been obtained by its Authors from sources believed to be reliable and are correct to the best of their knowledge. However, the Alagappa University, Publisher and its Authors shall in no event be liable for any errors, omissions or damages arising out of use of this information and specifically disclaim any implied warranties or merchantability or fitness for any particular use. Vikas® is the registered trademark of Vikas® Publishing House Pvt. Ltd. VIKAS® PUBLISHING HOUSE PVT. LTD. E-28, Sector-8, Noida - 201301 (UP) Phone: 0120-4078900 Fax: 0120-4078999 Regd. Office: A-27, 2nd Floor, Mohan Co-operative Industrial Estate, New Delhi 1100 44 Website: www.vikaspublishing.com Email: [email protected] Work Order No. AU/DDE/DE1-15/Printing of Course Materials/2020 Dated 05.02.2020 Copies-200 SYLLABI-BOOK MAPPING TABLE Computer System Architecture BLOCK I: Fundamentals Unit 1: Introduction Unit 1: Introduction : Definition, trends, power in IC, cost (Pages 1-18) Unit 2: Performance : Dependability, measuring, reporting and Unit 2: Performance summarizing performance (Pages 19-34) Unit 3: Quality: Quality principles of computer design, performance Unit 3: Quality of Computer Design (Pages 35-42) BLOCK II : ILP Concepts Unit 4: Introduction: concepts and challenges, Basic computer Unit 4: Instruction Level Parallelism techniques for exposing ILP, reducing branch costs with prediction, (Pages 43-52) data hazards Unit 5: Scheduling Unit 5: Scheduling : dynamic scheduling, hardware based speculation, (Pages 53-70) multiple issue and static scheduling, advanced techniques for instruction Unit 6: Limitations of ILP delivery and speculation (Pages 71-78) Unit 6: Limitations of ILP: hardware and software speculation, multithreading BLOCK III : Thread Level Parallelism Unit 7: Multiprocessor and thread level parallelism: Introduction, Unit 7: Multiprocessor and Thread symmetric shared memory architecture Level Parallelism Unit 8: Performance and architectures: performance of symmetric (Pages 79-94) shared memory multiprocessors, Distributed shared memory Unit 8: Performance and Architectures architectures (Pages 95-102) Unit 9: Synchronization models: synchronization, model of memory Unit 9: Synchronization Models consistency, cross cutting issues (Pages 103-108) BLOCK IV : Memory Hierarchy Design Unit 10: Introduction to Memory Unit 10: Introduction : Optimization of cache performance, memory Organization technologyand optimizations (Pages 109-140) Unit 11: Protection: virtual memory and virtual machines Unit 11: Protection Unit 12: Issues : crosscutting issues in the design of memory hierarchies (Pages 141-162) Unit 12: Issues (Pages 163-166) BLOCK V : Storage Systems Unit 13: Introduction : advanced topics in Disk storage, real faults and Unit 13: Introduction to Storage failures, I/O performance, reliability measures and benchmarks Systems Unit 14: Issues : a little queuing theory, crosscutting issues, designing (Pages 167-180) and evaluating and I/O system, the Internet Archive Cluster Unit 14: Issues (Pages 181-192) CONTENTS BLOCK I: FUNDAMENTALS UNIT 1 INTRODUCTION 1-18 1.0 Introduction 1.1 Objectives 1.2 History of Computers 1.3 Computer Architecture 1.4 Answers to Check Your Progress Questions 1.5 Summary 1.6 Key Words 1.7 Self Assessment Questions and Exercises 1.8 Further Readings UNIT 2 PERFORMANCE 19-34 2.0 Introduction 2.1 Objectives 2.2 Factors for Measuring Performance 2.3 Dependability and Measuring Performance 2.4 Summarizing Performances 2.5 Answers to Check Your Progress Questions 2.6 Summary 2.7 Key Words 2.8 Self Assessment Questions and Exercises 2.9 Further Readings UNIT 3 QUALITY OF COMPUTER DESIGN 35-42 3.0 Introduction 3.1 Objectives 3.2 Quality Principles and Performance 3.3 Answers to Check Your Progress Questions 3.4 Summary 3.5 Key Words 3.6 Self Assessment Questions and Exercises 3.7 Further Readings BLOCK II: ILP CONCEPTS UNIT 4 INSTRUCTION LEVEL PARALLELISM 43-52 4.0 Introduction 4.1 Objectives 4.2 Concepts and Challenges 4.3 Compiler Techniques 4.4 Reducing Branch Costs 4.5 Data Hazards 4.6 Answers to Check Your Progress Questions 4.7 Summary 4.8 Key Words 4.9 Self Assessment Questions and Exercises 4.10 Further Readings UNIT 5 SCHEDULING 53-70 5.0 Introduction 5.1 Objectives 5.2 Dynamic Scheduling 5.2.1 Scoreboard 5.2.2 Tomasulo Algorithm 5.2.3 Difference Between Scoreboard and Tomasulo Algorithm 5.3 Hardware Based Speculation 5.4 Multiple Issue and Static Scheduling 5.5 Advanced Techniques for Instruction Delivery and Speculation 5.5.1 Increasing Instruction Fetch Bandwidth 5.5.2 Branch-target Buffers 5.5.3 Integrated Instruction Fetch Units 5.5.4 Value Prediction 5.5.5 Address Aliasing Prediction 5.6 Answers to Check Your Progress Questions 5.7 Summary 5.8 Key Words 5.9 Self Assessment Questions and Exercises 5.10 Further Readings UNIT 6 LIMITATIONS OF ILP 71-78 6.0 Introduction 6.1 Objectives 6.2 Hardware and Software Speculation 6.3 Multithreading 6.4 Answers to Check Your Progress Questions 6.5 Summary 6.6 Key words 6.7 Self Assessment Questions and exercises 6.8 Further Readings BLOCK III: THREAD LEVEL PARALLELISM UNIT 7 MULTIPROCESSOR AND THREAD LEVEL PARALLELISM 79-94 7.0 Introduction 7.1 Objectives 7.2 Multiprocessors 7.3 Thread Level Parallelism (Task Parallelism, Function Parallelism, Control Parallelism) 7.3.1 Parallel Architectures 7.4 Symmetric Shared Memory Architecture 7.5 Answers to Check Your Progress Questions 7.6 Summary 7.7 Key Words 7.8 Self Assessment Questions and Exercises 7.9 Further Readings UNIT 8 PERFORMANCE AND ARCHITECTURES 95-102 8.0 Introduction 8.1 Objectives 8.2 Performance of Symmetric Shared Memory Architectures 8.3 Distributed Shared Memory Architectures 8.4 Answers to Check Your Progress Questions 8.5 Summary 8.6 Key words 8.7 Self Assessment Questions and Exercises 8.8 Further Readings UNIT 9 SYNCHRONIZATION MODELS 103-108 9.0 Introduction 9.1 Objectives 9.2 Synchronization 9.3 Memory Consistency Models 9.4 Cross Cutting Issues 9.5 Answers to Check Your Progress Questions 9.6 Summary 9.7 Key Words 9.8 Self Assessment Questions and Exercises 9.9 Further Readings BLOCK IV: MEMORY HIERARCHY DESIGN UNIT 10 INTRODUCTION TO MEMORY ORGANIZATION 109-140 10.0 Introduction 10.1 Objectives 10.2 Memory Hierarchy Organization 10.3 Main Memory 10.3.1 Random Access Memory (RAM); 10.3.2 Read Only Memory (ROM) 10.4 Organization of Ram and Rom Chips 10.4.1 Memory Address Map; 10.4.2 Memory Connection to CPU 10.5 Auxiliary Memory 10.6 Associative Memory 10.7 Cache Memory 10.7.1 Basic Operation; 10.7.2 Performance 10.8 Mapping Process 10.8.1 Associative Mapping; 10.8.2 Direct Mapping 10.8.3 Set Associative Mapping; 10.8.4 Writing into Cache 10.9 Optimization of Cache Performance, Memory Technology and Optimization 10.10 Answers to Check Your Progress Questions 10.11 Summary 10.12 Key Words 10.13 Self Assessment Questions and Exercises 10.14 Further Readings UNIT 11 PROTECTION 141-162 11.0 Introduction 11.1 Objectives 11.2 Virtual Memory 11.2.1 Page Replacement 11.3 Memory Management Hardware 11.4 Direct Memory Access 11.5 Memory Management and System Performance 11.6 Virtual Machines 11.7 Answers to Check Your Progress Questions 11.8 Summary 11.9 Key Words 11.10 Self Assessment Questions and Exercises 11.11 Further Readings UNIT 12 ISSUES 163-166 12.0 Introduction 12.1 Objectives 12.2 Crosscutting Issues in the Design of Memory Hierarchy 12.3 Answers to Check Your Progress Questions 12.4 Summary 12.5 Key Words 12.6 Self Assessment Questions and Exercises 12.7 Further Readings BLOCK V: STORAGE SYSTEMS UNIT 13 INTRODUCTION TO STORAGE SYSTEMS 167-180 13.0 Introduction 13.1 Objectives 13.2 Storage Devices 13.2.1 Unit
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