Gordon Bell Bell’S Law for the Birth and Death of Computer Classes Sscs Nlfall08.Qxd 10/8/08 10:04 AM Page 2

sscs_NLfall08.qxd 10/8/08 10:04 AM Page 1 SSCSSSSCSSSSCCSS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS Fall 2008 Vol. 13, No. 4 www.ieee.org/sscs-news

Gordon Bell Bell’s Law for the Birth and Death of Computer Classes sscs_NLfall08.qxd 10/8/08 10:04 AM Page 2

Editor’s Column Mary Y. Lanzerotti, IBM, [email protected]

s in the past, the Newsletter in 2006, it has been team has been on board with us the goal of our vision to provide the Society’s every step of the way to convey our Athis issue is 11,000 members with a publication vision to SSCS members through the to be a self-con- that celebrates not only their techni- use of specially-requested design ele- tained resource, with cal accomplishments but also their ments that he took the time to incor- original sources and personal achievements by reporting porate into each issue on our behalf. new contributions awards and publishing photographs, Thanks to Paul, the layout of each by experts describing the current personal commentary, and special issue has uniquely highlighted tech- state of affairs in technology in view historical and business articles to nical articles by and about our feature of the influence of the original provide coverage depth and breadth. author, members’ accomplishments papers and/or patents. Throughout the past two years, and work-in-progress, educational Since launching the redesign of Paul Doto of the IEEE Newsletter outreach and our Distinguished Lec- turer Program, Society news, and key IEEE Solid-State Circuits Society activities of our conferences and chapters throughout the world. SSCS News Administrative Committee Elected AdCom Members at Editor-in-Chief: President: Large To forward our vision, Paul went Mary Y. Lanzerotti Willy Sansen Terms to 31 Dec. 08: above and beyond to personally IBM T. J. Watson Research K. U. Leuven, Belgium Wanda K. Gass Center [email protected] Ali Hajimiri design full-color full-portrait covers [email protected] Fax: +32 16 321975 Paul J. Hurst based on author-supplied photo- Fax: +1 914 945 1358 Vice-President: Akira Matsuzawa graphs and creative twists on our Technology Editor: Bernhard Boser Ian Young society’s red and black theme. The Richard C. Jaeger University of California Alabama Microelectronics Berkeley, CA Terms to 31 Dec. 09: distinguishing elements of our pub- Center Auburn John J. Corcoran lication are its cover portraits, red- University, AL Secretary: Kevin Kornegay [email protected] David A. Johns Hae-Seung (Harry) Lee and-black cover theme and straight- University of Toronto Thomas H. Lee forward red title, black cover back- Tutorials Editor: Toronto, Ontario, Canada Jan Van der Spiegel Rakesh Kumar ground, and interior section color Technology Connexions Treasurer: Terms to 31 Dec. 10: highlights. We have personally Poway, CA Rakesh Kumar Terri S. Fiez [email protected] Technology Connexions Tadahiro Kuroda promised all Feature Authors that Poway, CA Bram Nauta their photos will appear on the Associate Editor for Jan Sevenhans Europe/Africa: Past- President: Mehmet Soyuer cover, and Paul’s efforts have ele- Tony Harker Richard C. Jaeger gantly fulfilled these agreements. Alba Centre Alba Campus Alabama Microelectronics Region 8 Representative: Livingston Scotland EH54 7EG Center Jan Sevenhans Thank you, Paul!! It has truly [email protected] University, AL been a pleasure working with you. Region 10 Representative: Associate Editor for the Far Other Representatives: C.K. Wang Please consider sending a thank East: Representative to Sensors you to Paul for all of his hard work Pengfei Zhang Council Chairs of Standing Beken Corporation Darrin Young Committees: and commitment to our society’s Shanghai, China Representative from CAS to Awards John J. Corcoran mission. His email address is [email protected] SSCS Chapters Jan Van der Spiegel Domine Leenaerts Education C.K. Ken Yang [email protected]; his webpage is News Editor: Representative to CAS from Meetings Bill Bidermann http://www.pauldoto.com. Katherine Olstein SSCS Membership Bruce Hecht IEEE SSCS Un-Ku Moon Nominations Richard C. Jaeger In this final issue of the SSCS News, [email protected] Publications Glenn Gulak we feature Gordon Bell, who has con- For detailed contact informa- tributed an extensive new Feature tion, see the Society e-News: Article entitled “Bell’s Law for the Birth www.ieee.org/portal/site/sscs and Death of Computer Classes: A Executive Director: Administrator: Theory of the Computer’s Evolution.” Anne O’Neill Katherine Olstein IEEE SSCS-West: IEEE SSCS Dr. Bell is a principal researcher at 1500 SW 11th Avenue #1801 445 Hoes Lane Microsoft Research in Silicon Valley, Portland, OR 97201 Piscataway, NJ 08854 Tel: +1 732 981 3400 Tel: +1 732 981 3410 working in the San Francisco Labora- Fax: +1 732 981 3401 Fax: +1 732 981 3401 tory. His home page is: http:// Email: [email protected] research.microsoft.com/~GBell. We For questions regarding Society business, contact the SSCS Executive Office. Contributions for the are delighted to have the opportunity Winter 2009 issue of the SSCS Magazine must be received by 8 November 2008 at the SSCS Execu- to present Dr. Bell and his work. tive Office. A complete media kit for advertisers is available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS. continued on page 4

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Photo of Gordon Bell

Fall 2008 Volume 13, Number 4 Editor’s Column ...... 2 President’s Message ...... 4 A Returnee from the US Becomes Entrepreneur in China, Pengfei Zhang, Associate Editor for the Far East ...... 5 Solid-State Circuits Magazine and Redesigned Website to Launch in 2009, Anne O’Neill, SSCS Executive Director ...... 7 TECHNICAL LITERATURE Bell’s Law for the Birth and Death of Computer Classes: A Theory of the Computer’s Evolution, Gordon Bell ...... 8 Advances in Ultra-Low Power Design, Joyce Kwong and Anantha Chandrakasan 20 Gigasensors for an Attoscope: Catching Quanta in CMOS, Erik H. M. Heijne . 28 Microwatt Switched Capacitor Circuit Design: Prepared for a Summer Course at K.U. Leuven, 1981, Eric Vittoz ...... 35

PEOPLE 15 Ankush Goel and Shih-An Yu Receive SSCS Predoctoral Fellowships for 2008-2009, John Corcoran ...... 49 IEEE DL Vojin Oklobdzija Visits Istanbul, Izzet Cem Goknar ...... 50 Twenty New Senior Members Elected ...... 51 Tools: Tips for Making Writing Easier, Part 3: Focus on Your Key Message, Peter and Cheryl Reimold ...... 51

CONFERENCES 28 ISSCC 2009 Preview, Anne O’Neill ...... 52 ISSCC 2009 Student Forum, Anne O’Neill ...... 52 4th Asian Solid-State Circuits Conference – Digital Convergence for a Ubiquitous Lifestyle, Koji Kito ...... 53 ICCAD Previews Novel Program, Juan-Antonio Carballo ...... 54 ICUWB 2009 to Focus on Microwave and Millimeter Wave Band Technology, Lutz Lampe ...... 55

CHAPTER NEWS 56 First IEEE COMCAS a Mega Event in Tel Aviv, Mark Ruberto, Shmuel Auster, Barry Perlman ...... 56 SSCS-Singapore Hosts 90 at ISSCC 2007 Tutorial Replay, Katherine Olstein ...... 58 SSCS-Taipei Offers Short Course on CMOS Single-chip Radio Design, Eric Tsung-Hsien Lin ...... 59 SSCS DL Stefan Rusu Speaks at Santa Clara Valley Chapter Meeting, Katherine Olstein ...... 59 SSCS-Scotland Sponsors Technical Meeting, Jim Brown ...... 60 60 Leuven Student Branch and SSCS Chapters Organize 2nd SSCS-Benelux Microelectronics Symposium, Cedric Walravens ...... 61 Preview of EDSSC2008 in Hong Kong, KP Pun ...... 61 IEEE SSCS Joint Chapter Formed in Penang, Malaysia, Booon Eu Seow ...... 62 Romania SSCS Chapter Formed to Promote Circuit Activities in Eastern Europe, Marcel D. Profirescu ...... 63

SSCS NEWS SSCS AdCom Endorses Newsletter-Magazine Conversion in Summer Meeting . . . . .65 65 CEDA Currents: IEEE/ACM MEMCODE Contest Update ...... 66

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President’s Message Willy Sansen, K. U. Leuven, [email protected]

Vision 2020 mentary materials such as an e-jour- also whether they will reduce atten- Some level of happiness and satis- nal (whatever that means) may all dance at the ISSCC in February. faction was reached around the have to be defined for a more effi- The Vision 2020 Task Force table at our AdCom meeting in San cient conference. [What is a more report was heard in San Francisco Francisco on August 18th because efficient conference? -- Will net- by the Task Force itself, the of the conversion of the Newsletter working prevail over technical data ISSCC Long Range Planning Com- into a Magazine. transfer, or vice-versa? What is the mittee and ISSCC executive com- Although this may seem trivial, it common content between a confer- mittees, the SSCS Meetings Com- is not. -- The Magazine will have ence paper and a journal paper? mittee chaired by Bill Bidermann much better quality in appearance What is the most efficient way to and the SSCS Publications com- and editing and, most important of put together a paper in terms of mittee chaired by Glenn Gulak all, will be saved from obsoles- information transfer? Can the repro- and, finally, by the AdCom itself. cence, since it may be consulted ducibility of the results be Dennis must be complimented through IEEE Xplore. enhanced? What can be done today for this task. His set of 27 slides The Solid-State Circuits Society rather than in 2020?] not only addresses the future of has worked hard to make this Task Force actions taken already the ISSCC but of all SSCS confer- happen. -- It has been in the will result in four experimental ences, and even conferences in minds and on the table of Anne satellite conferences that will be general. This set of slides will be O’Neill, Katherine Olstein, and, of held next year in the Far East, with- used as a blueprint for a number course, Mary Lanzerotti. They in three weeks of the ISSCC. They of action committees within the deserve to be complimented for will use the audio/video recorded Society. Obviously, they will also their achievement. sessions of the ISSCC and duplicate be used to tune results with rec- Discussions that peered further some of them within two to three ommendations generated by into our future, however, about the days for local engineering commu- other Societies. breathtaking recommendations of nities. The same audio/video Exciting times, indeed, as noted an ad hoc committee formed last recorded sessions are currently several times by Dick Jaeger, Past- year to explore how ISSCC might available under ISSCC’s “Replay-on- president of the SSCS. look in 2020 were overwhelming. Demand” program four months after According to the final report of the Conference. Its success is slow- ISSCC’s Vision 2020 Task Force pre- ly rising. Whether this product will sented in San Francisco six times in reduce conference attendance is an three days by Dennis Monticelli, the open question. Everybody is also Willy Sansen conference may go virtual, and e- anxious to see how successful the President papers, an e-digest, and comple- satellite conferences can be, and

Editor’s Column continued from page 2

We also print an original paper Capacitor Circuit Design,” in this issue. Dr. Zhang received his by Dr. Eric Vittoz, who was the Summer Course on Switched Ph.D. degree from Tsinghua Univer- Feature Author of our Summer ‘08 Capacitor Circuits, June 9-12, sity in Beijing, China, and was a issue, and two additional articles 1981, ESAT, Katholieke Uni- post-doctoral scientist in the UCLA about his work: versiteit Leuven, Heverlee, Electrical Engineering Department (1) “Advances in Ultra-Low-Voltage Belgium. from 1994 to 1996. In 2005, Dr. Design,” by Joyce Kwong and With this issue I would also like Zhang co-founded Beken Corpora- Anantha Chandrakasan (MIT); to welcome Pengfei Zhang as our tion in Shanghai. (2) “Gigasensors for an Attoscope,” new Associate Editor for the Far Thank you for reading the SSCS by Erik H. M. Heijne (CERN). East. Please take this opportunity to News! Please send comments and (3) E. Vittoz, “Microwatt Switched read his first column, which appears feedback to [email protected].

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A Returnee from the US Becomes Entrepreneur in China

Beken Corporation Founder Muses about the IC Community in Shanghai Pengfei Zhang, Beken Corporation, Shanghai [email protected]

s I walked out of that conference room in the Shanghai ARiverfront Business Hotel on 23 June, 2008, I was so impressed by the enthusiasm of the audience of 300 or more, and by the quality of their questions, that I turned to Prof. Ping Ko, the world’s authority on device modeling and a pioneer in China IC venture investment, who said smilingly, “Rather encouraging indeed!” That was not just another day. On June 23rd, most if not all analog IC designers, students and engineers had gathered in Shanghai to attend More than 300 engineers -- virtually the entire analog IC design community in a seminar on “A New Transceiver Shanghai – gathered in June to hear SSCS DL Behzad Razavi speak on “A New Transceiver Architecture for the 60-GHz Band.” Architecture for the 60-GHz Band,” by Prof. Behzad Razavi, a real celebrity to the Chinese IC design When I started Beken, recruiting to me for yet another reason, as community. seemed to be a daunting task, as the Beken was celebrating the ship- Held at Shanghai’s Zhangjiang Hi- talent pool was small at best and ment of the 10,000,000th piece of its tech Park, one of the best technolo- was hunted by an unprecedented very first product -- a 5.8-GHz gy incubators in China, the seminar number of design houses in the CMOS transceiver for wireless voice was co-sponsored by the Shanghai country. Three years had passed applications. Beken's 30-people Association for Science and Technol- and, judging from the size and cal- team had good reason to be proud ogy (SAST), the Shanghai Integrated iber of the audience in Prof. Razavi’s of what it had achieved within three Circuit Industry Association (SICA), seminar, I had no doubt that indus- years. and Beken Corporation (www. try and academia had both been As a returnee entrepreneur lead- bekencorp.com), an IC design house productive in spawning a new gen- ing one of the 500-and-more IC I founded three years ago after mov- eration of analog IC designers. design houses in China, needless to ing back to Shanghai from the States. June 23, 2008 was a special day say, I encountered challenges and

From left, Prof. Zi Xue, Vice General Secretary of Shanghai’s The author at Beken Corporation. Integrated Circuit Association, Prof. Ping Ko, Prof. Behzad Razavi, and Pengfei Zhang.

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difficulties constantly, and tastes of ing to deliver the most cost effec- ly the prospect of a China domestic success, too, sometimes with a bit of tive CMOS solution for then newly stock market and, more interesting- luck. It has been an exciting journey emerged IEEE 802.11a WLAN stan- ly, a Taiwan stock market (if opened that I am happy that I made the dard. That's where I began my to the mainland – a progressively decision to start. Nothing can com- RFIC design career, which led to a greater possibility, as the newly pare to the excitement of seeing design engineering manager's job elected leader in Taiwan seems to one's own design go into millions of at RF Micro Devices after its acqui- have more practical views). One of products that could indeed make sition of Resonext in 2002. Pursu- the corner stones of the prosperity people’s lives easier; this of course ing the dream of being part of the of China’s IC business is the unique is on top of the sense of fulfillment rapid development of China’s IC ecosystem in China’s Pearl River that a great team has been built and industry, I returned to Shanghai Delta -- a topic which will be the trained. with a group of friends after more focus of my attention in the 2009 So that's me. After graduating than ten years in the United Spring issue. from Tsinghua University in Bei- States. In the Summer of 2009, I plan to jing, China with a Ph. D. in micro- Deeply submerged in the world's share some observations on product electronics in 1994, I luckily had largest consumer market, inside a definition and marketing strategies the opportunity to work on shal- fast-growing design community with for an IC design house by focusing low junction formation and SOI intensive semiconductor supply on platforms. device modeling as a post doctor- chain contacts and an extremely In the Fall 2009 issue, I will be al fellow in Prof. Jason Woo's active capital market, I plan to examining the current IC design group at UCLA for two years report my first hand observations in industry in China and its competi- before I joined the industry, work- my column for readers of the IEEE tive dynamics, as well as the ing for Rockwell Semiconductor SSCS News. prospects of the China IC design Systems, Fujitsu Microelectronics In the winter issue of 2009, I will business. Inc., and later Resonext Communi- be looking at various exit options So stay tuned to the east side of cations, a startup in San Jose striv- for IC Investment in China, especial- the globe!

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Solid-State Circuits Magazine and Redesigned Website to Launch in 2009 Anne O’Neill, SSCS Executive Director, [email protected]

he SSCS Newsletter will morph First Issue to be Mailed in February organizers will include instructions into the IEEE Solid-State Cir- To maximize readability and reader for applying for SSCS technical co- cuits Magazine with the winter interest in content we’ve already sponsorship and how to use SSCS T come to appreciate, the award win- for publicity. issue of 2009, along with a revamped website that will debut in early ning IEEE Magazine staff has been December, 2008. engaged to design and produce our Platform for the Latest News new publication. The print quarterly The revamped SSCS website will New Magazine to Prioritize Education Magazine will continue to be mailed also feature breaking news about According to a survey in 2002, Soci- to SSCS members at no cost. The chapters, distinguished lectures, ety members want more education- first issue will be mailed in early and IEEE conference and field al material. The IEEE Solid-State Cir- February, just in time for the ISSCC. awards, as well as new IEEE mem- cuits Magazine will be the delivery The Magazine will also be hosted ber programs like Expert Now and vehicle for achieving that goal. in IEEE Xplore to provide readers IEEE.tv, which offer content by As the successor of the quarterly the advantages of searchability, RSS SSCS experts that can be challeng- SSCS Newsletter, each issue of the feeds, and email alerts when issues ing for members and potential Magazine will continue to be a self- are posted. members to find. Additional web contained resource for fundamental Non-member subscriptions in pages will provide useful “How to” theories and practical advances 2009 will cost $25 for the print pub- instructions for acquiring SSCS within the field of Integrated Cir- lication, $10 for the electronic mag- products such as ISSCC Replay on cuits (ICs); thanks to Newsletter Edi- azine in Xplore, and $30 for both. Demand DVD’s and other pub- tor-in–Chief, Mary Lanzerotti, the lished conference articles on disk. founding fathers of IC fundamentals Website Redesign Aims at Cutting After the launch of the new web- have been telling us how it all start- Edge site, sscs.org will be redirected to a ed. Mary was the driving force The Society’s new homepage will new host at IEEE headquarters but behind the evolution of the SSCS carry scrollable windows listing the will retain its name. News into a full-color, magazine- contents of the current issue of the style publication and will become Society’s flagship Journal of Solid- Quarterly Email Blasts Editor-in-Chief of the Magazine. State Circuits and the new Solid- Written at a tutorial level and ide- The SSCS membership email blast State Circuits Magazine. Best of all, will continue to provide announce- ally in narrative style, it will feature it will be linkable to any recent articles by leaders from industry, ments about important upcoming article a user selects from either conferences, application deadlines, academia and government that publication. explain historical milestones, cur- and member activities on a schedule that will be revised to maximize rent trends and future develop- One-Stop Shopping for Sponsored- ments to provide technical informa- their timeliness, apart from the Mag- Conference Information azine’s print calendar. More infor- tion to practitioners in the field who The Society’s revamped website otherwise may have insufficient mation will be announced in an will offer a comprehensive list of email blast in January. resources for keeping up to date. SSCS-sponsored meetings. Derived Exceeding the format of the from the IEEE conference database Newsletter, the Magazine will offer Feedback on a regular basis, it will ensure SSCS is interested in feedback from tutorials, special interest pieces, bib- consistent reporting and provide a liographies, and distillations of cut- the IC community about our Maga- “one-stop shop” for conference zine and website plans. Please dis- ting-edge work from scholarly pub- dates and locations, manuscript (or lications and technical conference cuss the changes we have described abstract) submission deadlines, and with any AdCom member, or send papers under the direction of Asso- links to conference home pages ciate Editors Dick Jaeger and Rakesh email to the Executive Director, and conference homepages in [email protected]. Kumar. Newly appointed Associate Xplore. Information for conference Editor Pengfei Zhang will provide local news from the Far East and Parallel Processors are the Future Because Smaller Isn’t Cool Australia (IEEE Region 10), while Associate Editor Tony Harker will Just as CPUs are becoming more parallel instead of smaller, so is news continue to represent Europe, the for the IC community. With the launch of our new Magazine and web- Middle East and Africa (IEEE Region site, everyone will be able to receive email alerts for the Society and print 8). Katherine Olstein will maintain versions of the JSSC and Solid-State Circuits Magazine. Or they can sim- coverage of SSCS chapter, member- ply check-out the Society website for links to it all. ship and conference news.

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TECHNICAL LITERATURE Bell’s Law for the Birth and Death of Computer Classes: A theory of the Computer’s Evolution1 Gordon Bell, Microsoft Research, Silicon Valley

Introduction the 3rd generation integrated circuits c1965-1990. In In 1951, a person could walk inside a computer and the second or current period, with the 4th generation, by 2010 a single computer (or “cluster’) with millions marked by the single processor-on-a-chip, evolving of processors has expanded to building size. More large scale integrated circuits (1971-present) CMOS importantly, computers are beginning to “walk” inside became the single, determinant technology for estab- of us . These ends illustrate the vast dynamic range lishing all computer classes. By 2010, scalable CMOS in computing power, size, cost, etc. for early 21st cen- microprocessors combined into powerful, multiple tury computer classes. processor clusters of up to a million independent A computer class is a set of computers in a partic- computing streams will certainly exist. Beginning in ular price range with unique or similar programming the mid 1980s, scalable systems have eliminated and environments (e.g. Linux, OS/360, Palm, Symbian, replaced the previously established, more slowly Windows) that support a variety of applications that evolving classes of the first period that used intercon- communicate with people and/or other systems. A nected bipolar and ECL ICs. Simultaneously smaller, new computer class forms roughly each decade estab- CMOS system-on-a-chip computer evolution has lishing a new industry. A class may be the conse- enabled low cost, small form factor or cell phone quence and combination of a new platform with a sized devices; PDA, cell phone, personal audio (and new programming environment, a new network, and video) device (PAD, PA/VD), GPS and camera con- new interface with people and/or other information vergence into a single platform has become the processing systems. worldwide personal computer, c2010. Dust sized Bell’s Law accounts for the formation, evolution, chips with a relatively small numbers of transistors and death of computer classes based on logic technol- enable the creation of ubiquitous, radio networked, ogy evolution beginning with the invention of the implantable, sensing platforms to be part of every- computer and the computer industry in the first gen- thing and everybody as a wireless sensor network eration, vacuum tube computers (1950-1960), second class. Field Programmable Logic Array chips with 10s- generation, transistor computers (1958-1970), through 100s of million cells exist as truly universal devices for the invention and evolutions of the third generation building “anything”. TTL and ECL bipolar Integrated Circuits (1965-1985), and the fourth generation bipolar, MOS and CMOS ICs Bell’s Law Origin & Motivation—The Computer His- enabling the microprocessor, (1971) represents a tory Museum, a By-product “break point” in the theory because it eliminated the In 1966, after six years as a computer engineer at Dig- other early, more slowly evolving technologies. ital Equipment Corporation, designing the first com- Moore’s Law (Moore 1965, revised in 1975) is an puters that established the minicomputer industry and observation about integrated circuit semiconductor the first timesharing computers, I joined the faculty of process improvements or evolution since the first IC Carnegie Mellon University. While mentoring me for chips, and in 2007 Moore extended the prediction for six years, Allen Newell and I wrote Computer Struc- 10-15 more years: tures: Readings and Examples (Bell & Newell, 1971) which posited notations to describe computers, their (t-1959) ≤ ≤ 16 Transistors per chip = 2 for 1959 t 1975; 2 behavior, and a taxonomy of computers including (t-1975)/1.5 ≥ x 2 for t 1975. their constituent components. Working with Newell stimulated a deep concern about the origin of com- In 2007, Moore predicted another 10-15 years of puters, classifying them (e.g. size, function, price, per- density evolution. The evolutionary characteristics of formance), and especially their evolution. Several of disks, networks, display, and other user interface tech- us wrote a paper (Bell et al, 1972) that showed com- nologies will not be discussed. However for classes to puters were falling into several different price bands form and evolve, all technologies need to evolve in over time, similar to other manufactured goods e.g. scale, size, and performance, (Gray, 2000) though at cars, planes and in addition, new computers were comparable, but their own rates! being introduced in lower price bands afforded by the In the first period, the mainframe, followed by min- logic and memory technology. imal computers, smaller mainframes, supercomputers, On returning to Digital in 1972 as its VP of Engi- and minicomputers established themselves as classes neering, I started collecting computer logic and mem- in the first and second generations and evolved with ory technology in my office. Simultaneously, Ken 1 An abridged version of this paper has appeared in the Communications of Olsen, acquired two historically important MIT com- the ACM, Vol. 51, No. 1, January 2008. puters: Whirlwind (c1951), and TX-0 (c1956) that

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TECHNICAL LITERATURE

should be preserved for history, and that might be part of some eventual display. In 1975, I curated an exhibit of logic and memory in a converted coat clos- et of Digital’s main office building, Maynard, MA that eventually moved and occupied the lobby of at Marl- boro MA. Maurice Wilkes opened the Digital Com- puter Museum there in 1979. As head of engineering and curator of a potential Computer Museum, I first spoke at MIT and else- where (Bell, 1972) about the future of computing based on logic technology. It also became clear that once established, a class stays roughly constant price. Figure 1. Taxonomy of computer functions (applications) I used this basic idea to look back in time to create taxonomy divided into personal and non-personal, i.e. early generations: manual (1600-1800), mechanical institutional infrastructure computers that carry out calcu- (1800-1890), electro-mechanical (1890-1930, vacuum lation, record keeping and transaction processing, net- tube (1930-1960), transistor (1959-1966), integrated working and personal communication (e.g. word process- circuit 1966-1990), microprocessor (1971-present). In ing, email, web), control, personal health, and entertain- 1980 I gave a talk at Stanford’s First Forsythe Lecture, ment functions. Note the convergences: personal media “Generating Computer Generations” describing my device, PDA, camera, cell phone become the Smart Phone; theory on computer classes based on structure, tech- Entertainment devices of TV, Media Centers & Servers. nology, need, and actual use that has since been The class creation, evolution, and dissolution refined as I describe. process can be seen in the three design styles and The museum became a public 501c(3) institution price trajectories and one resulting performance tra- when it opened in Boston in 1983. In 1995 the arti- jectory that threatens higher priced classes: an facts moved to Silicon Valley, as the Computer Histo- established class tends to be re-implemented to ry Museum, Mountain View, CA. maintain its price, providing increasing performance; minis or minimal cost computer designs are Bell’s Law created by using the technology improvements to A computer class is a set of computers in a particu- create smaller computers used in more special ways; lar price range defined by: a programming environ- supercomputer design, i.e. the largest computers at ment e.g. Linux, Windows to support a variety of a given time, come into existence by competing and applications including embedded apps; a network; “pushing technology to the limit” to meet the and user interface for communication with other unending demand for capability; and the inherent information processing systems including people increases in performance at every class, including and other information processing systems. A class just constant price, threaten and often subsume establishes a horizontally structured industry com- higher priced classes. posed of hardware components through operating systems, languages, application programs and unique content e.g. databases, games, pictures, songs, video that serves a market through various distribution channels. The universal nature of stored program computers is such that a computer may be programmed to replicate function from another class. Hence, over time, one class may subsume or kill off another class. Computers are generally created for one or more basic information processing functions– storage, computation, communication, or control (see Figure 2. evolving computer classes based on technology Figure1 Taxonomy). Market demand for a class and and design styles: 1. constant price, INcreasing Perfor- among all classes is fairly elastic. In 2010, the num- mance; 2. sub-class, lower price and performance to ber of units sold in classes vary from 10s, for com- extend range; 3. supercomputer – largest computers that puters costing around $100 million to billions for can be built that extend performance; and 4. new, mini- small form factor devices e.g. cell phones selling for mal, order of magnitude lowe priced class formations under $100. Costs decline by increasing volume every decade. through manufacturing learning curves (i.e. dou- All of the classes taken together that form the bling the total number of units produced result in computer and communications industry shown in cost reduction of 10-15%). Finally, computing Figure 2, behave generally as follows: resources including processing, memory, and net- 1. Computers are born i.e. classes come into exis- work are fungible and can be traded off at various tence through intense, competitive, entrepre- levels of a computing hierarchy e.g. data can be neurial action over a period of 2-3 years to held personally or provided globally and held on occupy a price range, through the confluence the web. of new hardware, programming environments,

TECHNICAL LITERATURE

networks, interfaces, applications, and distribu- of a small fractional part of the state-of-the-art tion channels. During the formation period, 10s chips. For example, the 100 fold increase in to 100s of companies compete to establish a component density per decade enables smaller market position. After this formative and rapid chips, disks, screens, etc. at the same function- growth period, 2 or 3, or a dozen primary com- ality of the previous decade especially since panies remain as a class reaches maturity powerful microprocessor cores e.g. the ARM depending on the class volume. use only a few <100,000 transistors versus over 2. A computer class, determined by a unique price a billion for the largest Itanium derivatives. range evolves in functionality and gradually Minimal computers design. Building the small- expanding price range of 10 maintains a stable est possible computer accounts for the creation market. This is followed by a similar lower of computers that were used by one person at priced sub-class that expands the range anoth- a time and were forerunners of the workstation er factor of 5 to 10. Evolution is similar to New- e.g. Bendix G-15 and LGP 30 in 1955, but the ton’s First Law (i.e. bodies maintain their first truly personal computer was the 1962 Lab- motion and direction unless acted on external- oratory Instrument Computer (LINC). LINC was ly). For example, the “mainframe” class was a self-contained computer for an individual’s established in the early 1950s using vacuum sole use with appropriate interfacial hardware tube technology by Univac and IBM and func- (e.g. keyboards, displays), program/data filing tionally bifurcated into commercial and scien- system, with interactive program creation and tific applications. Constant price evolution fol- execution software. Digital Equipment’s PDP-1 lows directly from Moore’s Law whereby a (1961), followed by its more “minimal” PDP-5 given collection of chips provide more transis- & 8 established the minicomputer class that tors and hence more performance. were predominately designed for embedded A lower entry price, similar characteristics applications. sub-class often follows to increase the class’s System-on-a-Chip (SOCs) use a fraction of a price range by another factor of 5 to 10, attract- chip for the microprocessor(s) portion or ing more usage and extending the market. For “cores” to create classes and are the basis of example, smaller “mainframes” existed within 5 fixed function devices and appliances begin- years after the first larger computers as sub- ning in the mid 1990s. These include cameras, classes. cell phones, PDAs, PAD (personal audio & 3. Semiconductor density and packaging inher- video devices) and their convergence into a ently enable performance increase to support a single cell phone sized device (CPSD) or small trajectory of increasing price and function form factor (SFF) package. This accounts for 3.1 Moore’s Law single chip evolution, or the PC’s rapidly evolving microprocessor’s abil- microprocessor computer evolution after ity to directly subsume the 1980’s workstation 1971 enabled new, higher performing class by 1990. and more expensive classes. The initial 5. Computer classes die or are overtaken by lower introduction of the microprocessor at a priced, more rapidly evolving general purpose substantially lower cost accounted for computers as the less expensive alternatives formation of the initial microcomputer operating alone, combined into multiple that was programmed to be a calculator. shared memory micro-processors, and multiple This was followed by more powerful, computer clusters. Lower priced platforms more expensive classes forming includ- result in more use and substantially higher vol- ing the home computer, personal com- ume manufacture thereby decreasing cost puter, workstation, the shared micro- while simultaneously increasing performance computer, and eventually every higher more rapidly than higher priced classes. class. 5.1 Computers can be combined to form a 3.2 The supercomputer class c1960 was single, shared memory computer. A established as the highest performance “multi” or multiple CMOS microproces- computer of the day— however, since sor, shared memory computer displaced the mid-1990s supercomputers are bipolar minicomputers c1990 and main- formed by combining the largest num- frames c1995, and formed a component ber of high performance computers to for supercomputers. form a single, clustered computer sys- 5.2 Scalable, multiple computers can be net- tem in a single facility. In 2010 over a worked into arbitrary large computer to million processors will likely constitute form “clusters “that replace custom ECL a cluster. Geographically coupled com- and CMOS vector supercomputers puters including GRID computing e.g. beginning mid 1990s simply because SETI@home are outside the scope. arbitrarily large computers can be creat- 4. Approximately every decade a new computer ed. Clusters of multiprocessors were class forms as a new “minimal” computer called constellations; clusters using low either through using fewer components or use latency and proprietary networks are

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MPPs (massively parallel processors). The taxonomy is divided first into personal and 5.3 Generality ALWAYS Wins! A computers non-personal or invisible and shared, institutional created for a particular, specialized infrastructure systems that would be operated function e.g. word processing, interpret- within or for a company, government or institution ing a language, used for a particular as a service. This dichotomy of personal versus application is almost certain to be taken shared; invisible versus institutional determines over by a faster evolving, general pur- characteristics of price and scale, programming pose computer. The computer’s univer- environment, user interface, and network. Func- sality property allows any computer to tion though critical, will be neglected. take on the function of another, given The named classes and their price range c2010 is sufficient memory and interfaces. given in Figure 3. David Nelson, founder of Apollo. 5.4 Small form factor devices subsume a and I (Nelson, Bell 1986) posited that the price of a personal computing functionality as computer was roughly $200 per pound. Figure 4 they take on the communications func- gives the introduction price and date of the first or tions of the PC (e.g. email and web defining computer of a class. Table 1 gives the browsing), given sufficient memory and defining constituent technologies, operating sys- interfaces. Small form factor devices or tems, languages, networks, and interfaces of the television sets or kiosks accessing various classes. supercomputers with large stores, sub- The discussion will use the aspects of Bell’s Law sume personal computing functionality. described above and follow a timeline of the class The large central stores retain personal formations beginning with the establishment of the information, photos, music, and video. first computer classes (mainframe, supercomputer, The paper will describe how these characteristics shared personal professional computers or worksta- of the classes account for the birth, growth, diminu- tions, and minicomputers) using vacuum tubes, tion, and demise of various parts of the computers transistors, and bipolar integrated circuits that con- and communications industry. tinue through the mid 1990s. The MOS microprocessor introduced in 1971 ultimately overtook Overview of the Birth and Death of the Computer bipolar by 1990 to establish a single line based on CMOS technology. Classes 1951-2010 Figure 1 is a computer function taxonomy based: The section is followed by the three direct and first on buyers/users and second, by application. indirect effects of Moore’s Law to determine classes: The information processing elements i.e. applica- 1 Microprocessor transistor/chip evolution c1971- tion functions are: memory or storage for record 1985 establish: calculators, home computers, keeping that was the province of IBM and other personal computers and workstations, and card tabulation equipment makers prior to the lower (than minicomputer) priced computers. computer’s invention; computation or calculation 2 “Minimal” designs establish new classes c1990 characterizing science and engineering use; net- that use a “fraction” of the Moore number. working and communication that provide the Microsystems evolution using fractional Moore’s interconnection infrastructure; control of other sys- Law sized SOCs enable small, lower perform- tems (e.g. process control); and interface with ing, minimal personal computer and communi- humans and other information processing entities. cation systems including PDAs, cameras, cell phones, personal audio/video devices. 3 Rapidly evolving microprocessors using CMOS and a simpler RISC architecture appear as the “killer micro” c1985 to have the same performance as supercomputers, mainframes, mini-supercomputers, super-minicomputers, and minicomputers built from slowly evolving, low density, custom ECL and bipolar integrated circuits. ECL survived in supercomputers the longest because of its speed and ability to drive the long transmission lines, inherent in large systems. In the end, CMOS density and faster system clock overtook ECL as shown in Figure 5. The “killer micro” enabled by fast floating point arithmetic, first subsumed the workstation followed by the minicomputer especially when combined to form the “multi” or multiple microprocessor shared memory computer c1985. “Multis” became the component for scalable clusters when interconnected by high speed, low latency networks. Clusters allow Figure 3. Computer Classes and their Price Range 2005

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arbitrarily large computers that are limited only by dreds of millions, of small form factor devices, customer budgets. Thus scalability allows every may evolve more rapidly to subsume a large frac- computer structure from a few thousand dollars to tion of personal computing. Finally tens of bil- several hundred million dollars to be arranged into lions of dust sized, embeddable wirelessly con- clusters built from the same components. nected platforms that connect everything are In the same fashion that killer micros sub- likely to be the largest class of all enabling the sumed all the computer classes by combining, it state of everything to be sensed, effected, and can be speculated that much higher volume, hun- communicated with.

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The Past: How we got here The Beginning (1951-1990): mainframe, supercomputer, shared personal workstation, and minicomputer classes By 1970, vacuum tube (50s), transistor (60s), and small scale integrated circuit (late 60s) technologies enabled the establishment of four classes of computers that continued almost without change until the 80s: 1. Mainframes for commercial, record keeping, etc. and mainframes for Scientific and Engi- neering Computation were the very first computers; a sub-class of smaller computers formed that were used in the same fashion. 2. Minimal design, small, shared computers that were used directly as personal workstations 3. Minimal computers for process and machine control, communication, and embedded apps 4. Supercomputers constructed at the limits of circuit, interconnect, and architectural complexity utilizing clock speed and parallelism Eckert and Mauchly, operating as the UNIVAC division of Remington Rand delivered the UNIVAC 1 as the earliest commercial computer in 1951, roughly concurrent with the British LEO (Lyons Electron- ic Office) computer, and followed two years later by the IBM 701 (1953) for scientific applications. These first computers with delay line and electrostatic Figure 4. Introduction price versus date of the first or early platforms to establish a computer class or lower priced (Williams Tube) memories of only a few thousand sub-class orginating from the same company or industry. words were priced at $1 million or more ($8.5 million in 2007 dollars) to establish the mainframe class. By 1955, IBM had introduced both scientific (701, 704) and commercial (702, 705) computers that were differentiated by their ability to deal with floating point data of high precision versus the predominately alphanumeric and decimal arithmetic operations typifying data processing. From the graph, the mainframe increased to $4 million and continued to maintain the price range. A set of smaller computers were introduced in the price $0.1- 1 million range e.g. IBM 1401 and 650 for departmental and smaller organization use. These could be classified as subclass of mainframes or super-minicomputers. During the mainframe’s formation, eight US and five? European companies competed to establish the class. The US Group was known as Snow White and the Seven Dwarfs or BUNCH (Burroughs, Univac now Unisys, NCR, CDC, Honeywell)+ GE & RCA. With IBM’s introduction of System 360 on April 7, 1964, the dominant architecture was established and will doubtlessly remain to run legacy applications “forever” – given the trillions of dollars of software and data that this ecosystem hosts. Small or minimal computers priced between Figure 5. Faster evolving CMOS microprocessors are able to overtake and eliminate slowly evolving TTL and ECL $60,000 to $120,000 that a person signed up for and bipolar integrated circuit based computer classes includ- used directly for calculation or personal computing ing minicomputers, superminicomputers, mini-supercom- at work were introduced beginning in the mid 1950s puters, mainframes, and supercomputers. A number of (Bendix G-15, Librascope LGP-30), as well as the companies built one or more Too many ECL computers transistorized IBM 1620 that dominated the class. In including CDC, Cray, DEC, Fujitsu, Hitachi, and IBM before 1961, the DEC PDP-1 was applied to telegraph line switching to ECL. message switching as a prelude to computer net-

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working, peripheral computers for mainframes (like camera evolve about as rapidly as Moore’s Law, the 1401 or CDC 160), and were used as prototypes requiring more memory and speed to handle the for timesharing system. images with constant response. Similarly, disk mem- The PDP-8, introduced in 1965 at a price of $18K ories have to evolve rapidly to store the higher res- is the first “minicomputer.” It was minimal, designed olution photos, higher quality videos, etc. as both the smallest computer that could be built Nathan’s Law, also attributed to Bill Gates, and as a component to be used for controlling other explains software’s increasing demand for devices e.g. process control, lab instruments, termi- resources: nal concentrators. On occasion it was used as a 1. Software is a gas. It expands to fill the con- workstation on a personal basis with an operating tainer it is in. system that was a pre-cursor to DOS. The PDP-8 2. Software grows until it becomes limited by had a dozen implementations following a minimal Moore’s Law. cost trajectory with single chip versions beginning 3. Software growth makes Moore’s Law possible in 1975 to both define and increase its marketabili- through the demand it creates; and ty including its use as a dedicated word processor 4. Software is only limited by human ambition to the early 1980s. During the minicomputer class and expectation. formation period, 92 companies formed to establish “Marketing” nominally fueled by user feedback the minicomputer class with only IBM and HP for more functionality, forms the critical link in sup- remaining by 2000 to make computers in this class port of Nathan’s Law that minimalist refer to as fea- albeit with substantially changed architectures. turitis, bloat, etc. enabling upgrades to support peri- Including DEC VAX in this class, the price range odic obsolescence. increased to cover a range of $10,000 to $1,000,000 We might expect to buy a new computer in three servers and covering the entire potential application years at 1/4 the price of today’s computer using space of the day. The most expensive VAXen, and chips that are 1/4 the size of an earlier model per- VAX clusters competed with IBM smaller System/360 haps from the same manufacturer. Why not? New class and sub-mainframes. microprocessors sell at the same or even a price The reliable and fast transistor circuitry c1960 premium because they have 4x the transistors, faster enabled a substantially larger number of compo- clock speed and deliver more performance. For nents to be integrated into a unified system, limited example, Intel and AMD are not inclined to build mostly by the maximum feasible selling price, archi- microprocessors with less transistors and lower cost tectural complexity, and interconnection density. because they don’t see such a market – and as such Early on, vying for the title of world’s fastest com- do not participate in establishing the new, lower puter, were the Manchester Atlas I and the IBM 7030 price classes. Also, a computer is made of other (“Stretch”), both introduced in 1961. Five years later, parts e.g. metal and power supplies that may the CDC 6600 supercomputer was introduced as the increase in price and act to hold the system price culmination of several years of effort by a small constant with only system manufacturing learning team led by Seymour Cray. It used about 500,000 curves left to decrease price. densely packaged silicon transistors and stunned The “numbers” support a next generation product the world with its performance—easily an order of of constant price and increasing performance, not magnitude faster than any computer shipping at the one of decreasing prices and constant performance. time or even being contemplated. “Cray sytle” com- Assume the total cost of ownership is at least 3x the puters based on parallelism functional units, fol- computer’s sales price, and for a computer of per- lowed by vector processors continued relatively formance = 4. unchallenged for 30 years. In the mid-90s, things performance/total cost = 4/4 had changed somewhat architecturally but bipolar Assume a new, constant price, double perform- technology still reigned. The fastest machines were ance computer performs at 4 x 2 or 8, then shared memory, vector processors using small scale Performance/total cost = 8/4 or 2. Contrast this ECL ICs. Successful challengers at Fujitsu and NEC with a constant performance computer of 4, whose uses the “Cray” formula to build even faster price is just 3/4, giving a total cost of 3.75 machines with the NEC Earth Simulator holding the Performance/Total cost = 4/3.75 or 1.07 title from 2002-2005. The final and most important incentive to hold price constant and provide more capability is to Why Computer Classes Evolve at Constant Price, retain a user’s substantial investment in legacy applications and data that have been created togeth- Increasing Performance Once a computer class forms, several factors deter- er with the implied user and organizational learning. mine the price of the “next” evolutionary model. The value of data is most likely to be 10-100 times Building the next model in 3-5 years with chips that the hardware cost. A user retains an old computer have 4 to 6 times more transistors is the natural pre- unless it is unreliable, or there is a substantial dicted progression of Moore’s Law. increase in functionality – as long as the new model Increases in processing power and memory size accepts legacy apps and data. The cost to switch to are essential for the new data-types such as music, another computer, even with the same capability is photos, and data-bases. The number of pixels per so high that the incentive must result in a significant

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benefit as the above numbers show. Microprocessor Evolution c1971-1985: Personal Com- Finally, most goods e.g. cars, construction materi- puting (Calculators, Home Computers, Personal Com- al, energy, and food not subject to CMOS integra- puters, Workstations, and Game Console Platforms) tion, increase in price with inflation (Table 2). How- Calculators, home computers, personal computers, ever, computers have defied inflation -- the 1984, 9” and workstations were established as classes as the monochrome 128 Kbyte, single floppy, integrated processor on a chip evolved to have more transistors $2495, Apple Macintosh costs $1500; in 2007, the with wide data paths and large address spaces as same, as a 13” color portable with 1 GB memory shown in Figure 6. and 80 GB disk. In 1971, Intel’s 4004 with 4 bit data path and ability to address 4KB was developed and programmed to Table 2. Consumer Price Index showing Buying Power since be the Busicom Calculator; instead of developing a the introduction of computers in 1951 Versus $1 in 2007. special chip as had been customary to implement cal- 1950 1960 1970 1980 1990 2000 2007 culators, a program was written for the 4004 for it to 8.5 6.9 5.3 2.5 1.6 1.2 1 “behave” as or “emulate” a calculator. The 4004 with a 4 bit data path was not suited for storing text and Microprocessors 1971: The Technological Force for larger numbers other than in a serial fashion, although New Classes in the Second Period it was used for numerous applications and to spawn Figure 6 shows the microprocessors derived directly an “embedded computer” market just as the mini- from the growth of transistors/chip beginning in 1971. computer had done a decade earlier. It shows the trajectory of microprocessors from a 4-bit In 1972, Intel introduced the 8008 microprocessor data path through, 8-, 16-, 32-, and 64-bit data paths coming from the Datapoint terminal requirement, and address sizes. The figure shows a second path – with 8 bit data path and ability to access 16 KB that the establishment of “minimal” computers that use less allowed R2E’s Micral computer (France) and Scelbi to than 50 thousand transistors for the processor, leaving build limited, programmable computers followed by the remainder of the chip for memory and other func- more powerful 8080-based systems that M.I.T.S. used tions e.g. radio, sensors, analog I/O enabling the com- to introduce its “Atltair” personal computer kit in plete SOC. Increased performance, not shown in the 1975, that incidentally stimulated Gates and Allen to figure, is a third aspect of Moore’s Law that allows the start Microsoft. The more powerful and upward com- “killer micro” formation to subsume all the other, high patible Zilog Z80 was useful in helping to establish a performance classes that used more slowly evolving personal computing platform. In 1977, the 16-bit 6502 bipolar TTL and ECL ICs (Figure 5). The final section microprocessor and higher-capacity memory chips will discuss the challenge of having a single chip with enabled personal computers for use in the home or billions of computing elements (functional units, classroom built by Apple, Commodore and Radio processors, computers, wireless links and other I/O). Shack—computers that sold in the tens of millions because people bought them to use at home versus corporate buyers. By 1979, the VisiCalc spreadsheet ran on the Apple II establishing it as a “killer app” for personal computers in a work environment. Thus the trajectory went from a 4-bit data path and limited address space to a 16-bit data path with the ability to access 64KB of memory. This also demonstrates the importance of physical address as an architectural limit. In the paper on DEC’s VAX (Bell, Strecker 1975), we described the importance of address size on architecture: “There is only one mistake that can be made in a computer design that is difficult to recover from – not providing enough address bits for memory addressing and memory management…” The 8086/8088 of the first IBM PCs had a 20-bit, or 1MB address space, the operating system using the remaining 384KB. Concurrent with the introduction of the IBM PC, professional workstations were being created that used the Motorola 68000 CPU with its 32-bit data and address paths (4GB of maximum possible memory). Apple Computer used the Motorola “68K” in its Lisa and Macintosh machines. IBM’s decision to use the Figure 6. Moore’s Law that provides more transistors per lntel architecture with limited addressing, undoubt- chip, has resulted in creating the following computer class- edly had the effect of impeding the personal com- es: calcultaors, home computers, personal computers, work- puter by a decade as the industry waited for Intel to stations, “multis” to overtake minicomputers, and clusters evolve architecture to support a larger address and using multiple core, multi-threading to ovetake mainframes virtual memory space. Hundreds of companies start- and supercomputers.

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ed up to build Personal Computers (“PC-clones”) products eventually overtake the established, slowly based on the IBM PC reference design c1981. Dozens evolving classes served by sustaining technology. of companies also started to build workstations based From the mid 1980s till 2000, over 40 companies on a 68K CPU running the UNIX operating system. were established and wiped out attempting to exploit This was the era of “JAWS” (Just Another WorkSta- the rapidly evolving CMOS microprocessors by inter- tion) to describe efforts at Apollo, HP, IBM, SGI, SUN connecting them in various ways. Only Cray, HP, IBM, and others based on 32-bit versus 16-bit micro- SGI and SUN remain in 2007 to exploit massive par- processors and including specialized systems for allelism through running a single program on a large Word Processing (Wang, Xerox), Market Analysis number of computing nodes. (Metaphor), CAD (Intergraph, Daisy, Valid), and Let’s look at two potentially disruptive technolo- high-level programming (Lisp Machines and Symbol- gies, establishing new classes: ics). Virtually all of these “workstations” were elimi- The OLPC (One Laptop Per Child) project of nated by simple economics as the Personal Comput- Nicholas Negroponte aimed at a $100 PC (costing er--based on massive economies of scale and com- about $188 in 2007) is quite likely disruptive as a moditization of both the operating system and all “minimal” PC platform that relies on the internet for constituent hardware elements) evolved to have suf- storage of programs and data. Cost reduction is ficient power and pixels. achieved by substituting 500 MB of flash memory for disk, reduced screen size, small main memory, and built in mesh networking to reduce infrastruc- “Minimal” CMOS Microsystems on a Chip c1990 ture cost. An expected selling price of $200 with a Establish New Classes Using Smaller, Less Expen- $188 cost that is about half the price of the least sive, Chips expensive PCs in 2007, is characteristic of a new In 2007, many systems are composed of microproces- sub-class. OLPC will be an interesting development sor components or “cores” with less than 50,000 tran- since Microsoft’s Vista requires almost an order of sistors per microprocessor core at a time when the magnitude more system resources. leading edge microprocessors chips have a billion or The evolving small form factor devices such as more transistors cf Figure 6. Such cores using lower cell phones are likely to have the greatest impact cost, less than the state-of-the-art chips and highly- on personal computing, effectively creating a effective, rapid design tools allow new, minimal class- class. For perhaps most of the 4 billion non-PC es to emerge allow new, minimal classes to form. users, it becomes their personal computer and PDAs, cameras, cell phones, and personal audio & communicator, wallet... map, etc. since the most video devices have all been established using this common and often only use is of personal com- “minimal” computer design style based on small puters is for email and web browsing – both state- “cores”. In 1990, the Advanced RISC Machine (ARM) less applications. formed from a collaboration between Acorn and Apple as the basis for embedded systems that are Application of Bell’s Law-- Planning VAX and the used as computing platforms and achieve two billion VAX Strategy units per year in 2006. Other higher volume microsys- In 1975 when VAX was in the planning stage, I used tem platforms using 4-, 8-…64-bit architectures the theory of classes to posit a compatible line of including MIPS exist as core architectures for building computers that had the same instruction set and pro- such systems as part of the very large “embedded” gramming environment that could be used in a range market. of uses including personal computers, process control , departmental timesharing, and clusters for large Rapidly Evolving “Killer CMOS Micros” c1985 Over- scale apps. The planning was based on the different take Bipolar ICs to Eliminate Established Classes sized memories resulting in different prices according In the early 1980s, the phrase “killer micro” was to the following pricing model: introduced by the technical computing community as System Price = 5 x 3 x .04 x memory size/ 1.26 (t- they saw how the more rapidly evolving CMOS micro 1972) K$ would overtake bipolar based minis, mainframes, Where 5x: Memory is 20% of cost; 3x: DEC markup; and supers if they could be harnessed to operate as .04x: $ per byte; 26%: price change a single system and operate on a single program or Figure 7 shows the prices for systems of various workload. sized memories. The large price declines were in In the Innovator’s Dilemma, Christensen describes fact one of the root causes of the demise of Digital the death aspect basis of Bell’s Law by contrasting in the late 90s. In effect, the large memories two kinds of technologies. Sustaining technology required to maintain pricing in a price band provides increasing performance enabling improved required larger amounts of processing that were products at the same price as previous models using served by clusters of microprocessor based comput- slowly evolving technology; disruptive, rapidly evolv- ers connected as clusters. Another cause at DEC was ing technology provides lower priced, products that continuing with ECL at a time when CMOS overtook are non-competitive with higher priced sustaining it in speed and especially exorbitant cost when class to create a unique market space. Over time, the nearly zero cost, microprocessors were outperform- performance of lesser performing, faster evolving ing ECL.

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Figure 7. Original VAX Planing model Computer Prices versus time from 1975 showing different memory sizes and resulting prices 1964-1986. In 1998, the model was reviewed retrospecively. The price changes, though accurate, were so rapid to be unbelievable and hardly actionable.

The Challenge of Constant Price, 10-100 Billion improved user interface including speech pro- Transistors per Chip, Multi-threaded, Multi-proces- cessing for text to speech and spoken commands sors, for General Purpose Computing 4. Multi-core and multi-threaded processor evolu- The future is not at all clear how such large, leading tion for large, high performance scientific sys- edge chips will be used in general purpose comput- tems that are carefully programmed using FOR- ers as used at the desk top. As ever, the resilient and TRAN-MPI, as FORTRAN turns 50.Remodel the creative supercomputing and large scale service cen- desktop architectures at the language level to be ter communities will exploit the largest multi-core, able to highly parallelize apps using the vector- multi-threaded chips. There seems to be no upper ization and parallelization that has proven appli- bound these systems can utilize! cability in the multi-vector processor machines, However, without high volume manufacturing, the betting on the need virtuous cycle is stopped -- in order to get the cost 5. Develop image processing enabling “computers and benefit for clusters, a high volume personal com- to see” and be controlled by motion and emo- puter market must drive demand to reduce cost. In tion using hands and face. The Nintendo Wii 2007, the degree of parallelism for personal comput- seems to have something here. ing in non-gamer desktop systems such as Linux and 6. A BKA or “BIG KILLER APP” that exploits these Vista is nil either reflecting the impossibility of the structures, EVERYONE needs, and compatible task or our lack of creativity. with our PC environment. Several approaches for very large transistor count 7. Something BIG, based on a dramatic new way to i.e. 10 billion transistor chips with more than a few program e.g. Transactional Memories, Functional (e.g. 2-10) processors could be, in order of difficulty: Programming, block structured dataflow requir- 1. Small chips with only as many processors that ing changes in language, tools, training, and new can be gainfully employed e.g. 2-4 processors applications. Systems are being introduced such system with primary memory on a chip for sub- as Microsoft’s F# to test this approach, and if suc- stantially reduced lower priced systems and cessful imply a change akin to the introduction greater demands that either require or imply pro- of objects. Software objects, requiring new appli- portionally lower cost software cation architectures may be alternative way of 2. Graphics processing, currently handled by spe- thinking versus the FORTRAN-MPI model. cialized chips is perhaps the only well-defined 8. Abandoning general purposeness using FPGAs application that is clearly able to exploit or that are programmed using inherently parallel absorb unlimited parallelism in a scalable fash- hardware design languages like parallel C or Ver- ion for the most expensive PCs e.g. gaming, ilog that could provide universality that we have graphical design. In effect, this just cost reduces never before seen, and the system by eliminating graphics chips. Independent of how the chips are programmed, 3. Dedicated functional processing for networking, the biggest question is whether the high volume per-

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sonal computer market can exploit anything other by sensing and effecting is clearly a new class that has than the first three paths, and even those require care- been forming since 2002 with a number of new com- ful programming beyond 2007 operating systems. panies that are offering – “un wiring”, and hence Let’s apply the Carver Mead 11 year rule – the time reduced cost for existing apps e.g. process, building, from discovery and demonstration till use. Perhaps home automation and control. Standards surrounding the introduction of a few transactional memory sys- the 802.15.4 link that competes in the existing unli- tems have started the clock using a programming censed RF bands with 802.11xyz, Bluetooth, and methodology that claims to be more easily under- phone are being established. stood. A simpler methodology that can yield reliable New applications will be needed for wireless sen- designs by more programmers is essential in order to sor nets to become a true class versus just unwiring utilize these multiprocessor chips. the world. If, for example, these chips become part of In a way, the opportunity or rather need for paral- everything that needs to communicate in the whole IT lelism is reminiscent of the 1982 Japanese Fifth Gen- hierarchy, a class will be established. They carry out eration research effort based on parallelization, AI, three functions when part of a fixed environment or and PROLOG. (The Denelcor HEP was also installed a moving object: sense/effect; recording of the state of then.) This time, it’s not research. The problem needs a person or object (things such as scales, appliances, a tractable solution. Without it, Moore’s Law slows. switches, thermometers and thermostats) including its location and physical characteristics; and communication to the WiFi or other special infrastructure net- Will Small Form Factor Devices Impact Personal work for reporting. RFID is part of this potentially Computing? very large class of trillions. Just as “billions of clients Users are likely to switch classes when the perform- needed millions of servers” a trillion dust wireless ance and functionality of a lesser priced class is able sensing devices will be coupled to a billion other to satisfy their needs and still increase functionality. computers. Since the majority of PC use is for communication and web access, evolving a small form factor device as a Summary single communicator for voice, email, and web access Bell’s Law explains the history of the computing is quite natural. Two things will happen to accelerate industry based on the properties of computer classes the development of the class: people who have never and their determinants. The paper posits a general used or are without PCs will use the smaller, simpler theory for the creation, evolution, and death of vari- devices and avoid the PC’s complexity; and existing ous priced-based computer classes that have come PC users will adopt them for simplicity, mobility, and about through circuit and semiconductor technology functionality e.g. wallet for cash, GPS, single device. evolution from 1951. The exponential transistor den- We clearly see these small personal devices with sity increases forecast by Moore’s Law (1965,1975) annual volumes of several hundred million units being the principle basis for the rise, dominance, and becoming the single universal device evolving from death of computer classes after the 1971 micro- the phone, PDA, camera, personal audio/video processor introduction. Classes evolve along three device, web browser, GPS and map, wallet, personal paths: constant price and increasing performance of identification, and surrogate memory. an established class; supercomputers – a race to build With every TV, becoming a computer display, a the largest computer of the day; and novel, lower coupled SFF becomes the personal computer for the priced “minimal computers”. A class can be sub- remaining applications requiring large screens. Cable sumed by a more rapidly evolving, powerful, less companies will also provide access via this channel as expensive class given an interface and functionality. TV is delivered digitally. In 2010, the powerful microprocessor will be the basis for nearly all classes from personal computers Ubiquitous Wireless. WiFi, Cellular Services, and and servers costing a few thousand dollars to scala- Wireless Sensor Nets ble servers costing a few hundred million dollars. Unwiring the connection around the computer and Coming rapidly are billions of cell phones for per- peripherals, TV set, etc. by high speed radio links is sonal computing and the tens of billions of wireless useful but the app is unwiring, and not platform cre- sensor nets to unwire and interconnect everything. In ation. Near Field Communication (NFC) using RF or 1951, a man could walk inside a computer and by magnetic coupling offers a new interface that can be 2010 a computer cluster with millions of processors used to communicate a person’s identity that could has expanded to building size. More importantly, form a new class for wallets and identity. However, computers are beginning to “walk” inside of us2. most likely the communication channel and biometric technology taken together just increase the functionality of small devices. Acknowledgements Jim Gemmell, Jim Gray , Robert Hasbun, and Chuck Wireless Sensor Nets: New Platform, Network, and Thacker of Microsoft; John Gustafson, Craig Mudge, Applications Dag Spicer, Computer History Museum, and Doron Ubiquity: combining the platform, wireless network Swade, British Science Museum. and interface into one to integrate with other systems 2 Courtesy of Dag Spicer, Curator, Computer History Museum

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Bibliography About the Author [1] Bell, C.G., A. Newell, “Computer Structures: Read- Gordon Bell has been a principal ings and Examples” McGraw-Hill, 1971. researcher at Microsoft Research, since 1995, researching the lifetime capture [2] Bell, C. G., R. Chen and S. Rege, "The Effect of and storage of everything for an indi- Technology on Near Term Computer Structures," vidual. Previous roles include VP of Computer 2 (5) 29-38 (March/April 1972). R&D, Digital Equipment Corp. (1960- 1983); professor, Carnegie-Mellon Uni- [3] Bell, C. G. On the Future of Computers. http://research. versity (1966-72); founding assistant microsoft.com/~gbell/Mit288.asx A 1972 talk at M.I.T. director of NSF’s Computing and Information Sciences describing a model for future computers, including and Engineering (CISE) Directorate (1986-1988); computer classes based on logic technology evolution. chairman, cross agency committee (FCCSET) for creating the Internet(1987-1988); advisor /investor in [4] Bell, C. G., "The Mini and Micro Industries", Com- 100+ start-up companies; and a founding trustee of puter (17) no. 10, pp. 14-30 (October 1984). the Computer History Museum, Mountain View, CA. Since 1987 he has sponsored the Association for [5] Bell, C. G., "Multis: A New Class of Multiprocessor Computing Machinery’s (ACM) Gordon Bell Prizes for Computers", Science, Vol. 228, pp. 462-467 (April parallelism awarded annually at Supercomputing. He 26, 1985). has bachelor and master of science degrees from MIT (1956-57), is a University of New South Wales Ful- [6] Bell, G., W. Strecker, "Computer Structures: What bright Scholar (1957-58), has an honorary doctorate in Have We Learned from the PDP-11" IEEE Computer Engineering from Worchester Polytechnic Institute Conference Proceedings, Florida (November 1975). (WPI) (1993), and is a fellow of the American Acade- my of Arts and Sciences (AMACAD), Assoc. for Com- [7] J. Gray, P. Shenoy, “Rules of Thumb in Data Engi- puting Machinery (ACM), the Institute of Electrical neering,” Proc ICDE200, San Diego, March 1-4, and Electronics Engineers (IEEE), and the National 2000. IEEE press. Academies of Engineering (NAE) and Science (NAS). Awards include: ACM-IEEE Eckert-Mauchly Award; [8] Christensen, C.M. The Innovator’s Dilemma, Har- the IEEE’s Computer Pioneer and McDowell Awards; vard Business School Press, 1997, pp 225. the IEEE’s Von Neumann Medal; the Computer Histo- ry Museum Fellow Awards; the American Electronics [9] Moore, Gordon E. Cramming more components Association (AEA) Inventor Award for the economic onto integrated circuits, Electronics, Volume 8, No. contribution to New England; the IEEE 2001 Kara- 39 April 19, 1965. Article predicted transistor dou- petoff Eminent Member's Award of Eta Kappa Nu; bling annually; revised 1975: 18 months doubling. and the 1991 National Medal of Technology "for his continuing intellectual and industrial achievements in [10]Nelson, D. L., C. G. Bell “The Evolution of Work- the field of computer design and for his leading role stations”, IEEE Circuits and Devices Magazine, in establishing…computers that serve as a significant July 1986, pp 12-15. tool for engineering, science, and industry."

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TECHNICAL LITERATURE Advances in Ultra-Low-Voltage Design Joyce Kwong, Anantha P. Chandrakasan, Massachusetts Institute of Technology, [email protected]; [email protected]

consumed by a digital circuit. To this end, authors in Ultra-Low-Power Electronics and Sub-threshold [5] examined energy and performance contours of a Operation characterization circuit as VDD and Vt are varied. The In the near future, a number of systems will be pow- contours showed the existence of an optimum VDD ered using energy scavenging technologies, enabling and Vt which minimizes energy. Importantly, the exciting new applications such as medical monitoring, optimum VDD does not necessarily occur at the low- toxic gas sensors and next-generation portable video est voltage at which the circuit functions. For circuits gadgets. Energy harvesters typically provide output that require higher performance than is possible at power in the range of 10 – 100μW, setting a constraint the minimum energy point, the contours give the on the average power that can be consumed by the (VDD, Vt) which lead to the lowest energy consump- load circuitry for self-powered operation. This will tion at the required performance. Effects of varying require the electronic circuits to operate with utmost the circuit activity factor and temperature were also energy efficiency while performing the required func- investigated. tionality. Energy minimization requires a system-level For a system where Vt is fixed (i.e. no body bias- approach optimizing not only the signal processing and ing), Figure 1 shows how energy varies with VDD scal- interface circuits but also the energy processing func- ing, using a 65nm ALU as an example. As VDD tion. A major opportunity to reduce the energy con- decreases from 1.2V, the energy per clock cycle first sumption of digital circuits is to scale supply voltages reduces, then reaches a minimum at around 0.3V, and below 0.5V driving them to sub-threshold operation. finally increases again. This trend occurs because of a The idea of exploiting weak-inversion operation for trade-off between the active switching and leakage low power circuits was pioneered by Dr. Eric Vittoz components of energy. At high supply voltages, active 2 in the 1960’s and some history associated with the switching energy (EACT = CVDD ) dominates. There- development of these circuits is featured in the Sum- fore, as VDD decreases, the circuit energy is reduced mer 2008 issue. Weak-inversion circuits as proposed quadratically, as shown in Figure 1 for VDD > 0.5V. by Dr. Vittoz [1] have had a major impact on the design of micro-power integrated circuits and systems. This includes not only wristwatch circuits and calculators, but also a number of mixed-signal applications such medical electronics and sensors. The special MOS models developed by Dr. Vittoz and his colleagues were crucial for ultra-low-voltage operation and weak inversion analog circuits. The early work was later extended to the well-known EKV model [2] specifically designed for low-voltage and low-current analog circuit analysis. Based on this model, Dr. Vittoz developed expressions for static and dynamic behavior of sub-threshold logic in [3]. Anoth- er critical early development was the work of Swan- son and Meindl [4], which derived the minimum supply voltage at which CMOS digital circuits can func- Figure 1: Energy versus VDD curve of 65nm ALU, showing tion, and demonstrated inverter VTC down to 0.2V. trends in active, leakage, and total energy. Today, sub-threshold operation provides a com-

pelling solution for a number of emerging energy- However, as VDD is lowered to sub-threshold levels constrained systems implemented in scaled CMOS the propagation delay increases exponentially, since technologies. This article outlines some of the recent device currents depend exponentially on both VDD advances and challenges associated with sub-thresh- and Vt in weak inversion. Now, the leakage energy old circuit design. This includes the design of new per clock cycle (ELEAK), which equals the leakage logic and memory circuits, support circuitry (e.g., DC- power integrated over one clock period, also goes up DC converters) and the use of redundancy. exponentially and eventually dominates the total energy. This is seen in Figure 1 for VDD < 0.3V. Minimum Energy Digital Logic The concept of aggressive VDD scaling has been ELEAK= OPILEAKVDDdt explored to minimize energy dissipation. An important question involves finding the optimal VDD and These two opposing trends imply that the total threshold voltage (Vt) which minimize the energy energy (ETOT = EACT + ELEAK) reaches a minimum

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point. The VDD which minimizes energy (minimum not pull the output of a logic gate fully to VDD or energy point, or MEP) depends on the relative con- ground. This is especially apparent in circuits where tributions of active and leakage energy components many parallel leaking devices fight one or several [5], [6], [7]. If a circuit has high activity factor (i.e. a active devices in series, for example in the tiny XOR large portion of the circuit switches in any given gate [9] or in register files [10]. To address this, [10] cycle) and relatively large proportion of EACT, then derived analytical models for the output voltages and the decreasing trend in EACT dominates until VDD input requirements of such circuits, as well as their becomes very small. In this case, the MEP occurs at minimum operating voltage. a low supply voltage. Conversely, if a circuit has low Process Variation activity factor or a relatively large ELEAK component, then the MEP occurs at a higher voltage. For most Process variation can further skew the relative systems, the MEP occurs in or near the sub-threshold strengths of devices to adversely affect the functional- region, since E begins to increase rapidly when ity of logic gates. Global variation affects all devices LEAK on a chip equally and causes device characteristics to VDD decreases and approaches Vt. Process technology scaling provides smaller switch- vary from one chip to the next. In sub-threshold logic, ing capacitance. However, leakage current in recent its main effect is seen at skewed P/N corners with technology generations have increased substantially, strong PMOS and weak NMOS, or vice versa [9]. In in part due to decreasing threshold voltages to main- deeply scaled technology nodes, local variation, tain performance while the nominal supply voltage is which affects devices on the same chip differently, scaled down. Figure 2 examines the net effect of these has become a significant concern. In sub-threshold, trends on the energy of a 32-bit adder simulated with the dominant source of local variation is random predictive models [8] and interconnect parasitics. The dopant fluctuation (RDF) [11], in which placement W/L of devices in the adder is kept constant as the and number of dopant atoms in the device channel lengths are scaled to the 65nm, 32nm, and 22nm cause random shifts in Vt. Correspondingly, both ION nodes. At nominal V (0.8V-1V), the reduction in and I in sub-threshold are exponentially affected DD OFF σ active energy with process scaling is apparent. Impor- by these Vt shifts. In 65nm, for example, a ±4 Vt shift tantly, the MEP occurs at a higher voltage at the from RDF can cause the drain current to change by deeply scaled nodes, due to the larger relative contri- three orders of magnitude. bution of leakage energy. Nevertheless, for this par- The compound effects of reduced ION/IOFF and ticular circuit, the MEP still occurs in the sub-thresh- process variation are illustrated by the voltage trans- old region. fer curve (VTC) of a two-input NAND in Figure 3. At the strong-PMOS weak-NMOS global corner, the VTC is shifted towards the right. Additionally, local variation causes random perturbations in the VTC, in some cases significantly degrading the output logic levels. This implies that even the static CMOS logic style does not provide guaranteed functionality. To design robust sub-threshold circuits, it is no longer sufficient to consider only the nominal case or the global corners; we should also account for the statistical effects of local variation.

Figure 2: Trend in minimum energy point of 32b adder with technology scaling using predictive models [8].

Challenges in the Ultra-Low-Voltage Regime

Reduced ION/IOFF We have seen that aggressive voltage scaling affords significant energy benefits. However, ultra-low-voltage design must address two key challenges which Figure 3: Impact of global and local variation on NAND impact circuit functionality. In sub-threshold, drive gate VTC. current of the on devices (ION) is several orders of magnitude lower than in strong inversion. Corre- In addition to affecting functionality, process varia- spondingly, the ratio of active to idle leakage currents tion increases uncertainty in circuit delays. At low volt- (I /I ) is much reduced. In digital logic, this ON OFF ages, increased sensitivity to local variation causes the implies that the idle leakage in the off devices coun- delay distribution to widen. Figure 4(a) shows the teract the on devices, such that the on devices may

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sive simulation of 30000 timing paths in a 0.3V microcontroller under local variation [12]. Each horizontal cross section represents the delay distribution of one timing path. Note that adjacent paths with similar means can exhibit substantially different variances, as reflected by the lengths of the distribution tails. Conventionally, methodologies to verify setup/hold time constraints in a logic circuit treat logic gate delays as deterministic, taking points at the tails of the delay distribution to represent the maximum and minimum delays under process variation. However, very few gates exhibit delays found at the tails and most of the gates lie in the middle of the distribution. Conse- quently, conventional approaches give unrealistic results when applied to sub-threshold circuits. As with logic gate design, statistical methodologies such as those described in [13] are necessary for robust ultra- low-voltage operation.

SRAM Design SRAMs typically form a dominant portion of the area and power of a system. Therefore, energy and leakage power reduction through low-voltage operation is highly desirable. However, the traditional 6-transistor (6T) SRAM cell relies on ratioed device sizing to set the relative device strengths required for reading and writing. Since sizing changes current linearly while Vt variation has an exponential impact in sub-threshold, variation can easily overwhelm the effect of sizing to cause bit-cell failures. Data retention in a 6T SRAM bit-cell is determined by the cross-coupled inverters M1-M4 shown in Fig- Figure 4: (a) Delay distribution of timing path at 1.2V and ure 5(a). By superimposing VTC of one inverter on 0.3V under local variation. Both histograms contain 1k the inverse VTC of the other, we form a butterfly plot samples. (b) Delay distributions of 30k microcontroller which can be used to determine if a bit-cell is bi-sta- timing paths [12] at 0.3V, fast global corner. Each horizon- ble (i.e. if it can hold data). The presence of two bi- tal cross-section represents distribution of one path. stable intersection points in the butterfly plot indicates delay distribution of a 65nm logic timing path at 0.3V that the bit-cell can support “0” and “1” logic levels, (sub-threshold) and 1.2V (nominal). To compare the and thus proper data retention. The static noise mar- dispersion around the mean, both distributions are gin (SNM) indicates the maximum amount of noise normalized to their sample means, highlighting the that can be applied to the storage nodes of the bit-cell order-of-magnitude larger variability at 0.3V. This is before the state of the cell is destroyed. The SNM is similarly illustrated in Figure 4(b), by the comprehen- measured as the edge length of the smaller of the two

Figure 5: (a) Hold SNM and (b) read SNM of 6T SRAM cell. (c) 8T cell with two-transistor read buffer. (Courtesy of N. Verma)

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inscribed square in the butterfly plot [14]. If variation causes both VTCs to be shifted by more than this amount, the butterfly plot would no longer have bi- stable intersection points, indicating failure of the bit- cell to hold a required data state. In the 6T cell, the read operation is performed by precharging the bit-lines (BLC/BLT in Figure 5(b)) and then asserting the word line (WL) to turn on the access transistors M5 and M6. The storage node which stores a “0”, for instance NT, causes the bit-line BLT to discharge. However, since the bit-line is initially precharged, M5 tends to pull NT high while M1 attempts to pull it low. The fight between M1 and M5 raises the voltage at NT. Accordingly, the butterfly plot for a 6T cell during read is squashed on one end, as illustrated in Figure 5(b). As VDD is decreased, both read and hold SNM correspondingly become smaller. Further, process variation can shift the VTCs in the butterfly plot to cause Figure 6: Redundancy significantly reduces overall error bit-cell instability. As is apparent from Figure 5, the probability in SRAM sensing network [15]. read SNM is considerably smaller than hold SNM, and thus limits low-voltage operation. An alternative 8T bit-cell avoids the read SNM lim- conditions, the ability to track the MEP is crucial to itation with the use of a two-transistor read buffer. maximize energy savings. Figure 7 shows the archi- Shown in Figure 5(c), this read buffer M7-M8 isolates tecture of such a tracking loop [16] which automati- the internal storage node from the read bitline (RDBL) cally adjusts its output voltage to the minimum ener- so that it is not disturbed during a read. Since data gy point of the load circuit. The energy sensor circuit retention in the 8T cell now depends on the larger and the energy minimization algorithm set the reference voltage (Vref) of the DC-DC converter. The DC- hold SNM, VDD can be lowered further down to sub- threshold. This bit-cell, along with other peripheral DC converter, in turn, will adjust its output (VDD) to circuitry to assist sub-threshold writing and to match Vref, thereby enabling the load circuit to oper- improve bit-line integration, was demonstrated in a ate at its MEP. 65nm, 256kb SRAM functional down to 350mV [15]. Redundancy is another powerful technique for managing variation in ultra-low-voltage systems. In designing SRAM sense amplifiers, we are faced with a trade-off between their statistical offset and area. The offsets of sense amplifiers exhibit a distribution due to process variation, whose standard deviation relates inversely to the areas of the input devices. However, instead of upsizing the input devices to reduce offset, consider putting N redundant sense amplifiers within the same area as one full-size circuit, and then select- ing the one with the smallest offset. Although each copy has smaller devices and thus larger individual probability of error (defined as |offset| > 25mV in Figure 6), the error probability in the sensing network is now the chance that all N sense amplifiers fail. N Therefore, PERR, total = (PERR, N) , where PERR, N is the error probability of one of the N redundant sense amplifiers. As shown in Figure 6, even a small amount of redundancy (N=2) significantly improves the error Figure 7: Architecture of minimum energy tracking loop probability [15]. and energy sensor circuitry [16]. The energy sensor circuitry senses the energy per Tracking Circuits and DC-DC Converters clock cycle consumed by the load circuit in a digital Minimum Energy Tracking Loop manner. By avoiding high-gain amplifiers and analog Powering sub-threshold memory and logic circuits blocks, this scheme significantly reduces the overhead requires energy delivery circuitry that can efficiently power. As illustrated in Figure 7, the voltage on the convert a battery supply to sub-threshold voltages at storage capacitor Cload is first stored on C1. During microwatt load power levels. Moreover, since the energy sensing, the DC-DC converter is disabled. minimum energy point (MEP) of a circuit changes Therefore, voltage on Cload droops to V2 after N oper- with workload, temperature, and other environmental ations of the load circuit, and is subsequently stored

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on C2. The energy per operation of the load circuit is The switch matrix partially shown in the inset of given by E = C (V 2-V 2)/2N. Further, if V is suf- Figure 8 contains the charge transfer switches and the op load 1 2 ≈ 2 ficiently close to V1, (V1 + V2) 2V1, and hence Eop is charge transfer capacitors. Importantly, the total approximately proportional to V1 (V1 – V2). V1 is the charge transfer capacitance can be arranged in five reference voltage to the DC-DC converter and is different gain settings to help minimize linear con- known digitally. (V1-V2) can also be found digitally by duction loss, which is a major efficiency-limiting discharging C1 using a current sink while a fixed fre- mechanism in switched capacitor converters [17]. quency clock drives a counter. The fixed frequency Generally the maximum efficiency is limited by the clock, together with the constant current sink that ratio of the voltage supplied to the load circuit (VL) to drains C1, quantizes voltage into time steps. The num- the output voltage of the converter with no load (Vno- ber of fixed frequency clock cycles required for C1 to load). Accordingly, the converter contains multiple droop down to V2 is directly proportional to (V1-V2). gain settings to provide different levels of Vno-load. From this, the digital representation of Eop is calculat- When we wish to supply very low VL (e.g. 0.3V to a ed and is then used by a slope descent algorithm to sub-Vt SRAM), we can choose the suitable gain setting arrive at the MEP. with a small Vno-load to maximize the achievable effi- Since the MEP usually lies in sub-Vt where load ciency. The two gain settings shown in Figure 8, for power demands are very low, the DC-DC converter in instance, are suitable for supplying VL < VBAT/2 and VL the MEP tracking loop is designed to supply low volt- < VBAT/3. ages (0.25V-0.7V) at microwatt power levels. The converter employs a synchronous rectifier buck converter design with external passives. The all-digital con- Demonstration Systems trol circuitry is optimized for minimal power over- Emerging micro-power applications have generated head, enabling the DC-DC converter to achieve >80% much interest in sub-threshold circuits. In the past efficiency down to 1μW load power levels. few years, researchers have demonstrated a variety of systems functioning at very low voltages. For example, a sub-threshold DLMS filter was designed for a Switched Capacitor DC-DC Converter hearing-aid application, and an 8x8 carry save array Minimizing the number of external components is μ highly desirable in embedded applications such as multiplier test-chip was fabricated in 0.35 m [18]. biomedical implants. For micro-power applications, a This test-chip published in 2003 explored adaptive body biasing and operated down to 0.3V. In 2004, an switched capacitor DC-DC converter design is attrac- μ tive since the power conversion circuitry can be com- 180mV FFT processor in 0.18 m was demonstrated in pletely integrated on-chip. Figure 8 shows a switched [9]. The processor, pictured in Figure 9, featured an capacitor converter [17] which can provide variable energy-aware scalable architecture supporting vari- supply voltages and achieve >70% efficiency while able bit precision and FFT length. Device sizing supplying from 1μW up to 1mW load power. The strategies for logic gates accounted for global process converter uses an all-digital pulse frequency modula- variation, and the register file design employed a tion (PFM) mode of control to regulate the output multiplexer-based hierarchical-read-bitline scheme to address weak I /I . Combining the energy bene- voltage. In this type of control, the converter stays ON OFF fits of sub-V operation with Dynamic Voltage Scaling idle until the load voltage V falls below the reference t L (DVS), [19] presented an Ultra-Dynamic Voltage Scal- voltage (VREF), at which point a clocked comparator enables the switch matrix to transfer one charge pack- ing test-chip with a 32b Kogge-Stone adder in 90nm. et to the load. The PFM mode of control is essential In this technique, we can operate the circuit at its to achieving high efficiency while providing extreme- MEP during periods of very little activity, and dynamically raise V when short bursts of high perform- ly low power levels to the load circuits. DD ance are needed. The test-chip showed 6800X performance scaling as VDD is varied from the MEP of 330mV to 1.1V, and provided 9X energy savings over single-VDD operation. Systems with constant throughput constraints can also benefit from substantial VDD reduction by lever- aging extreme parallelism to compensate for speed decrease. For example, a 400mV baseband radio processor [20] was able to support 500M samples/s throughput by distributing computations to many parallel hardware blocks. A 200mV, 0.13μm sub-threshold sensor processor was demonstrated in [21] and features an 8b ALU, 32b accumulator, and 2kb SRAM. The standard cell library to implement the processor was carefully selected to exclude cells with a fan-in more than 2 as well as pass-transistor logic. Another sub-200mV processor in Figure 8: Switched capacitor DC-DC converter architecture 0.13μm examined the effectiveness of body biasing in [17], [12].

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the analog domain at voltages below 500mV, comparator redundancy and reconfigurability are employed to tolerate large comparator offsets (> 1 LSB) and improve linearity. Current mode logic in weak inversion was presented in [25]. To operate at low bias currents, a novel PMOS load device was proposed to provide high resistance and large voltage swing. Published work on sub-threshold SRAMs has explored a range of bit-cell and peripheral circuit designs. The survey here is organized according to process technology. At the 0.13μm node, authors of [26] demonstrated a 512x13b SRAM with a register- file-based cell, a multiplexed read scheme, and self- timed keepers to achieve functionality at 216mV. The 0.2V, 480kb SRAM [27] used a 10T bit-cell designed to eliminate data-dependent bit-line leak- Figure 9: Die micrograph of 180mV FFT Processor [9]. age. Access devices are lengthened to take advantage of reverse short channel effects and improve mitigating variation and several logic gate sizing sub-Vt writability. A virtual ground replica shifts the strategies for performance tuning [22]. trip point of the inverter-based sensing circuit to Looking forward, technology scaling enables improve sensing margin. [28] explored use of a 6T 2 reduced CVDD energy and increased density, but cell modified for single-ended read and improved presents heightened process variation. Most recently readability. This came at the cost of reduced in 2008, a 320mV 411GOPS/Watt motion estimation writability, which was recovered by allowing the accelerator in 65nm [23] employed optimized data- bit-cells’ virtual VDD and ground rails to droop dur- path circuits to address variation and weak ION/IOFF, ing a write. The 2kb SRAM array was fully function- as well as to improve performance. [12] presented a al from 1.2V to 193mV. 65nm system-on-a-chip which features a 16b micro- At the 65nm node, local variation becomes more controller, a 128kb 8T SRAM, and an on-chip switched prominent. A 256kb SRAM [29] employed a 10T bit- capacitor DC-DC converter (Figure 10). The system cell to eliminate the read SNM limitation as mentioned demonstrated approaches for library design and tim- in the SRAM section. Stacked devices in the reading analysis, as well as circuit techniques to enable buffer reduced bit-line leakage and improved bit-line sub-threshold operation down to 300mV. integration, while floating the cell supply voltage assisted sub-Vt writes. The SRAM was able to fully read and write at below 0.4V. The 8T design described previously [15] featured peripheral assist circuitry to enable functionality in sub-Vt. During a write, the cell supply voltage is reduced by a write driver, to ensure that PMOS devices are weakened relative to access devices. During a read, the feet of all unaccessed read buffers are pulled to VDD, eliminating their sub-Vt leakage currents which would otherwise degrade the read bitline voltage.

Next Steps Significant advances have been made in the recent year related to sub-threshold circuit design. Important issues such as device variability have been addressed through circuit design and system architecture. To transition these concepts to products, it will be critical to develop design methodologies and CAD tools to encapsulate variation-aware methodology (e.g., statis- Figure 10: Die micrograph of 65nm sub-Vt microcontroller [12]. tical timing tools compatible with low-voltage design). A number of exciting new applications can leverage In the mixed-signal domain, an ADC functioning ultra-low-voltage operation to dramatically reduce down to 200mV has been demonstrated in [24]. This energy consumption. This includes sensor networks, highly digital 6b flash ADC removes the need for a medical electronics and multimedia devices. resistor string reference voltage ladder by building voltage offsets directly into each dynamic, regenera- Acknowledgements tive comparator through sizing. As comparator and The authors thank DARPA for funding, and Texas reference voltage offset compensation is difficult in Instruments and National Semiconductor for chip fab-

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rication. J. Kwong is supported by the Texas Instru-

ments Graduate Woman’s Fellowship. The authors are 65nm sub-Vt microcontroller with integrated grateful to Dimitri Antoniadis, Yu Cao, Eric Wang, and SRAM and switched-capacitor DC-DC converter,” Wei Zhao for help with the predictive models used in IEEE International Solid-State Circuits Confer- this article. ence, pp. 318-319, Feb. 2008. [13] A. Srivastava, D. Sylvester, D. Blaauw, Statistical References Analysis and Optimization for VLSI: Timing and [1] E. Vittoz, J. Fellrath, “CMOS analog integrated Power, New York: Springer, 2005, pp. 79-132. circuits based on weak inversion operation,” [14] E. Seevinck, F. J. List, and J. Lohstroh, “Static- IEEE J. Solid-State Circuits, vol. SC-12, no. 3, pp. noise margin analysis of MOS SRAM cells,” IEEE 224-231, June 1977. J. Solid-State Circuits, vol. SC-22, no. 5, pp. [2] C. Enz, F. Krummenacher, E. Vittoz, “An analyti- 748–754, Oct. 1987. cal MOS transistor model valid in all regions of [15] N. Verma, A. P. Chandrakasan, “A 256 kb 65 nm operation and dedicated to low-voltage and low- 8T subthreshold SRAM employing sense-amplifi- current applications,” Analog Integrated Circuits er redundancy,” IEEE J. Solid-State Circuits, vol. and Signal Processing, vol. 8, pp. 83-114, 1995. 43, no. 1, pp. 141-149, Jan. 2008. [3] E. Vittoz, “Weak inversion for ultimate low- [16] Y. K. Ramadass and A. P. Chandrakasan, “Mini- power logic,” Chapter 16 of Low-Power Electron- mum energy tracking loop with embedded DC- ics Design, Editor, C. Piguet, CRC Press LLC, 2005 DC converter delivering voltages down to [4] R. M. Swanson, J. D. Meindl, “Ion-implanted 250mV in 65nm CMOS,” IEEE International complementary MOS transistors in low-voltage Solid-State Circuits Conference, pp. 64-65, Feb. circuits,” IEEE J. Solid-State Circuits, vol. 7, no. 2, 2007. pp. 146-153, Apr. 1972. [17] Y. K. Ramadass and A. P. Chandrakasan, “Voltage [5] A. Wang, A. P. Chandrakasan, S. V. Kosonocky, scalable switched capacitor DC-DC converter for “Optimal supply and threshold scaling for sub- ultra-low-power on-chip applications,” IEEE threshold CMOS circuits,” IEEE Computer Society Power Electronics Specialists Conference, pp. Annual Symposium on VLSI, pp. 5–9, Apr. 2002. 2353-2359, June 2007. [6] B. H. Calhoun, A. Wang, A. Chandrakasan, [18] C.H.-I. Kim, H. Soeleman, K. Roy, “Ultra-low- “Modeling and sizing for minimum energy oper- power DLMS adaptive filter for hearing aid appli- ation in subthreshold circuits,” IEEE J. Solid-State cations,” IEEE Trans. VLSI Systems, vol. 11, no. 6, Circuits, vol. 40, no. 9, pp. 1778-1786, Sept. pp. 1058-1067, Dec. 2003. 2005. [19] B. H. Calhoun, A. Chandrakasan, “Ultra-dynamic [7] B. Zhai, D. Blaauw, D. Sylvester, K. Flautner, voltage scaling using sub-threshold operation “The limit of dynamic voltage scaling and insom- and local voltage dithering in 90nm CMOS,” IEEE niac dynamic voltage scaling,” IEEE Trans. VLSI International Solid-State Circuits Conference, Systems, vol. 13, no. 11, pp. 1239-1252, Nov. pp. 300-301, Feb. 2005. 2005. [20] V. Sze, A. Chandrakasan, “A 0.4-V UWB base- [8] W. Zhao and Y. Cao, “New generation of predic- band processor,” IEEE International Symposium tive technology model for sub-45nm early design on Low Power Electronics and Design, pp. 262- exploration,” IEEE Trans. Electron Devices, vol. 267, Aug. 2007. 53, no. 11, pp. 2816-2823, Nov. 2006. [21] B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Available at http://www.eas.asu.edu/~ptm/ Minuth, R. Helfand, S. Pant, D. Blaauw, and T. [9] A. Wang and A. Chandrakasan, “A 180-mV sub- Austin, “A 2.60pJ/Inst subthreshold sensor threshold FFT processor using a minimum ener- processor for optimal energy efficiency,” Sympo- gy design methodology,” IEEE J. Solid-State Cir- sium on VLSI Circuits Dig. Tech. Papers, pp. cuits, vol. 40, no. 1, pp. 310-319, Jan. 2005. 154–155, June 2006. [10] J. Chen, L. T. Clark, Y. Cao, “Maximum Ultra-Low [22] S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, Voltage Circuit Design in the Presence of Varia- M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. tions,” IEEE Circuits and Devices Magazine, pp. Austin, D. Sylvester, D. Blaauw, “Performance 12-20, Nov. 2005. and variability optimization strategies in a sub- [11] B. Zhai, S. Hanson, D. Blaauw, D. Sylvester, 200mV, 3.5pJ/inst, 11nW subthreshold proces- “Analysis and mitigation of variability in sub- sor,” Symposium on VLSI Circuits Dig. Tech. threshold design,” IEEE International Sympo- Papers, pp. 152–153, June 2007. sium on Low Power Electronics and Design, pp. [23] H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agar- 20-25, Aug. 2005. wal, R. Krishnamurthy, and S. Borkar, “A 320mV [12] J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. 56μW 411GOPS/Watt ultra-low voltage motion Huber, H. Moormann, A. Chandrakasan, “A estimation accelerator in 65nm CMOS,” IEEE

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International Solid-State Circuits Conference, Anantha P. Chandrakasan received pp. 316–317, Feb. 2008. the B.S, M.S. and Ph.D. degrees in Elec- [24] D. C. Daly, A. P. Chandrakasan, “A 6b 0.2-to-0.9V trical Engineering and Computer Sci- highly digital flash ADC with comparator redun- ences from the University of California, dancy,” IEEE International Solid-State Circuits Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he Conference, pp.554-555, Feb. 2008. has been with the Massachusetts Insti- [25] A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer, tute of Technology, Cambridge, where “Ultra low power subthreshold MOS current he is currently the Joseph F. and Nancy P. Keithley mode logic circuits using a novel load device Professor of Electrical Engineering. concept,” IEEE European Solid State Circuits He was a co-recipient of several awards including Conference, pp. 304-307, Sept. 2007. the 1993 IEEE Communications Society's Best Tutori- [26] J. Chen, L. T. Clark. T.-H. Chen, “An ultra-low- al Paper Award, the IEEE Electron Devices Society's power memory with a subthreshold power sup- 1997 Paul Rappaport Award for the Best Paper in an ply voltage,” IEEE J. Solid-State Circuits, vol. 41, EDS publication during 1997, the 1999 DAC Design no. 10, pp. 2344-2353, Oct. 2006. Contest Award, the 2004 DAC/ISSCC Student Design [27] T.-H. Kim, J. Liu, J. Keane, C. H. Kim, “A high- Contest Award, the 2007 ISSCC Beatrice Winner Award for Editorial Excellence and the 2007 ISSCC density subthreshold SRAM with data-independ- Jack Kilby Award for Outstanding Student Paper. ent bitline leakage and virtual ground replica His research interests include low-power digital inte- scheme,” IEEE International Solid-State Circuits grated circuit design, wireless microsensors, ultra-wide- Conference, pp. 330-331, Feb. 2007. band radios, and emerging technologies. He is a co- [28] B. Zhai, D. Blaauw, D. Sylvester, S. Hanson, “A author of Low Power Digital CMOS Design (Kluwer Aca- sub-200mV 6T SRAM in 0.13μm CMOS,” IEEE demic Publishers, 1995), Digital Integrated Circuits International Solid-State Circuits Conference, (Pearson Prentice-Hall, 2003, 2nd edition), and Sub- pp. 332-333, Feb. 2007. threshold Design for Ultra-Low Power Systems (Springer [29] B. H. Calhoun, A. Chandrakasan, “A 256kb sub- 2006). He is also a co-editor of Low Power CMOS threshold SRAM in 65nm CMOS,” IEEE Interna- Design (IEEE Press, 1998), Design of High-Performance tional Solid-State Circuits Conference, pp. 2592- Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005). 2593, Feb. 2006. He has served as a technical program co-chair for the 1997 International Symposium on Low Power About the Authors Electronics and Design (ISLPED), VLSI Design '98, Joyce Kwong received a Bachelor of and the 1998 IEEE Workshop on Signal Processing Applied Science at the University of Systems. He was the Signal Processing Sub-committee Waterloo in 2004 and a master’s degree Chair for ISSCC 1999-2001, the Program Vice-Chair for in Electrical Engineering at the Massa- ISSCC 2002, the Program Chair for ISSCC 2003, and chusetts Institute of Technology in 2006. the Technology Directions Sub-committee Chair for She is currently working towards a Ph.D. ISSCC 2004-2008. He was an Associate Editor for the at MIT. She is the recipient of the Texas IEEE Journal of Solid-State Circuits from 1998 to 2001. Instruments Graduate Woman’s Fellow- He served on SSCS AdCom from 2000 to 2007 and he ship for Leadership in Microelectronics and the was the meetings committee chair from 2004 to 2007. NSERC Postgraduate Fellowship. Her research inter- He is the Technology Directions Chair for ISSCC 2009. ests include sub-threshold design methodology and He is the Director of the MIT Microsystems Technol- system implementation. ogy Laboratories.

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TECHNICAL LITERATURE Gigasensors for an Attoscope: Catching Quanta in CMOS Erik H.M. Heijne, CERN, [email protected]

The experiments study the fundamental physics Silicon Takes the Stage in Particle Physics Experiments processes between elementary particles at the highest The gigantic experiments at CERN, the elementary momenta on earth. Particle beams circulating in particle accelerator laboratory in Geneva, Switzerland opposite directions with thousands of bunches of pro- rely on custom-designed CMOS for much of their tons are accelerated to 7 TeV, and then made to col- functioning. Close to a million CMOS chips, silicon- lide head-on in 4 crossing points. The experimental based sensors and other sensitive material, such as set-up around an interaction point consists of succes- scintillating crystals or liquid argon, fill the space in sive shells of different detectors in which one records and around a superconducting magnet, the size of a all the effects in the miniature explosions that result 6-stories building. The chips have to process small when quarks inside these protons occasionally fuse electrical signals, typically 10 to 20 thousand elec- together. Figure 2 illustrates the variety of reaction trons, generated by the ionizing particles in the sen- products in a rare, sought-after type of collision. sor elements. Silicon is sensitive to light, but very thick diode structures also deliver signals that are proportional to the energy loss of swift particles that pass through. The sensor cells have been connected in a fully parallel approach to their integrated readout amplifiers and further signal processing, because the 'snapshots' of the successive interactions are uncorrelated, and take place every 25 ns: 40 million pictures per second. These massively parallel detector systems with close to 109 sensor cells have become possible only by exploiting the miniaturization of electronics. The CERN experiments are situated deep underground along the 27 km circular accelerator called the ‘Large Hadron Collider’ LHC. Figure 1 gives an idea of such a collider detector, still under construction.

Fig. 2 Simulated interaction in the Atlas detector with all outgoing reaction products traversing the successive shells of the detector. The central region where most particles are colored red, represents the inner tracker detectors. The surrounding heavy calorimeters provoke show- ering around the absorbed particles. The yellow track to the right is an escaping muon. The scale of the figure is ~10m across. Photo CERN/Atlas.

Only a tiny ‘needle’ fraction of the ‘events’ represent new physics phenomena, and these have to be filtered out from the majority 'haystack' of uninterest- ing data. A particle or quantum with 1 TeV energy has an equivalent wavelength of one attometer (10-18m), compared to a micrometer for visible light, and so one can say that these experiments in the TeV energy range act as 'attoscopes' rather than microscopes, when they look at the properties of these energetic quanta on the atto-scale. The introduction of silicon chips in particle physics Fig. 1 Part of the Atlas team assembled in between the end- experiments went by steps, and in this article I trace caps, in the underground cave. Several thousand scientists and some of the history of silicon detectors and readout technicians have worked on the Atlas construction. The blue chips for tracking detectors. These form the inner cylinder is a shielding block that surrounds the entry/exit of the not yet installed beam pipe. The magnet and the main bar- shells of the equipment. As shown in Figure 2, they rel are to the left, invisible here. Photo CERN/Atlas. record the trajectories of the ionizing particles in a

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somewhat similar way as cloud chambers, spark first also discrete components were used for readout, chambers or bubble chambers did in the earlier times. but the need for integrated circuits now was obvious. Although providing fewer measurement points along Several teams initiated analog design work: Hyams, a track, the main advantage of the silicon tracker sys- Parker and Walker started at Stanford with an NMOS tems is the fully electronic operation and the ns col- chip, called Microplex [8]. Their design used a lection time of the signals in the silicon layers. switched capacitor feedback amplifier and evolved Already in 1976 at the EPFL, the Swiss Federal Tech- later, thanks to Kleinfelder [9], Spieler [10] and nical University in Lausanne, during a workshop 'Lim- coworkers at Lawrence Berkeley Lab into a family of its on Miniaturization' my colleague Pierre Jarron and CMOS chips, used still now at Fermilab in the CDF I became enthusiastic to apply developments in and D0 Tevatron collider experiments. In Germany, microelectronics for detection of particles. As shown a team of the Munich Heisenberg Laboratory and the in the next section, segmentation is the key to the sil- Duisburg Microelectronics Institute, with Lutz and icon trackers, and in 1980 we introduced the silicon Buttler, together with Manfredi et al. at the University diode 'microstrip' detector with full parallel readout, of Pavia, developed a 128 channel CMOS circuit with following a visit at the nuclear physics institute IKO in JFET frontend transistors [11]. Later this chip was Amsterdam. Then the design of custom chips for sil- called CAMEX and was used in the electron collider icon detector readout was started at SLAC in 1981 and experiment Aleph at CERN, from 1989 to 2001. All at CERN in 1986. Now, 25 years later a community of these circuits used a front-end amplifier with switch- designers and users supply the various integrated cir- ing feedback and double correlated sampling, con- cuits for detection and signal processing in the exper- trary to the continuous feedback in 'Amplex' that I iments at CERN, at Fermilab near Chicago, at the Stan- will discuss in the next section. ford linear accelerator SLAC, and other facilities world- But first more on the ‘ultimate’ segmentation: for wide. The most recent development with ‘ultimate’ the planned proton collider experiments in the USA segmentation for particle tracking, ~ 1995, was the true and Europe, with their large number of simultaneous 2D silicon pixel detector, for which Eric Vittoz and his particles, from the early 1980's we at CERN wanted to coworkers in CSEM and at the EPFL contributed sig- push towards parallel sensor cells of micrometer nificantly, with advice, designs and training. dimensions in a true 2D matrix, using photolithogra- phy [12]. Damerell had shown the power of 2D meas- Segmentation of Sensors, Serial or Parallel Readout urements by using CCD [13] but the serial readout The use of a contiguous array of segmented diodes restricts this method to particular situations of low on monolithic silicon for nuclear particle detection, as repetition rate or experiments where the beam can be far as I know, was first proposed ~1961 by Leo Koerts stopped after an interesting interaction, such as in a from Philips/IKO in Amsterdam. Their ‘checker board’ linear accelerator. The question was, if we could detector with Schottky barrier strips on the front and implement conventional, ns signal processing and full orthogonal ohmic strips on the rear, both with 1.2 mm parallel readout on a microscopic area with reason- pitch, was described by Hofker in 1966 [1]. This was able power dissipation. We approached Eric Vittoz the device that Jarron and I took as the example for with this question in 1986. For the first Workshop on our silicon diode ‘microstrip’ detectors, with much Pixel Detectors in Leuven [14] Vittoz analyzed this smaller segmentation at 200 µm [2] and later at 50 µm problem, and he summarized some parameters in pitch. The readout of the checker board was not yet Table 1. Also he sketched the signal processing chain fully parallel, but it had single analog amplifier chan- in Figure 3, and came with positive conclusions on nels, for front and rear of the sensor, together with a series of pick-up transformers for position determina- tion along the diode array. The full system ‘BOL’ with 8000 'pixels' [3], operational 1968-1974, needed several cubic meters of electronics for this readout. It is interesting to remember that around this time monolithic 2D matrix approaches for imaging of visible light also were studied at Philips and at Bell Labs. Within a few years these proposed respectively BBD [4] and CCD [5] for imaging, and both approaches used serial signal readout. The earliest system with fully parallel readout for a sizeable array of sensing elements was the Multi-Wire Proportional Chamber (MWPC) for particle position measurement in 1968 [6] which earned Georges Charpak a Nobel prize in 1992. A separate amplifier connects to each wire and with a typical distance between wires of ~5mm, this electronics could be fabricated with the discrete components of the time. For the 'microstrip' detectors, made on kΩcm Si wafers by Schottky barriers and later by ion-implantation [7] at

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were made, such as a latched input circuit, in order to obtain low power dissipation. By Christmas the layout was ready, the chip was processed in the 3 µm SACMOS technology at Faselec AG in Zurich. With self-aligned contacts (SAC) this technology offered increased density, allowing a small pixel area of 200 µm x 200 µm. In June 1989, after dicing at CSEM we made the microphoto of Figure 4, which shows one corner of the matrix with 8 input contacts and readout cells. Fig. 3 Schematic by Eric Vittoz for the analog front end for Michael Campbell and I made the first measure- an integrated pixel detector[14]. ments over the summer, and our late paper was accepted for presentation at the 1989 Nuclear Science power and noise. Such small pixels pinpoint positions Symposium near San Francisco. The chip worked well, of the particles in space with much better precision, with noise below 500 e- rms, detection threshold but also have the pleasant characteristics of low ~3000 e- and power of 30 µW/pixel, all well below the capacitance and reduced dark current. design goals. But then some strange problems beset This allows low electronic noise, and recent matri- the first publication. The Symposium was cancelled ces achieve ~ 100 e- r.m.s.equivalent, at the input of because of the 17 October San Francisco earthquake. the signal processing circuit, even with ~100ns signal Despairing, we submitted the paper to Nuclear Instru- shaping. The signal generated in the Si sensor by ion- ments and Methods [15]. The Conference eventually izing quanta is typically between 2000 and 20000 elec- was rescheduled in a different, undamaged hotel tron-hole pairs, so that one has a comfortable sig- where Michael Campbell presented the paper only in nal/noise ratio. In 1987 I dubbed these devices January 1990 for a small audience. We also found that ‘micropattern’ detectors, because I imagined that the planned bump-bonding could not be made eventually they would be able to recognize useful because of a mm wide guard ring that is needed interactions from pre-defined patterns in the image. around the active sensor area, and this would obscure In practice the name ‘pixel’ detectors has now the wirebond pads on the electronics readout chip. become the standard. In the English language, con- We initiated the design for a next chip, now aiming trary to the French, there is an ambiguity between at an asynchronous input amplifier and a large, more ‘detector of patterns’ and ‘detector with patterns,’ and practical matrix of 16 columns and 63 rows. The 64th the latter meaning has more recently been adopted in row was dedicated to a provision for dark current the field of gaseous devices. compensation. Each pixel of 75µmx500µm contained ~80 transistors. The chip was again manufactured in the SACMOS3 technology, and after bump-bond assembly at GEC-Marconi in Caswell, the first particle tracks were measured at CERN on 20 October 1991. These measurements were presented at the 1991 Nuclear Science Symposium in Santa Fe [16], two years after those of the first chip. In the scientific community, with relatively modest resources long iteration times are typical, also because the design teams are involved in the development and testing of the full application system. Indeed, the following, third chip in this series was the LHC1/Omega3 [17], which became available early in 1995, nearly four years later. This chip with a 16x128 matrix of cells used the SACMOS 1µm technology, which represent- Fig. 4 Corner of the first pixel readout chip, showing 8 ed at the time a submicron component density in pixels with input contacts for bump bonding and some comparison with normal CMOS. The smaller pixel output pads for wirebonds. Design and layout by François area of 50µmx500µm could now contain as many as Krummenacher and Christian Enz, Dec 1988. Made in SAC- 400 transistors. I wonder if we can call this a 'hyper- MOS3 technology. Photo CERN. active' pixel, after Eric Fossum just before [18] had claimed the term 'active pixel sensor' if each pixel contains at least one transistor. It may also be worth The Earliest ‘Micropattern’ Pixel Detectors mentioning that the Faselec/Philips SAC1 process, In 1988, after the Workshop in Leuven, the design although developed in Zurich, in 1994 just was trans- work started on a first prototype of a 9x12 pixel ferred to the Taiwan Semiconductor Manufacturing detector matrix, by Smart Silicon Systems, a startup Company TSMC, with the Swiss technology specialist from the EPFL, with Christian Enz and François Krum- J. Solo making many trips between Zurich and Taipei. menacher as designers, Eric Vittoz as adviser and the That technology was never actually implemented any- CERN team as the critical customers and users. With more at the Zurich foundry of Faselec, illustrating the a future particle collider in mind some design choices

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swift worldwide concentrations in microelectronics manufacturing. Only 10 years earlier, there still were several MOS factories in Switzerland, serving the local high-tech industries, described in the Summer Newsletter dedicated to Eric Vittoz.

Active Feedback Compensates Dark Current In semiconductor diode detectors, systematically one has to cope with the dark leakage current at reverse bias and often the input is AC coupled, in order to

Fig. 6 Schematic diagram of the front end by Krummen- acher with sinking of dark current via M2. This scheme can be implemented in each pixel [23]. chip for SLAC had been designed some years earlier. The UA2 silicon detectors had a surface area of more Fig. 5 Schematic diagram of the connection of segmented than 1 m2, and this was at the time the largest silicon diode elements to an Operational Transconductance detector ever. Amplifier (OTA) with a feedback that restores the operat- For the silicon pixel detector with their thousands ing point if there is a large current Idark at the input [19]. of sensor cells and amplifiers, the DC coupling is the only practical possibility and a current compensation avoid baseline shift and amplifier saturation. For high- has to be implemented, on the small area available. ly segmented devices, external filtering networks In the Omega2 matrix Michael Campbell replicated become impractical and these have to be implement- the currents from a row of reference pixels. François ed on the silicon sensor itself. DC interconnections Krummenacher proposed in 1990 a damped feedback would be preferable, but then a scheme is needed to illustrated in Figure 6 [23]. accommodate varying and sometimes large currents This can be implemented in each pixel, without the at the inputs of the front-end amplifiers. Sometimes need for reference cells. The transistor M2 can sink hundreds of nA have to be compensated, even more the leakage current Ileak, and with proper choice of C after extended irradiation, although the current is and g the tolerated I can be much larger than the strongly reduced by the sensor segmentation. For the m2 leak biasing current Ip With thousands of pixels, in practi- gaseous detectors this is not an issue, because the gas cal implementations a dark current as high as 1mA remains a perfect isolator, even at kV bias. per cm2 can be handled with this approach, and cur- At CERN, Pierre Jarron and I started in 1986 work rent fluctuations are slowly but automatically fol- on CMOS chip design for the segmented Si detectors lowed pixel by pixel. with a training course in the INVOMEC division at the just founded IMEC centre in Leuven, Belgium. Jarron Massively Parallel 2D Gigasensor Array followed the nuclear electronics tradition, and imple- The heart of three of the CERN LHC experiments is mented a continuous feedback scheme using a long formed by several layers of true 2D pixel matrix transistor, as shown in Figure 5 [19]. detectors, which record at 40 MHz the positions and With direct connection, the sensor dark current at timing of all particles that pass through. Every single the input modulates the effective resistance of the particle, representing a quantum of energy above the feedback, so that the operational level at the output detection threshold of ~ 5 keV is registered by these can be maintained, at the cost of a slight reduction of devices. The CMOS chips that are attached to the amplification. A current up to 450 nA per segment can sensor matrix not only record the signals, but store be compensated. The 16-channel AMPLEX chip [20] these in local memory for up to ~4 µs, until a request was produced in 1987 in the 3um CMOS technology for readout is received. Optical links could transmit of MIETEC in Belgium. By chance this AMPLEX chip a large fraction of the data but the off-detector data happened in 1989 to become the first integrated cir- processing is designed for analysis of ~kHz event cuit to be actually operational in a beam collider rates, corresponding to expected numbers of interest- experiment: the inner silicon array in the UA2 proton- ing interactions. The actual sensitive area of the inner antiproton experiment at CERN [21] was used a year silicon pixel arrays ranges from 0.22 m2 and 1200 before the vertex detector at the MARKII in SLAC was chips in ALICE, to 1 m2 with 16000 chips in CMS and taking data in July 1990 [22] although the Microplex 1.8 m2 with 28000 chips in ATLAS. A much larger

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Fig. 7 Final assembly work on the Atlas pixel barrel (half). One can see the modules along the ladders. The white stubs are connecting tubes for the cooling channels, one for each ladder. Photo CERN/Atlas. Fig. 8 Layout for the Medipix3 chip of a 55µm pixel cell in a 2 area, up to 400 m , is covered in the next shells with 130 nm CMOS technology. Preamplifier, shaper and com- 1D silicon microstrip detectors. Also these detectors parators, resp. 1, 2 and 3 form the analog part, while 3-7 are employ tens of thousands of CMOS chips for the sig- the control logic, counters, configuration and arbitration cir- nal readout and data processing. At the start of the cuits. This pixel has more than 1080 transistors [25]. LHC the overall number of pixels per experiment is not quite 109 yet. It is expected that a higher beam allows selection of energy bands and representation intensity in a couple of years will bring a need for of the image in different “colours.'’ Thresholding elim- upgrades with more pixel layers, to replace the cur- inates various types of background and long expo- rently installed layers of 1D silicon microstrip detec- sures can be made, such as needed with low intensi- tors. If the particle density in each beam crossing is ty, nanofocus X-ray sources. Our group at CERN, with increased, the projective 1D detectors can not cope Michael Campbell as team leader, has designed the with the ambiguities between several coincident par- family of 'Medipix' imagers [24], building on the ticles anymore, and true 2D detectors are necessary. expertise in ionizing particle detectors. Figure 8 It is not possible here to describe in detail all shows the layout of a pixel in the Medipix3 readout aspects of these complex systems, such as the data chip [25], the first particle detector where each pixel readout systems, the power distribution (~ 50 kW for communicates in real time with all of its neighbours, the inner silicon detectors) and the cooling. Figure 7 to compare and add up coincident signals that belong gives an impression of the pixel detector for ATLAS, to the same incident radiation quantum. showing half of the barrel under final construction. The Medipix chips are 3-side buttable, and the con- This device will sit tightly around the beam pipe, struction of a large area array will be needed to allow detect millions of particles per second and undergo a for use in medical applications. For a CT scanner a 2 large amount of radiation over the planned lifetime of detector array of ~m may be required. With ~ 50 000 2 ~10 years. The survival of the CMOS as well as the pixels per cm then such a device also will present 9 silicon sensors has been studied and the use of stan- close to 10 sensor cells, another gigasensor. dard technologies has been found acceptable. The In conclusion, CMOS chips in conjunction with sil- unavoidable increase of sensor dark current and the icon diode matrices are now used on a large scale for changes of material properties can be mitigated by ionizing particle imaging. They are catching quanta operating the detector well below 0 degree C. With in physics experiments as well as in X-ray imaging. the installation completed, the number of dead sensor Eric Vittoz has been instrumental in guiding the early elements is still below 1%, and the 'giga' detectors are developments leading to these gigasensors. Not only practically ready to take beam. computing and consumer electronics but also various branches of science can profit from the progress in microelectronics. Some Future Developments The increased density in CMOS allows to integrate References ever more functionality in each pixel while keeping [1] W.K. Hofker, D.P. Oosthoek, A.M.E. Hoe- dimensions of some tens of µm. This can improve berechts, R. van Dantzig, K. Mulder, J.E.J. Ober- precision in space and time for particle experiments. ski, L.A.Ch. Koerts, J.H. Dieperink, E. Kok and Eventually, trigger selectivity may profit if signatures R.F. Rumphorst, The checker board counter: a for useful interactions could be determined. In other semiconductor dE/dx detector with position fields of science various new applications of particle indication, IEEE Trans. Nucl. Sci. NS-13 (June detectors begin to appear. For example, pixel arrays 1966) 208 are now used for X-ray imaging with individual pro- [2] E.H.M. Heijne, L. Hubbeling, B.D. Hyams, P. Jar- cessing of each incoming photonic quantum. This ron, P. Lazeyras, F. Piuz, J.C. Vermeulen and A.

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Wylie, A silicon surface barrier microstrip detec- ickx, C.C. Enz, E. Focardi, F. Forti, Y. Gally, M. tor designed for high energy physics, Nucl. Instr. Glaser, T. Gys, M.C. Habrard, E.H.M. Heijne, L. Meth. 178 (1980) 331 Hermans, R. Hurst, P. Inzani, J.J. Jæger, P. Jarron, [3] L.A.Ch. Koerts, K. Mulder, J.E.J. Oberski and R. F. Krummenacher, F. Lemeilleur, V. Lenti, V. Man- van Dantzig, The 'BOL' nuclear research project, zari, G. Meddeler, M. Morando, A. Munns, F. Nucl. Instr. Meth. 92 (1971) 157 and following Nava, F. Navach, C. Neyer, G. Ottaviani, F. Pelle- articles in the issue grini, F. Pengg, R. Perego, M. Pindo, R. Potheau, [4] F.L.J. Sangster and K. Teer, Bucket - brigade elec- E. Quercigh, N. Redaelli, L. Rossi, D. Sauvage, G. tronics - New possibilities for delay, time-axis Segato, S. Simone, G. Stefanini, G. Tonelli, G. conversion, and scanning, IEEE J. Solid-State Cir- Vanstraelen, G. Vegni, H. Verweij, G.M. Viertel cuits SC-4 (1969) 131 and J. Waisbard , A 1006 element hybrid silicon [5] W.S. Boyle and G.E. Smith, Charge coupled pixel detector with strobed binary output, IEEE semiconductor devices, Bell Syst. Techn. J. 49 Trans. Nucl. Sci. NS-39 (1992) 654 also: (1970) 587 CERN/ECP 91-26 [6] G. Charpak, R. Bouclier, T. Bressani, J. Favier [17] E.H.M. Heijne, F. Antinori, D. Barberis, K.H. and C. Zupancic, The use of multiwire propor- Becks, H. Beker, W. Beusch, P. Burger, M. tional counters to select and localize charged Campbell, E. Cantatore, M.G. Catanesi, E. Chesi, particles, Nucl. Instr. Meth. 62 (1968) 262 G. Darbo, S. D'Auria, C. DaVia', D. Di Bari, S. Di [7] J. Kemmer, P. Burger, R. Henck and E. Heijne, Liberto, T. Gys, G. Humpston, A. Jacholkowski, Performance and applications of passivated ion- J.J. Jaeger, J. Jakubek, P. Jarron, W. Klempt, F. implanted silicon detectors, IEEE Trans. Nucl. Krummenacher, K. Knudson, J. Kubasta, J.C. Las- Sci. NS-29 (1982) 733 salle, R. Leitner, F. Lemeilleur, V. Lenti, M. [8] J.T. Walker, S. Parker, B.D. Hyams and S.L. Letheren, B. Lisowski, L. Lopez, D. Loukas, M. Shapiro, Development of high density readout Luptak, P. Martinengo, G. Meddeler, F. Meddi, P. for silicon strip detectors, Nucl. Instr. Meth. 226 Middelkamp, M. Morando, P. Morettini, A. (1984) 200 (3rd Munich Symposium1983) Munns, P. Musico, F. Pellegrini, F. Pengg, S. [9] Stuart A. Kleinfelder, William C. Carithers Jr., Pospisil, E. Quercigh, J. Ridky, L. Rossi, K. Robert P. Ely Jr., Carl Haber, Frederick Kirsten Safarik, L. Scharfetter, G. Segato, S. Simone, K. and Helmuth G. Spieler, A flexible 128 channel Smith, W. Snoeys, C. Sobczynski, J. Stastny and silicon strip detector instrumentation integrated V. Vrba, LHC1: a semiconductor pixel detector circuit with sparse data readout, IEEE Trans. readout chip with internal, tunable delay provid- Nucl. Sci. NS-35 (1988) 171 ing a binary pattern of selected events, Nucl. [10] H. Spieler, Analog front-end electronics for the Instr. Meth. A383 (1996) 55 Hiroshima Symp SDC silicon tracker, Nucl. Instr. Meth. A342 CERN ECP/96-3 (1994) 205 Hiroshima STD Symposium [18] Sunetra K. Mendis', Sabrina E. Kemeny and Eric [11] G. Lutz, F. Maloberti, P.F. Manfredi, V. Re, V. R. Fossum, A 128 x 128 CMOS Active Pixel Image Speziali, W. Buttler and H. Vogt, on the design of Sensor for Highly Integrated Imaging Systems, a JFET-CMOS front-end for low noise data acqui- Digest of technical papers 1993 IEEE Interna- sition from microstrip detectors, Nucl. Instr. tional Electron Devices Meeting IEDM paper Meth. A264 (1988) 391 22.6, p.583 [12] Erik H.M. Heijne and Pierre Jarron, Development [19] Erik H.M. Heijne and Pierre Jarron, A low noise of silicon pixel detectors: an introduction, Nucl. CMOS integrated signal processor for multi-ele- Instr. Meth. A275 (1989) 467 (1st Leuven Work- ment particle detectors, Proc. ESSCIRC'88 Conf., shop) p.66 UMIST, Manchester, UK [13] C.J.S. Damerell, R.L. English, A.R. Gillman, A.L. [20] E. Beuville, K. Borer, E. Chesi, E.H.M. Heijne, P. Lintern, F.J. Wickens, G. Agnew and S.J. Watts, Jarron, B. Lisowski and S. Singh, AMPLEX, a low- CCDs for vertex detection in high energy noise, low-power analog CMOS signal processor physics, Nucl. Instr. Meth. A253 (1987) 478 (4th for multi-element silicon particle detectors, Nucl. Munich Symp) Instr. Meth. A288 (1990) 157 (5th Munich Sym- [14] Eric A. Vittoz, Tradeoffs in low-power CMOS posium 1989) analog circuits for pixel detectors, Nucl. Instr. [21] R. Ansari, E. Beuville, K. Borer, P. Cenci, A.G. Meth. A275 (1989) 472 (1st Leuven Workshop) Clark, A. Federspiel, O. Gildemeister, C. [15] M. Campbell, E.H.M. Heijne, P. Jarron, F. Krum- Gössling, K. Hara, E.H.M. Heijne, P. Jarron, P. menacher, C.C. Enz, M. Declerq, E. Vittoz and G. Lariccia, B. Lisowski, D.J. Munday, T. Pal, M.A. Viertel, A 10 MHz micropower CMOS front-end Parker, N. Redaelli, P. Scampoli, V. Simak, S.L. for direct readout of pixel detectors, Nucl. Instr. Singh, T. Vallon-Hulth and P.S. Wells, The silicon Meth. A290 (1990) 149 (CERN/EF 89-21, 7 detectors in the UA2 experiment, Nucl. Instr. Nov.1989) Meth. A279 (1989) 388 (Como 1988) [16] F. Anghinolfi, P. Aspell, K. Bass, W. Beusch, L. [22] C. Adolphsen, R.G. Jacobsen, V. Lüth, G. Gratta, Bosisio, C. Boutonnet, P. Burger, M. Campbell, E. L. Labarga, A.M. Litke, A.S. Schwarz, M. Turala, Chesi, C. Claeys, J.C. Clemens, M. Cohen Solal, I. C. Zaccardelli, A. Breakstone, C.J. Kenney, S.I. Debusschere, P. Delpierre, D. Di Bari, B. Dier- Parker, B.A. Barnett, P. Dauncey, D.C. Drewer

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and J.A.J. Matthews, The MARK II silicon strip About the author vertex detector, Nucl. Instr. Meth. A313 (1992) Erik Heijne (F '77) studied physics at 63 the University of Amsterdam, where he [23] F. Krummenacher, Pixel detectors with local assisted in projects on hydrogen/deuteri- intelligence: an IC designer point of view, Nucl. um in palladium (1969) and on quantum Instr. Meth. A305 (1991) 527 (2nd Leuven Work- effects in thin silicon films (1970). He shop) came to CERN in Geneva in 1973, to [24] M. Campbell, E.H.M. Heijne, G. Meddeler, E. work on silicon detectors for the moni- Pernigotti and W. Snoeys, A readout chip for a 64 toring of the neutrino beams. In 1980 the introduction x 64 pixel matrix with 15 - bit single photon of the silicon microstrip detector opened new ways for counting, IEEE Trans. Nucl. Sci. NS-45 (1998) charm and beauty physics. A stay in Leuven (B) in 751 also CERN-ECP/97-010 1984 led to the start of a microelectronics design group [25] R. Ballabriga, M. Campbell, E. H. M. Heijne, X. at CERN. Learning through different contacts in the Llopart and L. Tlustos, The Medipix3 Prototype, IEEE, around 1995 he introduced at CERN the ideas for a Pixel Readout Chip Working in Single Photon radiation hardness by design, which eventually Counting Mode with Improved Spectrometric became the basis for widespread use of CMOS in col- Performance, IEEE Nucl Science Symp. Confer- lider experiments. He is a Fellow of the IEEE and in ence Record 2006, p 3557 1999 received the Merit Award of the IEEE Nuclear and Plasma Sciences Society.

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Eric A. Vittoz was born on 9 May 1938 in where he was appointed Executive Vice-President, respon- Lausanne, Switzerland. He obtained a Dipl. sible for Integrated Circuits and Systems from 1991 to 1997 Ing. degree in 1961 from the Ecole Poly- and for Advanced Microelectronics later. While pursuing technique de l’Université de Lausanne his work on very low-power systems, he championed the (EPUL) and a Ph.D. degree in 1969 from idea of biology-inspired collective processing by means of the Swiss Federal Institute of Technology in analog VLSI; his team has since developed several inte- Lausanne (EPFL), both in Electrical Engi- grated vision systems based on this concept. From 1999 to neering. After spending one year at EPUL as a research 2004, he was partially retired from CSEM, with the position assistant, he joined the Centre Electronique Horloger S.A. of Chief Scientist. He is now fully retired from CSEM. (CEH), Neuchâtel, in 1962, where he participated in the In 1975, Dr. Vittoz introduced the first course on IC development of the first electronic wristwatch. He design at EPFL, emphasizing low-power devices and worked out various possible approaches for very low- circuits. Becoming Professor in 1982, he lectured and power crystal oscillators and frequency dividers in bipo- supervised undergraduate and graduate student proj- lar technology, and co-published the first low-voltage ects in analog circuit design until his retirement in CMOS integrated frequency divider in 1969. 2004. He is still connected with EPFL as an invited In 1971, Dr. Vittoz was appointed vice-director of professor, co-supervising some Ph. D. student proj- CEH, supervising and working on advanced develop- ects. He has participated and still participates in ments in electronic watches and other micropower sys- numerous post-graduate and summer courses there, tems. While developing CMOS frequency dividers that and in many countries around the world. became the standard in Swiss watches, he introduced the A Life-Fellow of IEEE, he has published more than 140 first true single-clock logic circuits. He later pioneered papers and holds 26 patents, receiving the Gold Medal several new techniques for low-power and low-voltage from the Swiss Society of Chronometry and three ESS- CMOS analog design. These include circuits based on CIRC best paper awards. He is an ESSDERC/ESSCIRC Fel- weak inversion operation (that he first applied to the low, after contributing to the organization of these Euro- watch crystal oscillators), bipolar-operated MOS transis- pean conferences for more than 25 years. He was also a tors and pseudo-resistive circuits. These techniques were member of the European Program Committee of ISSCC progressively applied to other low-power systems from 1977 to 1989. As European representative to the including biomedical devices, hearing aids, pagers, sen- IEEE Solid-State Circuits Council from 1987 to 1989, he sor interfaces and various portable instruments. participated in the creation of the SSC Society as one of Together with several colleagues and students at the first AdCom members, and gave lectures for many CEH and EPFL, Dr. Vittoz progressively developed a years as a SSCS Distinguished Lecturer. He was the recip- model of the MOS transistor applicable to low-current ient of the 2004 IEEE Solid-State Circuits Award “For pio- and low-voltage circuit design, which later became neering contributions to low-power modeling and CMOS known as the EKV model. He recently co-authored a circuit design.” book on this original model with Christian Enz. Besides enjoying life with his family, Dr. Vittoz still In 1984, he joined the newly created Swiss Center for pursues technical activities in teaching, writing and spo- Electronics and Microtechnology (CSEM) in Neuchâtel, radically consulting in low-power circuits and systems.

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PEOPLE Ankush Goel and Shih-An Yu Receive SSCS Predoctoral Fellowships for 2008-2009 John Corcoran, SSCS Awards Committee, [email protected]

nkush Goel of USC and implementation of multi-mode multi- Shih-An Yu of Columbia antenna reconfigurable radios. He has AUniversity have won the designed and developed the theory of Solid-State Circuits Society Predoc- concurrent dual-frequency oscillators, toral Fellowship for 2008 - 2009. dual-loop phased-locked loops and Their advisors are Hossein Hashe- concurrent phased-arrays. He has mi and Peter Kinget, respectively. published two MTT papers and one This year the Society had nine in JSSC related to that work. During very qualified nominees, seven his Ph.D. studies, he also worked from U.S. Universities and one on design and theory of sub-dB each from China and India. The noise-figure, high-gain, wideband nominations were reviewed and LNA. ranked by a team of four profes- Shih-An Yu received the B.S. sors from leading universities. and M.S. degrees in electrical engi- (None of these universities had Ankush Goel neering from National Taiwan Uni- nominees in the running for this versity (NTU), Taipei, Taiwan in year’s awards.) 1999 and 2001, respectively. For According to the reviewing his M.S. research, he worked on team, Ankush and Shih-An “stand wideband amplifiers with multiple out through their excellent aca- feedback loops, and 5GHz VCO demic records combined with an and image rejection receiver impressive list of high-quality jour- designs for ISM band applications. nal and conference publications.” From 2001 to 2003, he designed In addition, they said “the research self-calibrated fractional-N frequen- of the two recipients is very inno- cy synthesizers and mixed-mode vative and has the potential to analog baseband circuits for multi- have significant impact on the field standard mobile phone and WLAN of solid-state circuits.” Please join transceivers at VIA Technologies us in congratulating Ankush and Inc., Taiwan. From 2003 to 2005, Shih-An for their achievements and he was a research assistant at NTU for receiving this year’s Fellowship Shih-An Yu and did research on quantization awards. noise suppression in fractional-N Ankush Goel received the From 2003-2004, he was an frequency synthesizers. He also B.Tech. degree in electrical engi- Analog Design Engineer with designed the baseband circuits for neering from the Indian Institute of Texas Instruments, India. While he an energy-efficient transceiver for Technology-Madras, Chennai, India was there, he designed a slew-rate long-term wireless bioactivity mon- in 2003. He was the recipient of the controlled pad driver in digital itoring applications, presented at Prof. Achim Bopp Endowment CMOS process for USB 2.0. the ISSCC in 2006. Prize for best undergraduate hard- Mr. Goel is a recipient of the 2007 Since 2006, he has been work- ware project. He received the M.S. USC Annenberg Graduate Fellow- ing towards his Ph.D. degree at degree in electrical engineering ship. During the summer of 2008 he Columbia University in New York, from the University of Southern Cal- was an intern at IBM T.J. Watson NY under the guidance of Prof. ifornia (USC), Los Angeles with a Research Center, NY, and worked Peter Kinget. His research focuses GPA of 4.0 in 2006. Earlier that year, on the design of a compact, low- on highly scalable design tech- he received an award from USC for power, low phase-noise, wideband niques for RF frequency synthesiz- outstanding academic achievement. digitally controlled oscillator. ers addressing ultra-low supply He is currently pursuing his Ph.D. At USC, his research has focused voltage challenges, robustness degree at USC and is a research on analyzing nonlinear systems issues and area scaling challenges assistant in the Electrical Engineer- exhibiting multiple modes of opera- in extremely scaled CMOS tech- ing - Electrophysics Department. tion and exploiting them for the nologies. He has designed a 0.65V

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fractional-N 2.4GHz frequency ultra wide-band, multi-standard cuits. These Fellowships provide a synthesizer that was presented at frequency synthesizers for soft- $15,000 stipend and up to $8,000 in ISSCC 2007. He was also part of ware-defined radio applications. tuition and fees for the student, and the student team designing a 0.6V At Bell Laboratories, Alcatel- an additional $2,000 for the stu- highly integrated receiver for Lucent, Murray Hill, NJ, he is par- dent's department. The awards are 2.4GHz applications in 90nm ticipating in the design of a frac- granted to students who show CMOS that was presented at ISSCC tional-N frequency synthesizer promise for outstanding doctoral 2008. His latest results on a operating from 50MHz to 8GHz. research, and who have shown 0.042mm2 fully integrated dual Mr. Yu was the recipient of the concrete evidence of achievement band 2.5/5.0GHz analog PLL in a 2008 Outstanding Student Designer early in their graduate careers. 45nm CMOS technology will be Award presented by Analog Nominations are typically due by presented at ESSCIRC 2008. This Devices, Inc. He has published May 1 of each year; see //sscs. ultra-compact PLL incorporates a eight papers in conferences and five org/awards/predoctoral.htm for more customized stacked capacitor- papers in journals. He has one U.S. details on qualifications and the inductor structure that overlays the patent application under review. application process. tank inductor over the loop filter The Solid-State Circuits Society To view a list of prior Fellow- capacitor, achieving a significant grants Predoctoral Fellowships each ship winners see //sscs.org/ reduction of the active area. He is year to two deserving graduate stu- awards/predoctoral.htm#Pastrecip- also investigating architectures for dents in the field of Solid-State Cir- ients.

IEEE DL Vojin Oklobdzija Visits Istanbul in May Focuses on Low Power Digital Design in Talks at Two Universities

SSCS DL Prof. Vojin Oklobdzija lectured on 29 May, 2008 at Istanbul’s Bogazici University (left) and at Istanbul Technical University (right).

EEE Distinguished Lecturer Prof. size on power efficiency, and some tinuous-time filters and increasingly Vojin Oklobdzija of UC Davis design suggestions to reduce power chaotic circuits with digital design delivered two talks on low power consumption. A long discussion fol- are ITUís main areas of interest. I lowed each lecture. Prof Oklobdzija The IEEE Turkey Section is one digital design in Turkey, one on the morning of 29 May, 2008 at Istanbul was delighted by the contributions of of the most rapidly developing sec- Technical University (ITU) and the the attendees, who in turn enjoyed tions in Region 8, with around 15 other later that day at Bogazici Uni- and profited immensely from his talk. chapters and more than 40 student versity (BU), also in Istanbul. Each ITU and BU are two of the lead- branches; both universities have lecture attracted about 25 participants ing universities in Turkey. BU has very strong competing IEEE Stu- from within the institution and from an active IC Design laboratory with dent Branches. At Dogus University neighboring universities, design com- competence in analog integrated an IEEE student branch organizes panies, and research centers. Prof. circuit design, CAD tool develop- an annual student project contest Oklobdzija focused on the problem ment, and low power design; ITU entitled “PROJISTOR,” sponsored of increasing power consumption by is becoming a center for IC design, by IEEE-Region 8, the IEEE Turkey high-complexity digital integrated cir- with several national microelec- Section, and local companies. cuits, what prospects lie in the future, tronics-based studies and projects how power efficiency can be located at its VLSI Laboratory, Izzet Cem Göknar defined, the effect of some parame- which holds Europractice member- CAS Professor, IEEE Fellow ters such as power supply and device ship. Data converters, RF ICs, con- IEEE-CAS Turkey Chapter

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PEOPLE Congratulations New Senior Members 20 Seniors Elected in May, June and July and August Daniel Brookshire Dallas Section C. Andrew Lish New Hampshire Section Dorin Calbaza Toronto Section Chao Lu Santa Clara Valley Section James Chu Atlanta Section Wing Luk New York Section Frank Dunlap San Francisco Section Ron Maltiel Santa Clara Valley Section Luiz Franca Neto Santa Clara Valley Section Mohammad Monzer Mansour Lebanon Section Prince Francis Toronto Section Joo Tham Santa Clara Valley Khosrow Ghadiri Santa Clara Valley Section Antonio Mondragon Torres Dallas Section Steven Gillig Chicago Section Vladislav Potanin Santa Clara Valley Section Alireza Kaviani Santa Clara Valley Section Mohammad Shakiba Toronto Section Ronald Kubacki Santa Clara Valley Section Roger Sheppard Oregon Section Tools: Tips for Making Writing Easier Part 3: Focus on Your Key Message Peter and Cheryl Reimold, www. Allabout communication.com

n the last two columns we dis- paper”? Of course not! You would result—rewarding produced solu- cussed quick ways to structure probably say, “Here are the three tions—captures the essence of the your writing to ensure that you articles you requested,” and then list sentence. I the titles, thus giving the reader more tell your readers what they want to know in a format they can easily fol- information in much easier language. Put the most important words low. Now we come to the writing Don’t worry about sounding too at the end of the sentence. itself: putting one word after the informal if you trust your voice. Inap- In English, the last words get the most other. To choose the best words and propriate or inelegant words will emphasis. To get the reader to focus place them in the most readable jump out at you as you read over on the main point of your sentence, order, focus on your message. What your piece (which you must always try to put it there. Consider some exactly are you trying to say? If you do). In the example you might have famous sentences: To be or not to be, find yourself getting tangled up in said, “Here are the three articles you that is the question (Shakespeare). fuzzy words and complicated struc- asked to see.” Although this is still When you come to a fork in the road, tures, stop and ask yourself just that: not nearly as bad as the original take it (attributed to Yogi Berra). Either What am I trying to say? Don’t write pompous statement, it could be that wallpaper goes, or I do (said to be a thing until you are satisfied with smoother. Check your action words. the last words of Oscar Wilde). Now your answer. Then try the following If you find strings of small words look what happens if we reverse the suggestions. (like asked to see), try to substitute a order: The question is whether to be single verb (like requested). or not to be. Take a fork in the road Trust your voice. Don’t just trust it— when you come to it. Either I go or use it. Say your sentences to yourself Put your main thought in the that wallpaper does. Enough said. (quietly!) before you commit them to main parts of the sentence: the Cheryl and Peter Reimold have the paper or screen. Mouth them, subject, verb, and object. Because been teaching communication skills to whisper them; utter them any way we tend to think and speak directly, engineers, scientists, and business peo- you choose but do not put them on you will usually follow this rule if ple for more than 20 years. Their firm, paper until you have heard them. you trust your voice. Overcomplicat- PERC Communications (+1 914 725 After a while you will find that you ed, wordy writing almost always vio- 1024, [email protected]), offers busi- hear them in your mind as you write lates it. It is an easy rule to test, and nesses consulting and writing services, them. Then you can dispense with it can clarify your sentences most as well as customized in-house courses the embarrassing mumbles. wonderfully. Here is an example. on writing, presentation skills, and on- This is the most important rule for The fact that we rewarded all ideas the-job communication skills. Visit clear and simple writing. Almost all in the brainstorming meeting had their Web site at http://www.allabout- the puffy polysyllabic verbiage peo- the effect of inducing more solu- communica tion.com.This article is ple produce in the name of business tions. Here the subject is fact, the gratefully reprinted with permission or technical writing would never verb had, and the object effect. The from the authors as well as permis- arrive to torture its readers if the writ- result— fact had effect—is meaning- sion from the IEEE Professional ers had been forced to say the mes- less. Let’s try a rewrite. Rewarding all Communication Society Newsletter sage out loud first. Can you imagine ideas in the brainstorming meeting Editor. This article is reprinted from yourself saying, “Per our discussion, produced more solutions. Here the the July/August 2003 issue, Volume enclosed are copies of the docu- subject is rewarding, the verb pro- 47, Number 4, page 10 of the IEEE ments referenced in our conference duced, and the object solutions. The PCS Newsletter.

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CONFERENCES ISSCC 2009 Feb 8-12 Preview Anne O’Neill, SSCS Executive Director, [email protected]

s the world’s leading forum for the presenta- ten 90-minute tutorials still under development will be tion of advances in solid-state circuits and sys- published on the conference site. Atems-on-a-chip, the International Solid-State Circuits Conference offers a unique opportunity for Theme: Adaptive Circuits and Systems engineers working at the cutting edge of IC design Along with the numerous topics that registrants and read- and use to maintain technical currency and to net- ers have come to expect from the ISSCC, many papers work with leading experts. among the 250 in 2009 will focus on the theme “Adap- Here are some highlights of the Society’s flagship San tive Circuits and Systems.” Contributions were encour- Francisco-based conference as of the time of print; cor- aged from researchers and designers who have demon- rections and details may be found in the official Advance strated novel adaptive circuits and system techniques in Program published in November. The web site for con- the subject. ference registration will open at the end of November. Technology scaling is enabling the integration of vast www.isscc.org/isscc. Forums, Tutorials, and the ISSCC systems, encompassing billions of transistors on a single Short Course require special registration. silicon chip. Along with opportunities for integration, In 2009 there will be four plenary presentations, sub-50nm technologies present new challenges of approximately 250 technical papers and nine evening device variability, reliability, and low voltage operation. panels/special evening sessions, with panelists to be Environmental constraints on power consumption and announced; all are included in the registration price. cooling are further complicating the design space. The schedule and details of the all-day Short Course Adaptive circuits and systems offer the potential to on “Low-Voltage Analog and Mixed-Signal CMOS Cir- dynamically optimize operating parameters such as per- cuit Design,” the eight circuit design forums, and the formance and power. ISSCC Student Forum 2009 Anne O’Neill, SSCS Executive Director, [email protected] SSCC’s Student Forum features the highly acclaimed progress is expected, and results with actual silicon communications challenge for hi-tech, the 5-minute implementation are highly encouraged. Papers that presentation. It will return to ISSCC in 2009 on Sun- have been accepted at ISSCC will not be considered for I the Student Forum. However, papers that significant- day afternoon, February 8 and extend into the evening with poster presentations. ly extend an ISSCC publication will be considered. The objective of the ISSCC Student Forum is to pro- Submission will be via the ISSCC web site and are vide a networking venue for students to exchange limited to one per faculty advisor. There will be 30 ideas at an early stage in the graduate education to 40 presentations selected with effective regional process. The presentation opportunity exposes stu- balance in mind. dents to ISSCC quality and encourages future paper Presentations at the Student Forum are not consid- submissions. The five minute limit on presentations ered ISSCC papers; they will not be published or ref- provides a challenge that improves communication erenced as a paper, and do not constitute prepub- skills and will continue this year with shorter and more lication. focused dialogs during the evening poster sessions. For details about submission see www.isscc.org/ Speakers for the Student Forum will be selected isscc/studentforum/ (The deadline is October 31, based on a brief recommendation letter from the advi- 2008). Please contact Professor Anantha Chandrakasan sor (1 paragraph) and research results (a 200 to 250- (Student Forum Chair) at [email protected] , TEL: word abstract and 4 to 6 Power Point slides). Work in 617-258-7619, if you have any questions.

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CONFERENCES 4th Asian Solid-State Circuits Conference - Digital Convergence for a Ubiquitous Lifestyle More than 100 Papers Selected for Meeting on 3 – 5 November, Fukuoka, Japan Koji Kito, A-SSCC 2008 Organization Committee Chair, [email protected]

he fourth Asian Solid-State Circuits Conference Submissions Represent 26 Countries will be held on November 3 - 5, 2008, in Fukuo- A-SSCC 2008 received 309 paper submissions, of Tka, Japan, at the JAL Resort Seahawk Hotel locat- which 116 were selected for presentation. The paper ed on the scenic waterfront of the city. Sponsored by submission distribution is: Taiwan 68, Japan 53, China the IEEE Solid-State Circuits Society, this annual confer- 51, Korea 42, USA 22, India 14, Iran 11, Singapore 11, ence has travelled around major Asian countries includ- Canada 6, Vietnam 5, Sweden 4, Belgium 3, Australia ing Taiwan (2005), China (2006), and Korea (2007). It 2, Finland 2, Hong Kong 2, Poland 2, Switzerland 2, offers a unique opportunity for engineers, researchers Austria 1, Egypt 1, Germany 1, Malaysia 1, Netherlands and business leaders to come together on-site to 1, Portugal 1, Spain 1, Romania 1, United Arab Emi- explore the future of circuit design technologies and to rates 1. Since the TPC consist of a balanced mix of feel the influence of Asian countries in the rapidly glob- experts from both industry and academia, the final alizing IC industry. The theme of this year’s conference technical program covers the interests of attendees is “Digital Convergence for a Ubiquitous Life Style.” from most IC product segments.

Four Tutorial Sessions and Two Panels Tutorials on November 3rd are “Design of Femto-joule Energy Efficient ADCs in CMOS,” ”Advanced SiP Design,” “Economic and Design Choices for Nano-scale Electronic Systems,” and “Advanced Clock Distribution Systems.” The two panel discussions on 4 November are entitled ”SiP2.0: What, When, and How?” and “Digitally Assisted Analog and RF Circuits: Potentials and Issues.” Mr. Yoshiaki Dr. Young Hwan Dr. Bill Krenik Kushiki Oh Industrial Program In A-SSCC’s unique “Industry Program,” speakers pres- Plenary Talks ent cutting-edge product chips, not only in a detailed Three plenary talks will be presented by distin- chip or circuit description but also through demonstra- guished leaders in the IC industry: tions and evaluation results to show how customers have improved their performance by using the chips. The first speaker, Mr. Yoshiaki Kushiki, Senior Fel- Student Design Contest low of Panasonic (Japan) will give a speech entitled Authors of the eight outstanding chip designs accepted “Aiming for an Environmental-Oriented CE Platform.” for the conference program will offer demonstrations and commentary at the conference site. The student The second speaker, Dr. Young Hwan Oh, Presi- design that best reflects the high research standards of dent and CEO of Dongbu HiTek Semiconductor Asian academies will be selected from the eight. (Korea) will talk on “Foundry- Fabless Collaboration I am looking forward to seeing you in November for Semiconductor SoC Industry in Korea.” in Fukuoka, and hope that you will enjoy an excellent meeting and warm hospitality at the conference. The last speaker, Dr. Bill Krenik, CTO of TI (USA) For more detailed information about A-SSCC, will give a talk on “4G Wireless Technology: When please visit the web site: www.a-sscc.org will it Happen? What does it Offer?”

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CONFERENCES The International Conference on Computer Aided Design (ICCAD) Previews Novel Program External Workshops will Collocate with ICCAD on 10-13 November in San Jose Juan Antonio Carballo, ICCAD Publicity Chair, [email protected]

lready past its 25th anniversary, the Internation- top of emerging design fields. This year’s meeting al Conference on Computer-Aided Design offers superb papers and tutorials within a venue for A(ICCAD) continues to evolve with an outstand- maintaining and growing one’s network and touch- ing technical program in 2008. Offering high quality ing base with all aspects of the electronic design technical papers, interactive panels, networking recep- automation sector. tions, and embedded and stand-alone tutorials, ICCAD From 458 worldwide submissions, a 90-strong tech- will also open its doors to new external workshops, nical program committee selected 122 outstanding which will be collocated with the conference and will papers for presentations split into 40 sessions over leverage the professional management for which it is three days. ICCAD will also feature four half-day tuto- known. rials plus three embedded tutorials and two special designer sessions providing additional broad per- Outstanding Keynotes and Special Talks in Emerg- spectives. To enable registrants to attend tutorials and ing Fields collocated workshops, tutorials will run in parallel In the opening session, a keynote address by Mary with technical sessions, while workshops will be held Lou Jepsen, founder and CEO of Pixel Qi and chief on Sunday and Thursday. hardware architect and first CTO of the “One Laptop Recognizing the increasing value of networking, per Child” project will focus on innovating computing ICCAD will host numerous social events and meetings platforms for emerging low-income geographies. Dr. designed to keep attendees in touch with like-mind- Jepsen will also speak on CAD for displays. ed colleagues. These events include ICCAD’s tradi- Our second keynote will feature the world- tional Monday evening panel on the future of tech- renowned Dmitri “Mitya” Chklovskii, of Janelia Farm, nology plus numerous meetings for CEDA, SIGDA, Howard Hughes Medical Institute, whose research is DATC, and other organizations. on the human brain and how it relates to conventional computers. About ICCAD During lunch on Tuesday, November 11, Giovanni The International Conference on Computer-Aided de Micheli, a distinguished EDA (Electronic Design Design (ICCAD) is the world’s premier conference in Automation) veteran will discuss exciting new fron- electronic design technology and has served EDA and tiers in biology and environmental engineering. design professionals for the last 25 years by highlighting new challenges and breakthrough innovative World Class Technical and Non-technical Program solutions for integrated circuit design technologies ICCAD continues to be the ideal place for discover- and systems. To learn more, please visit the ICCAD ing top design technology innovation and staying on website at www.iccad.com.

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CONFERENCES ICUWB 2009 to Focus on Microvave and Millimeter Wave Band Technology IEEE International Conference on Ultra-Wideband Will Meet on 9–11 September 2009 in Vancouver Lutz Lampe, General Chair, 2009 IEEE ICUWB, [email protected]

he IEEE International Conference on Ultra- customers of UWB technology. The ICUWB program Wideband (ICUWB) of 2009 will center around of 2009 will feature invited plenary sessions and sym- the general topic of UWB transmission in posia by international experts and new product dis- T plays by market leaders in the field. micro-wave and millimeter wave bands and over power lines. The technical program will extend over three full Continuing a series of annual international UWB days and include topics in conferences held in Baltimore (2002), Reston-VA • UWB Hardware Architecture and Implementation (2003), Oulu (2003), Kyoto (2004), Zurich (2005), (RF modules, circuits and systems, low power con- Waltham-MA (2006), Singapore (2007), and Hannover sumption techniques, pulse generation and detec- (2008), it will focus on the latest advances in UWB tion, OFDM implementations, integrated circuits technology, current and future applications ranging designs, and system architectures) from UWB communication for personal area and sen- • Antennas and Propagation (UWB antennas and arrays, sor networks to UWB-based localization and posi- channel measurements and modeling, field trials) tioning systems to UWB vehicular radar and imaging • UWB Cognitive and Cooperative Systems (energy systems, and standardization and regulation for UWB efficient cross-layer design, spectrum sensing and transmission. dynamic spectrum sharing) The conference venue is the Hyatt Regency Vancou- • Communication and Signal Processing (coding and ver, located in the heart of the city. Main technical and modulation, ranging, localization and positioning) social functions will be held at the Hyatt’s Perspectives • Applications (wireless personal/body area net- Level on the 34th floor, from which ICUWB attendees works, sensing and medical imaging, home net- will have a stunning picture-postcard view of Vancou- working, radar, consumer electronics) ver and its surrounding scenery. The social program • Standardization and Regulation (spectral manage- includes a welcome reception, luncheons, and the gala ment, co-existence, emerging wireless standardiza- conference banquet, tions). ICUWB has evolved since 2002 into the leading Prospective authors are invited to submit technical annual conference solely dedicated to UWB technol- papers until 23 February 2009. All accepted papers will ogy, bringing together more than 200 researchers and be published by the IEEE and included in IEEE Xplore. engineers from academia, industry, government and For more information visit the 2009 ICUWB web- standardization organizations, as well as vendors and site www.icuwb2009.org.

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CHAPTERS First IEEE COMCAS a Mega Event in Tel Aviv SSC Sessions Span Two Days Mark Ruberto, IEEE Israel Chapter Chair of the Solid-State Circuits Society, [email protected], Shmuel Auster, COMCAS Conference Chair, [email protected], Barry Perlman, COMCAS Technical Program Chair, [email protected]

he annual meeting of the from many companies and R&D rooms and a large professional Israeli Chapter of the Solid- institutions, encouraged and exhibition with 62 booths. The State Circuits Society took inspired the organizers to work program offered a very impressive T with other IEEE societies to take list of speakers, including expert place at the Hilton Hotel in Tel Aviv on 13-14 May, 2008 within the on the challenge of organizing an R&D engineers, top scientists and framework of the first IEEE Confer- even greater event with the help of managers from Asia, the US, ence on Microwaves, Communica- the larger IEEE and global techni- Europe, Latin America, the Far East tions, Antennas, Solid-State Circuits cal community. The three addition- and Israel. and Electronic Systems (IEEE COM- al IEEE societies, namely the Solid- The disproportionately large CAS 2008). State Circuits Society (SSCS), the number of solid-state circuit con- Building on the yearly IEEE Communications Society (Com- tributions required the extension Israel AP/MTT & AES Chapters Soc), and the Electromagnetic of the original, one day SSCS ses- Symposium, this exciting, two- Compatibility Society (EMCS) sion to two full days. On the first, day conference and exposition joined forces with the Microwave Tuesday, May 13, there were was organized as a multidiscipli- Society (MTT-S), Antennas and eight papers in Analog/Mixed nary forum for internationally rec- Propagation Society (AP-S), and Signal and five papers on VLSI/ ognized scientists and engineers Aerospace & Electronic Systems SoC/Sensors. On Wednesday, and students from various com- Society (AES-S) to create this May 14, there were four papers plementary disciplines to meet mega-event. on VLSI/SoC/Sensors, 14 papers and discuss subjects of common COMCAS 2008 delivered on the on RFICs, and three papers on Si interest. promise of attracting the global MEMS. Last year’s very successful 21st community to Israel, with over 700 There were two keynote speak- IEEE AP/MTT&AES Chapters Sym- participants, 146 papers, 15 techni- ers: The first was Raviv Melamed, posium, with over 500 participants cal sessions, five parallel meeting General Manager, Mobile Wireless

Group lunch at COMCAS 2008 on the Mediterranean 62 exhibitors operated booths at COMCAS 2008. Coast of Israel.

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COMCAS 2008 keynote speakers were Linda Katehi and Raviv Melamed.

Group, Intel Corp., Haifa, Israel. Data Base Issues Barry Perlman, U.S Army Commu- The title of his talk was “Future • Phased Arrays, Communications nications-Electronics RD&E Center Wireless Applications and Tech- Networking (CERDEC) and incoming MTT-S nologies.” The second keynote • C3/C4 modeling and simulation, President. SSCS Technical Sessions speaker was Prof. Linda Katehi, and analysis (MS&A) were organized by Mark Ruberto, Provost, University of Illinois, USA • RF Propagation to MMW Wave- SSCS Israel Chapter Chair, David whose talk was entitled “Advanced lengths Gidony, and Miki Moyal, all from Component Architectures.” Both • High Power Amplifiers the Israel Design Center of Intel keynote addresses were very well • Advanced Devices for Commu- Corporation. received. nications The full technical program can Other conference sessions had • RF Filters, Modeling for EMC, be seen on the conference web- an interesting breadth of technical MEMs page at www.comcas.org, and papers, from leading edge • Ultra-wide Band Technology papers from the conference are microwave devices, ingenious • Metrology and Parameter Extrac- now available in IEEE Xplore. It is architectures, advanced analog tion the intent of the Israel SSCS Chap- and mixed-signal circuits to clever • Space-time Adaptive Processing ter to participate annually in sub- antenna technology, and informa- • Cognitive Radios/Radar and sequent COMCAS conferences as tion on new and old RADAR and Spectral Processing the main venue for its annual tech- communication systems. Many COMCAS 2008 was chaired by nical meeting, and to encourage a local practitioners, engineers and Shmuel Auster of Elta Systems. The larger foreign participation as well. decision makers from the technol- Technical Program Chair was Dr. ogy, communication, radar and electronic systems communities participated and many presented papers on technology, circuits, system aspects and innovations in these fields. Fascinating up-to-date topics were also presented to enrich the microwave, antenna, communication, EMC, solid-state circuits (RFIC) and electronic systems communities with knowledge, ideas, applications and challenges. Emphasis was on applications-oriented research and development, from devices and components to circuits and systems, to antennas, communications and networking, sensors and radar and software, on a variety of subjects including • FICs • Low Power Solid-State Circuits • Microwave Plasmonics and Nano- Mark Ruberto (center), a COMCAS 2008 Technical Session organizer, receiving meta materials a certificate of appreciation from COMCAS Chair Shmuel Auster (left) and Barry • Novel Antennas and Spectrum Perlman, COMCAS Technical Program Chair.

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CHAPTERS SSCS-Singapore Hosts 90 at ISSCC 2007 Tutorial in August DVD Replay Combined with Colloquium on How to Write an ISSCC Paper

Prof. Yong Ping Xu moderating an ISSCC DVD tutorial replay at the National University of Singapore in August.

o encourage submissions to ISSCC from industry in Asia, TSSCS-Singapore hosted an ISSCC 2009 promotional event in August featuring a replay of the 2007 Conference tutorial “Continu- ous-time Sigma-Delta Data Con- verters” by Yiannos Manoli. Spearheaded by Prof. Yong Ping Xu., Singapore Chapter Treasurer, in cooperation with the Department of Electrical and Computer Engi- neering of the National University of Singapore, the event was open to academics and students and attracted 24 from industry. Admission was free and light refreshments were served. Dr. Xu also moderated the replay of the Manoli tutorial as well as a presentation of the audio tutorial “Writing a good ISSCC paper,” created by ISSCC Press/Awards Chair Kenneth C. Smith and past ISSCC Program Chair Prof. Jan Van der Spiegel of the University of Pennsylvania, who is SSCS Chapters Chair. It is available at the Societyís website //sscs.org/Chapters/07ChptL- nch/ 07FEBCafe.htm. SSCS-Singapore expects to hold more ISSCC 2007 DVD replay events at Nanyang Technological University and at other sites.

Katherine Olstein, SSCS Administrator, [email protected]

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SSCS-Taipei Offers Short Course on CMOS Single-chip Radio Design Programs in Hsinchu and Taipei Funded by SSCS Extra Chapter Subsidy Eric Tsung-Hsien Lin, IEEE SSCS Taipei Chapter, [email protected]

Dr. Bogdan Staszewski of Texas Instruments presenting his lecture on CMOS single-chip radio design at National Chiao- Tung University, Hsinchu, on August 20, 2008 (left) and at National Taiwan University, Taipei, on August 21, 2008 (right).

ntegrated radios for multi-GHz Approximately 45 participants ital phase-locked loop (ADPLL). frequencies have recently attended his lecture “Digital RF Various aspects of ADPLL design, migrated to low-cost nanome- Processor (DRPTM) for Single-chip including theoretical analysis, sys- I Mobile Radios: All-digital PLL, Trans- tem modeling, sub-circuit designs, ter-scale CMOS processes. Unfortu- nately, this environment, which is mitter and Discrete-time Receiver” at and simulation considerations optimized for digital circuits, is National Chiao-Tung University in were discussed, including transmit- extremely unfriendly for conven- Hsinchu, and 35 attended the same ter design based on the ADPLL. Dr. tional RF and analog designs. As a course at National Taiwan University, Staszewski next presented a direct- result, a paradigm shift is occurring Taipei, on August 20 and 21, 2008, sampling discrete-time receiver that transforms RF and analog cir- respectively. Participants from design and several more design cuit design complexity to the digi- industry and academia were about examples. tal domain for wireless transceivers equal, an indication that the topic His course, which included a to enjoy the benefits of digital elicited wide interest from the Tai- good mix of theoretical and practi- approaches, such as process node wanese IC research and develop- cal design knowledge, was well- scaling and design automation. ment communities. received and considered valuable In light of this shift, SSCS-Taipei Dr. Staszewski began with an for the research of many attendees. invited Dr. Bogdan Staszewski of introduction to the DRP approach The Taipei Chapter greatly Texas Instruments to give a two- and explained how it was con- appreciates the financial support day short course on the subject of ceived initially. He then described of the IEEE Solid-State Circuits CMOS single-chip radio design. the design principles of an all-dig- Society for this program.

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CHAPTERS SSCS DL Stefan Rusu Speaks at Santa Clara Valley Chapter Meeting in August Katherine Olstein, SSCS Administrator, [email protected]

SCS DL Stefan Rusu, a Senior Principal Engineer at Intel Cor- Sporation, addressed the Soci- ety’s Santa Clara Valley chapter on 21 August about “Power and Leak- age Reduction in the Nanoscale Era.” One attendee, Himanshu Arora said, “I rate his talk among the top 1% of presentations that I have ever attended at IEEE local meetings.” The slides that Dr. Rusu used may be found on the chapter website, at //ewh.ieee.org/r6/scv/ssc/index.html. Dr. Stefan Rusu discussed nanoscale power and leakage reduction with mem- Lectures by Ali Niknejad of UC bers of SSCS Santa Clara in August. Berkeley, Michael H. Perrott of MIT and Boris Murmann of Stan- communication links; and the design low jitter and high PLL bandwidth is ford are planned for the chapter’s of several key building blocks, such required by discussing techniques for September, October and Novem- as the LNA, mixer, and PA. achieving high performance digital ber meetings, respectively. Dr. Perrott (now with SiTime, Sun- fractional-N synthesizers, including Prof. Niknejad will speak on nyvale, CA) will discuss the imple- high resolution time-to-digital conver- research at the Berkeley Wireless mentation advantages provided by sion, digital quantization noise can- Research Center (BWRC) related to digital phase-locked loops compared cellation, and low-jitter divider struc- mm-wave electronics, including to their analog counterparts, and tures. Prof. Murmann will present active and passive design techniques; explore the question of whether such “Future Directions in Mixed-Signal IC circuit approaches, and system archi- digital structures can support high Design” in his talk. The Santa Clara tecture for short range mm-wave performance applications in which Valley Chapter Chair is Dan Oprica. SSCS-Scotland Sponsors Technical Meeting in September K. Kundert Speaks on Verification of Complex Analog Circuits Jim Brown, SSCS-Scotland Chapter Chair, [email protected]

round 40 people from local Dr. Ken Kundert is President industry and academia gath- and co-founder of Designer's ered at the Central Edinburgh Guide Consulting, a company that A is guiding the industry towards the offices of Dialog Semiconductor on 28 September, 2008 to hear Dr. Ken adoption of formalized analog ver- Kundert talk about Verification of ification. He worked previously at Complex Analog Integrated Circuits. Cadence and HP, where he created The historic background of Edin- Spectre, SpectreRF, Verilog-A/MS burgh Castle contrasted with a topic and HP's (now Agilent's) harmonic which is at the leading edge of tech- balance simulator. He has written nology development. three books on circuit simulation Verification is becoming widely and modeling and created "The recognized as one of the most Designer's Guide Community" important issues in designing large From left: SSCS-Scotland members Dr. website. He received his Ph.D. in complex analog and RF mixed-sig- Sebastian Loeda and Dr. Paul Ham- Electrical Engineering from UC nal circuits. As a result, design mond, with Dr. Ken Kundert. Berkeley in 1989 and was elevated methodologies are starting to to the status of IEEE Fellow in Jan- change, mirroring a comparable Kundert showed why the problem uary 2007 for contributions to sim- change in digital design 10-15 has become so significant, and ulation and modeling of analog, years ago. In his presentation, Dr what people are doing to control it. RF, and mixed-signal circuits.

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CHAPTERS Leuven Student Branch and SSCS Chapters Organize 2nd SSCS-Benelux Microelectronics Symposium Cedric Walravens, IEEE Student Branch, Leuven, [email protected]

fter the success of last year’s first Microelectronics Sympo- Asium, the IEEE-Leuven Stu- dent Branch and SSCS-Benelux chapters again put their hands together to organize a second symposium at the Electrotechnical Engi- neering Department of K.U.Leuven. This year’s meeting set out to investigate how industry and research institutions cope with the various budgets encountered by engineers, in particular how constraints, such as cost, energy consumption, and silicon area drive [or “empower”] them to go beyond From left, Raff Rovers (NXP), Willy Sansen (SSCS President), Damien Mac (On the current state-of-the-art. Semiconductor), Ramses Valve kens (EASICS) and Cedric Walravens (IEEE Leu- Sponsored by On Semiconduc- ven Student Branch Chair). Missing from this picture are Wimp Deane (K.U.Leu- tor (formerly AMIS) and NXP on 19 ven) and Tim Piessens (ICsense). March, 2008, the event included a • Ramses Valvekens (EASICS) and • Damien Macq (On Semiconduc- total of five speakers, who pre- Tim Piessens (ICsense) reported tor) presented an overview of sented their views on “Power of the results of the fruitful cooper- both digital and analog commer- Budget”: ation between their companies, cial solutions currently available • Professor Wim Dehaene (K.U. both spin-offs of K.U.Leuven, on to customers world-wide and Leuven) gave an introduction a project concerning novel com- the different challenges encoun- to Wireless Sensor Networks mercial RFID applications. tered during their development. (WSN) and presented the cur- • Professor Willy Sansen (K.U.Leu- • Raf Roovers (NXP) covered the rent status of the Flemish-funded ven and SSCS President) elabo- whole design process from IWT-sbo Pinballs research proj- rated on the question of whether research to the final development ect that focuses on the in-door Moore’s Law will save microelec- of a W-USB product in a wrap-up localization of ultra-low power tronics and whether there is such speech, and shared his experi- RFID nodes. a thing as “Moore than Moore.” ences in tackling different hurdles. Preview of EDSSC2008 in Hong Kong Three-Day Program in December to Feature 150 Papers and Plenary Talks by SSCS DLs T. Kawahara and I. Young KP Pun, General Co-Chair, EDSSC'08, [email protected]

he 4th IEEE International Con- ference on Electron Devices Tand Solid-State Circuits (EDSSC 2008) will be held at the Renaissance Kowloon Hotel in Hong Kong from 8 to 10, December, 2008. The conference hotel is next to the famous Victoria Harbour, where attendees can enjoy Hong Kong’s most beautiful night views. Organized by the IEEE Electron Devices/Solid-State Circuits Hong Kong Joint Chapter and sponsored by the Hong Kong Applied Science and T. Kawahara and I. Young will deliver plenary talks at EDSSC in December 2008.

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Technology Institute and K. C. Wong renowned experts in the ED/SSC Clocking and Analog Circuits in Education Foundation, EDSSC 2008 is fields. High Performance Processors,” by a three-day program covering broad The first is “SPRAM (SPin-trans- Dr. Ian Young, Intel Senior Fellow, areas in electron devices and solid- fer torque RAM) Technology for and Director of Advanced Circuit state circuits. It is expected that 150 Green IT World,” by Dr. Takayuki and Technology Integration, Tech- technical papers will be presented by Kawahara, Chief Researcher, Cen- nology and Manufacturing Group, authors both from academia and tral Research Laboratory, Hitachi Intel Corporation, USA. industry around the world. Ltd., Japan. Details about the conference can Highlights of the conference The second is “The SOC trans- be found at the conference web- include two plenary speeches by formation of the Microprocessor - site: www.ee.cuhk.edu.hk/edssc08.

IEEE SSCS Joint Chapter Formed in Penang, Malaysia Yut Hoong, Chow. Chapter Chair, IEEE MTT-ED-SSCS Joint-Chapter, Penang, Malaysia Boon Eu, Seow. Secretary, IEEE MTT-ED-SSCS Joint-Chapter, Penang, Malaysia

ounded by Dr. Grant A. Ellis niques Society, the IEEE Elec- Penang - Malaysia’s “Silicon in 2005, Penang’s MTT/ED/ tron Devices Society and the Island” AP chapter was the first IEEE Solid-State Circuits Society Located in the north of Malaysia, F (MTT/ED/SSC) joint chapter IEEE chapter in the Bayan Lepas Penang is one of the world’s high- Free Industrial Zone, Penang, A website that details the pres- tech manufacturing centers, with Malaysia. ent and past activities of the chap- more than 33 years of electronics A plan to start an IEEE SSCS ter can be viewed at //ewh.ieee. industry activity, begun in 1972 chapter in Penang was started org/r10/malaysia/mttedssc. with the establishment of the first by Mr. Boon Eu Seow in 2006, Free Trade Zone in the country. but delayed due to the insuffi- The Penang Chapter Mission Penang's Bayan Lepas Free The IEEE Penang chapter hopes ciency of SSCS members there. industrial Zone (FIZ) was started in to support and accelerate the Two years later, MTT/ED/AP 1972 by YAB Tun Dr. Lim Chong growth of electronic industries in Chapter Chair Mr. Yut Hoong Eu, former Chief Minister of its region by sponsoring and Chow proposed that the AP unit Penang. Bayan Lepas FIZ. At the organizing seminars and lectures of MTT/ED/AP be replaced by size of 1300 acres, it serves as the by subject matter experts. In this SSCS to better focus on related country's free trade zone and has regard, IEEE distinguished lectur- industries in the Bayan Lepas been home for over three decades ers have been very supportive, Free Industrial Zone. The group to some of the world's top tech- delivering many well-received was reorganized officially on 15 nology companies, such as Intel, and well-attended lectures to our May, 2008 and renamed the IEEE Motorola, Agilent Technologies, group. Microwave Theory and Tech- Robert Bosch, Osram Optosemi-

Map of Penang, courtesy of Penang RF Cluster, www.investpenang.gov.my/PRFC.php

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conductor, Seagate, AMD, Hitachi and Clarion. ISSCC 2007 Short Course DVD Replayed in Penang in Today, more than 700 transna- August, 2008 tional and local companies operate in the industrial parks in Penang, including Penang Biotech Park (also known as Penang Science Park), Perai Free Industrial Park, Perai Industrial Park, Seberang Jaya Industrial Park, Bukit Tengah Industrial Park, Bukit Minyak Industrial Park and Mak Mandin Industrial Park. The State, whose economy for over three decades has been anchored in its manufacturing sector, is now moving upstream to include R&D and product development. Multinational companies including Motorola, Intel, Avago, Agilent, Altera, Renesas and Span- sion have set up significant R&D Attendees at SSCS-Penang’s DVD replay of "RF Transceiver System Design in centres to design MMICs, two-way Nanometer CMOS" on 5 August, 2008. SSCS’s new table skirt may be seen radios, analog and digital ICs and on the right. measuring instruments. Penang’s skilled and knowl- This presentation reviewed the history of transceiver design, which edgeable workers are strongly sup- has led to the inclusion of all-CMOS transceivers in handheld phones ported and incubated by the insti- as a fast-becoming norm. It also examined the changes in the CMOS tutions of higher education in the environment - the side effects of all those shrinking gates that are state, including the University of driving the trend toward digitally assisted, and sometimes even dis- Science Malaysia, Wawasan Open appearing, analog circuits. It also showed examples of how this trend University at George Town, the is making itself felt in the RF arena. Penang Skill Development Center (PSDC) at Bayan Lepas, and the Abstract Malaysia-Japan Technical Institute In articles, textbooks and research papers we are told again and again at Bukit Minyak. that even as CMOS gate lengths become ever smaller, "the analog SSCS-Penang would like to doesn't shrink." But cell phones have gotten smaller somehow, and thank Professor Jan Van der the smart money says they will continue to pack more features in the Spiegel of the University of Penn- same or smaller form factor for some time to come. sylvania and SSCS Administrator, Many of the secrets behind this apparent contradiction lie in IC sys- Katherine Olstein for their advice tem-level design. The RF transceiver designer is faced with myriad and support in setting up the design choices that have huge impacts on overall IC performance; chapter. choosing the performance targets for the IC is not to be taken lightly. We would also like to take this For example, just as in the digital and traditional mixed-signal opportunity to thank our chapter domains, a goal of minimizing die area as opposed to minimizing cur- sponsors, the Motorola Penang and rent draw can lead to a vastly different set of choices for the LNA, Penang Skill Development Center Mixer, baseband filter, and data converter parameters. Likewise, those (PSDC) for allowing us the use of ever-shrinking gate lengths do indeed lead one to make sharp turns their halls and facilities for our along the path toward the final block specifications. chapter meetings and seminars.

Romania SSCS Chapter Formed to Promote Circuit Activities in Eastern Europe Marcel Profirescu, Chapter Chair, [email protected]

fter the. IEEE Romania Sec- SSCS Chapter for quite some time sensus among my colleagues, pro- tion was established in 1986, to stimulate local activities in cir- fessors from other universities, and and EDS-Romania formed in cuits, and to promote circuit activi- experts from design houses was A ties in Eastern Europe. The con- that a local SSCS chapter would 1992, I had the idea of founding an

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help to support SSCS’s 30 members ter will respond to the interests Electronics and Telecommunica- in Romania and foster a stronger and needs of the local industrial tions at the University Politehnica connection between the academic and academic communities: Uni- of Bucharest, established in 1953. and industrial circuit design versities with advanced research There has always been a close research communities and the topics in IC design are spread all two-way interaction between aca- Romanian EDS Chapter. With the over Romania. In the past ten demia, research and industry; Pro- encouragement of Professors Jan years, many design houses have fessor Roman Stere was CTO of Van der Spiegel, SSCS Chapter been established and their num- the first foundry in Romania. Pro- Chair, and Cor Claeys, EDS Presi- ber is expected to increase. The fessor Draganescu founded ICCE, dent, I formed the chapter about a short range goals of the chapter a semiconductor research institu- year ago. It was the right moment to include: tion which continues today as the set up a solid-state circuits forum to • inviting distinguished lecturers National Institute of Microtechnol- enhance the influence of SSCS in to local technical events; ogy. Many generations of local the area. • co-sponsoring local conferences, semiconductor college graduates Shortly afterward, I attended the workshops and seminars; are now spread all around the first SSCS pan-European Chapter • increasing the number of SSCS world. Chair Meeting in Munich on the members; occasion of ESSCIRC 2007, where I • fostering collaboration and the talked to IEEE Region 8 officials, cross fertilization of ideas among About the Author SSCS officers and European lead- SSCS and ED members; ers. Of great help were Professor • paying special attention to SSCS Richard Jaeger, then SSCS Presi- student activities to fulfill the dent, Professor Jan Van der needs of the already demanding Spiegel, Anne O’Neill and Kather- IC circuit and system design ine Olstein, SSCS staff, and also national labor market. Professor Cor Claeys, EDS Presi- In the long run, the new SSCS dent, and William Van Der Vort, chapter is expected to increase the Executive Director of EDS. visibility of IEEE and SSCS in In October 2007, EDS and the Romania and to consolidate its emerging SSCS Chapter organized contacts with the international sci- NADE- (Nanoelectronic Devices), entific communities. a very well attended mini-colloqui- Romania’s origins in semicon- Marcel D. Profirescu graduated um in Sinaia reported in the EDS ductor devices and ICs, both in from the Electronics and Telecom- Newsletter of January 2008, where academic/research and design/ munications Department of the 15 well known international manufacturing predates 1960. At University Politehnica of Bucharest speakers presented papers on nan- the beginning of the 1960’s, a syn- in 1964 and received a Ph.D. from odevices and nanocircuits, This ergetic interaction between the University College, London in mini-colloquium was organized on already-consolidated academic 1974. He teaches Electronic the occasion of the 30th anniver- track and the newly launched Devices and Circuits and TCAD, sary of the CAS-International Semi- semiconductor industry took and heads two research centers in conductor Conference, the equiva- place. A semiconductor school Micro and Nanoelectronics, re- lent of the ESSDERC/ESSCIRC con- was founded in Romania by Pro- spectively in ICT, and a Microelec- ference in Eastern Europe. A first fessor Mihai Draganescu, a bril- tronic Design company in Bucharest. meeting of SSCS members was also liant visionary who wrote a fun- Dr. Profirescu is an IET Fellow, held in Sinaia. The chapter was damental book on Electronic IEEE Senior Member nominated subsequently approved by SSCS, Processes in Semiconductor Devices for FIEEE, EDS Distinguished Lec- IEEE Region 8 and RAB, thanks and Circuits in 1962. It was a nat- turer, ED and SSCS Romania Chap- to. the prompt help of Jean ural out growth of the electronics ters Chair, the EDS SRC Vice Chair Gabriel Remy, Region 8 Director and telecommunications school for Europe, Africa and Middle East and Professor Willy Sansen, SSCS established before the second and the ED/LEO South Africa President. world war by Professor Tudor Chapter Partner. The new SSCS-Romania Chap- Tanasescu, and of the Faculty of

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SSCS NEWS SSCS AdCom Endorses Newsletter-Magazine Conversion in Summer Meeting ISSCC Task Force Previews Ground-Breaking Initiatives Katherine Olstein, SSCS Administrator, [email protected]

n a formal motion at its biannual trative structure, and budget of the also heard a work in progress report meeting on 19 August, 2008 in IEEE Solid-State Circuits Magazine from the ISSCC 2020 Task Force. San Francisco, the SSCS AdCom approved by the IEEE Technical Launching in January 2009 as an I Activities Board (TAB) in June. It official migration of the SSCS endorsed the tone, scope, adminis- Newsletter, which had already SSCS Staff Honored grown into a magazine, the IEEE Solid-State Circuits Magazine will SSCS Executive Director Anne O’Neill and SSCS have formal Editorial and Advisory Administrator Katherine Olstein were honored at Boards and expand upon the SSCS the AdCom’s Executive Committee meeting on News with the addition of regional 19 August, 2008 for the excellence of their work Associate Editors, Technology Sur- on the Society’s enhanced newsletter and their veys, and Tutorials. For more vision during its conversion to Magazine status. information about the conversion of the SSCS News into the Solid- State Circuits Magazine, please read Anne O’Neill’s Executive Director column on page 7 of this issue.

ISSCC Task Force Proposes Far- Seeing Innovations Commissioned in 2007 to build a long-term vision for the conference, the ISSCCC 2020 Task Force has focused on broadening the conference venue beyond San Francisco and on migrating print materials to electronic formats, SSCS Past President Richard C. Jaeger (left) and President Willy Sansen pre- beginning with the conference sented SSCS Executive Director Anne O’Neill (third from left) and Adminis- digest. trator Katherine Olstein with plaques in recognition of their work on the SSCS News and magazine migration. Satellite Conference Program At the meeting, Ms. O’Neill was presented with a plaque by Presi- To Maximize Global Attendance dent Willy Sansen and Past President Dick Jaeger citing her foresight and Minimize Travel Costs and leadership: According to Task Force spokes- “The SSCS AdCom recognizes the outstanding vision and leadership man Dennis Monticelli, ISSCC has of Anne O’Neill in the elevation of the SSCS Newsletter to a Magazine. been structured for nearly half a Her experience and coordination among IEEE staff and volunteers century as a must-attend yearly throughout the world have been crucial to the continuing develop- event in San Francisco in Febru- ment of the publication.” ary. The new satellite confer- Ms. Olstein was presented with a plaque recognizing her attention ences are envisioned as a set, or to detail and outstanding management of the SSCS News: sets, of regional events, each “The SSCS AdCom recognizes the outstanding execution and atten- built around a collection of out- tion to detail of Katherine Olstein in the elevation of the SSCS standing ePapers, and an eDigest Newsletter to a Magazine. Her acquisition of Society news, editing, from the mother conference, with and interactions with authors, volunteers, and the IEEE staff has locally determined forums, work- been crucial to the continuing development of the publication.” shops, and social events, and a It is wonderful to work with both Anne O’Neill and Katherine locally-determined admissions Olstein as we migrate the SSCS News to the IEEE Solid-State Circuits policy and business model tai- Magazine, debuting in Winter 2009. lored to the needs of the specific region. Mary Yvonne Lanzerotti, The satellite program promises Editor-in-Chief to “differentiate ISSCC from the crowd” in the 21st century,” said

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Monticelli. Four SSCS chapters in Asia selected as beta sites for early March 2009 will be “a litmus test for delivering our value to emerging regions,” he said. SSCS Task- force members are Willy Sansen, C.K. Wang, Anantha Chan- drakasan, Yoshi Hagihara, and Nicky Lu. Details about the ISSCC Satellite program will be reported in the new Solid-State Circuits Magazine and Society emails, and on the SSCS website. In an additional AdCom announce- ment, Awards Committee Chair John C. Corcoran reported that elected AdCom member Tom Lee has agreed to serve as the Society’s representative to the National Inventors Hall of Fame, which will rank nominees for recognition in 2009, the 50th anniversary of the integrated circuit.

CEDA Currents: IEEE/ACM MEMOCODE Contest Update Patrick Schaumont, Virginia Tech, Krste Asanovic, UC, Berkeley, James C. Hoe, Carnegie Mellon University

he second annual IEEE/ACM- entries, and the winners were for- description of the design problem MEMOCODE Hardware-Soft- mally announced at this year’s and the contest rules, go to rijn- ware Codesign Contest con- MEMOCODE on 5-7 June, 2008 in dael.ece.vt.edu/memocontest08. For T Anaheim, California, which was col- more information, please contact cluded successfully on 9 March, 2008. This annual contest was con- located with the Design Automation Patrick Schaumont [email protected]). ceived for the ACM-IEEE Interna- Conference (DAC). tional Conference on Formal Meth- This year’s contest will award CEDA Honors Richard Brayton ods and Models for Codesign CEDA hosted a luncheon on 10 (//memocode-conference.com)to June, 2008 at this year’s DAC to help highlight the issues distinct to honor Robert Brayton, winner of hardware-software codesign and to the 2007 Phil Kaufman Award, for expand the conference’s emphasis his impact on the field of electron- on design and practice. On 8 Febru- ic design through contributions in ary, 2008, a ‘‘secret’’ design problem two $1,000 cash prizes in the cat- EDA. Brayton gave a lecture high- involving the AES (Advanced egories of the Highest Perfor- lighting his career path and chal- Encryption Standard) algorithm and mance Design and the Most Effi- lenges, and shed light on some of sorting was revealed on the contest cient Design. In addition, Xilinx the turning points he has wit- website. Contestants were given is sponsoring a special $1,000 nessed while working in industry one month to produce working cash prize for the best entry and academia. In addition to this hardware-software codesigned solu- employing a high-level design lecture, EDA award recipients tions, which would be judged on methodology. Along with the (IEEE Fellow, IEEE Technical Field the basis of performance and ele- three of us (who organized this Awards, and others) were recog- gance of design. Eleven finalists suc- year’s contest), the panel of nized for their accomplishments. cessfully completed the design, judges also includes Kees Vissers from 27 original teams drawn from (Xilinx) and Satrajit Chatterjee (Intel). This year’s contest is IEEE Annual Honors Ceremony diverse geographic regions in the The annual Honors Ceremony, sponsored by Nokia, Xilinx, Blue- US, Europe, and Asia. A panel of considered to be the EEE’s most judges evaluated the final design spec, and CEDA. To see a

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prestigious event, recognizes architec-tures, or simply networks learning about the latest technical exceptional contributions that have on chips (NoCs). CAD tools allow trends in electronic design and made a lasting impact on technol- an exploration of the interconnect automation and to being engaged ogy, society, and the engineering design space early in the design with a community of volunteers. If profession. The program honors cycle and automate the building of you are interested in participating or achievements in industry, research, efficient application-specific inter- have an idea about new topics of education, and service. Seventeen connect architectures. The NoC interest for our conferences, please institute-level award recipients paradigm results in a structured, contact William Joyner (william.joyn- were recognized at this year’s cer- modular interconnect design with [email protected]), CEDA vice president of emony, which was held on 20 Sep- improved performance and energy conferences. tember, 2008 in conjunction with efficiency. the IEEE Sections Congress in The main goal is to let designers 3rd International Conference on Quebec, Canada. explore trade-offs in interconnect Nano-Networks (Nano-Net) This year’s IEEE Honors Ceremo- design—for example, between 15-17 September, 2008, Boston ny started at 6:00 pm, with a dinner band-width, power, reliability, and www.nanonets.org and afterglow reception immediately cost. State-of-the-art methods exist following. The event was hosted by to solve some of the most impor- 18th International Workshop on 2008 IEEE President and CEO Lewis tant, time-intensive problems Power and Timing Modeling Opti- Terman. The theme was “Innovating encountered during interconnect mization and Simulation (PATMOS) to Meet the World’s Challenges.’’ All design, such as interconnect topol- 10-12 September, 2008, Lisbon, those attending the Sections Con- ogy synthesis, core mapping, Portugal www.fpl.uni-kl.de/congress were invited. For further infor- crossbar sizing, route generation, ferences/patmos/patmos.html mation, please see ‘Awards News’ on resource reservation, and RTL the IEEE web site or contact William code and layout generation. Appli- 16th IFIP/IEEE International Con- Joyner ([email protected]). cation-specific inter connect opti- ference on Very Large Scale Inte- mization can lead to significant gration (VLSI-SOC) Perspective: NoCs and EDA Tools improvements in all relevant cost 13-15 October, 2008, Rhodes Improve MP SoC Designs metrics. Improvements by factors Island, Greece Many multiprocessor SoCs (MPSoCs) of 2 to 5 are not uncommon, and //vlsi.ee.duth.gr/vlsisoc-2008 are used in devices where low- become even greater with technol- energy operation of the system is ogy and architectural complexity Embedded Systems Week critical. As technology advances, scaling. Design automation sup- (ESWEEK) wire scaling is not on par with port is essential to guarantee that 19-24 October, 2008, Atlanta transistor scaling. Moreover, the these custom-fit solutions can be www.esweek.org number of communicating compo- readily deployed, tested, and veri- nents in the chip, along with their fied. Although the state of maturity IEEE/ACM International Confer- speed of operation, is increasing. of these tools is not perfect, results ence on Computer-Aided Design Because of these factors, the com- are promising, and automated (ICCAD) munication between the cores is interconnect design is poised to 10-13 November, 2008, San Jose, causing a major bottleneck for become an essential component in California system performance and energy energy-aware SoC design and vali- www.iccad.com/2008/index.html consumption. With architectures dation flows. becoming more interconnect-dom- Direct any questions and com- Formal Methods in Computer inated, achieving an energy-effi- ments about this report to Srinivasan Aided Design (FMCAD) cient on-chip interconnect archi- Murali ([email protected]). 17-20 November, 2008, Portland, tecture tailored to the needs of the Oregon applications running on the chip is //es.fbk.eu/events/fmcad08 an important challenge that Upcoming CEDA Events designers face. IEEE CEDA currently sponsors or CEDA Currents is a publication In recent years, researchers have cosponsors ten conferences and of the IEEE Council on Electronic addressed this challenge in two workshops, and two additional con- Design Automation. Please send ways: by developing methods and ferences in which it is in technical contributions to Jose Ayala (jay- CAD tools to achieve an energy- cooperation with other societies. [email protected]) or Anand Raghu- efficient design and by developing Our conferences provide excellent nathan ([email protected]). scalable micro network-based opportunities for those interested in

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SSCS EVENTS CALENDAR Also posted on www.sscs.org/meetings SSCS SPONSORED MEETINGS Lecce, Puglia, Italy 2009 Radio Frequency Integrated Circuits 2008 Asian Solid-State Circuits Conference Paper due date : Passed Symposium www.a-sscc.org/ Contact: [email protected] www.rfic2009.org/ 3-5 November, 2008 7-9 June 2009 Fukuoka, Japan 2008 International Conference on Computer Aided Boston, MA Contact: Secretariat of A-SSCC2008 Design (ICCAD) Paper deadline: 6 Jan 2009 E-mail: [email protected] www.iccad.com/ Contact: Larry Wicker, [email protected] 9-13 November 2008 2009 ISSCC International Solid-State San Jose, CA 2009 Design Automation Conference Circuits Conference Paper due date : Passed www.dac.com www.isscc.org Contact: Kathy MacLennan, Conference Manager 27-31 July 2009 8– 12 February 2009 [email protected] San Francisco, CA San Francisco, CA, USA Paper deadline: 19 Nov 2008 Paper deadline: 22 Sept. 2008 Conference on VLSI Design Contact: Kevin Lepine, Conference Manager Contact: Courtesy Associates, vlsiconference.com/vlsi2009/ [email protected] [email protected] 5-9 January 2009 New Delhi, India Hot Chips 2009 Symposium on VLSI Circuits Paper Deadline: Passed www.hotchips.org www.vlsisymposium.org August, 2009 16-18 June, 2009 IEEE International Conference on Microelectronic Stanford, CA Paper deadline: 14 Jan 2009 Test Structures Contact: Phyllis Mahoney, [email protected] www.see.ed.ac.uk/ICMTS/ ISLPED International Symposium on Low Power 30 Mar – 2 Apr 2009 Electronics and Design 2009 Organic Microelectronics Workshop Oxnard, CA www.islped.org/ www.mrs.org Paper Deadline: Passed 2009 Date TBD July 6-9, 2009 Technical Chairman: Richard Allen Contact: Diana Marculescu, San Francisco, CA 94103 [email protected] [email protected] Contact: Edwin A. Chandross, [email protected] Design Automation and Test in Europe (DATE) 2009 IEEE Integrated Circuit Ultra-Wide Band 2009 ICUWB 2009 Custom Integrated Circuits Conference www.date-conference.com/ www.icuwb2009.org www.ieee-cicc.org/ 20-24 April 2009 9-11 Sep 2009 20–22 September 2009 Paper Deadline: Passed Vancouver, Canada San Jose, CA, USA Nice, Alpes-Maritime, France Paper deadline: 23 Feb 2009 Paper deadline: TBD Contact: Lutz Lampe, Chair, [email protected] Contact: Ms. Melissa Widerkehr, VLSI -TSA/DAT Conference Manager [email protected] vlsitsa.itri.org.tw/2009/General/ ESSCIRC/ESSDERC 2009- 39th European Solid 27-30 April 2009 State Circuits/Device Research Conferences SSCS PROVIDES TECHNICAL Hsinchu, Taiwan www.esscirc2007.org CO-SPONSORSHIP Paper deadline: 18 Oct 2008 14 - 18 Sep 2009 Sensors Conference VLSI-TSA Contact : Clara Wu Athens, Greece www.ieee-sensors2008.org [email protected] Abstract deadline: 4 Apr 2009 26-29 October 2008 VLSI-DAT Contact: Ms. Elodie HO [email protected] Contact Cor Claeys, IMEC, [email protected]

SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State Circuits Society of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member of the Solid-State Circuits Society. This newsletter is printed in the U.S.A and mailed Periodicals Postage Paid at New York, NY and at additional mailing offices. Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane, Piscataway, NJ 08854. ©2008 IEEE. Permission to copy without fee all or part of any material without a To maintain all your IEEE and SSCS copyright notice is granted provided that the copies are not made or distributed for direct commercial subscriptions, email address corrections to advantage and the title of publication and its date appear on each copy. To copy material with a copy- [email protected] right notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man- To make sure you receive an email alert, keep ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966. your email address current at sscs.org/e-news

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