DOCSLIB.ORG

NP-4™ Network Processor

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
NP-4™ Network Processor NETWORK PROCESSOR PRODUCT BRIEF † HIGHLIGHTS ™ NP-4 Network Processor – Single-chip, programmable, 100-Gigabit throughput (50-Gigabit full duplex) wire-speed 100Gbps NPU for Carrier Ethernet Applications network processor – Line card, services card, pizza box and switch card applications Mellanox’s NP-4 is a highly flexible network processor providing wire-speed packet processing with both an integrated traffic manager and a control CPU. NP-4 provides the silicon core of – Based on Mellanox’s NP-3 with performance next-generation Carrier Ethernet Switches and Routers (CESR). scaling and an enhanced feature set – On-chip CPUs for control CPU offload Through programming the NP-4 delivers a variety of applications such as L2 switching, QVLAN – On-chip Fabric Interface Controller for stacking, MPLS and VPLS, and IPv4/IPv6 routing coupled with QoS for providing flow-based interfacing to Ethernet fabrics as well as third- service level agreements (SLA). party fabric solutions Mellanox’s NP-4 is a highly flexible network processor providing wire-speed packet processing – System-wide traffic management with with both an integrated traffic manager and a control CPU. The NP-4 offers the speed of an hierarchical scheduling ASIC combined with the flexibility of a programmable microprocessor. It provides the silicon – Flexible processing with programmable packet core of next-generation Carrier Ethernet Switches and Routers (CESR). Through programming parsing, classifying, modifying and forwarding the NP-4 delivers a variety of applications such as L2 switching, QVLAN stacking, MPLS and – IP reassembly VPLS, IPv4/IPv6 routing coupled with QoS for providing flow-based service level agreements – Enhanced support for video streams and IPTV (SLA). – Embedded search engine eliminating the need The NP-4 integrates into a single chip several functions that would normally be found in for external co-processors separate chips: – On-chip OAM protocol processing offload – 50-Gigabit full-duplex processing – Integrated MACs: – Serdes interfaces configurable to various – Classification search engines – 48 1-Gigabit MACs network interfaces: – 50/100-Gigabit traffic manager – Ten 10/20-Gigabit Ethernet MACs – Ten XAUI/RXAUI interfaces – On-chip Control CPU – Three Interlaken MACs – 24 quad-speed SGMII ports or 48 tri-speed – On-chip Quality of Service CPU – One 40-Gigabit MAC QSGMII ports – Fabric Interface Chip (FIC) functionality – Three Interlaken MACs – Support for OC-768 framer, switch fabrics and FLEXIBLE PACKET PROCESSING external 100G Ethernet MAC – Single 40G MAC NP-4 provides exceptionally flexible packet processing enabling system designers to future – Internal TCAM proof their designs to support new protocols and features through software updates. Packet – On-chip hardware time-stamping supporting parsing is supported for any field anywhere in the packet. Various table lookup options are IEEE1588v2 provided with support for long lookup keys and results. Flows are classified based on any combination of extracted packet information. Any packet header and content can be edited – Support for Synchronous Ethernet ITU-T G.8261 as required by Circuit Emulation Services and packets can easily be replicated to support multicast applications. A ‘run to completion’ processing model guarantees support for processing scenarios of any complexity. Large code – PCI-Express external host interface space is provided to support complex applications as well as true hitless code updates. – Comprehensive on-chip diagnostic hardware support ©2017 Mellanox Technologies. All rights reserved. † For illustration only. Actual products may vary. Mellanox NP-4 Network Processor page 2 FEATURES SUMMARY Integrated Traffic Management Stateful Classifying & Processing • External statistics memory interface: – 180Mpps throughput – Access to all 7 layers for classify and modify • RLDRAM2-SIO – Dynamic hitless resource allocation – Maintains state of millions of sessions • 533 MHz DDR; 2x18 bit, 1 or 2 devices simultaneously – Dynamic hitless reconfiguration • ECC protected counters – LAG shaping – On-chip state updates and learning of millions of – External TCAM interface: – Work conserving and non-work conserving sessions per second • Especially useful for fast lookups through large schedulers Programming tables with wildcards, such as Access Control – Frame sizes from 1 byte to 11 KB – Large code space memory for multiple and Lists (ACL) – Total frame memory up to 4 Gbytes complex applications – Hitless code upgrades OAM Offload – Up to 8M frames – Single-image programming model with no – KeepAlive frame generation for precise and – Per Flow Queuing (PFQ) with 5-level hierarchical parallel programming or multi-threading scheduling: accurate session maintenance operations – Automatic ordering of frames • 32 interfaces – KeepAlive watchdog timers for fastest detection – Automatic allocation of frames to processing • 256 ports time engines (TOPs) • 4K subports – 802.1ag compliant message generation/ – Automatic passing of messages among TOPs • 32K classes/users termination offload – Microcode compatible with Mellanox’s NP-2, • 256K flows NP-3 and NPA network processors – Per OAM session state tracking and reporting – Policing: Per-flow metering, marking and policing – Flexible statistics and performance monitoring for millions of flows Interfaces – Serdes interfaces configurable to various network Statistics and Counters – Configurable WRED profiles interfaces – Per flow per color WRED statistics – Up to 16M 64-bit counters via external memory – 40 Gigabit Ethernet MAC compatible to 802.3ba – Shaping: Single and Dual leaky bucket on – Per-flow statistics for programmable events, standard over XLAUI Multi Lane Distribution over committed/peak rate/bursts (CIR, CBS, PIR, PBS), traffic metering, policing and shaping 8 physical lanes with IFG emulation for accurate rate control – Programmable threshold settings and threshold – Ten XAUI interfaces: – Scheduling: WFQ and priority scheduling at each exceeded notification • Ten on-chip 10G/20G MACs hierarchy level • 3.125Gbps; 6.25Gbps per lane – Dynamic allocation and auto association between – Per frame timestamp and timeout drop • Channelized operation with up to 256 transmit counters and flows. Counters are automatically – Hardware flow control per port and TM Interface/ channels recycled when a flow is deleted or aged. Port/Subport and Class • In band and out of band flow control – Auto implementation of token bucket per flow – Link-level flow control generation management • Connection to Ethernet and TDM framers scheme based on flexible traffic aggregation per (srTCM, trTCM or MEF5): • Support for SPAUI packet mode source/destination TM congestion • Hardware implementation of token bucket • Support for RXAUI protocol – Class-based flow control calculations and coloring (green, yellow, red) – 24 quad-speed SGMII/1000Base-X Ethernet Packet Manipulation & Reassembly interfaces or 48 tri-speed QSGMII Ethernet Power Management – TOPs control of TM buffered data interfaces – Per interface power-up/power-down – Data reordering – Three Interlaken MACs – Configurable number of active TOP engines at – Data reassembly (e.g. IP reassembly) – External Host interface: each stage, for best power optimization per Enhanced Video Transmission • 1-lane PCI-Express 2.5Gbps for control CPU application – Caching video streams for retransmission interface Physical Specifications – Video data awareness, IPTV fast channel zapping • Additional 2xSGMII GE ports – Package: HFCBGA, 1895 pins, 45x45 mm – Video de-multiplexing • MDC/MDIO master interface for external PHY – Process: 55nm – Video streams path redundancy control; continuous polling mode by HW Integrated Search Engines – LED interface for port status exporting – Power supply: 1.0V core voltage – Flexibly defined switching, routing, classification – External memory interfaces: – Power dissipation typical: NP-4: 35W, and policy lookup tables with millions of entries • External TM memory interface (optional): NP-4L: 25W per table • DDR3 SDRAM Models • 666 MHz DDR; 8x16 bit – Programmable keys and results (associated – NP-4 with 100-Gigabit throughput (50G full information) per table • ECC protected data duplex) – Support for long keys and long results per table • External lookup table memory interface: – NP-4L with 50-Gigabit throughput (25G full entry • DDR3 SDRAM duplex) – Table entries stored in DRAM to reduce power • 666 MHz DDR; 8x16 bit or 16x8 bit dissipation and cost and provide large lookup • ECC protected structures – Both devices have same package, pin out, tables headroom interfaces and are software compatible ©2017 Mellanox Technologies. All rights reserved. Mellanox NP-4 Network Processor page 3 SAMPLE APPLICATIONS NP-4’s flexibility and integration allows system vendors to deliver cost effective solutions that can easily adapt to changing market requirements. Figure 1. Interfaces Diagram Typical applications include: CPU or Host Network Ports CPU – Line cards in modular chassis: 2xSGMII PCI Express • Metro Switches 2x1GE MACs Host • 4x32bit Edge and Core Routers 48xG1E 666MHz 2xSGMII MACs • Wireless Backhaul Aggregation Switch/Routers or DDR3 Lookup 48xQSGMII Tables or Packet • Enterprise Backbone Switches 10x10GE Lookup Interfaces 10xXAUI/SPAUI MACs Tables or – Stand-alone box solutions: 3xIntertaken NP-4 TCAM Optional 3xInterlaken or MACs ACLs • Ethernet Aggregation Nodes 40GE 40GE MAC TM Memory Statistics • EPON/GPON OLTs and cable CMTS 4x32bit 2x18bit 666MHz 533MHz • Firewalls,
Load more

Recommended publications
  • C5ENPA1-DS, C-5E NETWORK PROCESSOR SILICON REVISION A1
    Freescale Semiconductor, Inc... SILICON REVISION A1 REVISION SILICON C-5e NETWORK PROCESSOR Sheet Data Rev 03 PRELIMINARY C5ENPA1-DS/D Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. Silicon RevisionA1 C-5e NetworkProcessor Data Sheet Rev 03 C5ENPA1-DS/D F o r M o r Preli G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m m d u c t , inary Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. C5ENPA1-DS/D Rev 03 CONTENTS .
    [Show full text]
  • Design and Implementation of a Stateful Network Packet Processing
    610 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 25, NO. 1, FEBRUARY 2017 Design and Implementation of a Stateful Network Packet Processing Framework for GPUs Giorgos Vasiliadis, Lazaros Koromilas, Michalis Polychronakis, and Sotiris Ioannidis Abstract— Graphics processing units (GPUs) are a powerful and TCAMs, have greatly reduced both the cost and time platform for building the high-speed network traffic process- to develop network traffic processing systems, and have ing applications using low-cost hardware. The existing systems been successfully used in routers [4], [7] and network tap the massively parallel architecture of GPUs to speed up certain computationally intensive tasks, such as cryptographic intrusion detection systems [27], [34]. These systems offer a operations and pattern matching. However, they still suffer from scalable method of processing network packets in high-speed significant overheads due to critical-path operations that are still environments. However, implementations based on special- being carried out on the CPU, and redundant inter-device data purpose hardware are very difficult to extend and program, transfers. In this paper, we present GASPP, a programmable net- and prohibit them from being widely adopted by the industry. work traffic processing framework tailored to modern graphics processors. GASPP integrates optimized GPU-based implemen- In contrast, the emergence of commodity many-core tations of a broad range of operations commonly used in the architectures, such as multicore CPUs and modern graph- network traffic processing applications, including the first purely ics processors (GPUs) has proven to be a good solution GPU-based implementation of network flow tracking and TCP for accelerating many network applications, and has led stream reassembly.
    [Show full text]
  • Embedded Multi-Core Processing for Networking
    12 Embedded Multi-Core Processing for Networking Theofanis Orphanoudakis University of Peloponnese Tripoli, Greece [email protected] Stylianos Perissakis Intracom Telecom Athens, Greece [email protected] CONTENTS 12.1 Introduction ............................ 400 12.2 Overview of Proposed NPU Architectures ............ 403 12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks . 403 12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs .............. 405 12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching ......... 407 12.3 Programmable Packet Processing Engines ............ 412 12.3.1 Parallelism ........................ 413 12.3.2 Multi-Threading Support ................ 418 12.3.3 Specialized Instruction Set Architectures ....... 421 12.4 Address Lookup and Packet Classification Engines ....... 422 12.4.1 Classification Techniques ................ 424 12.4.1.1 Trie-based Algorithms ............ 425 12.4.1.2 Hierarchical Intelligent Cuttings (HiCuts) . 425 12.4.2 Case Studies ....................... 426 12.5 Packet Buffering and Queue Management Engines ....... 431 399 400 Multi-Core Embedded Systems 12.5.1 Performance Issues ................... 433 12.5.1.1 External DRAMMemory Bottlenecks ... 433 12.5.1.2 Evaluation of Queue Management Functions: INTEL IXP1200 Case ................. 434 12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware ................ 435 12.5.2.1 Optimization Techniques .......... 439 12.5.2.2 Performance Evaluation of Hardware Queue Management Engine ............. 440 12.6 Scheduling Engines ......................... 442 12.6.1 Data Structures in Scheduling Architectures ..... 443 12.6.2 Task Scheduling ..................... 444 12.6.2.1 Load Balancing ................ 445 12.6.3 Traffic Scheduling ...................
    [Show full text]
  • Network Processors: Building Block for Programmable Networks
    NetworkNetwork Processors:Processors: BuildingBuilding BlockBlock forfor programmableprogrammable networksnetworks Raj Yavatkar Chief Software Architect Intel® Internet Exchange Architecture [email protected] 1 Page 1 Raj Yavatkar OutlineOutline y IXP 2xxx hardware architecture y IXA software architecture y Usage questions y Research questions Page 2 Raj Yavatkar IXPIXP NetworkNetwork ProcessorsProcessors Control Processor y Microengines – RISC processors optimized for packet processing Media/Fabric StrongARM – Hardware support for Interface – Hardware support for multi-threading y Embedded ME 1 ME 2 ME n StrongARM/Xscale – Runs embedded OS and handles exception tasks SRAM DRAM Page 3 Raj Yavatkar IXP:IXP: AA BuildingBuilding BlockBlock forfor NetworkNetwork SystemsSystems y Example: IXP2800 – 16 micro-engines + XScale core Multi-threaded (x8) – Up to 1.4 Ghz ME speed RDRAM Microengine Array Media – 8 HW threads/ME Controller – 4K control store per ME Switch MEv2 MEv2 MEv2 MEv2 Fabric – Multi-level memory hierarchy 1 2 3 4 I/F – Multiple inter-processor communication channels MEv2 MEv2 MEv2 MEv2 Intel® 8 7 6 5 y NPU vs. GPU tradeoffs PCI XScale™ Core MEv2 MEv2 MEv2 MEv2 – Reduce core complexity 9 10 11 12 – No hardware caching – Simpler instructions Î shallow MEv2 MEv2 MEv2 MEv2 Scratch pipelines QDR SRAM 16 15 14 13 Memory – Multiple cores with HW multi- Controller Hash Per-Engine threading per chip Unit Memory, CAM, Signals Interconnect Page 4 Raj Yavatkar IXPIXP 24002400 BlockBlock DiagramDiagram Page 5 Raj Yavatkar XScaleXScale
    [Show full text]
  • Intel® IXP42X Product Line of Network Processors with ETHERNET Powerlink Controlled Node
    Application Brief Intel® IXP42X Product Line of Network Processors With ETHERNET Powerlink Controlled Node The networked factory floor enables the While different real-time Ethernet solutions adoption of systems for remote monitoring, are available or under development, EPL, long-distance support, diagnostic services the real-time protocol solution managed and the integration of in-plant systems by the open vendor and user group EPSG with the enterprise. The need for flexible (ETHERNET Powerlink Standardization Group), connectivity solutions and high network is the only deterministic data communication bandwidth is driving a fundamental shift away protocol that is fully conformant with Ethernet from legacy industrial bus architectures and networking standards. communications protocols to industry EPL takes the standard approach of IEEE standards and commercial off-the shelf (COTS) 802.3 Ethernet with a mixed polling and time- solutions. Standards-based interconnect slicing mechanism to transfer time-critical data technologies and communications protocols, within extremely short and precise isochronous especially Ethernet, enable simpler and more cycles. In addition, EPL provides configurable cost-effective integration of network elements timing to synchronize networked nodes with and applications, from the enterprise to the www.intel.com/go/embedded high precision while asynchronously transmitting factory floor. data that is less time-critical. EPL is the ideal The Intel® IXP42X product line of network solution for meeting the timing demands of processors with ETHERNET Powerlink (EPL) typical high performance industrial applications, software helps manufacturers of industrial such as automation and motion control. control and automation devices bridge Current implementations have reached 200 µs between real-time Ethernet on the factory cycle-time with a timing deviation (jitter) less floor and standard Ethernet IT networks in than 1 µs.
    [Show full text]
  • And GPU-Based DNN Training on Modern Architectures
    An In-depth Performance Characterization of CPU- and GPU-based DNN Training on Modern Architectures Presentation at MLHPC ‘17 Ammar Ahmad Awan, Hari Subramoni, and Dhabaleswar K. Panda Network Based Computing Laboratory Dept. of Computer Science and Engineering The Ohio State University [email protected], {subramon,panda}@cse.ohio-state.edu CPU based Deep Learning is not as bad as you think! • Introduction – CPU-based Deep Learning – Deep Learning Frameworks • Research Challenges • Design Discussion • Performance Characterization • Conclusion Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 2 GPUs are great for Deep Learning • NVIDIA GPUs have been the main driving force for faster training of Deep Neural Networks (DNNs) • The ImageNet Challenge - (ILSVRC) – 90% of the ImageNet teams used GPUs in 2014* https://www.top500.org/ – DL models like AlexNet, GoogLeNet, and VGG – GPUs: A natural fit for DL due to the throughput-oriented nature – GPUs are also growing in the HPC arena! *https://blogs.nvidia.com/blog/2014/09/07/imagenet/ Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 3 https://www.top500.org/statistics/list/ But what about CPUs? • Intel CPUs are everywhere and many-core CPUs are emerging according to Top500.org • Host CPUs exist even on the GPU nodes – Many-core Xeon Phis are increasing • Xeon Phi 1st generation: a many-core co-processor • Xeon Phi 2nd generation (KNL): a self-hosted many- core processor! • Usually, we hear CPUs are 10x – 100x slower than GPUs? [1-3] – But can we do better? 1- https://dl.acm.org/citation.cfm?id=1993516 System Count for Xeon Phi 2- http://ieeexplore.ieee.org/abstract/document/5762730/ 3- https://dspace.mit.edu/bitstream/handle/1721.1/51839/MIT-CSAIL-TR-2010-013.pdf?sequence=1 Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 4 Deep Learning Frameworks – CPUs or GPUs? • There are several Deep Learning (DL) or DNN Training frameworks – Caffe, Cognitive Toolkit, TensorFlow, MXNet, and counting...
    [Show full text]
  • Effective Compilation Support for Variable Instruction Set Architecture
    Effective Compilation Support for Variable Instruction Set Architecture Jack Liu, Timothy Kong, Fred Chow Cognigine Corporation 6120 Stevenson Blvd. Fremont, CA 94538, USA g fjackl,timk,fredc @cognigine.com Abstract running embedded applications. these application specific instruction set processors (ASIPs) [1, 2] use instruction sets customized towards a specific type of application so they Traditional compilers perform their code generation can deliver efficient run-time performance for typical pro- tasks based on a fixed, pre-determined instruction set. This grams written for that application area. Because the instruc- paper describes the implementation of a compiler that de- tion set is pre-determined, the compiler is built and config- termines the best instruction set to use for a given pro- ured to generate code based on a custom, fixed instruction gram and generates efficient code sequence based on it. We set [16]. first give an overview of the VISC Architecture pioneered at Cognigine that exemplifies a Variable Instruction Set Ar- The Variable Instruction Set Communications Architec- chitecture. We then present three compilation techniques ture (VISC Architecture ÌÅ ) from Cognigine represents a that, when combined, enable us to provide effective com- very different approach in the attempt to provide greater pilation and optimization support for such an architecture. configurability in compiling embedded software. The VISC The first technique involves the use of an abstract opera- Architecture can perform a complex set of instructions con- tion representation that enables the code generator to op- sisting of multiple, fine and coarse grain operations that op- timize towards the core architecture of the processor with- erate on multiple operands at the same time in one fixed out committing to any specific instruction format.
    [Show full text]
  • NP-5™ Network Processor
    NETWORK PROCESSOR PRODUCT BRIEF † NP-5™ Network Processor 240Gbps NPU for Carrier Ethernet Applications HIGHLIGHTS Mellanox’s NP-5 is a highly-flexible network processor with integrated traffic management, targeting Carrier Ethernet Switches and Routers (CESR) and other Carrier Ethernet platforms – 240Gbps wire-speed network processor aimed that require high performance, flexible packet processing and fine-grained traffic management. at Carrier Ethernet applications TARGET APPLICATIONS – Integrated 240Gbps traffic management NP-5’s flexibility and integration allows system vendors to deliver cost effective solutions that providing granular bandwidth control can easily adapt to changing market requirements. – Up to 480Gbps peak processing data path and Typical applications include: Stand-alone pizza box solutions: CoS classification • Line cards in modular chassis: • Ethernet Aggregation Nodes – Suited for line card, services card and pizza box • Edge and Core Routers • Server Load Balancing Switches applications • Transport Switches • Multi-10Gbps Firewalls & VPN – On-chip control CPU for host CPU offload • Data Center Switches • Intrusion Detection Appliances • 3G/4G Wireless Infrastructure Equipment • Network Monitoring and Analysis Services – Power management for minimizing line card and system power dissipation SOFTWARE TOOLS – Operations, Administration and Management Mellanox supplies a comprehensive set of software tools to facilitate system design for NP-5 (OAM) processing offload based products. The toolset manages the data plane and allows designers to edit, build and – Synchronous Ethernet and IEEE1588v2 offload debug microcode applications for the Mellanox’s network processors with a unified GUI. for Circuit Emulation Services Designers can quickly develop and test the microcode using cycle-accurate simulation and debugging tools including breakpoints, single-step program execution and access to internal – IP reassembly for advanced packet processing resources.
    [Show full text]
  • Network Processors the Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology
    Network Processors The Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology The Designer’s Guide to VHDL, Second Edition Peter J. Ashenden The System Designer’s Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs Axel Jantsch ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification Bruce Wile, John Goss, and Wolfgang Roesner Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Configured Processors Steve Leibson ESL Design and Verification Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon System-on-Chip Test Architectures Edited by Laung-Terng Wang, Charles Stroud, and Nur Touba Verification Techniques for System-Level Design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad VHDL-2008: Just the New Stuff Peter J. Ashenden and Jim Lewis On-Chip Communication Architectures: System on Chip Interconnect Sudeep Pasricha and Nikil Dutt Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu Processor Description Languages: Applications and Methodologies Edited by Prabhat Mishra and Nikil Dutt Network Processors Architecture, Programming, and Implementation Ran Giladi Ben-Gurion University of the Negev and EZchip Technologies Ltd.
    [Show full text]
  • Synchronized MIMD Computing Bradley C. Kuszmaul
    Synchronized MIMD Computing by Bradley C. Kuszmaul SB mathematics Massachusetts Institute of Technology SB computer science and engineering Massachusetts Institute of Technology SM electrical engineering and computer science Massachusetts Institute of Technology Submitted to the Department of Electrical Engineering and Computer Science in partial ful®llment of the requirements for the degree of Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY May 1994 c Massachusetts Institute of Technology 1994. All rights reserved. : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : : :: : :: : :: : : :: Author : Department of Electrical Engineering and Computer Science May 22, 1994 :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : : :: : :: Certi®ed by :: Charles E. Leiserson Professor of Computer Science and Engineering Thesis Supervisor :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : :: : : :: : :: : : :: Accepted by : F. R. Morgenthaler Chair, Department Committee on Graduate Students 1 2 Synchronized MIMD Computing by Bradley C. Kuszmaul Submitted to the Department of Electrical Engineering and Computer Science on May 22, 1994, in partial ful®llment of the requirements for the degree of Doctor of Philosophy Abstract Fast global synchronization provides simple, ef®cient solutions to many of the system problems of parallel computing. It achieves this by providing composition
    [Show full text]
  • A Network Processor Architecture for High Speed Carrier Grade Ethernet Networks
    TECHNISCHE UNIVERSITAT¨ MUNCHEN¨ Lehrstuhl f¨urIntegrierte Systeme A Network Processor Architecture for High Speed Carrier Grade Ethernet Networks Kimon Karras Vollst¨andigerAbdruck der von der Fakult¨atf¨urElektrotechnik und Informationstechnik der Technischen Universit¨atM¨unchen zur Erlangung des akademischen Grades eines Doktor-Ingenieurs (Dr.-Ing.) genehmigten Dissertation. Vorsitzender: Univ.-Prof. Dr.-Ing. Wolfgang Kellerer Pr¨uferder Dissertation: 1. Univ.-Prof. Dr. sc.techn. Andreas Herkersdorf 2. Univ.-Prof. Dr.-Ing. Andreas Kirst¨adter,Universit¨atStuttgart Die Dissertation wurde am 13.05.2013 bei der Technischen Universit¨atM¨unchen einge- reicht und durch die Fakult¨atf¨urElektrotechnik und Informationstechnik am 24.03.2014 angenommen. Preface This work was performed at the Institute for Integrated Systems of the Technical University of Munich under the auspices of Prof. Dr. sc.techn. Andreas Herkersdorf and Dr.-Ing. Thomas Wild, both of whom I have to whole-heartedly thank for giving me the opportunity of working with them and for their invaluable help and guidance throughout the five years of my stay at the institute. A further thanks goes to all the people at the institute with whom I've cooperated over the years and who have made life enjoyable both on a professional and on a personal level. A very great thanks is due to Daniel Llorente for keeping me company and bearing with me during most of this time. His contribution to this thesis is immense and without him it wouldn't have been possible. Muchas gracias, companero~ ! Furthermore I would like to thank all the partner companies and participants of the 100GET project, which formed the basis for this disseration.
    [Show full text]
  • Object-Oriented Reconfigurable Processing for Wireless Networks Andrew A
    Object-Oriented Reconfigurable Processing for Wireless Networks Andrew A. Gray, Clement Lee, Payman Arabshahi, Jeffrey Srinivasan Jet Propulsion Laboratory, California Institute of Technology 4800 Oak Grove Drive, MS 238-343, Pasadena, CA 91101 USA Abstract – We present an outline of reconfigurable processor while at the same time being sensitive and potentially error technologies and design methods with emphasis on an object- prone and costly. oriented approach, and both full and partial dynamic To address these issues, we present design methods reconfiguration. A specific broadly applicable architecture for that facilitate flexibility (leading to prolonged processor implementing a software reconfigurable network processor for lives), and dynamic reconfigurability, along with a generic wireless communication applications is presented; a prototype of which is currently operating in the laboratory. This reconfigurable processor architecture. Dynamic partial architecture, its associated object oriented design methods, and reconfiguration of the network processor will greatly partial reconfiguration techniques enable rapid-prototyping increase the value of the processor within the network. For and rapid implementations of communications and navigation instance the processor’s ability to perform a very large signal processing functions; provide long-life communications number of temporally separated (time-multiplexed) infrastructure; and result in dynamic operation within functions will dramatically increase network elasticity and networks with heterogeneous nodes, as well as compatibility compatibility (see Fig. 1). with other networks. This work builds upon numerous The paradigms will also empower the design engineer advances in commercial industry as well as military software with tools required for rapid prototyping and radio developments to space-based radios and network processing. The development of such radios and the network implementation of a wide variety of signal processing processor presented here require defining the correct functions.
    [Show full text]