Residue Arithmetic in Digital Computers

r* 6 l't ¡r

"RESIDUT ARITHMETIC IN

DIGITAL COIIPUTERS"

RAMESH CHANDRA DEBNATH/ M.SC.

BEING A THESIS SUBMITTED

FOR THE

DEGREE OF DOCTOR OF PHILOSOPHY

IN THE

DEPARTMENT OF ELECTRICAL ENGINEERING

THE UNIVERSITY OF ADELAIDE

IVIARCl-i I979

SUIq¡4ARY

The number systems used have great impact on the speed of a computer, At present at least 4 number systems (binary, negabinary, ternary and residue) are in use either for general purposes or for special purposes. The calîry plîopagation delay which j-s inherent to all weighted systems (binary, negabi-nary and ternary) is a limiting factor on the speed of computations. tlnlike the weighted system, the residue system is carry free which is the m¿rln attractj-ve feature of this system and therefore its potentiality in a general purpose computer, in the light of present day technology, has been investigated.

As the background of the investigation the binary and negabinary arithmetic have been thoroughly studied. A ne',r method for fractional negabinary division, and a correction on negabinary multiplì-cation have been proposed. It has been observed that the binary arithmetic operations are faster thair thcse ir. negabinary syslem.

The residue system has got. problems too. The sign detectj-on, operations j-nvolving sign detection (comparison, overflow detection, division) and the resj-due-to--decimal- con- version are difficult. Moreover, the residue systemT being an i.nteger: systetn, makes floati-ng poinc arithmetic operatlcns very difficult. The def:ails of the existing algorithms,/ methods to solve those problems have been thoroughly investigated and drawbacks of those algoritlrms/methods have been di scussed.

. This thesis proposes a new method on multiplj-cative overflow detect-ion in the residue system, a technique for the determination of the first approximation for residue integer division, algorithms for floating point arithmetic operations in the residue system and a method for the residue--to-decimal conv.rsion.

In order to verify those proposed methods and algorithms a 16-15 moduli- residue arithmetic unit has been designed using LS1 components. The unit together with (in this case) an SDK-80 microcomputer can perform all the integer and floating poi-nt arithmetic operations.

It has been obse::ved that t'he binary system still- main- tains its predominance over the residue system in general purpose digital computers. However, the residue system is faster where there is no operation involvi-ng sign detection, and also the carry free property, in very large systems, is of great i-mportance j-n minimj-sing the chip connectíons and inter chip delays. In future, investigation should be carried out on the possibility of using VLS1 components which may up- set the present conclusions which are generally in favour of the binary system.

ACKNOWI,EDGEMENT

The autholî likes t'o acknowledge the contributions of those who have, directly or indlrectly, assisted in this research and preparat-i-on of this t.hesis. The author is pleased to thank Dr D.A. Pucknell, the project supervisor, for his invaluabÌe grlid"rr." and encouragement.

The author likes to thank the Radio Research Board of Australia and the Col-ombo Plan Authority for their financial assistance for this project.

The author would like to thank t.he technical staff of the Department of Electrical Engineering, University of Adelaide and specially Mr R.C. Nash for his helping hand in the computer laboratory.

The author is pleased to thank Mr D.C. Pawsey, senior lecturer and Mr C.K. Linke, laboratory manager, of the Department of Electrj-cal Engineerirg, universj-ty of Adelaide, for their positive help in making a pleasant stay in Ausf:ra1ia.

The author likes to thank Mrs Mercaa Fuss for her excellent typing.

Fina1ly, the author wislies to thank his wife, Mrs Asha Rani Debnath, for her encouragement 'Ehroughout the research. PAPER WRITTEN BY THE AUTHOR with D.A. Pucknell, "Orr multiplicatlve overflow detection in residue number system". Electronics Letters, Vol.L4,

No.5, March 1.978, Þp. L29-130.

ERRATA: "On multiplicative overflor^¡ detection i-n residue number system", Electronj-cs Letters, Vol.14, No.l-2, June L978, p. 385. NOTATIONS

[x] The highest integer value of X, but less than X. (X may be an arithmetic expressi-on also. ) Fr (ArB) Floating point au].dition/ subtraction with operands A and B. rr (a. e) Floating point multiplicat1on with operands A and B. Fr (AlB) Floating point division with operands À and B. r (n) Shift T to n positions left. (_ Pol (r (n) ) Pol-arÍse r (n) . X+V Replace the value of X with V. (/ may be an arithmetic or a logical expression. ) rn( x, v,....) fnputs X, Y ,

SX or S (X) Sign of X. x V Swap the values of X and Y. - (X) E F"n, ,t,]

E(X ) G (X) 2

lx l* or [x ]* Residue of X with respect to module m. lxl Absotute value of X. Gate (qb,c,...Þ,L) Gate with inputs b, c, . . .lz ano output ,L at the location 4. on the residue arithmetic unit (net-t) board.

Coef f (a) :> d2 t a-7 0,2 and G.7 are the co-efficients of A. Exp (X) Exponent of X.

Mnr (x) MantÍssa of X. :l Contains. CONTBNTS

Page

L/ INTRODUCTION 1

1.1 Introductory Note 1

1.2 Number Systems an overview 2

2/ ÏNTRODUCTÏON TO BINARY AND NEGABINARY NUMBER SYSTEMS, B

2.L Binary Arithmetic B

2.I.1 Binary Addition and Subtraction 9 2.I.2 Binary Multiplication l_1 2.t.3 Binary Division t4

2.2 The Negabinary Number System 15 2.2.1 Negabinary Number Representation 15 ( lnreger) 2.2.2 Negabinary Number Representation (fraction) 15 2.2.3 Polarisation of Negabinary Number 16 2.2.4 Negabinary Addition/Subrraction l_6 2.2.5 Negabinary Multiplication 20 2.2.6 Negabinary Divislon 20 2.2.7 A Correction Proposed on Varrable Shift Ncgabinary Multiplication 22 2.2.8 Method Proposed on Negabinary Fracti-onal Divisicn 23

2.3 Concl-usion 27

3/ RESIDUE ARITHMETTC LITERATURE REVTEW 2B

3.1 Introduction 2B

3.2 Integer Residue ArithmetÍc an outl j-ne 29 3.2.1 Addition, Subl-raction and Multipl j-cation 29 3.2.2 Division 2c) 3.3 Overflow 33 3.3.1 Overflow due to Addition/ Sul:traction 34 3.3.2 Mul-tiplicative Overf low 34

3.4 Floating Poj.nt Arithmetic in a Residue Number System 35 3.4 1 The Representation of Floating Point Numbers 36 3.4.2 Floating Point Arithmetic 36

3 5 Transl-ation of Residue Numbers to Decimal Numbers 40

3.6 Conclusion 40

4/ RESIDUE ARTTHMETTC ALGORITHMS AND 43 TECHNIQUE PROPOSED

4.L Tntroducti-on 43 4.2 Multiplicative Overf l-ow Theoretical- Aspects 43

4 .2.L Logarithmj-c Distribution of Residue Numbers 44 4.2.2 Design Ideas for Overflow Detection 50 4.2.3 Desi-gn Example on Overflow Detection 52

4 3 General- Division 59

4.3.1 A Division Process 59 4.3.2 How to find the first approximation and successive approxJ-m- 61 ations

4.4 Floating Point Ari--hmetic 65

4.4.L Theoretical Concept 65 4.4.2 Floating Point Representation of a Number 66 4.4.3 Floatiug Point Arithmetic with Zero Exponent 66 ¿.Á.a Float-ing Point Ar:j thmetic with Non-zero Exponent 71, 4.4.5 How to find the co-eff-tcient of a mantissa 73 4.4.6 Error in the Proposed Floating Point Arithmetic Operations 73

4.5 Output Translation 74

4.5. 1 Theoretical- Aspects 74 4.5.2 Conversion Prrccedure 75

4.6 Conclusion 77

5/ DESIGN OF A REÀL TIME RESTDUE ARITHMETIC COIVIPUTER 79

5 1 Introduction 79

5 2 Addition, Subtraction and Multiplicat.ion 90 ( rnteger )

5 3 Comparison 9B

5 4 Overflow Detection 108

5.5 Integer Division 118 5.6 Floating Point Arithmetic r26

5.7 Output Circuit of the RAU t44

5 I Conversion of Residue Numbers to Deci-mal Numbers L47

9 How the Residue Arithmetic Computer Works L49

5. 10 FIow to Operate the RAC 151

5.11 Conclusion 153

6/ CONCLUSTON 155

BIBLIOGRÀPHY L70

Appendix- 1 Some fmportant Proofs A1 .T Appendix-2 Floating Point Val-ue otB A7 Appendl x-3 Table of mantlssa and A9 exponent 1 "f B Appen

Appendix-5 Mixed Radix Conversion A24

Appendix-6 Program Listings A26 À

1 INTRODUCTION

1.1 Introductory Note

The number system has a great impact on the speed of computer arithmetic which, together wÍth other factors access ti-¡ne of memories, memory hierarchy and computer architecture, inflüence the speed of a computer as a whole. scientific probrems such as the solution of rarge sets of linear equations, problems embracing the field of structural design, traffic f-icw, signal processing etc. are associated- with a great deal of computation. A number system with its associated arithmetic algori-thms can greatly effect the speed of computat j-on.

The choice of a number system depends on the availab- ility of efficient arithmetic algorithms. Technology also influences the choice a great deal. For example, a decimar system would be preferable to a binary system if technology could provide low cost reliable ten valued logic circuits. one nuirrber system can offer advantages on a particular cperation, but may be unsuitable from the consideration of overall s;peed of computatl-on. For example, in a resi_due system, mu]-tiplication is faster, however, other operations such as si-gn detection, comparison and overflow detection are slow processes" rt is, therefore, worthwhile to investigate which of the existing number systems can offer the greatest overall

1 2 speed advantage in computer arithmetic for general purpose computers. The rest of this chapter is an overvj-ew of the existing number systems and their advantages and disad.van- tages. Chapter 2 ð,iscusses the arithmetic operations in binary and negabinary systems. The existing arithmetic algorithms in the resldue system have been discussed in Chapter 3. A few improved techr:iques and algorithms for residue arithmetic have been proposed in Chapter 4 and the design of a residue arithmetic computer, on the basis of the proposed techniques and algorithms, has been shown in Chapter 5. Chapter 6 glves conclusions on the comparative studj.es of binary and residue systems.

1-.2 Number Systems - an overview

To represent all numbers, a number system must have unique sets of representation. A number system may be a weighted system or a nonweighted system. Some examples of the weighted systems are the binary system, negabinary system, and ternary system,' whereas the residue system is a nonweighted svstem.

A nurnber in a weighted system can be expressed as

N x = t aiwi i=o

where a.í are the sets of integers and øi are the sets of weights. Tf T,IJí ATC the successive power of radix r,rJ, the number system is ca1led a fixed radix system; otherwise it is a mixed radix system. The binary sys t.em (w= 2) , negablnary 3 system (w= - 2 ) and ternary system (r,0= 3 ) are in the family of fixed radix systems. Examples of a mixed radix system have been given in Appendix 5.

Number systems which have found use in digital computers are the binary system, negabinary system I f], lZl, ternary system [ 3] and the residue system. Tn subsequent sections brief discussions now follow on these number systems.

L .2 .1 e*ilery. NumÞ_er S stem

The binary number system is a tr¡/o digit (0,1) number system having a radix *2. The decimal value of a binary number depends on the posj-tion of 1. Thus for example (11011) 2 = L -24+I -23+0.22+!.2r+L.20 = (27) to

Due to easy converslon from binary number to octal number (ø=8) and vice versa, some digital computers such as the TBM-7099, Data General Nova-l, Nova-2 and many others, use the octal system for easy input-output operation. The conversion of binary number to octal number is done by for- mlng groups of three consecutive bits and expressing each group as an octal digit (O thrcugh 7). Thus above binary number can be expressed in octal form as (01-1, 011)2 = (::¡r = 3.BI+3.80 = (27]lto

The octal number is converted to binary number by simply expressing the octal digits in binary forln. Thus (75)a = (111,101)2. 4

Presently some computers fBM-360, IBM-370 and many mi-croprocessors make use of hexadecimal numbers (w=t6). The sixteen digits of hexadecimal numbers are 0,L,2,3,4,5,6,7,8, 9,A,B,C,D,E,F. A binary number is converted to hexadecimal form by taking groups of four consecutive bits and representing each group by a hexadecimal digit. Thus (1101, 1111)z = (DF)ro = 13.16t+15.160 = (ZZZ¡ro l{hen hexadecimar digits are represented in binary form, it gives equivalent binary number. For example (94)rs = (1001, 101-0)2.

Another code which is often used is the blnary coded decimal number (eCO). This number is really a decimal number, the digits of which are expressed in binary form. Thus (789) (0111, r o = 1000, 1001) uro B.inary states (0,1) are easily realisaÌ:le in a physical system and is one of the main advantages of binary systems and this is the reason why almost all present day computers use binary number systems. The obvious disadvantage which is inherent in a1-1 weighted systems is the carry propagation delay which limits the speed of computation for examÞle, in addition and especially in multiplication which is a process of additj-ons a¡rd shifts. Another disadvantage is the sign correction required in complement (1's or 2's) multipli-cation. These are the reasons why the potentiality of other number systems should be investigated. The speed of arithmetic i,s particrrlarly important in the growing field of real tj.me processing in which a v¡jde range of digital computers/micro- processors are being applied. 5

I .2. Z _NeggÞl-ns.ry Numþe! Svst_em

A negabinary system, like a binary system, is a two digit system. But unlike the binary system the radix j_s -2 For example

(a) (1101I) -z 1. (-2)a+I. (-2) t+0. (-Z)2+L. (-Z) t+1. (-2) 0 16-B+0-2+1 = (7)ro

(b) (0100r) _z 0. (-z) u+1 . (-2) 3+O . (-z) 2+t. (-2) 0 o-8+o+o+1 = (-7)ro

The advantage of this system is that no sign correctiorr is needed for multiplicatj-on. The disadvantages are: (i) duri-ng add.ition dcuble carries are generated (to be dj-scussed in Chapter 2) and therefore it is difficult to mainr.ain speedy propagation of carries, (ii) from examples (a) and (b), it is seen that when the most signifi-cant l is in an odd posi.tion, the number is negative and if it is in an even position, the number is positj-ve. Thj-s means that the sign is implicit. The detection of implJ-cit sign is not so easy as that of explicit sign as in the case of the binary system, and (ij-i) from the example (a) it is clear that to repr-esent (7) ro , this system needs 5 bits, whereas the binary system need.s only 4 bits (¡ bits for magnitude + 1 bit for sign). Furthermore, some of the arithmetic operations are not easy. Chapter 2 will dj-scuss its arithmetic operations.

L.2.3 Ternary Number Systems

A ternary lnteger number can be expressecl es

N v T ai3t r=o 6 where cLí (i=o, 1,, .....,N) are the coefficients and can have any value of the set (0,\,2) in an ordinary ternary system or any value of the set (-1,0,1) in a symmetric system. This number system, specially the symmetric one, offers poten- tial advantages fc¡r the following reasons (i) sign conversion is easy (simple inversion) (ii) roundíng is done by simpry t::uncating the number to the required numbe.r of

The Russian 'SETUN' is an example of a symmetri-c ternary computer. It used magnetic core s lzzl to realize three state logic.

A handful of papers j_s avaitabl_e on arithmetic algorithms lq), [s], [z] and rernary swirching functions IB ]- [12].

The ternary system sounds promising for the future and interest is rapidly growlng in the hardv¡are realization of three vatued logic, [o], Ir:] lz+1.

I.2.4 Res j-due Numbel Sy.stem

The residue number system is not a weighted system. Therefore its arithmetj-c operations are carry free which is the main attractive feature of the system. since carry does not propagate from one resio.ue to the next one, the speed of addition, subtraction and multiplicatj.on is faster than the eqnivalent binary system. Ì.{oreoveri in the case of multip- l-ication, the storing of the partial prorluct is not required. 7 However, sÍgn detection and operations involving sign detection (comparison, overflow detection and division) are not so easy as.in the binary system. Furthermore, sj-nce residue arithmetic is an integer arithmetic, floating point arithmetic is very dÍfficult. So far as j-t is known there is only one residue computer developed by RCA [Zg ]. Limited uses of residue numbers are found in error detection and correction algorithms lzs] lzll. The details of residue arithmetic operatj-pns will be discussed in Chapter 3. 2 INTRODUCTION TO BINARY AND NEGABINARY NUMBER SYSTEMS

As has been discussed earlier, the binary number system is a two val-ued (ù,1) number system with its radix (base) 2; whilst the negablnary system j-s a two valued system with radix -2. Since two state physical entities are readily avai-lable the binary system has an advantage over all other -systenìs. Holl'ever, carry propagation delay is the main dis- advant-age of the binary system," specially in multiplication, which involves a series of additions and speed is limited by the carry propagation

fn the negabinary system the si-gn is implicit therefore multiplication does not need correction for negative operands. However, this system has got a twin carry problem which is even worse than that of the binary system, and also due to the implicit nature of the sign, the sign detection is not so easy a.s .in the binary system.

Later sections give a review of arithmetic in binary and negabinary systems.

2.L Binary Arithmetic

Any of the standarct books l:0, 31^-'1 ) can give the background to b-inary arithmetic" Binary numbers are presented

B 9 either in signed 1's complement form, or signed magnitude form or 2's complement form, However, whatever be the form of representatiorr, the sign is always represented by the most significant bit (tuse¡ .

2.1,.1 Bina-sy Àddi-Eicn and Su.btr.asti-on

Tables 2.I, 2-2 and 2.3 show the algorithms of binary addition/subtraction of numbers in 1's complement form, signed magnitude form and 2's complement form respectively.

Table 2.I A1gor:ithms for binary addition/subtraction in l's complement form

Method Operation Remark

(i) Direct Addition 7=X+V Treat sign bit as a number as long as the register ( ii) Direct Subtraction 7=X-V capacity for the nunber is not exceeded. (ii i) Addition by Subtraction Z = X -V Add (or subtract) end round (iv) Subtraction by Addition 7=X+V carry (or borrow), whenever it occurs, to/fron least significant bit of surn (or difference) .

7 is l's complement of Y

Example: è^ddition of (+9) ro ano - (6) ,o in 1's complement.

0,1001 1, 1001 End Round Carry -->1 0 0010 I (sum) 0 0011 " 10

Table 2.2 AlEorithms for binary additionr/subtraction in signed magnÍtude form

Signs of X and }/ Operation Sign of Sum

Addition Same Z*=X*+V* s]-gn (z) = sign (x) Different z*+x*-V* sign (z) = sign (x), if it does not overflow s]-gn (z) = ;tgn (Ð , if it overflolvs * Subtraction Same z X* Y* sign (z) = sj gn (x), if it does not overflow sign (z) = sign (x), if it overflows Different 7* - Y* ¡ Yx sign (z) = sign (x)

In Table 2.2 negative number 7* (after operation) is in 2's complement form. To change negative 7* to the signed magnitude form the magnitude of Z*is 2's complemented.

Example: Addition of X +0101 (+5 ) and V -1001 (-e) .

0101 100 1 I 1100 overflow

Therefore, the sign of 7x is 1 [ = s j-gn ( x) l and the sum is 2's complement form of -4 . This must now be converted back to signeo magnitude form, i.e. to -0100. 1l_ Table 2.3 Algorithms for binary addition/subtraction in 2's complement form

Itfethod 0peration Sign bit

(i) Di.rect Addition 7=X+ v (ii) Direct Subtraction Treat sign bit as a number bit 7=X- v (ii i) Addition by subtraction as long as register capacity Z=X- v for nunber does not exceed. of 2t s complement (iv) Subtraction by Adclition 7=X+V

V is the 2's complement of V.

Exarnple: Additi-on : *(fO¡rand -(7)ro

(0,1010) z (t, t_oo1) z (0,00Lr) z 3

From the study of algorithms in Tabl-es 2.7, 2.2 and 2.3 it is obvj-ous that 2's complement addition/subtraction is easier than in any other form of representation. However, it is more difficult to form than 1's complement representation.

2.L.2 Binary Multipli cation Bi-nary multiplication is generally a repeated addition and shifting process. Multiplication can be performed hy using one of the following wide-.Iy used nethocls [¡O]. (i) Direct Multiplication Method (ii) Burks Goldstine Von Neumann Method (if f ) Robertson's !-irst Ivlethod (iv) Robertson's Second Method (v) Booth's Method (vi) A Short Cut Multi-plication Method. L2 Binary multiplicatj-on with signed magnitude form of number is much easier since it does not need sign correctj_on,. the sign of the resul't is the Exclusj-ve oR function of the signs of the operands. The magnitude of the result is simply the product of two magnitudes (operands). rn the case of signed complement numbers, the system needs correction if any onerlboth of the operands are negative. The Direct Multiplic- ation Method and short cut Multiplication luethod are most suitable for signeÈ magnitude multiplication. A1l the other methods are suitable for signed complement mul-tiplication and these algorithms have the property of needing correction for si-gned complement multiplj-cation.

A varj-ation of the above techniques is a multiple digits multiplication method [90]. In this merhod the two LSB of the multiplier are examined at a time and a decision of operation/no operation is taken accordÍng to the Table 2.4. This technique is sultable for signed magnitude multiplication.

Table 2.4 Table for decision modes in multiple digits multiplication

MultipJ.ier digits Operation Shift Riqht

00 No operation 2

01 Add multiple 2

10 Add 2 ' (multiplicand) 2

11 Add 3 (multiplicand) 2 13 In quatenary techniques [¡Z] three consecutive bits are examined and decision of operation/no operation j-s taken according to the Table 2.5. An extra one bit of storage is needed at the LSD position of multiplier which is shifted two bits rlght af'cer each examination; while the partial product j-s not shifted.

Table 2.5 Tabl-e for decision nLodes in quatenary multiplication

Multipl-ier bits Operation

000 No operation 001 Add 1 (muì.tipticand) 0 l_0 Add 2 ' (multiplicand) 100 Subtract 2 . (multiplicand) 101 Subtract 1 (multiplicand) 110 Subtract 1 ' (multiplicand) 111 No operation

Exanrple: Quatenary Mu1tiplj-cation with

Multiplicand X = 1100 : Multiplier Y 1111

Initial Partial Product: 00000000 Extra storage Multjplier Register: 1111 i 0 11110100 Subtract X 011,11 1 11110100 No operation I 00001 1 10110100 Addition of 16x Simultaneous multiplication [¡0 ] is a method of hardware multiplication in which the shifted multiplicand is simul-tan- eously added to the previous partial product. This technique

is f ast but expensive. Plenty of f -iterature ref erences [:A ] [52] are available on this technrque. L4 RoM mulriplicarion IS¡ ] , lS+] i= anothe:: approach to multiplication.

Integrated circuits for multiplicarion [SS I [SA ] are al-so avai-lable. These I. Cs can be cascaded to accommodate nrrmbers of large word length.

2.L.¡ sj¿ar.y Ð:feion Binary division is commonly performed using one of three methods [¡O ] Method (iii) Non-restoring Method. The ¡nost comrnonJ.y usecl method is the non-restoring method. The algorithm for the non-restoring method has been given in Table 2.6.

Tab1e 2-6 Algorithm for binary division by the non-restoring method

Remainder Rn = 2-rL rn Partial- remainder rn= 2rn-r+ Í-2q")V gn = 1 if rn-r and Y are of same sign Ç[n = o if rn-t and Y are of different sr-gn Quotient O-(-1+2-n) + î qi 2-( i-r ) I=I Correction Add (-1+z-o¡

Array divisions irnplementing non-restoring division method have been proposed in [Sg] [O¿ ]. An irrregrared circuit for binary division [ZZ ] is also available. 15 2.2

2.2.1 N .ine¡¡¿ Number resentation (fnteqers

General expression for a negative radix integer number i-s n s| 1 a(-ß) IJ 6"i ß (2. r) 1 = o

where 0 1 ai. ß-1

For negabinary the expression 2.I becomes n ø (-2) TJ a"í (-2)' i=o where0

The conve:-'slon of integer number of positive base to negative base and vice versa has been shov¡n in [00] - [0e].

2.2.2 lIçqeþf¡_rff lrlumJcer Repres_entation (ffactÍoq) No lj-teratu::e on the representati-on of fractional negabinary number is avai.lable, however, the general expression of fractj-onal number j-n neqabina-rir system is given by n -i+l a(-2) .L CL (-2) Q -2\ 1=O - i.{- r 16 where a"í f (0,1)

The representation of fractional negabinary number thus needs two extra bits before negabinary point. Thus

r+1-x o+Ox - - z (11.0111)-z Lx(-2) (-2) ( -2) t+tx (-Z¡ +l-x ( -2) 3+1x (-Z¡ - u f r rglaì - lroJ ,o .

2.2.3 Polarisation gE Ne$þin_AÐa Numbe.r Similar to, the 'complement'of Binary Numbers there exists a 'Polarisation' IZO] of Negabinary Numbcrs. The procedure to polarise a negabinary number can be stated as follows: Starting from the LSB complement immediate next bit following a '1' .

Example: (a) polarisation of (5) ro = (0101) -z is

(11!1) - z - (5) ro

(b) Polarisation of (-3) ro = (11-01) - 2 l_s

(0111) -z (3) ro

2.2.4 Neqabinary traction A truth table for negabinary additicn, ês presented in [OS], has been shown in Table 2.7. L7 Table 2.7 Logic table for negabinary addition

Number xy Sum, S Carry Cr Co

00 0 0 0

0 1 1 0 0

i 0 I 0 0

i i 0 I 1 Twin Carry

The twin carry gro\^¡s to unmanageable numbers as the addition moves towards the MSB position. However, carry-borrow techniques [Og ] ana llZl can minimize the twin carry accümulatj-on. The technique can be summarised as: A carry generated in any bit position is consldered to be a borrow to the next bit position¡ a borrow generated in any bit position is considered to carry to the next bit position. Example:

(5) ro 0 0 1 0 i

+ (3) ro 0 0 I I t

(8) ro L 1 0 0 0

Truth tables of addition and subtraction, according to carry-borrow technique, have been shown in Tables 2.8 and 2.9 respectively. L8 Table 2.8 Addition Truth - Table

Generated Carry Borrow Sun Generated Catry Borrow

XY Ci Bi S ci* r Bi*t

0 0 0 0 0 0 0

0 0 0 a I 1 0

0 0 x 0 I 0 0

0 1 0 0 1 0 0

0 1 0 1 0 0 0

0 I I 0 0 0 I

I 0 0 0 1 0 0

I 0 0 1 0 0 0

L 0 L 0 0 0 1

I I 0 0 0 0 I

1 1 0 L 1 0 0

I L I 0 7 0 I 19 Tab1e 2.9 Subtraction Truth Table

Generated Generatecl Numbers Carry Borrow Sun Carry Borror'¡

xy Ci Bi S Ci+ r Bi+l

0 0 0 0 0 0 0

0 0 0 I 1 1 0

0 0 1 0 l- 0 0

0 1 0 0 1 1 0

0 L 0 1 0 1 0

0 1 1 0 0 0 0

1 0 0 0 1 0 0

1 0 0 L 0 0 0

I 0 1 0 0 0 1

1 1 0 0 0 0 0

1 1 0 1 1 l- 0

1 1 1 0 1 0 0

Subtraction can also be performed by the method of addition of the polarised subtrahend l'lZ). This technique is like subtraction by addition of a cornplemented subtrahend in binary subti'action.

The addition and subtraction methods discussed so far have been of a 'ripple carry' type. For fast addition, a carry look-ahead adder has been proposed by Agrawal Izo]. 20 2.2"5 Neqabinary Multiplica-uion

The methods of multiplication in negative base have been discussed in [70] and 114). Hoh¡ever:, a variable-bit- shift negabinary multiplication process IZg] is an interes- ting method. In this method trn¡o consecutive l-east significant bits of the multiplier are examined at a tj-me and the decisi-on of arithmetic operation,/no operation is t.aken according to the Table 2.LO-

Table 2.IO Table for decision modes in negabinary multiplication

T\so bits of Arithmetic operati-on Number of right multiplier required shift /i+ r V i

0 0 No operation 2

0 1 Add Multiplicancl 2

1 0 No operation 1

1 1 Subtract Multiplicand 2

However, this method does not work when two bj.ts of the multiplier are 10. Multiplication of a non-zero multiplicand with the multiplier 10, will produce zero result according to table 2.IOi whereas the actual result should be (-Z x multiplicand). Therefore, this method needs correction. A correction has J¡een proposed in section 2..2.7.

2.2.6 Negabinary Divi sion

Elaborate discussions on J-nteger di.vision in the negative h¡ase systern Ìtave been qiven in lzo ] ano [zr ]. 2T Agrawal has presented the method of negabinary j-nteger division in IZS¡, and this has been described below.

Let (1, b, and q be the non-zero dividend, non-zero poJ.arised divisor and quotient respectively. The at b and q can be exp::essed as

m (L= ç ai( -2)í 1=o m b L 6i ( -z ¡i i=o m-n+ 1 q L c¡ -z)í o i(

The division is started with a leading zero added to a" and the most signifj-cant bits (t"ISss) of b alì-gned to a.. The quotient bit is evaluated after shifting the polarised divisor one bit to the right. The quotient is taken to be I if the addition of the polarised divisor is possible. cener- ally any one of the following conditions exists after shifting the polarised-divisor one bit right when the l-th, quotie:rt is being evaluated-

(i) o 4í*n- I a-i 4s 6-r, 6rr- I 6'o

(ir) 4i+n 4i+n-1 eí+r'-2 0,í d-s

6n 6rr-r Tn- z 6o

(iii) eí+n 4i+n- a &g &í*r*l 1 i+n- 2 6" 6o- r 6n-2 6o If condition (fii) exists, the polarised additj-on is always possible. If condition (ii ) exists, the polarJ-sed addj-tion i s never pos,sible . If condition ( j" ) exi sts , polarl. sed addition Ís possible when the rnagnitude of Pcri is equal to or 22 smaller than the dividend (or the partial remainder) . pcri j-s given by the multiplication of 6 ny e.rí, where ctcrí 1s given as:

Bit No i i-l í-2 i-3 2r0

Value of {cri o I I 1 111 the rightmost bit is 1 when i is even; otherwise it is zero.

'craÞ 6'Q.rl

However, the method described above is not applicable to negabinary fractional divisj-on. Therefore, one method for negabinary fractional division has been proposed in sectj_on 2.2.8.

2.2.7 å correction propgsed on variaþle shift neqabinary multiplication

Except for one correction, the method j_s the same as that di-scussed in section 2.2.5.

Table 2.It Algorithm for negabinary multiplication

Two bits of multiplier Operation Right Shi,'t ví*L vi

0 0 No operation 2

0 1 Add Multiplicand 2

1 0 Add (-2. rrlultiplicand) 2

1- 1 Subtract MultipJ-icand 2

[-Z'(muttiplicand) is obtained by shifting multiplicand one position left. ] 23

The correction is only for V i+ t V i = 10.

EXa¡plç.: MultÍplication of (3) ro by - (10) ro

(3) ro (0111) -2

(-10) ro 1010 01110 1110 (Negabinary Addition) (100110)-2 = (-30)ro

According to the proposed correction, the multiplier is a 2-shift multiplier and algorithm is same as bhat of binary multiple digits multiplicatj-on (table 2.4) .

2.2.8 Method Prgpo.Ped on_ Nsggþj-nall¿ Fr.a.cjio! Divi sion

The proposeC method assumes that both divisor and divj-dend are fractional and divisor is greater than dividend (i.e. X

e = atG2)'+ao (-2)'+a-r, (-2)-'*o- r(-2)-'+ t&-n(-2)-n

= -or(2)t+a.o (2) o*r!, a-í(-Ð-í

0 Let -a (Z)r+æo (2) be represented by two bits QtQo Therefore n e - QtQs+.'i a-í(-2)-í I=I

If CL_i = 1 then (i) (-r)-í o-í = -1 if i is an odd numk¡er. : (ii) (-f)-''a-í = lif í is an even number. If tl-i = ot 'then

(iii) (-1)-'a-í = o 24 In the negabinary system -l is repl:esented by two bits, 1 1. Therefore, at feast two bits are needed to represent the set (0,1,-1) in negabinary system.

In other words 0 can be written as n r-Fao ol.z-í Q = QtQo +I Iot ( ( i= I -2) -Ð n -i+1 -l = QtQu + L (-a72 *0"s2 l- = -at2-1+r+ao2-t can be denoted by two bits

Q-i+t Q-í n ThenO-eteo+ t Q-í+tQ-í ]- =

(fne negabinary point lies just after Qo bit)

Fig 2.I shows the flow chart of negabinary fractional division process, and it is similar to the non-restoring fractional division j-n the binary system.

Divide 15 by 3 64 IO B l0 Irs] X= (00.110007) - z [øaJ ro ( 3 v- ( 01. l-0I) - z B 1,, 25

00. 11001 01 . 101 Addition, since sign does not agree 00.011001 sign agrees with the sign of V. Therefore QtQo = 11 l-eft shift 00. L1001 polarisation

00. 0101 1 01_.101 subtraction 00. 0c1 1 1 sign disagrees with that of Y. Therefore

Q oQ't = 00 left shift 00.0111 polarisat j-on 00.1L01 01 . 101 addition 00.0111 sign agrees with that of Y. Therefore Q-tQ-z = 01 left shift

00 . 111 polarlsation

01 . 101 01. r_01" subtraction 00.000 (for zero rentainder Q-zQ-z = L t, since i=3 is an odd humber)

Therefore Q = etQo+8oe-t+Q-tQ-z*Q-ze-z

5 - B' 26

tN ( xrY) i.-0

Yc s No 5¡: SY ?

T + X+ Y T <_ X_Y

Ycs ST SY =7

q <_.t I q r9o <- 00

Yes ls N n ?

x <- porlt'(il X+ PotI l) ] q q T <-' X +Y T <-- X+Y Q+- k:0 -k rl ir- +l i+ i+ t

END

5 T:0 Yes 7

ls Yes ls Ye 5 od J ST SY 1 2 <- 0l e- ll 1

¡¡. q. e 00 -l.l -l

ls No Yes o dd ,,

q <- lt o-i ot -

proccess' Fig.2.1 Fiow chort of negobinory f roctionol division 27 2.3 Conclusion The details of binary and negablnary arithmetic methods have been discussed in the preceding sections. It is clear from this study that al-l the methods of binary arithmetic can, with slight modification, be used in negabinary arithmetic. However, the twj-n carry propagation is the main disaclvantage of the negabinary system. The carry- borrow technique of additionr/subtraction is serial in nature; therefore, it is inherently s1ow. The negabinary carry look ahead adder is complex and has no speed advantage over a binary adder. Polarisatíon, similar to complement in the binary system, is a serial type of operation,' therefore, it is a slow process. Negabinary multiplication does not need correction, but additions of partlal products (pp) are slower, since negabinary addition is slower than binary addition. The proposed negabinary fractj-onal division method is similar to the non-restoring binary fractional division, however, since polarisation and negabinary adoition are sl-ow in comparison with the complement and binary addition, the process of negabinarlr division is slower than that in the binary system. Above all it can be concluded that the negabinary system has no speed advantage over a binary system. Therefore, other irumber systems which are carry free are well worth investigating, 3 RESIDUE ARTTHMETIC I.,ITERATURE REVIEW

3. 1 fnt oducti-on

Due to the carry free property of residue arithmetic, addition, subtraction and multiplication are all faster in the residue system than in the binary system. However, sign detection, operations involving sign detection (comparison, overflow detection) and dlvision are slow processes. Also since residue ariLhmetic is an integer arithmetic, residue floating point arithmetic is very difficult. Similar1y output translation (resj-due to decimal) which, aÌthough less frequently usecl, is still a problem. However, due to the carry free properties, residue arithmetic systems are, well worth investigating as an alternative to the conventional (binary) system. A comprehensiwe knowledge of residue arithmetic can be gained from [ze ] , lZgf.

To be of use in any general purpose computer any number system needs efficient aJgori-thms on sign detecti-on, overflcw detection, division, iloating point arithmetic and output translation. Later work in this thesis investigates suitable i-mprovement in some of these areas for the residue system.

The remaining sections of this chapter discuss resj-due addit-ion, sr.rbtracti.on. multiplication, existÍng algor-ithms on division, overflcl detection, floating point arithmetic and output transl-ation.

2B 29 3.2 Tnteûer Residue Arithmetic an outlÍne

3.2"L Acldition Subtraction and Multipl ication

rf (Prr, þzx¡ þsx, , Þay) and (Vrqo Pzq, PsA, pn,j) are the residues cf the operands X and V respectì-vely in the residue system of moduli *i (í=7,2,3, , ñ), then addi ti on/ subt::act ion and multiplication can be expressed as

(f) Ai{dition/subtraction:

|lXtVl !M = lnr*.n rql,-r', lpr*.P rql^r, tpnql lnr*tnrql^r., ,lnn* mn

where M-trl m 1= I 1 (ii) Multiplication:

lX'/lr,r lPrx'Pyll^r, lPr*'P4jl^r,

lPrx'Pr,¡ln r', ,lPn*'PnU,l ^n

Combinational logic or look up tables in suitabl-e memories can be used to impl-ement addition-subtraction and multiplication processes. The modulus whj.ch needs the most time in operation determines the speed of each overall operation.

?t) Di.vi sion

3.2.2a Jhç tvpes of division

There are three types of division [ze ] each of which must be considered in contemplati-ng poss.ible implementations. 30

Category 1: Division Remainder Zero : Tn this category of division, the dividend is a multiple of divisor.

Category 2z Scaling : Division by factor,/fact.ors of M.

Category 3: General Division : Division by any arbitrary numbers.

General Division is of particular interest, since in a general purpose computer both divisor and dividend are arbitrary numbers.

3.2.2b Methods of General Divlsion

There are at least two methods for accomplishing thís in a residue system - General- Division I I ze] , þol and

General Division II I Ze] .

General Division II process is slower than General Division I and is restricted by a special requirement. General Divi-sion I needs a look up table which contains the numbers 2' (í=0,L,2, ...., N) in residue form. (u is the highest. poi^rer to 2 contained in f$ -rl). rhe l.ook up table is formed in memories, where the address represents the exponent (power) to 2 and the contents gj-ve the value oÍ 2í in residue form. This method assumes that the dividend x and. the divisor Y are posi-Live and nonzero. The detail.s of the procedures are gi-ven below. 31

(i) Find c(y) =2k. (Starting with the highest arldress number ( N) , the contenLs of each location of the table is compared with V, until 2l' < y .2k*') . (fi) : 2N Find the first approximation, F c(v) ' (since 2N and G(/) are the numbers of powers of 2 and- c(y) t 2N, r can be found by division of Category 1. )

(i_ii ) Follow the j-terative process shown with the flow chart of Fig. 3. 1-

To determine c(v) by fpsqfithmic search technique [¡n ], it requires on t-he average tog, modular (3.1) \ " operations [¡o] (Where n is the number of moduli; c = logz W:/Z-L))

After c(y) has been obtained, to find F it requires (on the average) additional (n+2) modular operations (3 .2)

Iterative process needs on the average

c (n+1) modular operatiorrs (3.3) 2 Therefore +-otal division process requires, on the average n -Log c+n+ , * (n+l-) ; " i modular operations (3.4) 32

STA RT

L +-0 j <--o Qr-êo

i e- i+t

R.<- X- Y.F )

ls Rj ¡itive

L + L+ I qL <_ F

Is Yes ls R o? F=0?

F <_ F/2 a *ãou X<- R

ENO

Fig. 3.1 Ftow Chort 0f Iterot,ive Process in residue irrteger clivisioll . 33

The first approximation F can be det.ermined by fgg_ç_ technique from the value E(X) E(y) {fv¿.çfpn [¡O] of and " The steps that are followed are: (i) Convert X to its mixed radix form (Appendix-s) and pick up the most significant nonzero diqit

a (say). uv"

(ii) Find ç(.(aux+l )np) and c (øu*. nt ) from a look up table which contains the value of

( 2i' í=L ,2 , N), where N is such that

2N < (n-r) < 2N*1. (np R m Also find i= I l- ). n(lLux+r )np) and E (au*np) from another Ìook up table.

(iii) t¡ind x' x- c(lctu*+1 )np) and determine the sign of X' by another mj-xed radix conversion. If sj-gn is negative c(X) = G(a and E(X) = n(arr*nr). u "np) otherwise c(X) c((a +1)np) and E(X) = = UX E(lau*+r )np) (e (x) i where i = I,2,3, ....N).

Similarly find E ( Y) .

The F j-s given by E(X)-E(Y) F 2 (in residue form)

If two mixed rad.'i-x converters and assocj-a.ted look up tahles are available, F can be obtained in 2n rr,odular operati-ons.

3.3 Overflory

If m, (i=1,213, n) are the moclul-j. of a par.-ticul-ar t_ residue s¡,:stem and the modul-i are pairvrise ::elatively p::ime, then t-he range of the numbers that cen be rrniquely represented 34 l-s gr_ven by M = *.t_, *r. If one of the moduli is - l=r L even, then the range of the positive numbers (posit_ive half) and that of negative numbers (negative half) are defined by {o to tt/z -1] and {¡rt/z to M-1} respecrively.

An overflow is said to have occurred if the result of an arithmetic operation exceeds M or the range of positive half or negatlve half.

3. 3. 1 "a:¿eff].ç¡g due tq ditio subi:raction

An additive overflow can occur if two operands X and / are of same signs. rf oper:ands are positive and overflow occurs, the result falls j-n the negative half. For negative operands, the result falls in the positive harf. Therefore additive overflow can be easj-ly detected by detecting the incorrect sj-gn of the result. Subtractive overflow can occur if the signs of the operands differ. since subtraction can be reduced to addition (X + (-y) ), subtractive overflow detection is similar to the additive overflow detection.

3. 3. 2 ¡4qlÇjplrcel;LvC overf low

When multiplicative overf-'l-ow occurs, one of the two fol-l-owing phenomena occurs (-r.) the resul-t j-s of incorrect sign (exceeds the range of posit:i-ve half or negative half ) or (i-t¡ the result is of correct sign, but incorreet magnitude

(exceeds M) .

The overflow of 1=irst, category can be detected by checi

G lxY lr'r * c(v) (3.5a) x

Fi::st -lJj]-* t* calculated by techniques of General x xY Division I. Then G I I r,r x arithmic search technique. x time will be needed to find it. However, íf the expresslon

(3.5a) j-s w::j-tten as (3.5b), the division -ltn-l-O can be x avoided. c( (xy) r"l) c(v) (i.5b) G (X) I c((Xy)r,r), c(X) and c(f) can be obtained by fast technique proposed in [30]. Tf two mixed radix converters are available, the overflow of second category can be detection with 4n modular operations (3.5c)

Multi.plicative overflow can also be detected by using a redundant modulus [Za]. The time required. j-s at the most 3 MRC (t',lixcd Radix Conversioir,' Appendix-S) with n+1 moduli plus 1 modular cperation. This is equivalent to .3n+1 modular operations. (1MRc is equi-valent to (n-Ð modular operations fAppendi*-s] with n moduli).

3.4 1 tin Point Ari

At present it j.s diffjcu.Lt to perfo.rrn floatirrg point arit.hmetic in a residue number systenì. There is a lj-mit-ed

amount. of published work on this problem, for example, [¡¡ "] 36 has proposed 2 as t.he base of the exponent, while [:Z] has proposed a base cf 10. However, ho details of floating point arithmetic operations have been given. The algorithms p::oposed in [¡t] are of particular interest, since details of arithmetic operations have been presented with j-lIustration. Furthermore, the format used is different from the conventional format. The details of the algor-

ithms ha,ve been given in the f ollowing sections "

3.4.1 The representati-on o f ! : o_a_!i¡9. p-e.i¡tç. number:s

A floating number can be represented as

e k M M ^ (u-f where klt-¿ . * ) ì e- is an integer

M fimi (,s o) L i=^ t I

M 1 (,5 o) b n M IImi i= I

and In1 4 Ir2 ( In3 <

3.4.2 Floatinq Point Aqithmetic

8._ Ø,t Let X -k ML *o* and V k M7M X U ^a and 7 - Fr(x o v) =krL¿z Mo, where O denotes arithmetrc operations (addition, subtraction,

multiplication or division) .

3.4.2a AlcloJij-thms_ f o¿ floatinq point addj.tion subtr et- ion

(ft is assumed that Ø and X, / are positive) X U 3l

( 1) F.ind A¿ ø.. ø rf Lø > 2, ,l U

FI (X!Y ) x

(2) rf Lø = I, test whether Á >A a If it is true Fl(XtY) - X otherwise scale [Zg ]

k brv m- m mm *o mn. a 2 ^x ^ u*' ,* " Let the result be K R

(3) rf Az = 0, test whethe:: ¿.. = Tf it is true lt ^ a KR k Otherwise, scale k b)' m m +z a ll +1 ,5 ^ a a *O* and the result be KR.

(4) I'ind k= k* r K* and set Lz øX ,ì Áz = = ^x. þuut.to' is done using redundant mod.ulus rn¡+1. mn+ l-S SO chosen that (M-1) (NI . m¡+t 1) I -¿¡, + - and m' t ' ^r-r* l (5) Find the mj-xed radix digits (1"í (i = 1,213, n+1) of k which is associated with moduli mi. z_ If o"í are zeros, set 0 ¿z = ,L=0z

(6) se denote by & the most signifj-cant non- Otherwl , u diqi t IfU_ scale k, bv m and zero " n*l, +1 ^ increase by 1 rf - n, set á 0 and. ^ z ^ z z

Q- by 1 increase z âz+n (7) If U < n, multiolv k by mi t4 T_= A ,+ LL+ t which can be read fron-r a permanent table by using

U ancl á. , decrease ¿ by 1,, and increase .52 by U.

Tf step 5. If > n, increase ¿ ^

(B) If U n, test whether á. 0. If it is true.

k normal-ized. o, fetch I ( (u ) 7 is rf^ z I 2 lmo. +1) from look up table. Find 1 ( (rulmo.) lk.l - 2 +1) and determine the sign. Tf sign is negative

multiply k- by m¿ and decrease ¿ bv1 z 7 z-

3.4.2b Alqorithms for floatins poin! multipl j- cat j-on

(1) Find ln"lr. and lkrln,.{i = n*1, ni2t n+p) by method of base extension IZe]. r is done using p numbers of redun- l¡,tuttipticationL dant moduli to prevent loss of information due to multiplicative overflow. The redundant moduli are so chosen that p < n and

1 2 (M-1) m m m m -1). 4 -z'|(¡r n+I n+2 n+p and 'iln+r ( Irln+! < .... <

(2) Set e. =Ø+e z x a ^ z ^.x

(3) rf 0, find k k . kA, and if L 1_ ^ a x a fíndk -k k . ITI¡ r where the residue repres- zx a entat-ion of mr l_s read from look up tabl-e. Other-

wise, increase Ø bv 1, find k* k and scale the z a result bv m m mn to get k.. 6,,1! d a q*' (4) Find the mixed radix digits (Appendlx-5 ) o"i (i n+p) ofk the digits = 1, 2, ...., z If all arezeros, setu^z= 0 , O=-z 0. Otherwise denote the most significant non-zero digit by au. t: +u-n. ) (5) If U > n*2, replace k by k *t z z !Ía rn, j 39

and increase by LL-n. If ,5, = n, Set á 0 ^ z 7 L and increase 7 by 1. Go to step 4.

(6) rf u n*1, replace k by (kz m and increase z I ) ^z+r ¿ bv1 . rf = n, setá =0andincrease Ø z' ^ z 7 z bv 1. retcrr I (M-1) (in resiclue form) fronr a table, compute (M-1) and find the sisn. lk. l + j-ve, If sign is posit replace k, by (n. l^0 ) r., , and j-ncrease o, by 1 rf [ n, set ó to zero 7 - z and increase u, by 1

3.4.2c Al-qorj-thrns for f1oat-14q p_g¿n! clivi sion

Let X and / be the dividend and divisor respectively.

(1) rind lk* l*1 and ifrl*1 (i = n*1, n+2, n+p) by method of base-extension.

(2) Multiulv k by x A which can be read from a look up table. r I The value of A depends on and ó L ^ x U a)' rfL > and ¿ 0 A=M x- ^ q U b) lfA and Á rJ 0 [=B.C X ^ a a

n C :îTm where B IT mi and ^x 1 í= 13 +t i-= a ^ x-Áa*t c) rf. L A and oq I O, A M x a d) rf A M B . D where ^ X ^ q x ^ n f = Tmi i=n+ó y-,5 ,+ t l

(3) If^<^, decrease a. by 1 and increase by x u. ^-z' n

(4 l-ind k (kx. A kt) by scal-ing. ) z I (rr k 0, division i,s undefined) z = ltO

3. 5 Translation of Residue Numbers to Decimal Numbers

A number j-n residue form j-s not readily understand- able. Therefore the resiclue systern needs a provision for translating residue numbers to decimal numbers. Since output translation is l-ess frequently used, more time can be al-lotted for translation than for arj-thmetic operations.

The Chinese Remainder Theorem [ZS] can be used for output translation provided that the system has the fac- iJ-ity of mod-M operation. The A(X) method [34] does nor need mod-M operation, however, it needs super modulus to determine a(X). and the method is applicable only if the base tÁ) (in this case 10) is pairwise relatively prir".e with mi. Benerjee and Brzozowski [35] pointed out that the method of base extension [24] can Ue used provided (i) gcd (ø,mi) =1 or (ii) gcd (w,mi) I 1 for only one modulus and (¿l ) ffi;I for that particular modulus.

lgca stands for greatest common djvisorl

3.6 Conclusion

It is obvious from above discussions that addition/ srii¡traction and multiplication are straight forward operations; and delay is equal to the delay of one modular cper- atlon. The c)peration-s can easily be j-mplemented with memor- i-es (took up tables). Therefore there is no real problem in practical implementation of these operations.

Division , hov/ever, is not so easy as addition/subtraction and multipJ-ication. Determinatlon of the first approx- 4t f-n imation F which needs logz c + n+ ,) moCular operations 12 using logarithmic search technique is obviously a t.ime- consuming operation. However, fast division technique can red.uce that time (for determination of F) to 2n modular operations. This irìêêrrs that the dlvision process will be faster. Still an investigation, whether a fast division technique can be :Lmplemented in a different way with speed improvernent, is wc::thwhi1e.

Mu-t-tipl-1 cative overf low detectlon in redundant res- i.clue system is faster (3n + 1 modular ope::ations) than in non-redundant system (4n moclular operatjons). However, a redundant system needs an extra modular operation which may not be desl::able. The choice of redundant modulus may be critical. This means that if the redundant modulus gets large, implementation of operation with that modul-us may be difficult and operation may get slow. Again, the introduction of a redundant residue decreases the available range of tÌre system which may not be appreciated. Therefore an alternate approach Ís to choose the non-redundant system and carry out an investigation for faster overflow detection technique.

As discussed earlier floating point multiplication and divj.sion need p numbers cf redundant moduli to prevent loss of information due to rnultiplicative overflow. This compels the system to have the capacity of (n+p) modular operation units anC the capacity of l.iRC hrith (n+p) modul-i. If p is large e"g" (p=n) , then MRC with (n+p=2¡) may be difficu-lt. If p is chosen to be smaLl-er, each redundant 42 modulus u¡ill get larger (to meet the requiremenL stated before) and mechanisation will be dj.fficult. Therefore it is worthwhile to investigate alternative floating point aì-gorithms and particularly those which can be implemented wlthÍn the intege.r- residue ar'-ithmetic env-ironment.

In output translation, the Chinese Remainder Theorem needs arithmetic r..'-ì-th mod-M which is a costly affair. The

A(X) method is restr'icted by the requirement tha'f: (ø,m. ¡ must be pain^lise relatively prime. In conversion of resiclue numbers to decimal numbers, the base is l-0 which is a com- posite of 2 and 5; and a residue system generally has one even moduJ-us to have well-defined positive half and negative harf; therefore the above requirements cannot be fulfilled. The methocl of using base extension covers a wide range of situations. However, in a system where IJ) . *i and gcd (w,m=) I, the base extension method Ís not applicable. a I fn that situation an alternatj-ve method must be investigated.

The next chapter proposes a few algorithms relating to the above problems. APPEND TO CI{APTER 3 OF THTSIS

"Residue Arithmetic in D'igital Computers" R.C. Debnath

FURTHER RELEVANT PAPERS

Jul I ien [82 ] establ i shes that the residue operations I i ke addition, subtraction, mult'iplication and scaling can be easì1y 'impl j emented wi th I ook-up tab'les n currentìy avai I abl e ROMs . He also contends that scaling by the metric vector estìmate process ìs ei ther equal ìy or more h'igh'ly ef f i ci ent than the exact divi si on techni que. Res i due arì thmet'i c operati ons ( addi tì on , subtracti on , mul ti pì i cat'ion and scal i ng ) ímp'lemented wi th I ook-up tab'les ì n h'igh densjty ROM can allow for a high speed digital processor.

The conversion of a residue number to a b'inary number is not an easy process. The method based on the Chinese Rema'inder Theorem requ'ires residue arithrnetic operation with Modulo-M, and ìs therefore a costly method. A nrore efficjent method is to use the Mixed Radix Decodìng technique [83] " This technìque needs less memory ìocatìons and can also be ìmplemented wjth current'ly ava'ilable ROMs or PROMs.

Add'i ti onal Ref erences : - t82l G.A. Julìien, "Residue number scal'ing and other operat'ions usìng ROM arrays", IEEE Trans. on Computers, Voì .C-27, N0.4, Aprìì I978, pp.325-336.

t83l . A. Baraniecka and G.A. Jul1ien, "0n decoding techn'iques for resi due number system real i zatì ons of di g'ita'l si gnaì process i ng hardware", IEEE Trans. on Circqits and Systems, Vol.-CAS 25, N0.11, No. 1978, pp.935-936. 44 from the following groupings of the numbers from 0 to M/2.

1- (0,1); Category Group-0 = Group-1 = (2,3, (M þ -rt 1, ((uf (M Group-2 = , f +r, vr/ 2)

2 (0,1) Category Group-0 = ; (2,3, Group-1 =) tr\f -t Group-2 =) ((+þ , r\f *t, M/2)

From the groupings of the numbers, it is clear that- no overflow occurs for (Group-0) . {(Group-1) or (croup-2)}; but overffow will occur for (Group-2) " (Group-2). Howe\/er, there is no certainty whether overflow will occur for (croup-l-) . { (croup-1) or (croup-2)}. Even if overf low occurs, it is not clear whether the product exceeds P(>z\ or N(%) or (M-1). This is due to poor resolutÍon of nurnbers in groups 1 and 2. Therefore a 'Logarithmj-c Distribution' which gives hiqh resolution of numbers in groups is proposed.

4 .2 . i- Loqarithmi c Di stribution of resldue numbers

The numbers 0 to M/2 (positive half ancl the highest negatj-ve number) are distributed among several groups according to the tabl-e 4 . L.

If g(x) and g (V) are the group numbers of X anC l/ respectively, then it can be shown from Table 4. i I Appendix-l; (apr (a)) I rhat

Case (i) : if g (X) +- U , no over,'ll-ow cccurs; case (ii) ; if g (X) + U, overflow must occur. Case (ii.i) : if tj(X) + LJ, or¡erf J-ow may or may not- 45 occuri hohrever, if it occurs, the product will be of incorrect sign.

Tabl-e 4 . L

Distribution of Numbers

Numbers qLa-up.

0 0

1 1 rñ-2Ár2 -3W -2-^*t 1 2 ^_^+ 3 vI .¿ w.2-L*u 1 3 I -> I I ..-6+ l,s- tl -^+^ w.¿ --> w .2 -1 _1" -^+^ -^+(Á+r) ^ vr.2 W VrI.2 1 -+. ^ -,5+(Á+t) -^+ l^+2) w.2 ¿ w-2 -1 Á+1 I , -¿+(A-t) I w.2 -+ M/2 u-L

fwn"r" a n*1, such that 2n S lr{ < 2n+l; in other words U is the highest power ro 2 contained in 2M. When A is even,

L w Q4í' and ¿ q/2 + 1. When A is odd , vr= (yþ, and tq*t) /zf ^

1, However, in most CASCS ï'rí' or ëþ is not an integer number. fn those cases the closest higher integer value of ,M-' wþ or l1)':-s chosen to be the value of W. The lowest 1) nurnber jn the (¿-i)th group (i L a Lt ¿-1) is ¡tre rounded integer value of L/2, whe.re L is the lowest integer h number in (a-ir-l-)th group. The lor,vest' rrumber in the (a +1. ¡t 46 group (k = I ,2 , , ó -3 ) is given by 2k .w. However, Ín case (iii-) in some situations, mult1plication of two highest numbers in two separate groups may be equal to or greater than M (due to rounding error and choice of the closest- higher integer value of (\iþ or ë-þ for w) . under these circumstances a minor adjustment of the highest integer is needed. The higl-rest number of the higher group of the two is clecreased by a minimum nurnber¡ say o, such that- the product of the decrease¿ num¡er and the ot.her highest number becomes l-ess than M. The lowest number of next higher group (w-ith respect to the higher group of the tivo)

is d.ecreased by the same number cx,.

7, Tf olf or ëþ is an integer number (i.e. M or M/2 is a rational number) and even, then t.he lowest number of

(Á-l)th group is to be increased by 1 arrd the highest nuin- ber of the (,s-Z¡th group is increased by 1.

Example 1: If m = 16, m 15, m = 13 and m = 11, 4 3 2 I construct a 'group table' . Solution:

(i) Jvl = 16x15x13x11 = 34320

(ii) 2t5 < M < 216 ; therefo::e rj = r6.

(iii ) (l{ þ = 185'256¡ therefore W = l-86.

( rv) 76/2+1-9 ^ (v) M/2 : 17160

(vi ) Table 4.2 47 Table 4.2

Group table for Example 1.

Numbers Group

0 0

l_ 1

2 2

3 5 3 -> 6 l-1 4 L2 23 5 24 + 46 6 47 92 7

93 ---+ 185 B 186 ?77 9 372 + 743 l_0 744 -à L487 11 1488 ---+ 2975 T2 297 6 ---i 5 951 13 5952 + 11903 L4

1 1904 77L60 15

Example 2z Form=2, m=3,andm=13, 3 2\ construct a 'grou.p table' . Solut.ion: (i) Pt=2x3xl-3=78

(ii ) 2e < M < 2t,' therefore U = 7 (iri) ëf = 6'24;thereforeW=7 (iv) = (q+L)/2 = 4 ^ (v) M/2 = 55

(v-t ) Table 4.2(a) 4B Table 4.2(a)

Group table for Example 2

Nr¿ntloers. qroup

0 0

1 1 2 -+ 3 2 6 3 4 --' 7 __> 13 4 L4 27 5 2B ---+ 55 6

It is seen from the table 4.2(a) that the product of 6 (ttre highest number in 3td group) and 13 (the highest ,th number in 4"" group) is equal to 78 (=M) . Therefore the hi.ghest number of 4th group is replaced by 1,2 and the lowest number of 5th group is replaced by 13. The correct 'group table' is shown in table 4.2(b).

Table 4 .2 (b)

Correct Çrol1Ð table for Example 2

Ntimbers GEalB

0 0

1 1 2 -+ 3 2 4 _.> 6 3 7 I2 4 13 -.-> 27 5 2B --b 55 6 49

Example 3: Ifm=2,m=LL,andm= 5 32t consl-ruct a 'group table' . Solution:

(i) ¡4- 2xtLx5 = 11-0

(ii) 2e < M < 27 ; therefore rj = 7 (iii- ) ëþ = 7'4L; therefore W = I (iv) ó - (a+I)/2 = 4 (v) M12 = 55

(vi ) Construct Table 4.3

Table 4.3

Group Table for Example 3.

Numbers Group

0 0

1 1

2 3 2

4 7 3 8 15 4 16 31 5 32 55 6

Therefore multiplicative overflows can be detected by (a) testing for incorrect sign of the procluct, and (b) comparing the sum of group numbers of multiplicand and multiplier with the total numbers of groups A. If sum is greater than U, overflow must occur; if it is l-ess than A, overflow wil-l not occur: 50

4.2.2 !çç.:gq. J-ùe*_e.s-- f,çr Overflow Detec'Lion

Since the group number:s descrj.bed pr:ev-ì-ousIy are assigned to the positive numbers and to M/2, and a number may be positive or negatj-ve, the inf crmat-.ion of slgn aird magnitude of the number is essent-Ía.l . The MRC (eppendix-5) is the only way to get sign and magnitude inform.ation. From the mixed radix digits (MRD) of a negatlve number it is possible to form the MRDs of its positj-ve 'counterpart' Iappendix-1, (apl (b)) ].

When number of MRDs gets larger, a par"t.ition between them is essential. This partition divides the L"iRDs into t\^¡o parts the most significant part (MSP) and the least significant part (LSP). If the modulus Mn is chosen to be even, and is placed at the most signifi-cant digit (t"ISn) position drt, then ArL contains the information of sign and falls in the MSP. With the sign informat-ion and MRDs of the LSP, a look up table is formed for the group numbers of positive/'counterpart' positive numbers j-n the LSP. ('fne table 1s formcd from the decimal value (DV) of the MRDs.)

When the number is negati.ve the MSP needs the rnfor- mation whether: the LSP is zero to form the MR.D of the poG- i-tive 'counterpart' . From this information (zero-LSP), the sign and the MIìD of MSP a look up table is f ormed, as--suming the IviRDs of the LSP are zeros. (rne table is formed from the DV of the MRDs.)

The group number of a nr¡mkrer: depencis oTì the DV of all Ir{RDs (MSp + LSP) . Frorn ihe observat-ion of the range of 51 numbers in a group of the MSP and the DV of the MSIJ, i L will be clear that the group number of certain MRDs of the

MSP will transit to the next higher group number if certain minimum numJ¡er from the LSP is adcled to the DV of those particular MRDs. Those MRDs may be 't-ermed as 'transition' MRDs and the min-imum number required for transition as 'transition' number. The transi-tion number is identifÍed by observing whether the number, obtained as a resul.t of subtraction of the DV of the MRDs in the MSP from the lowest number in the next higher group (wittr respect to the group of the MRDs in the MSP), falls within the range of the LSP. Therefore along with the group tables for the IvISP an

Overflow j.s detected by comparing t.he sum of the group numbers of operands wj-th the total number of groups and det-' ectillq the incorrect sign of the procìuct" 52

4"2.3 Des_i.gn E-:g-Up_lS. on Overflow nClCC!¿p:f

The moduli ffiq = 16, ffi,, = 15, ffiz = 13 and m, = lL have been chosen for this design example. The MRDs are designated by î*, &3, &, and ar. The range of the LSp is 13x11 = 143 (0 to I42) and thar of rhe MSp is 16x15x13x11 13xl-l- = 34L7 7 i.e. from 1,43 to 34t71 . The rrighest nurnber in the LSP is 142 and the MSp is norì-zero for a number grea'ter than I42.

Examining the Table 4.2 and the DV of tl-ie MRDs in the

MSP, Table 4 4 which shows the rtransiti-on' MRDs and 'transition' numbers, can be formed.

Table 4.4

Transition MRDs and transition numbers

The DV the Transition of Corresponding The lowest Transiti-on Transition MRDs nurnber in MRDs Group of the Number = d\.15. 13 . 11 the next &\, &, MRD * d2.13 . 11 higher group

0 t L t43 B 186 186- L43 =43 0 t 2 286 9 372 372- 286 =86 0 t 5 7Is 10 744 744- 7Is =?9 0 t 10 L430 1i 14BB 1488- 1430 =58 1 t 5 2660 L2 2976 2976- 2860 =775 2 t 11 5863 73 5952 5952- 5863 =83 5 t 8 1 1869 14 11904 11904-11869 =35

Figure 4 l- show.s the circuit for multiplicative overflow detector. The circuit in the sol id l lnect box detects incorrect sign of the product. If the Excl_us 1ve OR of the sign of the X, / and Z (SX,Sli, andSZ) is '0,, the sign of 53

r- lx IX lit t,, lxt 3 hr 3 t t, ¿RoM - I PRo M- z þ9]g.lt.t¡¡lo . . T¡ble lor Dl Tabta for 02 gates ). NZ( X ):'l' (Sec f i9.4.2(a)) (See fig.6.2(b)). meàns lXlt3 and lXl¡¡ T, 1 åfe r,.'n- zeÌos. DI l, D2 l, NZtX) P RO M - 3 PROM - 4 l¿bte lor D3 Tabls ¡e¡ e¡ and 01, (See lig.1.2(crt , (See f ig' 1,2(d','), xt 3 t, D3 Dl. a I PROM - 5 T¿ bt r a1, sx ¡ nd I(X). X I m¿â n a 04 are on-zcr05 e .) SX r(x) ; SX NZ(X) S SX (x) i. I t SY T sz f ¿B-O-l¡-:--9 PRo M -f PROM-8 BAau:-s NZ(x ) NZ(Y ) Tabtc lo r lrensition Negal¡ve Table I o r inary vatue grâup group numbers. I( t UM ber of lrs L s P number of (See fig. I SP. (S I( c e fig. L. (l s ee I t, I c(MsP ) I

Futt Adde rs. G(LS

Carry Fult Adders.

l(x ) t, 2:l r¡ e¡F r t(x + tecls 9(Y ! I (x) I 1 PR0M 0r Logic ckt. Gener¿tes 0VERFL0W signat.

overtlow Il 'l' tgroup rF From generatort ol Y f From 'sign detectort of Z

F¡9.¿.1 Schemotic diogrom for muttiplicotive overf lc\.',/ det ectío n irr the 16-15-13-11 residue system. 54

Function of PROM-1 ; (256x4)

D where It forns a table of l' D, = lo". 1l- + d, lr., wlrere tL" amd cL, are the lr{RDs of the LSP. a Xr,,- 2 If [r^r,l*],,' [.#,,],. & I lxl ,,

Fig 4 .?-(a) : Function of PROlt{-1

Function of PROM-2 t [256x4)

It forms a table of Dr, where

where Dz=lo, !7+et 1 5, a., and a", are same as in Fig 4.2(a).

Fig 4.2(b) : Function of PR0M-2

Function of PROM-3 t (256x4) t forrns a table of D 3' where

3 -D I 1*r,, l6 IP¡,. r6

Fig 4 .2(c) : Function of PRONI-S 55

Function of PlìOtr{-4 ; (256x4)

It forms a t¿rble of ctr, lvhere

tla lxl,u D I t5 15 15

D4 lo, | = d.', since 15 < l-6 16

I.'ig 4.2(d) ; Function of PROM-4

Function of PIlOlvf-5 (256x8)

It forns a table of nu, SX, I(X), wherc

& Dul 4 ln, 16 I6

SX = '1r if. nu > 7 ; I(X) t1t, if Da and Du are nonzero

Fig 4.2(e) : Function of PR0M-5

Function of PROIT{-6 ; 1512x4l It folms a table of group number of the MSP. If N7(x) r0;, = t0' or tl-r and SX = the decinal value, DV(O) = r0r 44 . 15. 13. 11 * D+ . 13. 11. If SX = '1' , NZ (X) = and Du is nonzero, the decinal value, DV(1) = (LS-a.+) .15.13.11 + (15-Dq).13.11. If SX = rir, NZ(X) =r0r and D,, is zero, the decinial value, DV(2) = (16-a.q) .1-5.13.11 + (15-D,f)'13.11. If SX = '1', NZ(X) =r1r, the decjmal value, DV[3) = (15 -cL+) .15.13. 11 'r (14-D+) . L3,1,1,. Tire grou¡t nuntbels arc as-signed ¿lccording to rhe Table 4.2.

Fig 4.2G) : Func.tion of Pl{0M-6 56

Function of Prom-7 t (s12xB)

It forms a table of rt:cansitionr number according to the table 4.4.

Fig 4.2(Ð : Function of PR0M-7

Function of PROlt{-8 (512x8)

It forms a table of negative binary value of the

LSP fron its decimal value. If SX = f 0', t-he decimal value, DV(4) = 42.tt + 4t. If SX = I l- | and a, is zero, the decrmal value, DV(s) = (I3-a"r).LL. If SX = 11' and a-, is nonzero, the decimal value DV(6) = (12-a).11 + (11-ar). e, and a, are same as shown in Fig a.2@)

Fig 4.2(h) : Function of PROM-B

Function of PROI'{-9 (sL2x4) It forns a table of group number of the

LSP fron its decinal value (shown in Fig 4.2(h) according to the Table 4.2.

Fig 4.2(i) : Function of PR0M-9 57

Function of IrROM-l-0 (256x4) It forns a table of overflow (not final overfiow) accorcling to

(i) Overflow = '0', if g(X) = g(V) < L6

(ii) Overflow = rlt , íf g(X) = g(V) > 16

Fig 4 .2(j) : Function of PR0M-10 the product is correct; otherwise the sign is incorrect.. However, false indication of overflovi is given if one oper- and is negative and another is zero. The cj-r:cujt rj-qht side of the circuit in solid-lined box detects whether any of the operands is zero.

Sj-nce lXlt. and lXltt contaj-n the informatjon on 0.2 and ar it is not necessary to generate 0,2 and a1. This saves use of one PROM. The circuit in the dash lined box generates the sign of X (SX), the MRD (ou) and the information of nonzero c-+ and Da. Two additional clrcuits- are required - one is for generation of the sign of y (Sy), the group number of y (g(V)) and Nl(V) and the other one is for the sign of the result Z (SZ) .

Performance: Delay in overflow detectj-on is the delay through the longest path v¡hich, for the circuit in Fig 4.I, is through the circuit reqr.ri-red for: overf l-ow detect:ion by the 'grouping technique' . Therefore 5B

Delay, D= (Dl = delay in sign detection)

+ (Dz= delay in getting Group Number of the LSP) +(Ds= B bits adder delay + 4 bits adder delay + 2zL multiplexer delay) + (D+ delay in PROM-l-0) + (os delay in OR-gate at the last stage).

Again Dt = 2Tt + Tz where

m.Ll access time of (?-56x4) pnou

J.2 access time of (256x8) PRoM

Let TRoo = delay in a 4-bit full adder. T"u" : delay in 2:1 multiplexer" To* = dei-ay in OR-gate. Therefore

+ + T + T1 + Ton D - 2Tt T2+T3+37 ADD MUX 3Tr + T2 * T¡ + 3T + T + T = ADD MUX OR (4.1)

where T3 = access time of (512x8) PROM

However, delay in generating group number (Og) is the delay in generating g (X) . Therefore Dg can be expressed as

Dg Dr *Dz *Da 2Tt*Tz*Ts+37 +T ADD MUX (4.la)

using TTL components (raure o. g (a) ), the delay in multi.pl-icative overflow detection is given h'y

D = 3 40+60+60+3.7t- 4 + 4 59 = 1.2O +L20 -F2I +B = 269 ns. (4.l_b)

The delay in generating grcup number is given by

Dg = 2.40+ 60+60+3- 7+4 = B0+60+60+2L +4 = 225 ns. (4.1c)

4.3

The method of division conslsts of two processes (i) determination of first approximatj-on F, and then (ii) iterations using successive approximation. (fne successive approximation is the number which is equal to the previous approximation divided by 2 ) , Since the group number contains the information on the magnitude of the number, i! is possible to use the same piece of hardwarerused for generation of group numbers, for determination of first approximation.

The F determined from the group numbers of the operands is alwalrs positive, however, division is not limited to positive operands on1y. The cjetail of the technique for determination of the first approxi.mation and successive approximation has been givenin section 4.3.2.

4"3 1 A Division Process

The division process can be best descrj-bed with a'flow chart in Fig 4"3. The sign of the result of division is the Exclrrsi.ve: OR function of the signs of the operands X ;"lnd y. (X is the dividend and / is the divisor.) 60

iN ( x, Y )

I û q. 0

e enera v hardware )

No Is Yes F 0 ? Vi, 4- Y'F 0,

Is 0oes Yes Yes the sígn No W 0verf Iow of tlre resutt +' 7 ?

No Is C hange q to Yes W> its negative 2 fornr . No ls e sign o the result +t E ND ,, No

X+X+W x <-x- iÂ/

i+l +- q, +p

F + Fl2. ( 2 s gene rated by hardware.) l=ig. ¿.9 Flcw cha rt cÍ res¡due integer d iv i sion P rocess 61

4.3.2 Hotg to_ f .r.:ê the f :!_r_q! êpp_Ë_o_ì(r]la!-t-A.q SUCCCSS]-V -an-è e aÐprox-]' mations

T\n¡o look-up tables are required t.o obtain F and successive approximation,' one is used to get F and other one to get success-ive approximation. The value of I- depends on the group numbers g (X) and g (V) as shown beIow. -s(Yl (i) rf s(x) > g(x) F 2e(xl

(ri ) rf s(x) < g(Y) F 0

(r or successive approximation is tabled irr residue form. )

Fi.rJ 4.4 is a schematic diagram of the computer cir- cuitry required to get F and successive approxination. The dotted line in Fig 4.4 indicates that eitherXor/data bus can be used to issue 'previous approximation' to the multiplexer. The function of the computer is to perform iterations and to issue X and V to get F or successive approximation from previous approxirrration.

If the address iines of an available are equal to or less than the sum of bits of each of the modul-1, then the cJ.rcuitry in Fig 4.4 Ís not feasible. An alternate approach rr¡hich needs a smaller number of address .l-lnes to PROIvI is sh.¡wn in Fig 4.5. Tn this case the PROM forms table of F (which also gives successive approxinLation), according to the number output from the subtractor. If the (r:+1)th bit is 'L' (i.e. negative) , the PROM gives zero value; otherwise it gives the residue number of 2k (where k is the positive out--put from t--he subtractor) " The conìputer receives t\,{o sets of information one j-s F or successive approximation and the other is the value of c-. r'or lth iteration the 62

C Prev i ous 6rouP ,dpp rox iÌn at ion'. c 0 Gene rat o r þ'l P U 9(Y ) 9r.X) T E R

tDiuid" 2:1 MuttiPt exer by 2' slgnal. ¡f it is '0', muttiPtexer setects 9(X) ¿nd g(y). Atso it divides the tocat¡ons {9(x)re(Y)} of PROM s into two Or hatves. 0ne hatf þrevious . , F other hatf APProrirna tt on' lor tSu ¡ for c cessiv€. Approx irnatíon"

@s The Tabtes cl F and Sqccessiv¿ APProx irnatio nt'

F or Successive AÞprox imationt

Scl-remGtic f o r gene rot ion Fig. h.trI "dioçrGm. of F qrì d Succes sc ve APProxirnr:ticn'" 63

I t

I Y Group Generator.

9(x ) g(Y ) C 0ne

n bits -r n bits. n bits l b its. 2:l 2"1 Muttiptexer. Mutt iptexer tDiv¡d. , b v 2 ¡ se tD c signat. l' Iects ivide by t 0 2 s ignat. C. M 'l' setec t s Subtracter P 0ne. U ï (n+r bits. E ) c R

(n+t ) bits EIgUr Table for F and n bits. Successive Appro ximation.

F or S u c c ess ive Appro xim a tio n

Fig.4.5 Schemqtic diogrorn of on olternote circuit f o;' F ond Success ¡ve Approximotion. 64 computer j-ssues the value of C (through the data bus X or V) which l-s equal to C' obtained during (i-1) th iteration and receives a new value of C' which is (c-f), and the approxintation.

Si-nce the number of bri.ts required to represent the group number is far less than the sum of bits of each modulus, it is possible to use PROM with less address 1ines. For example, 1n the case of the residue system of rnoduli 16, 7-5, 13 and LI, the sum cf bits of each modu]-us is 16.

Since a 64k PROM (f0 address lines) is not yet ar¡a j lab1e, the circuit j-n Fig 4.4 is not feasible. Whereas the circu:Lt in Fig 4.5 can be implemented with a PROMs with S,/more than 5 address lines.

Performance

Delay in obtaining F by the circuit j-n Fig 4-4 is given by

D (4.2) D(1) g + Tuux * Tr

where D delay in forming group. g = T¡,tux = delay in 2:1 multiplexer. T, = access time of the PROMs. According to the circuit in Fig 4.5, delay is given by

D (2) D +T +T +T (4.3a) I MUX SUB F

where truu = delay in subtraction"

Agtrin T, = t-rt uu INV ADD. Tr*u = delay in f nverter,' and T de-laf in where ADD

addit-i"on " 65

Therefore equ. (4 " 3a) becomes

D(2) Dg +T +T +T +T (4.3b) = MUX INV ADD F For 16-15-13-11 modul.i system, and using TTL components

(ranre 6.3 (a) ) , Dg = 225 ns (from 4.Lc) and

D (2) 225 +4+3+7+(Tn,=35) 274 ns (4"3c)

* l-t 35 ns for DM751'7, a (gZ B) PROM LF = IEO] l

4"4

Thj-s section proposes a new form of representat-ion of floating polnt numbert it is represented by an integer multiplied by a suitable base of exponent depending on the moduli of the residue system. An advantage of this form is that floating arithmetic can be performed within the integer residue arithmetic environment. without the need for any redundant modulus. The lmplementation is therefore economical-.

4 .4 .1 T'heoretical concs!

If R is the highest absolute value of mantissa of a computing system, and ß is a posj-tive integer such that (ß-t)' < R < ß", then any number A within the range from 0 to R can be represented by

A {[Alß] ]ßI + {a- ([Alß] ) ß]ßo

cLz ßl + cLt ßo (4.4\

Where (12 and G, are the co-efficj.ent-s of ßl a,nd ß0 r.e &2 Ialg] and cLt (A--{[Alß] ]ß)" 66

The range of the co-efficients is from 0 to (ß-1). SimilarIy R can be represented by

R'- rz ß + rr (4.5)

Case ( i) : For ß2 = R, fz = ß and r 0

2 Case (ii) : For (ß-1)2 < R < ß the max|mrrm and ml_n].mum values of R that can satisfy the al¡ol'e condition of ß can be denoted bY o"o* ttd Rrror respectively and expressecL as

*"o" = (ß-1)ß + (ß-1) (4.6) t-.e. r 2 : (ß-1) (4.6a) r r = (ß-1) (4.6b)

R"r* (ß-1)2 + 1 - (ß-2)ß + 2 ..... (4.7) l_.e r 2 = (g-2) (4.7a) r lz (4.7b)

4 .4.2 ¡l-o_e!:L¡O point representat j-on of a number

A number X can be represented in floating point form bv x = Aßt (4. g) Vthere A j-s the mantissa, and lies within the range from 0 t'o R. ß is tire base of the exponent which must satisfy the conditions stateci previously, and n is the exponent.

4.4.3 .¡'loating P_o_i4! Arithmetic with zerq-exponent

4.4.3a Fl-oatinc¡ point additi-qn'subtract.ion : with zero -e>(ponent

x Aßo A & ß + CL (say) (4.0¡ = 1

V = Bßo = B = b2 ß + It, ( say) (4.r0¡ 67 Therefore

7 Fl (Xty) (ez 1 br) ß + (a, + 6r)

7 c Þ + c (4.11) 2 I Where

c (ct 1 (4.11a) 2 2 br) c (a" + br) (4.l_1b)

4.4.3a (i) Floatinq point normalisat-ron (def i-ni-t-i on )

A number is said to be normalised i-f overflow occurs when the nurnber is multiplied by the base of the exponeni.

4.4.3a(ii) Normalisaiion r.q f!.g_?_!r¡q poi4t _è,idi!¿g2l subtraction (zero-exponen.t)

The process of normalisatj-on in floating point addition,/subtraction has been shown with the flow chart in

Fig 4.6. The exponent generated durj.ng normalisation may be termed as 'generated exponent' and denoted by g. In case of addition nonzero value of g is 1.

4.4.3b Floatinq point mul.tiplication (zer_o exponen!)

7 - Fl (X.V) (4. L2) From (¿. g) and (4. fO)

z (a (a + (o, b2)ß 2 b)s' + 2 bl)ß

+ (a b I

2 A ß + A g + Aß + A (4.13) 4 3 2 68

W <--c ß

0oes Yes w ove rf I o,¡v ?

K <- W +c.l

0oes

K flve rftow ?

Yes

No {Ê T

r <-[rc,-[ßlz])/n] T <- [tc,+þ t2Jrlt]l

P +-c, + T

Z: Kßf¡ I z P ß

* These are the steps END for rounding.

Fig.4.6 Process of normotisotion in ftooting Point res¡due ocldclition /subtroction c 69

Where A=& b 4 , 2

A CL bt 2 (4.13a) A=a" b z 2

A a. br

Again Z can be written as

z (4,* + D + D) g2 +c ß + c (4.13b) 2 I

Where D _ [A3 lß] D = ¡a, lßl 2 (4.l-3c) c 2 DBI + D, ß] 2 =[a lJ IA,

2 c l-\ I t

Finally z cg ß' i cz ß + cr (4 . 14)

Where ca (Au + Dl + D2)

c2 (4.14a)

cl ß

4.4.3b(r) Normali sation in floating Lo j-nt multiplicalion (zero-exponent)

Figure 4.7 shows the flow chart of normalisation for floating point multipJication- The generated exponent, 9, in case of multiplication, ranges from 0 to 2.

4 .4.3c Fl-oati- p--ar-n! divi s ion ( zero-exponent )

z = Fr(xlY) = ale A (1lB) (4.15 ) rle = Kß-x (say)

Where K is the mantissa (wj-thin the range from 0 to R) , and x is the exponent. The val-ues of x (except for B = 0 or l-) 1ie between 2 and 3. The conversj.on of f ls to its equiv- alen't f loating point number can be done by a look-up tal¡le. 70

W <-c ß

¡r These o re the ste ps oes Yes ove rf low for rounLJing. ?

P <- W+ c

oes ov erf Iow ? S cz + Yes 2 ï <- P.ß

K +-[(cr- lß12)l/nj K <-[(cz.fß/2]¡7ßl oes T ove rftow ) u+- +c No 7=U U<-T+c

Do es Yes U ove rtow ?

0 z Uß T a-[(cr-lß12]l/ßl T <--[(cr*[ ßl2lllßl

E ND U (- P*T

Fig.l,.7 Process of normolizotion in flooting point residue rnultipticcrtion. 1L Isee Appendix-2 for the eval-uation of tls.] Therefore 7 = A' Kß x \nl^ K)ß-Y ^ ".... (4.f0) (a . K) can be evaluated by floating point multiplication. That is FI (a K) - vß4 (=.y) (4 .17)

Therefore Z = Yß a g-x = vßq-* -- Vßff (4.18)

Where m = q-x

4.4.4 Floatinq point Arithmetic w-ith non-,zero .exponent + Let X -Aß ^ and \/ - B3o where ¿ and t are the exponents of X and y respectivelY.

Also X and !/ can be written as

x- (ar\ + o"r) g A (4.1e) t- (b2g + br)ß t (4.19a)

V{ithout loss of generality it can be assumed that /5>Í.

4.4 .4a Alqorílhms for alisnment anQ floatinq poin.L additi-s¡n/subt-rÈction (non-zero exponent) Let k - ^-L Case (i) : if lç = 0, then Lst step : compute D = Fl (etn¡ = cgg (say) 72

2nd step Compute p = +9. ^ lz = cßPl.

END

Case (ii) : If k - L, then *l-st step : Compute D = [tr,, + ¡telzlrle] (rr b, is negatÍve, acld | -ßlzl;

othenvise [ +ø | Z] )

*2nd step : Compute D' = &n + D; I The aligned mantissa takes the form of (0.ß + ¡-).]

3rd step : compute T - Fl (AlD') = cgg (say)

4th step : Compute p = ,s+t; lZ = CßP ].

END

Case (fii) : If k = 2, then

*lst step : compute D + Ltglz]] l àl = [tO,L-t '-J-'I Et b., is negative, add [-glz]t LI o'uherwise [+glZ]. The aliçrned mantissa rakes the forrn of (0.ß + ",]. 2nd. stcp compute T - Fl (AtD) = cgg (say) 3rd step Computep=^+grU=CßP].

END

* (these are the steps for making the aligned mantj-ssa a

roundecl f 1gur. e. )

Case (iv) : If k >- 3, then Z = Aß ^ 73 4.4.4b Floatinq poing multiplication alqorithms- (-4çp_ zefo e4pp-!S]]! ) L+t z Fl (x. v) (a. s) ß

g 1st step : Compute D Fl (A'B) = cß ( say) 2nd step : Compute p t+L+g t lZ = cßp l.

END

4. 4 . 4c Floating point -d-fyåq--i.a.n alqorithms ( no n - z e r o çëpp_qç¡-ï=)

z p1 (xlV)

g l-st step : Compute I) = Pr (aln) = cß ( saY)

2nd step : compute p = ,s+g-t ; lZ = cgP l.

END

4.4.5 How to tirìQ the co-efficients of a mantisea

The co-efficients of a mantissa A (in residue form) can be obtained by following steps: 1st step : comnute 4, = (residue integer [å] division)

2nd step : ComPute &, = A CL (residue 2 subtraction)

4-4 6 Errqr in the Arogore-è flqatinq point arithmetic operations.

Errors in floati-ng Point addition,/subtraction, and' multiplication are introduced during rcunding process (fig 4 -6 an.i Fig 4.7) in normalisation- Tn floating point division error may origj-nate from (i) error in approximation of 1 (j f,Loating point number of fr and r) error 1n floating Point multiplication " 14

4.4-6a Error j-n floatins pA-1.4._t_ ed.gitf-A-A,/ sub tr:actlort

The maximum relative error Itax (e) in f loating addition is

Max (e) Islz] (4.20) R (appentl.ix-4 (e) )

4.4.6b Elqçr in f loatinq Lq¡¡1_t_ multip.liçation

The maxj-mum relative error in float-ing point multip- "l.lcatj-on, when ß-ì-_s odd, is girzen by (..1 2(lßlz)¡' +g[slzl tt'2r) l-'-''Jooo*iU("o)l -----r--R \'r

(appendix-4 (26) )

!{hen ß is eIe_n, the maximum relatÍve error is given by (lß 2 2)t' (4.22) U {."¡ R MAX (appendix-4 ; (27))

4.5 Output Translation

The method proposed here requires Chat Ø . *i for at least one of the moduli. @ is the base to which conversion is to be done.) However, there is no restriction whether gcd(w,mil = l or not. The method can be applied for conversion to any base provided abcve condj-tion is satj-sfied.

4 .5 .1 Theoretical Asr>ects

Any Ínteger Io can be expressed in base ilJ as N N_I i fo = ú¿NøJ + c{¡-. 1r.ü + .."".' -l- a,i,N + + cLrt'J + ao N n l an n=o 75 The coefficients or digits arL (n=0,1, N) are given by drr-l = f.r-, Øf' for n = I,2, ....t N

where ro fïl lì-- J -specj-al case a¡ t,l 'N+.1.' gives the number of digits requi:red to represent the maxj.mum range of a computing system.

4.5.2 Conversion Proced.ure

The co-efficient (digits) in the base fil can be found by repeating the following 3 steps N times.

For n=1 2 lst step : Find f¡

2nd, step : Find Inb = dr.,

a 3rd step : Find n-I I n- I I nb

Last step (special) aN F;l

To convert a residue numL¡e¡: to its equi-valent decimal number at least one of the moduli must be greater than or equal to 10" The residue cf that particular modulus will represent the co-efficient (digit) after third step of the procedui'e. Therefore only one residue is required to be extracted. 76 Example:

Let B, 7 and 11 be the moduli of a residue system. The hi-ghest pos.itive and negative numbers that can be handled are (307) r 0 and (308) I o respectì-vely which are three digits figures.

Take for an example a resj-due number (0,5,10) which represents 208 in decimal- system.

Tbe procedure to get decimal digits out of 1-he residue number is

(rne residue representation of 10 is (2,3,10))

Forn=1

First steP : rl = (0,5,10) | (2,3,I0) = (4,6,9) = (20) t0 Second step: ï = (4,6,9)x(2,3,10) = (0 ,4 ,2) = (200) rb t'0 Thi rcl step : & = (0,5,10)-(O,4,2) = (0,1,9) = (B) 0 I t0 For n = 2

: I (4,6,g) (2 LO) (2. ,2 (2^, First step 2 ,3 , ,2) = to (2 (4,6,9) (20\ Second step: I zb ,2 ,2) x(2 ,3 , t})i = ' '10 Third step : & (4,6,9)-(4,6,9) (0,0,c) = (0) I I ' '10 f,ast step for 3rd digit is I (1 (2,2, 2 N-r 2 t^) I ["-

I o The:refore the decimal number is 208 (=a zxro2 +a rxro +a oxl-o )

[nivi-sion in t]re fj-::st step in each it-eration is a gen- e::al residue division. The arrow indicates the digits i.n tlre base lol 77 The arithmetic operatj-ons requi::ed for conversion are multiplication, divj-sion and subt-raction. Therefore arithmetic unit must have t.he provision for subtraction, multiplication and division in the residue numloer system.

4.6 Conclusion

According to the proposed method, multiplicative overflow det-ect-io': in 16-15-13-1.1- moduli system is considerably fast (269 ns). fn conventional fast technique, using PROMs of 40 ns access time, the deJ_ay would be 640 ns (- 4-4"40) . T'he hardware requirement is not insignificant, however, since sanÌe piece of hardware can be sharecl for sign detection and determination of first approxj_mation, the overall cost will not be much. The delay in obtaining the first approximation, according to the proposed technique is 274 ns (eq 4.3c); whereas in conventional fast division technique, the delay would be 2.4.40 = 32O ns.

Floating point arithmetic which was difficult j_n residue system, no\^/ can easily be implemented using proposed method. The prelirninary requirement is the existence of residue int.eger addition. subtraction, multiplicat-ive, division, comparison and multiplicative overfl"L)\lr detector. Provided circuits for those operations and a look-up ta.t¡le for approximate floatlng poj-nt number exist, floating "t å point arithmetic operat-ion can be performed in software (residing permanently in PROMs). Therefore implementation of floating point operatr-on rvill be cost effective. One departure from the convent-ional f.Loa'tlng polnt format (wirere 2 or 10 -is chosen to be the base of the exponent) is the 7B choice of the base of the exponent which depends on the moduli of the residue system and will differ from systen-r to system. The main advantage of. this choice of the base is that addition/subtraction/multiplication among the co-efficients does not produce overflow. Therefore the cost of usi-ng redundant moduli is saved.

Since output translation is a less f;:equently used operation, more time can be allotted for thi-s operation. where there exists all- the basic resi.due j-nteger operat-ions, the proposed method for output translation can be j-mplemented with no extra cost of hardware. Moreover, i-n a situation where base extension cannot be applied, the proposed method is the only cho j-ce. 5. DESIGN OF A REAL TIIUE RESIDUE ARITHMtrTIC COMPUTER

5.1 Introduction

The aim of the deslgn of the Residue Arj_thmetic Com- puter (naC¡ is to verify the algorithms proposed 1n the

Chapter 4, and study the feasibil-ity of residue system in a general purpose computer. The functional blocks of the RAC (r'ig 5.1) are (i) Intel SDK-80, B bit microcomputer (pig 5.2(a)) and (if) Residue Arithmetic unit. The microcomputer acquires and mani-puÌates data, while the RAU does all the basic residue arithmetic operations. The design of the RÀU, floatj-ng point arithmetic and residue to decimal conver.sion are the main topi-cs of discussion in this chapter.

From the consideratj-on of bit efficiency, moduli 16 and 15 (total 8 bits) have been chosen for the test s)zstem. This gives the range of the system frorn 0 to 239 (lvl=16x1-5= 2401 . The positive half starts from 0 to Lt9, and negative half f¡:om I2O to 239 representing . -L20 to -1 respectivelli.

The RAU has been designed on (22.Scm x 17.Bcm) vero-

. board (rtg 5 .2 (b) ) witb wire wrappinE technique (rig 5 " 2 (c) ) Thc.re are altogether fifty TC chips and seventy-six resistors

(ris 5.3 and Table 5.1) .

llhe microcomputer conirnunicates with the RÀU through a prograrnmable peripheral- intel:face (PPI) of the m-icre;cornputer

79 BO (fig 5.4). The A-port of PPI issues operation codes (fanle 5.2) and operands, while B-port receives the results from the RAU. The lower three lines (C0, c1 and C2) of C-port gj.ves the information of the sign of the resul-t (C0), the overflow (C1) and the Exclusive OR of the sign of divisor and dividend (c27, and the higher three lines (C4, C5 and C6) address the latches (table 5.3 and Fig 5.5) assigned to the operands and operation codes. The operation codes and operands are each eight bits long. Of the eight bits of each operands, the most significant 4 bits represent the residue of module L6 (mod-16) and the least significant 4 bits represent the residue of modul-e 15 (mod-15).

The f/0 device specifies operations with alphabetlc symbols (table 5.4) and issues operands to the microcomputer which makes decision on the type of operatlon (decode), enters the operands and operatj_on code to the RAU and then gets the result from t.he RAU. The final result is displayed on the f/O device in both residue and decimal forms with overflow character (if any by '?' ) and sign character ('+' or'-'). In case of compariscn, the character ) or =, or <, representing x is greater than, ot equal to or less than y, is dì. spl ayed.

The programmes requl-red for al1 operations re-síde in

PROMs from locations 400H t'o 49F H and from 800 il to FEFH, of the SDK-80 microcomputer memory.

l,ater sect--ions discuss the RÄU -i-n detail-. B1_

The R AC

i/0 M R ¡ D c Ë r o V c A I o m C p E u t U e r I J- J

Fig.5.1 Functionol blocks of the RAC

Fig. 5.2 (a) The S D K- B0 microcompu te r.

Fig. 5.2 (b) Top v iew of the RAU boqrd

8'+

Fig. 5.2(c) Bock vÍew of the RAU boord LO æ

2 3 t 5 6 L àtch L¿tch Latch Latch Latch Latch I ? a I I 't 0 ll l2 ; 5 PROM PROM PRO M PRO M PR OM PRO M L 7 tr æEsS +5V o I øsü<10 Ë ¡ a...r . i!2 H r3 "r t5 l3 1/. r5 ¡5 t7 t8 f t7 PRO M PRO M PROM PROM PRO M PR OM É. 19 @.-,-.r?-o 5v zt H"f-;izz Ë 23 H 25 H OJ l9 tt 22 l' PR0l.l PR0 tl PRO M PRO M PftO M C 27 r$ o 29 tËi 3l -i. Ël UI @.,-æ 3 2 33 2t 25 26 28 29 30 3l q, 35 C F..Æil 3 6 VultipIexer Muttiplexer Muttiptexer Multiptex er Mutt ¡ptere r Mutt¡pIe¡er MuI t ip texe r l.luitiptexer 37 o o_ 39 32 33 36 37 Jõ E L1 Multiplexer Mul.t ¡plexer Muttipterer FuIt Addcr Muttiplexer Mul,t¡ple xer o 43 til (J L5 39 40 tl r.2 43 1 o æ48 AND ANO ANO Inve rte: Inverter EX 0 R L9 iÑ* 50 C 15 46 t7 1A 49 50 ,o OR OR ANO Inverter Inverter EX. OR o (4 C g)o L O

(V) c, ol LL B6

Table 5.1 The list of components and their type numb er/ spec if icat ion

Functional Description of Type Number/ Loca,tion on the ion äAU BoarJ Quantity Components Specificat

Quad Latch DM 7475 6

Inte 1 Bipol ar 3601 t7 Prom [zg]

4 Bit Full ADDER D[,I 74LS83 (36) 1

Dual 4: L DM 741,53 (30) , (31) , (37), (38) 4 Multipl exe:r

Quad 2-input 9322 (54) , (3s) 2 Multiplexer

B Channel DI,t 74 15 1 (24) (2e), 8 Mul tipl exer (32) , -(33)

Quad 2-input AND DM 74H08 (39), (40),(47) J

Triple 3-input AND DM 74S11 (41) 1

2-input OR DM 7432 (4s) (47), (s0) Quad - 4 Quad 2-input DM 74586 (43) , (44) 2 Exclusive 0R

Hex Inverter DM 74504 (42) , (48), (49) 3

Resistors 1.8 K A (%lI) R1 R76 76

.n" ,... components used, excopt PRONfs, are of National for, Sernicoirductor rart 1 B7

SDK- 80 Mic rocompute r 1 2 Boo rd . +sV 3 4 5 6 7

g 0

1 B7 2 I 1 B3 J l. B6 I 5 E r 15 I L iBz 6 (, r- B5 3 7 () B m Ë81 6 È BL. I 3 1 20 BO 2\ É. 22 5 23 r+- 21 o rn c3 18 5 VI LO c2 t- (\¡ 5 o ì æ cl *o (u I (U i co C r- Cl 7 c E o o oLo 20 (J o F Â- Ècs I 26 (L 27 G) c4 21 gl I I E 0 IJ 2 A7 10 33 A3 3 A5 2 Þ I A2 t- 7 ß A5 () A1 È 12 I A1 0 AO 5 11 lr 42 13 25-Pin-Cannon 4t, Ptug _J 5 tE 7 &tt tr9 {t Fig. 5.1 Interconn¿ctlans between the PPI of nrierocomputer +5V and the edge connectors of the RAU boa rd , Table 5.2 B8

operation Codes and their definition

0peration Codes Definition þ7, 06, 05, 04, 03, þ2, 01, 0o

0 0 0 0 0 1 10 (i) Add

0 0 0 0 0 1 01 (ii ) Subtract

0 0 0 0 1. 0 1 1 (iii) It{ulti p1y

0 1 0 0 0 0 0 0 (iv) Compare (Unsigned)

1 0 0 0 0 0 0 0 (v) Cornpare (Signecl)

0 0 0 0 0 0 0 1 (vi) Get Fjrst Approxinate of Quotie:rt (Integer Division)

0 0 0 0 1 0 0 1 (vii) Get a nunber divided by 2

0 0 0 0 0 1 L L (viii) Get the equivalent mantissa of the reciprocal of divisor (floating point division)

0 0 0 0 0 0 L 0 (ix) Get the exponent of the reciprocal of the divisor

Table 5.3 Addresses of iatches

Address Latches c7, c6, c5, c4, c3, c2, c1, c0

Latch of X 0 1 100000

Latch of !/ 0 1 0 L 0 0 0 0

Latch of Operation Code 0 0 1 t 0 0 0 0 89

16 o ¿ d_ p 3 r15 e l'È 6l r e a h 1l RAU 3 10 Øz t I BOA RD h) c o n tg a ø4 c t15 o 5 c t1o ø6 d e (de þr

.lt -l 0 ct x4 o AO 2 P 18 n' QA '' e Ê0 t7 t 15 X5 5 I r 16 c (t A3 6 10 o ê f l5 h E 3 ô n ?? x7 5 (e) d x 21 2 2 t6 t9 a út 3 F t t5 X1 I X o 5 ! c4 o Ø 4S 2 .z L 9) ito o s -l-¿ c5 4) U 46 o Irg'l C C o lr7 c6 c) 2 16 y4 o o e (ô ul t't5 P 'tf Ys I c u e LU 10 y6 o f h ã 'i7 a ($u n c 16 e )o IJì t15 y1 I 1J o ito y2 Y 3 = (ds Y¡ r-- ttig.5.5 Lotchirrg r¡f op*. ret i c; n e ocie oncl operqnds - 90 Tab1e 5.4 Alphabetic symbols and operations

Alphabet Operat-i-on

A Addition (lnteger) B Subtraction (tnteger) c Multiplication (Integer) D Dj-visj-on (tnteger) E Compar-ison (unsigned, Integer) F Comparison (signed, Integer)

G Addition (Floating Point) H Subtraction (Ploating Point) f Multiplication (r'loating Point) J Division (Floating Point)

5,2 t Subtracti-on and Multi 1 ri n

Addition, subtraction and multiplication are performed slmultaneously by means of six look up tables (fantes 5.5 (a) , 5.5(b), 5.5(c), 5.5(d), 5.5(e) and 5.5(f)) stored in six (256x4) lntel Bipolar PROM (3601), each having a 70 ns access time. T\¡¡o PROMs are assigned to each operatj-on; one is for mod-16 and the other is for ¡nod-15 operatioi:s (fiq

5.6 (a) , 5.6 (b) and 5.6 (c) ) .

The lower 4 address lines (pins 5,6,'7 and 4) are connected to *;he 4 data lj-nes of operand x," while the higher

4 address lines (pins 3,2,1 and 15) are connected to the 4 data lines (corresponding residue) of operand y.

Irne proqram listings have been shown in Appendix-6," AP 0(a).1 9L

Table 5.5 (a)

Look up Table (Addition in lrlocl-16)

Each hexadecimal di git represents rloler 4 adclress bits t

O1234567B9ABCDEF

0 O1234567B9ABCDEF

1, L23456789ABCDEFO

2 234567B9ABCDEFO].

3 34567BgABCDEFO12

4 4 5 67 8 9AB CDE F O L23

5 56789A8C0EF01234

Eactr 6 67B9ABCDEFO12345 hexadecinal digit 7 7 8 9AB cDEF0123456 represents Ihigher 8 8 9 ABC DEF0t234567 4 address bitsr . 9 9 A BCD 8F012345678

A A B CDE F 0123456789

B B C DE F 0 t234s6789A

C C D EFO 1 23456789A8

D D E F01 2 3456789A8C

E E F 012 5 456789A8CD

F F 0 t23 4 56789AtsCDE 92

Table 5.5 (b)

Look up Table (Addition in lvlod-1.5)

Each hexadecimal digit Tepresents I lor'¡er 4 address bitst

01234s6789ABCDEF

0 0123456789ABCDE0

1 t23456789ABCDE01

2 23456789A8CDE012

3 34567B9ABCDEOT23

4 4 5 67B9ABCDEOL234

5 5 6 78948C08012345

Each 6 6 7 89ABCDEOT23456 hexadecimal digit 7 7 I 9ABCDEOT234567 represents rhigher 8 B 9 ABCDEOT2345678 4 address bitsr . 9 9 A BCDEOL23456789

A A B cDE0723456789A

B B c DE0L234s6789AB

C C D E0123456789A8C

D D E 012 3 4 s 6 7 B 9 A B C n

E E 0 123456789ABCDE

F 0 1 234s6789ABCDE0 93 Table 5.5 (c)

Look up Table (Subtraction in Nfod-16) Each hexadecimal rlj-git represents rlorver 4 address bitst

0123456789ABCD8

0 0123456789ABCD8F

1 FO1234567B9ABCDE ) EFO1234567B9ABCD

3 DEF0t23456789ABC

4 CDEFO1234567B9AB

5 BCDEFO1.234567B9A

Each 6 ABCDEFO1234567B9 hexadecinral digit 948CDEF012345678 represents rhigher 8 8 9 A B C D E F O T 2 3 4 5 6 7 4 address bitsr . 9 789ABCDEFO123456

A 6 7 8 9 A B C D E F 012 3 4 5

B 5 678gABCDEFO1234

C 4 56789ABCDEFO123

D 3 456789ABCDEFO12

E 2 34567B9ABCDEFO1

F L 23456789ABCDEFO 94 Table s.5 (d)

Look up Table (Subtraction in Mod-15)

Each hexadecimal digit represents tloler 4 address bitsr

0123456789ABCDEF

0 01 2 3 4 5 6 7 I 9 A B C E DO

1 EO 1 2 3 4 5 6 7 8 I .1{ B C DE

2 DE 0 1 2 3 4 5 6 7 B 9 A B CD

3 CD E 0 T 2 3 4 5 6 7 B 9 A BC

4 BC D E 0 1 2 3 4 5 6 7 B 9 AB

5 AB C D E 0 1 2 3 4 5 6 7 8 9A

Each 6 9A B c D E 0 L 2 3 4 5 6 7 B9 hexadecinal cligit 7 B9 A B C D E 0 1 ) 3 4 q 6 78 repÏesents rhigher B 78 9 A B C D E 0 L 2 3 4 5 67 4 address bits' . 9 67 8 9 A B C D E 0 1 2 3 4 56

A s6 7 8 9 A B C D E 0 1 2 3 45

B 4s 6 7 I 9 A B C D E 0 1 2 34

C 34 5 6 7 I 9 A B C D E 0 1 23

D 23 4 5 6 7 8 9 A B C D E 0 L2

E t2 J 4 5 6 7 8 9 A B C D E 01

F 01 2 3 4 5 o 7 8 I A B C D EO 95 Table 5.5(e)

Look up Table (Multiplication in Mod-16)

Each hexadecinial. digit represents t lower 4 address bits I

O1234567B9ABCDEF'

0 0000000000000000

1 0 123456789ABCDUI.'

2 0 2468ACEO2468ACE

3 0 3 6 9 C F 2 5 B B E T 4 7 A D

4 0 4BCO4BCO4BCO.lBC

5 0 5AF49E38D27CT68

Each 6 0 6C2BE4AO6C28E4A hexadecinal digit 7 0 785C3A18F6D4829 represents rhigher 8 0 808080808080808 4 address bitst . 9 0 9284D6F81A3C587

A 0 44E82C60A4882C6

B 0 B61C72D83E94FA5

C 0 c840c840c840c84

D 0 DA741EBB52FC963

E 0 BCAB642OECAB642

F 0 F8DC8A987654327 96

Tab1e 5. s (f)

Looh up Table (Ì,{ultiplication in lt{od-15)

Each hexadecimal- digit represents rlourer 4 address tlits t

O1234567B9ABCDE

0 00 0 0 0 0 0 0 0 0 0 0 0 0 00

1 2 3 4 5 6 7 B 9 B C D 01 ^ EO

o 2 02 4 6 o A C E 1 5 7 9 B DO

3 03 6 9 C 0 3 6 9 C 0 3 6 9 CO

4 04 B C L 5 9 D 2 6 A E 3 7 BO

5 05 A 0 5 A 0 5 A 0 5 A 0 5 AO

Each 6 06 C 3 9 0 6 C 3 9 0 6 C 3 90 hexadecinal digit 7 07 E 6 D 5 C 4 B 3 A ) 9 1 80 represents rhigher 8 08 1 9 2 A 5 B 4 C 5 D 6 E 70 4 address bitsr. 9 09 3 C 6 0 9 3 C 6 0 9 3 C 60

A OA 5 0 A 5 0 A 5 0 A 5 0 A 50

B OB 7 J E A 6 2 D I 5 L C B 40

C OC 9 6 J 0 C 9 6 3 0 C 9 6 30

D OD B 9 7 5 3 1 E C A B 6 4 20

q E OE D C B A 9 B 7 ó 4 5 2 10

F 00 0 0 0 0 0 0 0 0 0 0 0 0 00 91

'5ðxäðs:ss + 5v rããxë^<ìñ5 +5v

\¡ r/l N (rr \ll h,J PR0t,t (7\ PR OM (B}

a,ct A ts) (ô o Þ Þ '\) C' c) d CJ ¡\ (tr (t) \¡ (1)

l"lod - 16 Mod - 15 Fig.5. 6(sl Circuit for the 16-i5 moduti crddltion.

YXXXX\<

Fig.5.6(b) Circuit for the 16-15 rnodutî subtrqçtion.

5ãõXëts;X :rNããõtssts +5v +5v gl lJt rtl À N t, \¡ fn PR0M (11) PR0M (12)

(¡'ó=Ë ¿að:ß 7 c c (- c ¡- (J!r Cn \¡ c c c o t! G' \ f,. (^, À, o

Mod-16 Mod -t 5

Fig.5.6(c) Circuit for the 16-15 moduli rnuttptieation. 98 5.2 (a) De_ley in Addil-ion, Subtraction and Mul tiplicat j-on

The delay in addition,/subtractl.on/multiplication

1 PROM delay

70 ns (access time of 3601 PROM)

5. 3 Co¡nparison

There are tl.'c types of comparÍsons compari-sons with signed numbers and comparisons with unsigned numbers. Com- parisons with s:Lgned numbers involve either no operation or subtraction; whereas comparisons with unsigned numbers inrzolve either addition or subt::action. Table 5.6 is a truth table showing the comparisons, operations required and decision modes. It is clear from the Table 5.6 that subtraction is requJ-red (in both types of comparisons) it the signs of X and }/ agree; while addition is required (comparison with gned number) if the signs of X ancl / do not agree. 99 Table 5.6

Truth table for decision modes in comparison

Signed Decision Numbers

1 0 0 0 SUB. O 0 x> y

il L 0 C 0 0 1 x

t 0 0 0 ll 1 0 X=V y 1 0 0 l" No 0p x>

1 0 7 0 No 0p x

L 0 L 1 SUB 0 0 x>y

lt 1 0 1 1 0 1. x

il 1 0 1 1 L 0 X=V

tr y 0 1 0 0 0 0 x>

0 1 0 0 0 1 x

0 1 0 0 1 0 X=V

0 1 0 1 ADD 0 0 x> y

0 1 0 1 0 1 x

tt 0 1 0 1 1 0 X=V

il 0 1 1 0 0 0 x

lt 0 1 1 0 0 1 x> v

lt 0 I 1 0 1 0 X=V

0 1 1 L SUB 0 0 x

lt 0 1 L 1 0 1 x> v

It 0 1 l_ 7 1 0 X=V

[t'tote: SUB Subtraction; ADD Addition] 100 Comparisons require the sign of X, !z and the sign of the resurt of addition or subtraction. However, the results of addition, subtraction and multiplicabion are generated sim- ultaneously. Therefore, depending on signs of X ancl y, the result of addition /subtraction is to be selected for sign d.etection.

The sign is detected by a look up table (rabte 5.7) implemented v¡ith a PROM. 'rhere a-re artogetherthree sj-gn detectors; one is for X, one for V and the other one for the result (one of the results of addition, subtracti-on and multiplication) .

Fig 5.7(a) and 5.7(b) show rhe clrcuits used tor sign detection of X and f respectively. The data l-ines of the residue of mod-16 are connected to the lower 4 address lines of the PRoMs and that of mod-l5 to the higher 4 address llnes. The most significant bit of the output indicates the sign (' 1' for negative, '0' for positive) and the least signlfic- ant bit indicates zero/nonzero of the nurnber ('1' for zero- number). Thus SX and ZX give the information sign and zero/ nonzero of X respectJ-ve1y. Similarly so for y.

The appropriate result j-s multipJ exed to the sign detector by two bits (03, dîl of the respective operation code (fig 5.S). However, þT is not connected di.rectly to the selection pin (pin-i-4) of the mult:iplexers (two dual 4z1 multiplexers), since in case of comparison, the result of either addiLion or subtraction is 'fo be se-l.ected" Table 5.8 shov¡s the states of the selection pins and bhe sel-ected inputs. 10L Table 5.7 o Look up table for the sign and zero-nonzero of a num.ber

Each hexaclecinal digit lepresents Ilorver 4 address bitsr

O1234567B9ABCDEF

0 1B 8 I I B B I 8 0 0 0 0 0 00

1 00 B B (t 8 B 8 B B 0 0 0 0 00

2 00 0 B Ò B 8 B B 8 8 0 0 0 00

3 00 0 0 B B B 8 B I 8 I 0 0 00

4 00 0 0 0 8 8 I B B B 8 8 0 00

o 5 00 0 0 0 0 o 8 B B B 8 I B 00

Each 6 00 0 0 0 0 0 8 8 B 8 8 B B BO hexadecimal digit 7 00 0 0 0 0 0 0 B 8 B B 8 8 B8 represents rhigher 8 BO 0 0 0 0 0 0 0 I 8 8 B 8 88 4 address bitsr . 9 88 0 0 0 0 0 0 0 0 B 8 I B 88

A 8B I 0 0 0 0 0 0 0 0 I I 8 88

B 88 8 8 0 0 0 0 0 0 0 0 8 I 88

C 8B 8 8 B 0 0 0 0 0 0 0 0 8 88

D 88 8 B 8 8 0 0 0 0 0 0 0 0 8E

E 8B 8 8 8 8 I 0 0 0 0 0 0 0 08

F i.8 8 B I 8 8 8 0 0 0 0 0 0 00 I02

xãär.äérã +5V +5v (, 5 --1 Or grl (tl -\ N) n PR OM (I g) i\) ro (O FJ

SX zx

of X Fig. 5 .7(o) Circuit for sign detection in the 16-15 residue sYstem'

idt-¡-(^'Nro +5v +5v ¡-{Cnul G'N)(^) 7 n PR OM (15 ) (, ¡. \: (o N sy

Fis. s.7 (b) Circuit f or sig n detection of Y in the 16-15 residue sYstem 103

Table 5. B

The states of the select-ion pi-ns and corresponding selected inputs

States of '03 ' and. '01' (inverted '01) Sel-ected (table 5 Selected Pins Inputs of operation codes "2) 2, L4 ' r03', '01'

0 0 Addition 0 0

0 1 Sukrt ract-i on 0 1

1 0 Mult.iplication 1 0

1 l_ Not used

From the Table 5.8 it is clear that'03' and'01' can be di;ectly connected to the selection pins 2 and 14 respectively. However, since in comparisons the sign of the result of addj.tion (if the signs of X and l/ do not agree) / subtraction (if the signs of X and / agree) is required and the '03' bit of addition, subtraction and comparison codes (rab1e 5.2') 1s same (zero) , only '03' bit is directly conn:- ected,' whereas 'S-i' is gated thqough the Excluslve OR (44, t,2,3) to change conditionally the logic state of '01' to select the result of addition,/subtraction for sign detection during com;:arison.

For addition, subtraction and multiplication 'þ7' and '06' of the operation codes (rabte 5.2) are zeros; therefore the output of the AND gate (39 ,2, L,3) is ' O ' . The 'õ-1 ' passes out through the Exclusive OR (44,L,2,3) without inversion. In case of comparÍson, subtractiotr and dlvision, t-Ìre

'þ-1 'which is t.he input to the Exclusive oRs (44,5,4,6) and

(44 ,I ,2,3) is ' 1 ' . The output f ::c-¡m the Exclusive OR (44 ,5 , 104

4,6) is the::efore the invertecl S/. The actual Exclusive OR of the signs ofX and y (SX,Sy) is the output from the inverter (48, I,2) , since 'SC' = 1 @ Sy o SX = Sy @ SX = S/ @ SX. Therefore the 'SC' is also the Exclusive OR of the signs of di.visor and dividend. In comparisons, the output of the OR gate (45,1,2,3) is '1' . If the signs of the X and / does not agree 'St-' will be ' 1 and the output of the AND gate will be ' 1' v¡hich inverl-s Of ' (=' l-' in comparison) to '0' . Theref ore the states of the selection pins 2 an<1 1,4 are 'O' and '0' respectively and the result of addition will be sel-ected. ITowever, if the s-igns of .{ and / agrees '3?, wil.l be '0' and so the output from the AND. Therefore the output of the Exclusive oR (44,I,2,3) will be 'õT' (='f in comparison) ; the states of the sel-ection pines 2 and L4 are '0' and '1' respectively and the result of subtractlon will. be selected for sign detection.

The outputs from the multiplexers are connected to the sign detector (enou (fa¡¡. 'SZ' gives the sign of the result (addition/subtraction/multiplication) Z and ZZ gives the information of zero/nonzero of the result fUcte 'Lhat the Exclusive OR (44 ,5 ,4 , 6 ) and the inverter (48, L,2) could be omitted by connecting S/ to the pin 10 of the Exclusive OR (44,10,9,8) and the output from it ('SC') to the pin 2 of the AND gate. However, it has not omitted, slnce this circuit is also part of overflow detector (fiq 5.10) v¡here the sign of the subtrahend is to be j.nverted by'01' (='f in subtraction) for subtractive overflow detection]. l_0s

gl .€ ) 1st. Ex-0R 44 a fiJü

51. atl x 6 (t-4]l 6 O SS 19, \. 6t o\ \¡ r_ Tf 09 Or- (Lt-l ()ct 2nd.Ëx-0R/ B CJocça sc (4 t2 c 5) o øB) 3 C) tö o Ðc') UJ 19{ (3s)

t2 (lrl-l +-3rd. Ex-0R 3

<<ØV¡ÞÞ 33utØÞÞ CCccc]c' =<(rL4ÞÞccGc,gË ccccoo ëH€HQå (nòr¡¡'tJr¡\ t¡N(^rtvl4rÀJ âojoJo

rrt or6 ô. {ui oìä €l l\) N ÀJ o 1 ¿, MuttiPte xe r MultiPtexe r MultiPtexer Multiplexer 2 2 2 \t .f, \¡ 'D \(.o {co (¡o) (gr (sa s. ) ßz) ì9 ) lr) l¡J

+5v + 5v 3.\¡øUn Ð (1/, (¡¡ PRO M ) (¡, Lo À) SZ zz

Fig. 5 ,8 Círcuit for sign detection of the result of oddition/subtrnction / muttipticotio¡r in the 1ö*15 - resicJue systerÍì. 106 The finar decision in comparison is done with a lock up table (Table 5.9) formed in rhe pRoM (ZZ¡ (ri_g 5.9) . Altogether 32 locations (locations DoH to DFH and FoH to FFH) are required. The contents of the odd locations give the decision modes of comparison with sigr,ed numbers, whereas the contents of the even locations give the decisj_on modes of comparison with unsigned numbers. The 'þ7, bit of the operation code determines whether the l-ocations read are even or odd. If 'þ7' is 'L', the odd locations are selected; otherwise the even locations.

The output C00 'f indicates X is less than yì

C01 = '1' indicates X is greater than Y ; whi-1e Cþz = tl_' indicates X is equal toV

Table 5.9

Look up table for decision modes in comparison

4 bits of each hexadecimal digit represent tSVt, tSZt, tZZt and tþ7t 01234567 sgABCDEF

The second D 2244iI0022242L00 bit of each hexadecinal digit represents rSXt F 1 1 L 4 L 2.0 0 2 1 4 4 L 2 0 0 1,07

+5v

ø7 5 l2 P zz 6 sz R il sy 0 5

3 M t0 2 50 1 l23l I R r5 +5v

Fig. 5.9 Círcuit for decisíon rnodds in comPorison in 16 -1 5- residu e syste m . 108

5. 3 (a) Delay in Compar j-son

From Fig 5.8 and 5.9,

Delay in comparison = 1 PROM delay for operatlon of addition/subtractlon. + 1 tutultiplexer delay + (¡ Exclusive OR + 1 inverter + 1 AND) delay.

+ 1 PROM delay for sign detection + 1 PROM delay for decision modes. (70+ 2o+3x7+1"0+9+70+70) ns = 270 ns (for the elements used i-n the test facilities) .

5.4 Overflow Detection

Fig 5.10 shows the circuit for overflow detectÍon in addition, subtraction and multiplication. The circuits in the dash-lined box detect additive,/subtractj-ve overflow,' while the rest of the circuit is needed to detect multiplic^ ative overflow.

5.4 (a) Multiplicative Overflow Detection

V'Ihen multiplicative overflow occurs the product may be of incorrect sign or may be outsj-de the range of the I system.

An overflow characterised by j-ncorrect sj gn is detected by the circuit shown in the solid-lined box. The signal 'SC' is the Exclusive oR of the signs of X and / (rig 5. B) . In Fig 5.8, 'þ-f is 'O' for multiplication and addition. Therefore the output 'SS' from the Exclusive OR (44,5,4,6) is really S/ (sign of V) and the output'SC' from the Exclus- 1- 09 ive OR (44,10,9,8) is the Exclusive OR of 'Sy' and 'SX, (the signs of x and V) . Tabre 5.10 is the truth table of overflow characterised by incorrect sign.

Tab1e 5.10

Truth tabl-e of overflow characterised by incorrect sign

Sign of X, SX sign of V, SY sign of Z, SZ Overflow

0 0 0 0

0 0 1 1

0 1 0 1

0 1 0 0

I 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

From the Table 5.10 the overflow 6(þ') is given by ó(þ'' :ï l;".,î' From Fig 5.8 SC = '0,1' e 'SY' @ 'sx, (s.2)

For: multi-plication and additj,on, '[T' is 'o' , rherefore a SC=S/@SX.

The expression (5.1) becomes

6(þ') = SC Ø SZ (5.3). 110 In Fig 5.10, the output from the Exclusive OR (43,I, 2,3) is the Excl-usive OR of 'SC' and 'SZ'. However, a false slgnal of overflow occurs when a negative number j_s multiplied by zero" The zero operands are detected by the inverters (49 ,3 , 4) and (49 ,5 , 6) and AND gate (39 ,6 ,7 , B) . If one of the operands is zero the output from the AND gate (39,6,7,8) will be '0'; so is the output from the 3-input

AND gate (4I,5 ,3, L ,6) ( OT is , 1 , for multiplication) . This means no overflow indication wj-Il be given.

The circuit outside the boxes (fi-g 5.1-0) detects overflow by 'group technique'. The PROMs (18) and (f0¡ form look up tables (fable 5.L2) of group numbers of !¡ and X respec- tlvely (where X and / are the numbers from 0 to +119 and -1 to -L2O) corresponding to the Table 5.11. (fne number of groups is 8, since 27 < 240 < 28 and nt = 16.)

Table 5.11 Table of numbers and their corresponding group number

Numbers Group Number

0 0

1 1

2+3 2

4 3 I -+15 4 16 -+ 31 5 32 6 ->63 64 +L20 7 111 Tab1e 5.12

Look up table of group number of X or V

Each hexadecimal digit represents tlie residue of N{od-16 0123456789A8CDEF

0 04s6677777776654

1 514 s 6 6 7 7 7 7 7 7 7 6 6 5

2 6524s66777777766

3 6 6 s 2 4 5 6 67 7 7 7 7 7 7 6

4 7 6 6 5 34 s 6 67 7 7 7 7 7 7

5 7 7 6 6 s 3 4 s 6 67 7 7 7 7 7

Each 6 7 7766s3456677777 hexadecinal digit 7 7 77766s34s667777 represents the 8 7 777766543s66777 residue of ¡nod-15. 9 7 7777766s4s56677

A 7 77777766s435667

B 7 777777766s43566

C 6 6777777766s4256

D 6 667777777665425

E 5 6 6 6 7 7 7 7 7 7 7 6 6 5 4 L

F 0 4 5 6 677777776654 TI2

+5v + 5v XXXXXXXX +5v \i6r)ljls(^ttú-O {('rr¡¡$, l$rC¡

\¡ (tl L'ì ¡.\¡ølt,l LN a n ul n (^, F. ¡\ (16) õ' (18) ô @ .D co PR 0 M ot PROM JJ I'o .D o f\t o

tf¡ rÆ l") o

é-or^* I 13 F.ADDER (36I g¡ l,ll ìg ul t¡ 'o a¡ ñ ll' Të Fä Ulx N' f\, l.'l ¡., o,

'10 l1 (/.9) (49) (41) (1¡ ) 21 (16t 3

51 12 213 (16) (39) 67 (43 ) t11t 6 1l €¡ I 3 ¡\t I 15 €t u.7l Xrl 6 (41) t ) 12 u7t 3

(46 t (15 )

¡1t 0verf Iow.

ctors Ot the R AU board -

Fig. 5 .1 0 Circuít f or overflow detection ìn the 16-15 res id ue sYSte rn 113 If the sum of the group numbers of X and / is greater than B, overflow must occur, if less than B overflow does not occur, íf equal to 8 overflow may or may not occur, but if overflow occurs, the si-gn will be incorrect.

The group numbers are addecl- with the Full Adder. If the sum exceeds B, the M.S.B. (at Pin 15) will be 'l-' and at least one of other three bits wilt be nonzero. The first two OR gates (46,2,L,3) and (46,5,4,6) detect whether the least signifÍcant three bits is nonzero. rf it is nonzero and the M.S.B. is '1' , the output from the AND gate (4'l ,5, 6,6) will be 'f i.e. overflow has occurred..

In multiplication 'þ2' is '0' . This means that the output from the additive/subtractive overflow detectors (dash-lined box) is '0'. However, 'F' opens the ÀND gate (47,L,2,3). The output from the OR gate (46,13,L2,LI) gives the information of multiplicative overflow ('f indicates overflow) .

5.4 (b) Additive and Subtractive Overflow Detection

After inverting the sign of the subtrahend, the subtractive overflow is same as the adCi-tive overflow detection. The inve¡sion 1s done by the Exclusive OR (44,5,4,6) of Fig 5.8. In subtraction 'þT' is '1'; therefore the output 'SS' = 37. In addj-tion ' pf is 'O'i therefore the output is 'SS' = Sy. An additive overflow is saicl 1-o occur if the sign of the operands are same and the sign of result is incorrect. The Table 5. j.3 is a truth tabl-e of additive,/subtractive overflow decision modes. LI4

Table 5. 13 Truth table of additive/subtractive overflow decision modes

'ss , Sy/Sf Sj-¡rn of X, SX Sign of Z, SZ overflow

0 0 0 0

0 0 1 I

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1" 1 0 1

1 1 1 0

From the truth table the additive overflow d (0) can be expressed as

d (0) ='SS'. SX. SZ +'SS'. SX. SZ (s.4)

This function is to be ANDed with 'þ2' to signify that the overflow is due to addition/subtraction. Therefore the actual expression becomes ,SS,. d (ol = 'þ2' . d (O) = 'þ2' . ('3s '. sT. sz + SX. 9l (5.s)

The implementation of the expression (5.5) needs three inverters, tü¡o 3-input AND gates, one 2-input OR gate and One 2-inputANDgate. Assuming 'SS' exists, the total de1ay, accordlng to the delay characteristics of the components used in the test circuj-t, is One 2-input AND gate delay (g'S ns) + One 3-input AND gate delay (4'75 ns) + One 2-input OR 115 gate delay (tZ ns) 25 ns.

The actual circuit of additive,/subtractj-ve overflow is shown in the dash-lined box of Fig 5.10. The logic expression ú(A) of the circuit is

d (A) = (,þ2, . SX. 'SS') @ (,Q2,. g. SZ) (5.6)

where SC 'ss' @ sx (rig 5.8)

To form ('SS' @ SX) does not need any extra Exclusive OR, since this signal already exists (for multipticative overflow detection). Only requì-rement is to invert to form 'ss' @ sx.

Therefore implementation of expression (5.6) needs One fnverter, tÍro 3-input ÀND gates, and One 2-input Exclus- ive OR. The gate counts are less than that woul-d be required to implement the expression (5.5). Assuming 'SS' exists, the deJ-ay is --- One fnverter delay (g ns) + One 3-input AND gate delay (4'lS ns) + One Exclusive OR delay (l ns) = 15 ns. The delay is less than that would be for the expressi_on (5.5).

However, the expression (5.6) can be reduced to the expression (5.5)

(,þ2'. SX. 'SS') @ ('þ2'. SC. SZ) ,þ2'. [(SX. 'SS') @ (SC. SZ)]

' þ2' . ISX. 'ss' . (sc. sz) + (sx. ,ss'). se. sz]

'þ2' - t tsx + 'SS' ) ' (SX o-*S3l . SZ + SX. 'SS'.

(SX @ 'SS' + SZ) ] 116

'þ2',. Itsx * 'ss' ) (sx. 'SS' + sx. 'ss,) . SZ + SX. 'ss' (y. 'SS' + sx. 'SS' + V) ] ,þ2' . tsx. '33' . sz + sx. ss. Szl.

In addition,/subtraction 'þ2' -i s '0' . therefore the output from the multiplicative overflow detector is '0' . The output from the OR gate (46,13,13,11) gives the information of additive/subtractive overflow ('1' indicates overfl-ow) .

5.4 (c) Delay j-n Multiplicative Overflow Detection

Multiplicative overflow detectj-on needs trn/o processes (i) detecticn of incorrect sign of the result and (ii) detec- tÍon whether the product is outside the range of system (using group technique)

(i) The detection of incorrect sign of the product involves in detection of the sign of the result, 'SZ'.

De1a1r in finding 'SZ' is (from Fig 5.8)

D 2T +37 +T +T +T (5.7) SZ 3 xoR I AND MUX (Ot 2 ,5, one T: is needed to form product term) where t3 = the access tj-me of (256x4) pnotq.

TxoR = the delay in the ¡ixclusive oR' Tt = the deJ-aY in the Inverter' T¿,ut = the delay in 2-input AND gate '

TMux = the delay in 2 : i- multipl-exer -

For the components used in the circuit in Fig 5. B

T: T0nstTXOR=7ns,T I 10ns i tAND- 8.8 ns ïnu" = 20 ns. Therefore TT7

Dr, = L40+2L+10+B'8+20 = 200 ns.

From Fig 5.10 (circuit in the solid-lined Box), the delay 1n detecting incorrect sign, DIS is given by Drr=DsztT3a"o*Txon * To* (5.7a)

where T the delay in 3-input AND gate. 3AND = T the delay in OR gate. OR =

(since delay in forming 'SC' (z T*o*) is less than the delay in detecting 'SZ' , delay in forming 'SC' has been omitted.)

T L4 ns (for the OR-gate used in the circuit 5.10) OR Therefore Dr, = 2oo+7+8. B+l-4 = 230 ns (s.7b) (ii) Delay in overflow detectron by 'grouping technique' D is given by (from Fig 5.10) GT (5.7c) D"t=T3*T¿,oo+ATon+ 2TAND

where Taot = the delay in adding 4 bits. For the adder used in Fig 5.10, TADD = 25 ns. Tirerefore D = 7O+25+4xI4+2x8.8 = L69 ns (5.7d) From (5.7b) and (5.7d), it is seen that the overflow detection by 'group technique' j-s faster than by 'incorrect sJ-gn detectj-on' technique. This is due to the fact that the sign detection is not needed for the formation of group number. The (5.7a) gives the actual expression for delay in multiplicative overfl-ow in the present system. l_ 18 5.4 (d) Delav ilt additive/subtractive overflow detection

Delay in additive/subtractj-ve overflow detection D ADD is given by (from Fig 5.10) D =D +T +27 (5.2e) ADD SZ XOR OR =2OO+7+2x14 = 235 ns (for the components used in Fig s.10)

5.5 Integer Division fnteger division needs a first approximation of the quotient and then proceeds by successive approximations each of which is a number equal to the preceding approxlmation divided by 2. The first approxÍmation is formed from the information of the group number, g(X) of the dividend and the group number , g (V) of the divisor according Lo the Table 5.14. (fne first approximation and the successive approximations are positj-ve numbers. )

Table 5.L4 Table of first approximatj-on of quotient

Condition First Approximation (x) (v) rf g(x) > g(V) 2s s

rf g (x) s (v) Zero

(oivisj-on of zero or by zero j-s aborted.)

Tab1e 5.15 shows the possibl-e values of first apprîox- imations (in power of 2) and their residue forms in mod- l- 6 and mod-15. 119

Tabl-e 5. 15 Possible values of first approximations

First Approximation in First Approximation residue form mod-16 mod-15

7 2 0 B

6 2 0 4

5 2 0 2 4 2 0 1

3 2 8 I 2 2 4 4

1 2 2 2 0 2 1 1

0 0 0

Since the successive approximation is the number equal to the precedi-ng number divided by 2, Table 5. 15 also g j-ves the possible values of successive approximation (except Z7 ) .

For the successive approximations, the number to be divided by 2 is supplied by the X-data bus (ri-g 5.11). How- ever, all eight bits need not be multiplexed. Frcm the T'able 5.15, it is clear that the resiclue in mod-L6 is either zeÊo or equal to the residue in mod-l5. There.'ore only six bits of information 4 bits of the residue in mod-15, 1 bit of zero-nonzero information of the residue in mod-16 and one extra bit signifying 'division by 2' , are required. The requirement of 'division by 2' is commucicated by the 'Ô3' bit which iS connected to the input pin 13 of the multiplexer (34) and to the selection pin 1 of the multi1:lexer (34) and (35). O c\¡ !-t T]Ccc) o= o CJ. ¡rì ct ocr rn l.- + ¡- -?uO+ oJ ûz 5 gy0 2 l2 APO APO R 56 E 6 a I¿à XO 3 tr1 v, x 7 xã gy' 5 t1 PI ln AP' R 57 o.- XI b 9? I þ(u À 3 x2 0 AP2 Ìt AP2 R 58 È: = r-9 2 P'o 0 o_tslJ gy2 2 ',n ) 1 L o'i X3 3 I P3 AP3 59 ;¿l? r5 OO 4 €l_l-Øo_ ¡- o. Ln rtt ;o- \' I \' Itl\' -(O x4 r¡, ø3 08. 5 ãE- x5 lfl nl gx0 2 12 AP4 AP1 IJ I 6 3 x ØG) 7 tø-C. gxl 5 lrl 1l AP5 rf, AP5 R53 X6 o J 7 ';o+¡ 5 À : I ¿() 3 Ìt oo.- x7 cD t0 t-- AP6 o AP6 R s4 J I 2 P'o ao ox2 t1 Ð o- lt 1 C) l/l'{- ø3 3 9 AP7 AP7 5 I 2 l5

\' oì att rf) ó lr. 121, l{hen '03' goes high, four bits of the residue (X3,X2, X1,X0) in mod-15, one bit of zero/nonzero informati-on of the residue (X7 ,X6,X5,X4) i-n mod-l-6 and. '03' (- '1') are selected to the output of the multiplexers (Z:t multiplexer). I¡Íhen '03' goes low the group number of X, (gXI,gXI,gX2) and the group number of y (SVj,gVL,gV2) are selected instead. (fne group number of X and / are generated by the PROMs (f0¡ and

( 18 ) respectively of the circuit in Fig 5 . l- 0 . )

The multiplexed outputs are fed to the PROMs (19) and (20¡ which form two l-ook up tables of the first approxi-mation and successive approximations. one *-able (raUte S.16(a)) gives the residue in mod-16 and the other table (raUte 5.16

(b)) gives the residue in mod-15. Lo,cations (00H to 07H) , (10H to 17H), (20H to 27H) , (ZO H to 77 H) alrogerher 64 locations are allotted for first approximations and locations (80 H to 9F) altogether 32 locations are all-otted for successive approximations .

The integer division is an lterative process; and ir can be shown with the flow chart of Fig 5.L2. L22 Table 5.16 (a)

Look up table for first approximation and successive approximation in mod-16

0t23456789ABCDEF

0 0 0000000

1 0 L 0 00000

2 0 2 1 00000

3 0 4 2 10000 Z E R O 4 0 8 4 2L000

5 0 0 I 42100

6 0 0 0 84210

7 0 0 0 08421

I 0 I 0 0000000000000

9 0 0 1 0200000000000 A

B c Z E R O D

F L23 Tabl-e 5;16 (b)

Look up table for first. approximation and successive approximation in mod-15

0 L23456789ABCDEF

0 00000000 I 01000000

2 02100000

3 042L0000 Z E R O 4 0842L000

5 01842100

6 021842L0

7 04218421 I 0810200040000000

9 0010200040000000 A

B c Z E R O D

F L24

IN (X,Y ) l<-0; j+0; <-0

Input first approxima- F. iion: I

No Is Ycs f =o ? T<_Y Does Yes No overftow ? Is Is No th e sign the s ign of re the r e sutt + the t+tsut t 7 7 q q Q.ê 0- q<- Yes q, <- q, Ftag overf low.

Does No END T ove rftow 2

Yes Y¿s ls No T X ? Is Yes he sign of the No resutt + ? x (--- x-T X <- X +T

Q¡*r* Q¡ + F, i <--- i+1 + /z;i+-i+t

Fig. 5 .12 Process ol integer division in the l6-15 residue system. 125 Iterative processes continue such that the iterative values of X continue to decrease. Therefore T (in Fig 5.12) is added or subtracted from the iteratj-ve values of X depending on the sign of the result (Exclusive OR of the signs of X and }/ i.e. SX O Sy). From Table 5.I7, it is obvious that T is added if the sign of the result is negatj-ve; otherwise T j-s subtracted. (The first approximations and the successive approximatioi:s are positive.)

Table 5.L7

Tab1e to decide whether T is to be ' added or subtracted

Sign of the result SY SX Sign of T Operation SX @ sy

0 0 0 0 Subtraction

0 1 0 1 Addition

1 0 1 1 Addition

1 1 1 0 Subtracti-on

(The sign of T follows SY. )

The quotient generated is in positJ-ve form. Therefore it is ccnverted to negative forr.t (subtracting frorn zero), if the sign of the result is negati-ve.

The division of M/2 (fZO in this case) by 1 presents a problem. M/2 is a negative number and there is no 'counterpart' posj-tive M/2. The sign of the result of above division is positive; whereas quotient (M/2) is negative. L26

However,this problem can be solved by software. When the positive approximations are added successively, the last addition will show overflow wÌ:,en M/2 is divÍded by 11. There- fore when sign of the result is posj-tive and overflow occurs, then overflow signal is to be flagged. If the sign of the result is negative and overflow occurs, the quotient is M/2. (ffre software listings have been shown in Appendix-6; Ap6(a).)

5.5(a) Delay i-n findinq approximations

Delay in finding the first approximation, DFA is given by (ris 5.11)

DFA = Delay in finding the group number of X and V + I multiplexers delay (fig 5.11)

+ 1 PROM delay (rig 5.11)

= 1 PROM delay (rig 5.l_0) + 1 multiplexer delay + 1 PROM delay.

For the components used for the test circuit, DFA = 70 ns + I7 ns + 70 ns = L57 ns (5.8)

Delay in findrng a successive approxlmation Oro is given by (from Fig 5.11) ' DSA = 2 OR gate delay + 1 multiplexer ,1e1ay + 1 PRCM delay. = 2xI4+L7+10 = 115 ns (for the components used in the circuit).

5.6 Tloatinq Poiht Arithmetic

In this case the base of the exponent is chosen to be I' 12 S = @t¡2¡'' = (L20)'2 = 11. A number X j-s expressed as I27

X A. 1ln (s. g)

where A is the mantissa and n is the exponent, the range of which is from 0 to +119 and from -1 to -I20.

In floating point operations each mantissa is separateci into two terms such that A = az.Lt + o.y (5.9a)

0"2 and a1 êF€ the co-efficients of l-power and O-power of 11 respectively and the range is from 0 to 10. The steps to find the co-efficients are

(i) o.z (Integer Division)

(ii) d.¡ A a.2.IL

During normalisation a co-efficient oí is needed to be rounded. The steps that are requj-red for rounding are oí-, t 5 (i) Find T t 11 l (rr a negative (-5) is added; otherwise +5) í- I is (ii) rounded a. a +T Find the 1

Floating point arithmetj-c is done by sottware (appendix-6 (b) ) which resides in the PROMs of SDK-80 microcomputer.

5.6 (a) Floating Poip!. Addition

The floating point addition can be described with the flow chart of Fig 5.13 (a) , 5.13 (b) and 5. 13 (c) . L28

IN( XJ }

X = A.11nt n2 Y = 8.11 Yes 5 ño A:0 nl e0

No Yes n2e0

Coeff (A):) ql ,O2 Coeff (B) br bz Te-(nt-nz)

No T Yes

Negative ?

oiÈb1 ¡ o2+ b2 S(qt) --- 5(bl); Sloz)S S(bz)

Atignmeiìt of Mantissa.

Addit¡on of Mantis:¿=.

NormaIisation. E

Erponent & Sign Ot The Resu I t

END

Fig. 5.13(a) I Ftow chart of Floating Point Addit ion f n the l6-lS resídue system r29

Is Yes T >t ? Yes Is ls T 1 T 2 ? ? Yes T(2) <- O2 + 2 T(2) <- O2 T(r) <- o1 + þ1 T(l)ê01

ls s(bz) 1' Normalisatíon 7= + bt+ Yes Sign detect ion I of the mant i s sa * bz- 0 bt <- of the re sul t n * bz<-0 END

No Is s(b1)='r' 2

br+ bz+ br <- bz+ bze- 0 bz <-0

* Process of rounding .

Fig. 5 .13 (b, Proce s s of atignment and ftoating point addition in the l6- l5 residue system . 130

T + T(2).1.|

Does No Yes T ove rftow 7 T+ T+Til)

Do es Yes T ov c rft ? Yes Is No t+t T(t ) 2 T<- Tê. lry,] t

T+-T(2)+T Expt X) <-Exp(X)+1

Mnt(Z | + T Exp(Z¡+- ExP(X)

Find the sign of

Mnt (Z )

EIiD

Fi9. 5.13(c) Process of normati sat ion in floating Point add it io n in the l6-15 residu e system. 131 5.6(b) Floatinq Point Subtraction

After the subtraction of the mantissa of subtrahend from zero, the floating point j-s same as floating point addition. The flow chart of Fig 5.I4 shows the floating point subtraction.

5.6 (c) Floatlnq Point Multiplication

The theory behind the flóating point multiplicarion has been given in sections 4.4. 3 (b) and 4.4.4 (b) . The floating point multipl-icatj-on in 16-15 moduli system can be describe

To find the exponent of the result, Exp(Z) is a bit complicated process. The Exp(Z) can be written as

Exp(Z) = Exp(X) + Exp(Y) + g

where g is the 'generated exponent' (section 4.4.4 and

Fis 5. 1-5 (b) )

Vthen Exp(X) and Exp(/) are positive, the overflow in E*p (X) + Pxp (!/) j-ndicates that nxp (Z) is outside the range. (g is always positive.). When Exp(X) and Exp(l¡) are negacive, Exp(X) + Exp(/) may overflow, however, Exp(Z) may or may not remain wi-thin +.he range due to the addition of g.

In later case it has beenobservedthat when Exp(Z) 1s really within the range, and if Exp(X) + Exp(y) overflows, addition g makes a second overflow such that Exp(Z) comes within the range. t32

IN (XY) n1 X = A.11 n2 l= 8.1 1

B O- B

Ftooting oddition

E ND

Fig.5.1t, Flow chort of ftooting point subtroction in the 16- 1 5 residue system. 133

rN(xy) ¡= A-ilnl; Y= 8.tfl2

Coeff(Al+a1ra2 Coef f (B) :+ br, bz

T(3)<_a2.b2 ) T(2lea2.bl

T(l) <- at - b2 ; T(0, <- al. bt

t {P.| ] 7 TU,t<-T(2)-T-tl ; T(3)eT(3)+T t-[Hl ; T(5) eTfii- T.lr ¡ T(3)<- T(3)+ T T(2) <- T(r.) +T(5) t T(t) <- T(ol- T ¡ - [.,I!E] ; T(2t + T(2) +T .

Norrnatisation

Fi nd Exp (Z )

Find sig n of Mnt (Z

ENt)

Fig.5.15(o) Ftow chort of flooting poínt muttipticqtion in the 16-15 res¡cue system. 134

T<- T(3)'11

DocS No Yes T ove r ftow a, ls , T(5)+T+l(3) T(2) + 2

Does No T(5) ove rf tow T(4'+ 2 ? Nc T(4'<- 2 T(6)<- T( 5). r I il

oes t(z)+T(31+T(4) T (6, overflow 7

No T(4) <- T(6) + T(l) g<- 2

0oes T(4 ) ov erf tow 7 Is Yes No T(1) '+' ? Mnt(Z) ê- T(¿)

g<-0 (1)+5 fi T(4)<- T(4 ) <-

Mnt(Z¡ <-T(5) +T(4) Exp (Z) <-Exp(X) + Exp(y).rg

g<- 1

END

Fig. 5.15(b) Ftow chart of normatisation in the l6-15 moduti f loating point muttiptícat ion . 135

Therefore if overflow occurs twice or overflow does not occur at all, Exp(Z) is v¡ithin the range, otherwise EXP(Z) is outside the range. The flow chart of Fig 5.15(c) explains how to determine whether Exp(Z) overflows or not.

5.5(d) Floatinq Point Division

The flow chart of Fig 5.16(a) shows the floating point divj-sion. (The division of zero or by zero is aborted.)

The mantissa and exponent are two "t * Eenerated with look up tables,' one is for the mantissa and the "t å other for the exponent "t * The mantissa of the result, Mnt (7) is found by floating point murtiplication of the mantlssa of x and that "t å. This multiplication results in a 'generated exponent' , g.

The calculation of the exponent of floating point division is complicated too.

Exp(Z) = [exp(X) nxp(V)] + [g + EE] (rts s.1o(a))

Exp(X)-Exp(}/) may overflow,- however, Exp(Z) may remain within the range due to addition of the te.rm I g+EE ] which may be positive or negative and does not overflow. (g =0or1or2 andEE=0or-1or-2 or-3)

Applying the same reasonings as given in determining the overfl-ow conclition of Exp(Z) in case of floating multiplicatlon, the overflow condition of Exp(Z) in case of floating point division can be shown with the flow chart of Fig 5.16 (b) . 136

T <- Exp(X) * Exp(Y)

D oes Yes No T overf tow 2

T <-T + g T+- T + g

Does Does Yes No T overflow T ove rf tow 7 ?

No No ove rf low Ye s

0verflow. 0verf Iow

Fíg.5.15(c) Overftow detectíon of Exp(Z) in flooting point muttipticotion in the 16-15 resid u e syste m t37

rN(xy) n1 X = 4.11

EM + Mnt ( B ) EE E x p

Mnt( Z) e- Ft.Pt. (A'EM )

Erp(Zl+Erp(X)- Exp(Y)+ 9+ EE

END

Fig.5.16(ol Flow chort of f lootíng point division in the 16-15 residue syste m .

T+Exp(X)-Exp{Y) T0)+ 9 + EE

No Does Yes T ov¿ rf I

T- T + T(l) T ê- T + T(l)

0oe s Does Yas No T ov e rftow T ove rflow 7 ? No Yes No ove rf [ow 0v e rf[ ow No ove rf low

Fis. 5 .16 (b) Overf low detect io n of Exp(Zl tn ftooting point division ín the 16-15 res¡d ue syste m . 138 5.6(e) GgnerjrFion of mantissa and exponent "f + For a base of exponent ß, a general method to calculate the mantissa and exponent of f n"r been described in Appendix -2 Applying that method the values of mantissa and. exponent 1 for the base of exponent (eleven) have been of B ß=11 tabul- ated in decimal and residue forms shown in Appendix-3.

The mantissa and exponent in resj-due are of *IJ form stored in PROMs (fiq 5.17). The value B is fed to the PROM (I7), (21) and (231 through the X-data bus and PROM (17) and (Zt¡ output the mantissa in mod-16 and mod-15 respectively, while the PROM (23) gives the value of exponent.

exponent may be of any value of and 3 The "t * -L, -2 The residue form of those values are shown in Table 5.19

Table 5.19 Resj-due the exponent of 1 form of B

Exponent Exponent in Residue form in In Hex In Binary Decirnal form mod-16 noJ-15 nod- 16 ¡nod- 15

-1 F E 1111 1i 10

-2 E D 1110 1 101

-J D c 1 101 1100

From Table 5.1-9 it is seen that two most significant bits of the residues (in binary) in mod-16 and mod-l5 are same and constant (11). Therefore in the formation of a look up table, storÍng of these two bits is not necessary; only two least 139 significant bits of each residue are required. Therefore only one (256x4) PRotl is needed.

Two M.S.Bs are generated at the output cj-rcuit of the

RAU and this will be discussed in section \.7 .

The PROM(23) (rig 5.17) forms the look up rable for the generation of the two least significant bits of each residue of the exponent "t å The Tables 5.20(a), 5.20(b) and 5.20(c) show the contents of the pRoMs (L7) , (2I) and (23) respectively.

5.6(f) Delav in findinq the mantissa and exponent of 1 B

Delay 1 PROM delay (from FÍg 5.17)

70 ns (for PRoM, rntel 3601). 140

xt, 5 P ïw0 L. S. BITS OF x5 6 EEO R EXP. IN MoD-15 , X6 7 ll EEI x7 1 0 M 3 x0 10 EE1 xt IW0 L. S. BITS OF 2 ( zgl EXP. IN MOD - 16 X2 I EE5 X3 15 EEO EEI

EE4 6

xt' 5 EE 7 G) o X5 6 EMO EMO 64 a P12 o X6 7 a Rt EMI EMI 6 x7 t, rn o 0 3 I ) x0 10 EM2 Ìt E 56 M o o X1 2 2 l21l s E R 67 3 x2 EM3 o ) x3 5

=.tn U¡ o 5 x4 P o X5 6 12 EM4 EM4 R R X6 7 o 1t EM5 EM5 x7 I (o (p M XO 3 I 10 ËM6 ! E R41 o X1 2 $71 E x2 1 9 EM7 E R ¿5 X3 t5 +5v

point Fig. 5.17 C ircu it f or o pProx imote f tooting number of 1/ B in the 16 -1 5 residue system - 141

Table 5.20(a)

Look up table for the mantissa of I in nod-16 B

Each hex digit represents the residue of B in nod-16. (Lower 4 address bits)

01234s6789ABCDE

0 0 7 4 2 A E 13 s D F 2 6 E C 9

1 3Bt229E135DF26DB

2 AE D A 019 E 13 5 C E 15 C

3 c8A81F098135CE15

4 5 B 7 6 E 5 6 0 8 D t 3 5 4 2F

5 Each t 4 B 6 3 8 4 B F I D 0 5 4 C E hex digit represents 6 E 04 A 5 F 4 3 9 E 7 D 0 3 4C the residue ofVin 7 C EO 4 A 4 D 1 1 6 D 7 c 0 24 nod-15. (Higher 8 4 CE 0 4 9 5 A F F 3 c 6 c 02 4 address bits). 9 2 4C D 0 3 9 2 7 D c 1 B 6 c0 A F 24 c D 0 3 I 1 5 c 8 D A 5C

B B F2 4 B D F 5 8 0 A B 2 A 95

C 4 BF 2 4 B D F 2 7 0 1 F B 68

D 6 4B F 2 4 B D F 2 7 F 0 6 32

E D 53 A E 1 3 B D F 2 7 E E F5

F 0 74 2 A E 1 j 5 D F 2 6 E c9 L42

Table s .20 (b)

Look up table for the mantissa of'^ I in mod-15 B

Each hex digit represents the residue of B in nod-16. (Lorver 4 address bits) 0123456789A8CD8

0 0110 8 C 0 2 4 D 0 3 7 0 E E

1 8BAE07C024D057ED

2 c 313C87C024C826D

3 D AEA9BD7CO24CE26

4 6 c9AO44D6802431D

5 2 Each 5C87937C68E23CE hex digit represents 6 E 15B73525858E23C the residue 7 C E 15 B 612 0 2 5 A E 13 ofVin ^ nod- 15 . (Higher 8 5 C E 15 A 5 D O D E 9 4 A E 1 4 address 9 1 3CD74A4ADAC84AE bits) . A D tscD1.4938C6873A

B 9 Dl5BD()492880563

c 2 9 D 13 B D 0 312 4 6 51s

D 329D158D03815CEC

E 7 2L8C028D0380154

F 0 1ic8c024Ð0370EE L43

Table 5.20(c)

Look up table for two least significant bits of each (in nod-15 and nod-16) residue "f *

Each hex digit represents the residue of B in nod-16. (Lower 4 address bits) 01234567894BCDEF

0 0444444444444444

1 4844444444444444

2 4494444444444444

3 4449444444444444

4 4444994444444444

5 4444499444444444 Each hex digit 6 44444499 4 4444444 represents the residue 7 44 4 44449 9 4444444 of/in nod-15. I 44 4 44444 9 9444444 (Higher 4 address 9 44 4 44444 4 9944444 bits) . A 44 4 44444 4 4994444

B 44 4 44444 4 4499444

C 44 4 44444 4 4444944

D 44 4 44444 4 4444494

E 44 4 44444 4 4 4 4 4 4 4 E

F 04 4 44444 4 4444444 r44 5.6.1 Error in Floatinq Point Addition Subtraction and Multiplication glr) For ß = 11, t = 5. The highest positive number for the system under consideration is +119; and the highest negative number is -I2O.

5.6.1(a) Error in Floatinq Point Addition/ Subtracti-on

From (4.20) , the maximum relative error for positive numbers is

| ø¡z) 5 (i) Max (¿) .o42 R 119 The maximum relatj-ve error for negative numbers is

(¿) 5 (ii) Max L20 .o42

5.6.1.(b) Error in Floatinq Point Multiplication

From (4.2t¡ , the maximum relative error for positive n rs is l, ß/, j + 3' ß/t U (zo) max R

2 25+3 5 65 119 119 .55

The maximum relative error for neqatlve numbers i-s

U (¿ol 65 .54 L20 max

5 .7 Outr¡ut Circu t of the RAU

The outputs from the RAU are the results of addition, subtractl-on, multiptication, comparison, approximate quotient for integer division, and mantissa and exponent of $ tot floating division. 145 The sign of the result of addition, subtraction and multiplication, overflow signal and the Exclusive OR of the sJ-gn of the divisor and divj-dend are connected to the pins 4, 5 and 6 respectively of the RAU board (fig 5.8 and 5.10) and are eventually" connected to the C-port (lower part

C0, Cl, C2) of the SDK-80 microcomputer (fi-g 5.4) .

The result cf addition, subtraction, multiplication, comparison, approxi-mate quotient, and the mantissa and exponent 1 are multiplexed by three least significant bits "f Ë of the operation codes (fig 5.18).

The pin 2 of the multiplexers (24) , (25) , (28) and (2e) are connected to +5V through 1.8 K reslstors to generate two most significant bits for each residue of exponent of _l B

The pin 4 of the multiplexers (24) , (25) , (26) ,' (27) and (28) are connected to ground which generates zeros in the 5 MSB positj-ons of the comparison sj-gnals; only the three least significant bits give the information of comparr_scn.

Table 5.2L shows the states of the selectj-on pins and the selected inputs. L46

87 I 3 |,1V7 MU I c ct- +5V R60 2 t- +5v 61 2 7 3 AP6 1¡ BS -o ]. 5 13 5 m EM7 2 m EM6 2 x x m AD7 3 m (2t,' AD6 3 n (25) SU7 I 7 su6 l. 9 l0 I I 1011 ôz Qz þt $r B5 t 6o Ø 2 o 3 .S É. MU5 C MU4 C 2 r EE4 2 EE5 { -t C) 3 AP4 3 B4 co AP5 1' T' 5 1 m -> EM5 2 x EM4 2 mx m AD4 3 rft 3 AD5 7 ( 26 ) n Q7) su5 SU4 t, 9 1011 I 1t É. Øz ø 2 þt þ 1 B3 ûo ø 0 40 3 tr U3 1 c= c o +5Y 2 r +5v R6 2 J. -{ AP3 3 AP2 3 L T5 39 cþ2 }5 tJ) m- Ern2 2 m EM3 2 x )< É. AD3 13 m AD2 3 m (2 v ( 29) o su3 Ð 8' su2 1 F I 1011 I 10 11 (-) Øz Øz LU Qt Øt B1 z Øo z øo I O (J MUI MUO EEl 2 =c c= - EEO 2 t- 3 -{ { lrl APl APO 3 BO (9 1 't c0l cÉ0 I 7 EMI 2 P5rrl ->m ê EMO 2 ADl 3 x LTJ ¡ì ADO -! 3 m 14 n (32 (33) sul ) su0 I v 9 I r0 1l Øz Øz þt öt Øo Øo

Fig.5.18 Output circuit of the RAU L47 Table 5.2L

States of selection pins and selected inputs

States of selection pins Selected inputs þ2, þ1, 00 (¡ bits of op. code)

1 1 0 Addition

1 0 1 Subtraction

0 1 1 Multiplication

0 0 1 Approximate quotient

0 0 0 Compar j-son 1 1 1 1 Ma-ntissa of B 1 0 1 0 Exponent of B

The outputs from the multiplexers are connected to the pins 37 through 44 of edge connectors of the RAU board. The outputs are eventually connected to the B-port of SDK-80 microcomputer (fiq 5.4). The most significant 4 bits of the outputs represent the residue in mod-16 and the least significant 4 bits represent the residue in rnod-l5. In case of comparison, three least significant bits gives the information of the results of comparison.

5.8 Conversion of Residue Numbers to Decimal Numbers

The 1-6-15 residue system is a three-digit

Fig 5.19 shows the residue operations required to find one decimal diqit (residue form) of a positive number X. 1.48

IN (X}

i<-0

Yes Is 3 2

Extract O No t-f lrom T . T+

END b <- T. 10

c<- x-b

Extract O from b

x<- T i<- i+t

Fig . 5 .19 Process of re sid u e to decimq t conversion in the 16-15 res¡due system . L49 Since 16 and 15 are greater than 10, the residue of the decimal digit in mod-16 is equal to the residue in mod-15 and each residue is equal to the decimal digit. Only one residue is needed to be extracted. Decimal numbers are represented in signed magnitude form. Thcrefore if X is negative, it is converted to its positive form by residue subtraction from zero or by residue multiplication with -1.

Successive digits are found by taking T (ln Fig 5.19) as a new value of X.

The first decimal digit is extracted by residue multiplication with 01 and second digit by residue multip- Ii-cation with 10. The residue addition of first and second extracted digits gives two consecutive decimal digits which are stored at an 8-bit-byte location. The third digit (t'l.S.O) is extracted by resj-due multiplication with 0l- and is stored at another location. The contents of those locations, in proper order, give the decimal number of X.

(The program listings have been given in Appendix -6 (c).)

5.9. How the Residue Arithmetic Compute r Works

The RAU together with the SDK-80 microcomputer forms a real time residue arithmetic computer (nac). The communic- ation between the RAC and outside is thus made through a teletype or VDU using SDK-80 programmes.

With the starting command - G Boo) ( ù= carriage return), the RAC undergoes the phases of operations shown by the flow chart of Fig. 5.20. 150

START G 80oJ

tnitialise the p0RTs

Give signat to get the type of operation required.

Wait

Is operation avaitable ,)

Yes Give signat to get ope rand s .

Wa it

Are operands aveitabte 7 Yes Pe rf orm opera t ion and disptay the resutt .

Fig . 5. 20 Prog rom e loops of the R AC l_5 1

5.10 Ho$¡ to operate the RAC

with the teletype or vDU connected to sDK-80 microcomputer and power on to the SDK-80 and RAU, the SDK-80 is 'reset'. Then the procedures that are followed are

(i) Key in c Boo ) The computer responds with

0 = (for type of operation).

(ii) Key in any alphabet A through ,f for the requj-red operati-on. (see Table 5.4) If the operation is an integer operation the computer responds with M = (for fi-rst operand X).

(iii ) Key in two hex numbers (resj-due number) .

The computer responds with

M = (for second operand Y).

( iv) Key j-n two hex numbers (residue number) .

Thc computer displays Che result, first in residue form and second in decimal form with overflow (if anlr) and sign characters. (tt¡e overf low character j-s '?' . ) If operat j-on is a comparison one, the display is ) or = or < to indicate X is greater than or équal to or less than Y. The computer signals 0 = (for further operatlon). L52 If operation is a floating point one, the computer responds with

M = (for the mantissa of X).

(iiÍ ) Key in two hex numbers (residue number).

The conìputer responds with

E = (for the exponent of X).

(iv) Key in two hex numbers (residue number).

The computer responds with

M (for the mantissa of V).

(v) Key in two hex numbers.

The computer responds with

E (for the exponent of V).

(vi) Key in two hex numbers.

The computer displays the result as

M E (in residue form)

M (in decimal f orm).

(fne dash-line indicates the digits. The results are displavs with proper sign and overflow (i-r any) characters.)

Then the computer responds with 0 = (for further operation). 153 5.11 Conclusi-ons

The delay in multiplicative overflow detection, according to the proposed technique, is 230 ns; whereas deIay, accordj-ng to conventj-onal fast technique [-.rsing PROMs of 70 ns access tlme (tntel Bipolar PROM, 3601)] would be 4.2.70 = 560 ns. Therefore multiplicative overflow detection is considerably faster, accordlng to Lhe proposed technique. In determination of the first approximation for residue integer division, the proposed technique introduces a delay of I57 nsi whereas conventional fast division technique would need 2.2.70 = 28O ns. Therefore determination of first approximation is also faster in the proposed technique.

Until now there has been no residue computer which performs floating point operations. The introduction of floating point arithmetic in 16-15 moduli system reveals the fact that floating point arithmetic operations are feasible in residue system, and that these operations are cost- effective. The maximum relative errors that are introduced in addition and multiplJ-cation [section 5.6.1] are not really significant and quite normal for a single precision macl-^1ne. Therefore the proposed algoriuhms on floating point arithmetic have great impli-caticn in the residue system.

In the residue-to-decimal conversion process, where the conversion radix is 10 and the moduli are 16 and 15, neither A(X) methodnor base extensj-on is applicable. There- fore the proposed technique is the only choice. Moreover there is no reason for not using the proposed technique where 154 all- the integer arithmetic operations exist and more time can be allotted for output translation. CHAPTER VI tttrr 6 CONCLUSIONS

This concluding chapter presents a comparative study between residue and binary number systems, and puts forward a suggestion on further study on residue number systems.

The bases of compari-son are the speed, cost and power consumption in performing the basic operations multiplic- cation, addition,/subtraction including overflow detection.

For the purpose of comparison'16-15 and 16-15-13-11 moduli systems have been considered and the fastest available J-ogic components of both TTL and ECL technology have been chosen when dealing with implementations.

The range of 16-15 moduli system (16x1-5=24O) is lëss than 28, however, greater than 27; likewise the range

16-15-13-l-1 system (16x15x13x11 = 34320) 1s less than 2" , however, greater than 2rs . In this cornparison, however, a 16-15 residue system has been compared wj-th an B-bit binary system,: while the 16-15-13-11 residue system has been compared with a 16-bit binary system.

In multiplj-catj-on the 16-15-l-3-11- system needs four (256x4) pRO¡ls. The component requirement for multiplicative overflow detection (on the basis of Fig 4.L) has been shown in Table 6. 1 (a) .

155 1s6 In the circuit of Fig 4.L the generation of the group number of the operand X, g(X) has been shown. The generation of g (V) needs similar sorts of components as required for S (X). Again for the generation of g (X) the information of NZ(X) is required; and ñZ(X) can be formed with one B input NAND gate and one inverter with two levels of gate delay. Similar type of components are needed for NZ(V). The sign detectioi: (by mixed radix conversion) of the product (SZ) needs five (256x4) pRottts. The circuit configuration is sj-mi1ar to the circuit used for SX, except that (256x8) pnOU is replaced by a (256x4) Pnot"l.

The requirement when using ECL components is same as that of TTL components, however, since (256x8), (512x8) and (5L2x4) ECL PROMs are not available, those PROMs are to be built from available (256x4) enot"ts. The (256x8) is a PRoM with 8-bit address lines and 8-bit data li-nes. The function of that PROM can be confì-gured by using two (256x4) enOus. One is used for four J-east signi-ficant data outputs, and other one is used for four most significant data outputs. The (512x8) pno¡,t can be built from two (256x8) pRotqs (con- structed by above method). The B-bit address lj-nes are used to select any L:cation of (256x8) pnotq and the remaining address bit selects one of two (256x8) pRO¡,1s. The outputs from (256x8) pROt"ts are wire-ORed. Therefore four (256x4) PROMs are needed to construct an equivalent (512x8) enot'ts. construction of a (5I2x4) pno¡¿ needs tu/o (256x4) pRot"ts. The

8-bit address lines select any locatj-on of (256x4) PRO¡,1, whilst the remaining address line selects one of two (256x4) PROMs. The outputs of (256x4) pROt'ls are wire-ORed. Table L57 6. 1 (b) shows ECL required f or multipS-ication and its overflow detection in 16-15-13-L1 moduli system. In place of a 4-bit ful1 adder (nCf,) which Ís not available, a 4-bit Arithmetic Logic Unit (ef,U) has been chosen. Since an 8 input ECL NAND is not avaj-Iabl-e, 2 j-nput AND gates are to be used for the generation of Nl(X) and liJZ (y) . A total of fourteen 2-input AND gates are needed and the arrangement has three level-s of gate delay using currently available components.

In a 16-15 moduli system, multiplication needs two (256x4) pRotvls. The components f or multiplicative overf low detectj-on can be calculated f rom the cj-rcuits in Fig 5.l-0 anC 5.8. The circuit in Fig 5.8 has been used for sign SZ of the result Z. Tabte 6.2(a) shows the TTL components required for multi-plication and its overflow detection in a 16-15 moduli system.

The ECL components needed are the same as the TTL components, however, since ECL 3-input AND gates are not available, 2-input AND gates are to be used. Therefore for three 3-input AND gates, six 2-input AND gates are substituted. Tabl-e 6.2(b) shows the ECL components needed for nultiplication and overflow detectj-on j-n a L6-15 moduli system.

Of the TTL family Schottky TTL ISZ ] is rhe fasresr; therefore Schottky TTL components have been chosen. Of the ECL family [Se ], EcL-Iff is the fastest,- however, ECL-IIT has a limited number of functions, therefore ECL-10000 has been chosen for the ECL components. Tables 6.9(.) and 6.3(b) show the characteristics regarding delay, cost and power 158 consumption of TTL and ECL components respectively.

Table 6.1(a)

TTL cornponents required for nultiplication and its overflorv detection in a L6-15-15-1L modu1i system. (Yaking into account of generation of g(V) and SZ.)

Number Trpe Number of Function Conponent of Required No. Packages Conponents

Multiplication (256x4) PROM 82527 4 4

Overflow (256x4) PROM 82527 t4 t4 Detection: (According to (25óx8) PROM 825714 2 2 the circuit in Fig 4.1, (512x4) PROM 82S130 4 4 requirement for generation of (512x8) PROM 82S115 4 4 S(n and sign detection of 7 i.e. SZ.) 4-bit Ful1 Adder sN74S283 6 6

2:1 Multiplexer SN74S15B 2 2

2-input Exclusive OR SN74S86 2 1

2-input Al,{D SN74SO8 2 1

2-input 0R SN74S32 3 1

I B-input ttANl SN74S3O 2 a Inverter for SN74SO4 2 I generaticn of NZ (x) , (y) . l ^/z

42 (Total package count) 159

Table 6. 1(b)

ECL conponents required for multiplication and its overflow detection in a 16-15-13-11 noduli system.

Nunber Function Coml.ronent Type of Nunber of Reqrrired No. Packages Conponents

Multiplication (256^4) PROM 1014 9 4 4

Overflow (2s6xa) PRoM 10149 42 42 Detection: (According to 4-bit Arithneti" the circuit Logic Unit MC l_ 0181 6 6 in Fig 4.1, the require- 2:1 Multiplexer MC t0L73 2 2 nent for generation 2-input Exclusive OR lvfc 10L07 2 1 of g(V) and the sign 2-input AND MC 10104 16 3 detection (Hex AND) of Z i. e. SZ) 2-input 0R IvlC 10103 3 1

59 (Total package count) 160 Table 6,2(a)

TTL conponents required for nultiplication and its overflow detection in a 16-15 noduli systen.

Nunber Number of Conponent Type Functinn of Packages Requíred No. Components of gates

Muttiplication (2s6x4) PROM 82527 2 2 (rig s.6 (c) )

Overflow (2s6x4) PROM 82527 3 3 Detection: (According to 4-bit Ful1 Adder sN74S285 1 1 the circuits in Fig 5.8 2-input Exclusive 0R SN74S86 5 2 and 5. 10.) 2-input 0R SN74S32 5 2

2-input AND SNT4SOB 4 1

Inverter SN74S04 3 L 4:1 Multiplexer sN74S153 4 4 S-input AND SN74S1 1 3 1

(Tota1 package count) 161 Table 6.2(b)

ECL conponents required for multiplication and its overflow detection in a 16-15 moduli systen.

Nunber Number of Component Type Function of Packages Required No. Components of gates l4uttiplication (256x ) PROM 10149 2 2

Overflow (2s6xa) PROM 1 0149 3 3 Detection: (According to 4-bit ALU MC 10181 1 1 the circuits in Fig 5.8 2-input Exclusive MC 10107 5 2 and 5.10.) OR

2-input 0R MC 10103 5 2

2-input AIttrD MC 10104 10 2 (Hex AND)

Inverter IvlC 10195 3 L 4:1 Multiplexer MC 10174 4 4

L7 (Total package count) Table 6. 3 (a) Characteristics of TTL components required for Residue Multiplication and its overflow detection

Type Components Delay Power Manufacturers Number in ns Price*

(i) (256x4) pno¡,t 82527 40 .6 mwr/Bit 25.25 sisnetics [Ze ] il (ii ) (256x8) Pnou I2S 11_4 60 165 pwlnit 19.00 (iii) (51,2x4) pnou B25 1 30 BO .3 mw/eit 6.50 I (iv) (5i-2x8) pnou 825115 60 165 lw/sit 17.00 ll (v) 4-Bit Adder sN74s283 7 510 mw 2.O0 Texas Instrument ISZ ] il il (vi ) 3-input AND SN74S1 1 4.75 31 mw/gate .57

il il (vii ) Hex Inverter SN74SO4 3 19 mw/gate 1 .08 il ll (viii ) 2-input AND SN7 4S O8 4.75 32 mw/gate .57 (rx) 2-input OR SN7 4S3 2 4 35 mw/gate .57 il il (x) Quad Exclusive CR SN74S86 7 250 mw .85 ll il il il (xi ) 2:1 Multiplexer sN74s158 4 195 mlf 2.39 il It (xii ) 8-input NAND sN74s30 3 L9 mw/gate .86

I il (xiii ) 4: l- Multi-plexer sN74S15 3 6 225 m14r 2.39

79 -03 P Oì * All prices are i-n Australian dollars and sma1l quantity price. N Table 6. 3 (b) Characterj-stics of ECL components required for Residue Multiplication and its overflow detection

Type DeIay Function Power Pri-ce* Manufacturers Number in ns

(i) (256x4 ) pnopt LOL49 20 .66 mwr/Bit 22.32 Signetics [ 78] (ii) 4-bir ALU MC 10181 7 600 mw 35.24 Motorola Ise]

il (iii- ) Hex fnverter MC 10195 2 100 mwlekg 1.31

(iv) Hex 2-input AND MC 10104 2.7 140 mw/vkg .51

(v) 2:1 Multiplexer MC 1017 3 2.5 270 mw 7.10

(vi ) Triple Exclusive OR MC 1_01_07 2.5 110 mw,/ekg .55

(vii ) Quad 2-input OR MC 1010 3 2 100 mwlPkg .5 i-

(viii) Dual 4zI Multiplexer MC 10174 3.5 305 mw 7.06 ll

7 4.56

* A1I prices are in Australian dollars and small quantiti price. P (,Or L64

Presently the MPY/HJ family [56] of binary multi- p1j-ers are the fastest. Table 6.4(a) shows comparj-sons of a 16 x 16 multiplier Vs. 16-15-13-11 moduli multiplier and an B x B bits multiplier Vs. 16-15 moduli multiplier using TTL technology. The delay in overflow detection in a 16-15-13-11 moduli multiplj-cation has been calculated using the expression (4.1)r whilst the expression (5.7) and (5.7a) have been used for calculation of delay in overflow detection in the 16-15 moduli multiplication. Table 6.4(b) shows similar comparisons using ECL components.

From the examination of Table 6.¿ (.) and 6.4 (b) it is clear that residue multlplj-cation is much faster and more cost-effective, specially using ECL technology. How- ever, when residue multiplication is associated with overflow detection, the system gets slower and more costly. However, since the same piece of hardware, used for overflow detection, can be used for sign d.etection and generation of first approxi-mation for resj-due j-nteger dÍvision, the cost is not as much of a concerning factor as would at first appear. Table 6.4 (a) Comparison of (i) 16x16 binary multiplier Vs 16-15-13-11 mod muttiplier including its overflow detection (ii) 8x8 binary multiplier Vs 16-15 mod multj-plier including its overflow detection (TTL components. )

Component Number of Delay Function in Price* Power Required Components NS

(1) 16 x 16 bits multiplier rRw/ 1 100 , MPY-16 HJ $265.00 3w (2) Residue Multiplication See Table See Table 40 W (16-15-13-1l-mod) 6. 1 (a) 6. 1 (a) $101.00 2.56

(3) Overflow Detection See Table See Tab1e 269 18w 6. 1 (a) 6. 1 (a) $s06.21

(4) 8 x 8 bits multj-plie:: TRw/ MPY-8 HJ-]- 1 45 $120 1W (5) Residue Multiplication See Table See Table 40 $ 5o.so 1.78 vü (16-15 mod) 6 "2 (a) 6.2 (a) (6) Overflow Detectlon See Table See Table L29 6.2 (a) 6. 2 (a) $ e3.00 4W

* P All prices are in Australian dollars. Ol C¡ Table 6.4 (b) Com,oari-son of (i) 16x16 binary multiplier Vs 16-L5-13-11 mod multipl-ication including overflot¡ detection (ii) 8xB binary multiplication Vs 16-15 mod multiplication including overflow detection. (Using ECL.)

Delay Functi-on Component Number of in Price* Power Required Components NS

(1) Motorola @ 30.84ea L6 x 16 binary /L0L83 32 100 25.6 w multiplication (2x4 multiplier) 986.88

(2) Residue Multiplication See Table See Tab1e 20 89.28 2.7 W (16-1s-13-11) 6. 1 (b) 6. 1 (b) (3) Overflow Detection See Tab1e See Table L26 1165.39 33.16 W 6. 1- (b) 6. 1 (b)

(4) SxSbinary Motcrrola /I0Ig3 8 50 @ 30.84ea 6.4 w Multiplier 246.72 (5) Residue Multiplication See Table See Table 20 44.64 1. 35 V{ ( 16-15-mod) 6 .2 (b) 6 .2 (b) (6) See Table Table Overflow Detec;ion See 65 320.00 5vù 6.2 (b) 6 .2 (b)

* All prices are in Australian dollars. H Or Oì t67

A comparison of a 4-bit binary adder (fff, and ECL) with a 4-bit residue PROM adder has been shown in Table 6.5.

From the table it is apparent that in TTL technology a 4-bit binary adder is six times faster than a 4-bit residue PROM adder. Therefore in addition of equivalent 24 (=6x4) bits or higher, residue PROM wil1 be faster, provided the access time of the PRoMs used is 40 ns. However, since the cost of one (256x4) pnO¡¿ (TTL) is twelve times higher than that of a 4-bit binary adder (TTL), the residue adder is not cost effective.

In ECL technology, a 4-bit binary adder is three times faster than a -bj-t residue PROM adder. with ECL technology addition of equi-valent L2 (=3x4) ¡its or higher will be faster in a residue system assuming that the access time of the PROMs used is 20 ns. However, sign detection in 3 moduli (each module having 4 bits) system wilt need 40 ns [ = (3-I)'2O; see Appendix-S]; whereas the sign detection in a 12 bì-t binary system will need 3x7 = 2L ns.

From what has been discussed above, it is clear that present day technology still is not favourable towards the impiementation of resÍdue j-n general purpose computers. The binary system wil-1 maintain its p::edomillance. However, in special applications wÌrere there is no use of sion and overflow detection, residue multiplication will be the first choice and may also be a contender 1n very fast and large systems where the carry free property is of great importance in minimising the chip connections and inter chip delays. 168 Table 6.5

Comparison of a 4 bit binary adder (TTL and ECL) Vs. a 4 bit residue PR0M adder (TTL and ECL).

Nunber of Delay in Function Technology Conponents Price Conponents ns. in $'.4.

A4bit TTL sN74S283 1 7 2.00 binary adder ECL MC 10181 1 7 35.20

TTL 82527 1 40 25.25 A4bit (256x4) PROM residue PROM ECL 10149 1 20 22.32 adder (2s6x4) PROM

As it has been discussed earli-er that the residue floating point arithmetic can be performed in software provided all the residue integer arithmetic operations are avaj-1- ab1e. In fast processors the residue floating point operations will be fast. However, in comparison with binary floatj-ng point arithmetic the residue floating point ¿rrith- metic is sl-ower since (f ) the mantissa.s of the residue floating point operands are to be broken down into two co-efficients and (ii) in normalisation process the mul.tiplicative overflow information is required. However, at least it has been shown that the floating point arithmetic can be performed in the residue system, and the operations are cost-effective, since the only requirements are PROMS for generation of floating point numbers of the reciprocal of the mantissa of divisor and memories to store the prog- ramme required for resj-due floating point operations. 169 It is clear from the discussion above that the multiplicative overflow detection is the speed limiting factor in the residue system. Also sign detection is a problem. Thêrefore more efficient algorithms for sign detection and overflow detection should be investigated and also the possibility of using logic gates or FPLAs (instead of PROMs) should be looked at. In the near future VLSI circuit may open the way to j-mplementation of overflow detectors with combinational logic and a dj-fferent comparison between the systems may then result.

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58. "MECL Data Book", Motorola, Phoenix, Arj-zona, I976. 59. Jacobsohn, D.H. "A Combinatoric Division Algorithm for fixed Integer Divisors", IEEE Trans. on Computers, pp. 608-61-0. 60. Dean, K.J. "Binary Division Using a Data-Dependent fterative Array", Electronj-cs Letters , 721|-]:, JuIy 1968, Vol-4, No.14, pp.2B3-284. 61. Guild, H.H. "Some Cellular Logic Arrays for Non- Restoring Binary Division", The Radj-o and EIec- tronic Englneer, Vo1-39, No.6, June I970. pp. 345-348. 62. Dean, K.J. "Ce1lular Arrays for Bj-nary Division", Proc. IEE. Vol-11-7, No.5, May I970, pp.9I7-920. 63- Majetha, J.C. "Nonrestoríng Division Using a CeIl-- ular Array" , Electro¡rics Letters, 14th May 1970, Vol-5, No. 1û, pp. 303-304. 64. Cappa, M. and Hamachar, V.C. "An Augmented Iterat- ive Array for High-Speed Binary Division", IEEE Trans. on Computers, VoI-C-22, No.2, Feb. 7973. 65. V'Iadel-, L.B. "Negative Base Number Systems", IRE Trans. on Conìputers (corresp. ) Vol--EC-6, June 7957, p.I23. 66. "Conversion from Conventional Binary to Negative- base Number Representation", IRE Trans. on Electronic Computer, (Corresp. ) Vol-EC-10, Dec. 1961 , p.779 . t75 67. Zohar, S. "Negative Radix Conversioh", IEEE Trans. on Computers, Vol--C-19, March 1,970, pp .222-226. 68. Krishnamurthy, E.V. "Complementary Two-way Algor- ithm for negative radix conversionsrr, IEEE Trans. on Computers, Vo1-C-20, No.5, May I97I, pp.543-550. 69. Yen, C.K. "A note on Base -2 Arithiretic Logic", IEEE Trans. on Computcrs, YoI-C-24, L975, pp. 325-329. 70. Sankar, P.V., Chakrabarti, S. and Krlshnamurthy, E-V "Arithmetic Algorithms in a negative base", IEEE Trans. on Computers, YoI-C.22, Feb. 7973, pp. 1 2o-L25 . 7r. "Deterministic Division Algorithm in a negative base", fEEE Trans. on Computers, YoI-C-22, Feb. I973, pp.I25-L28. 72. Rao, G.S., Rao, M.N. and Krishnamurthy, E.V. "Logical Design of a negative binary adder-sub- tracLor", Int. J. Electronics, Vo1-36, No.4, L974, pp.537-542. 73. "A variable shift negabinary multiplier", Int. J. Electronics, I974, Vo1-36, No.6, pp.749-757. 74. Agrawal, D.P. "Arithmetic algorithms in a negative base", IEEE Trans. onComputers, Yo!-C-24, October L975, pp. 998-1000. 't5. "Negabinary Division and Square-rooting", Digital Process, Vol-l-,Autumn L975, pp.267-274. 76. "Negabinary Carry-look-ahead adder and fast multipli€r", Electronics Letters, Vol-10, July L975, pp.312-31-3. 77. Waser, S. "State-of-the-Art in High Speed Arithmetic fntegrated Circuits", Computer Design, Juì-y L978, pp.67-75. 78. "Signetics Bipolar and MOS Memory Data lulanual", L97i. 811 East Arques Avenue, Sunny Vale, California 94086. 79. "fnte1 Data Catalog", L975, fntel Corporation, 3065, Bower Ave., Santa Clara, CA - 95051-- 80. "Memory Data Book", L976, National Semiconductor Corp., 290O Semiconductor Drive, Santa CIara, cA - 95051. 81. "TTL Data Book", I976, National Semiconductor, 29OO Semiconductor Drive, Santa Clara, California 9505 1 . A1

APPENDIX - 1

Some Important Proofs

Apl (a) :

If 2rt U, overflow will occur- (ii) if gl(l+glVl < U, overflow will not occur' (iii) if g(xl+glvl = u, overflow may or may not occur. If it occurs, the sign of the product will be incorrect.

Proof:

The multiplication of the lor,/est numbers j-n two groups is gj-ven by (from Table 4.1) 7=W 2-^*glXl . v{ .2-^+glVl (1)

Z=W 2 2-Z^+glXl+slVl ( 1a)

Let glxl+TlV) = A+L- If A is an even number, W=(M it and ¿ = U/2+L. Therefore (1a) can be written as z(q/!+ll+¡tr+l z = M . 2 = M/2 .""(2a) Y!l¿ W= There- If A is an odd number, 2t and ¿ = lq+1)/2. fore (1a) can be written as -2{(q+1 | I 2}+U+1 z (M/2) . 2 = M/2 (2b)

The equarions (2a) and (2b) indicate that overflow positive numbers in two groups, will occur when the lowest r greater than is multiplied- The sum of which is U, |L A2 equations (2a) and (2b) do not indicate overflow if one of the lowest numbers is negati-ve, sínce M/2 is within the range of negative half. However, in most cases @þ or ëÌt is not an integer number. Therefore error will be introduced in determination of W, and this error will make 7 ín equdtions (2a) and (2b) greater than M/2, and therefore the product of the lowest numbers one of whÍch is negative will overflow" The method of determination of W and construction of group tabre when @þ or ëlt is not an integer number has been discussed in sectj-on 4.2.1) _t

(1a) Let g lxl +g lV I q. If. A is an even number, then can be written as

o ( Z=M 2-2lql2+11+a = |11 2-¿ 3a)

If A is an odd number, (1a) becomes 2{la+l1/2}+a -2 z (M/2) . 2 = M.2 ( 3b) The equatj-ons (3a) and (3b) indicate overflow will not occur.

The multiplicati-on of the highest numbers of two groups glxl and g(/) is given by

( ì z w 2-^+gt,Xl+i -1 2-^*glVl+t l. t ['' Z=w2 z-2^+g(Xl+SlV)+z _ hr . 2-^+glXl+1 -w.2-^+glVl+1 +1 ..... (4)

2 = !i[ 2-2^+slxl+slvl+1 _1 ,'s-9(vl l, W 1 g (xl ì z^ I +1 -w ) A3 =w z-2o*g(Xl+g(V)+t 1 z^-s(xl r.+r-fr.2^-s(vl !v +1 (4a)

Since group 1 contains number L, overflow will never occur on multiplication of number in group 1 with the number in any other groups. Therefore overflow for the groups greater than 1 will be consj-dered;

Let S lKl +S lY I A. The equation ( a) can be written as Z=vtrZ.2-2d+ti+1 1 z^-s(xl 1+1 W ì 1 z^-slvl +1 (4b) UI

The minimum value of Z depends on the minimum value of

1 lV I 1-+ -2^-s(xl -Ïl" .^-9 ( 4c)

The expression ( c) is mj-nimised when SlXl or S(Yl is equal to 2. Let glxl = 2. Therefore slvl = r1-2 (4d)

From the value of M, W can be expressed as n+l ,nl z

If tJ is an even number, then from (4c) and (4e)

-2 1 1 1-+ 2^ 2s-a+2 < I _ 2Ul2+1-2 vü ,nlz 2U/2+l-ti+2 ,n/ z A4 (n+1) 2 /2+1-Z 2ln*1ll/2+1-ln+1l¡+2 L- n/2 n/2 2 2

= L-+-2 l-2n+1 | I 2+3

l2+3 However, for n s 4, 2l-2n+f) t t Therefore the minimum value of ('ic) is a positive number for n > 4.

In other words for n > 4

2 1 vl Z-2o* U* (4f) z mtn

>M 2-2lU/2+11+q+7 orZ m1n =Pt.2 1 (5)

The expression (5) indicates that when the sum of group numbers is equal to {, multiplication of the highest numbers in two groups will produce overflow-

In similar way the expressed (5) can be proved to be valid for odd value of q. Again from (4)

2 -2^+g(Xl+SlVl+Z Z

Therefore for glx)+g(yl : A an<.l evnn value of ti, (frcm (6))

If glxl+glVl = A-!, and A is an even number then from (6)

orZ

Combining (2a) , (2b) and (5), it cêrr b€ written that if slxl+s(Vl > U, overflow must occur.

Combining (3a), (3n¡ and (6b), it can be concluded that if glxl +glyl < U, overflow will not occur-

combining (3a), (3b), (5) and (6a), it can be concluded that

if glXl+$lVl = U, overflow may or may not occur. If overflow occurs, the product will be of incorrect sign.

APl (b)

If d-nt 4n-t, ....., &zt At Afe the mixed radix digits of a number (positive or negative) in the system of moduli ffinr ffin-r t ¡ lfl2 ¡ III ¡ respectively, then the mixed radix dÍgits bnt bn-rt ....t br., br of the 'counterpart' n.mber (negative or positive number) are given by

b. { (mi 1) oi\ for oil 0 (i=n, nrl, k+l ) 1

bn {m. on] and þ 0 for ok nP 0 k p - l0and (p:k-l- , k-2, 2, 1). A6 Proof: The 'counterpart' number is formed by subtraction of the number from zero i.e.

(or, orr-, ok*, ou ok-, o" or)

(or, 4rr- on*, ou ou-, o, o i ,)

Since o" , to 4k-r are zeros, the kth digit is formed by (*r o*.) . This subtracti-on produces a borrow which propagates up to nth digit. Therefore other digits are formed by

bk*, = (^k* t 4k* r -1) { (m¡1 r -1) -a¡a , }

b\*, = (*k*. &k*, -1) { (mt+ z -L) -at*, } a I t b (m a _1) n n n {(mnn -L)-a }.

b 0 forp k-1, k-2, 2, 1. P

Example:

Ifm 2 7, R, 3 and 4 1 a 5 3 ,fr2 = 3 2

O.t = 0, then the MRDs of the 'counterpart' number is given by

6s = (2-1)-1 0

(7-5) 2 b-2 ô- 0. I A7

APPENDIX - 2

AP2z Point va.Iue Floating "t å For B > l- and positive,

L=g'. (1) BB g-2

a2 tB Let + (2) å=ou B where OB and rU are the quotient and remainder of the left hand side division in (2).

Case (i ) rf O ß R then is added to r and then B 7",) B divided by B.

+ r r B r (s) vt + B =Or B

The rounded Qu j-s given bY K where

K=Q + o (3a) B r

l- 2 ( Hence K ß 3b) B

Case (if) If QB ß < R, then

1 ß3 (s) BB ß-3

3 r p Let 3. o + (6) B P B vl is added to rp and then divided bY B t-.e. r+ tt D v^ (6a) =Q + B t B AB

The rounded O is given by H, where P

H o + 0 ( 6b) P t

Hence å-H ß-3 ( 6c) ff H > R, then H is taken to be equal to R

For B 1 *=ß B¡

The point value of negative 1 is negative floating B the form mantissa positive 1 The exponents of of B of both positive and. negatj-ve 1 same. B are Table 5.18: Table of nantissa and exponent of for B = 7 to I20. (11 is the base of exponen Mantissa in Residue Exponent in Numbers Mantissa in Exponent in Decinal Residue Form Residue Form Numbers Mod-15 Mod-16 Decinal Fonn Decimal Forn Mod-15 Mod-16 Mod-15 Mod-16

1 1 1 11 -1 B B E F

2 2 2 61 -2 D 1 D E

3 3 3 40 -2 8 A D E 'Ú 4 4 4 30 -2 0 E D E ztD 5 5 5 24 -2 9 8 D E H 6 6 6 20 -2 5 + D E I (r¡ 7 7 7 L7 -2 2 1 D E I 8 8 15 -2 0 F D E 9 9 9 13 -2 D D D E

10 A A t2 -2 c C D E

11 B B 11 -2 B B D E

T2 C C 111 -3 6 F C D

13 D D 102 -3 72 6 c D

14 E E 95 -3 5 F C D

15 F F 89 -3 E 9 C D

16 1 0 83 -3 8 3 c D c) o r+ Þ \c c o o- Mantissa in Residue Exponent in Decinal Residue Nunbers lvlantissa in Exponent in Forn Residue Fonn Nunbers Mod-15 Mod-16 Decinal Fonn Decinal Form It{od- 15 Mcd- 16 Mod-15 Mod-16

L7 2 1 78 -3 3 E c D

1B 3 2 74 -3 E A C D

19 4 3 70 -3 A 6 c D

20 5 4 67 -3 7 3 c D

2L 6 5 63 -3 3 F C D

22 7 6 61 -3 1 D c D

23 8 7 58 -5 D A C D

24 9 8 55 -3 A 7 c D 25 A 9 53 -3 8 5 c D

26 B A 51 -3 6 3 c D

27 c B 49 -3 4 1 C D

28 D C 48 -3 3 0 c D

29 E D 46 -5 1 E c D

30 0 E 44 -3 E C C D

3T 1 F 43 -3 D B C D

32 2 0 42 -3 C A C D

33 3 1 40 -3 A 8 c D t) o r+ Þ H. ts O o o. I,.{antissa in Residue Exponent in Decinal Residue Nunbers Itfantissa in Exponent in Form Residue Form Numbers I'fod-16 Decinal Forn Decinal Forn t{od-15 lvlo

34 4 2 39 -3 9 7 C D 35 5 3 38 -3 8 6 C D 36 6 4 37 -3 7 5 c D 37 7 5 36 -3 6 4 c D 38 8 6 55 -3 5 3 C D 39 I 7 34 -3 4 2 c D 40 A 8 33 -3 3 1 c D

4t B 9 32 -3 2 0 C D

42 c A 32 -3 2 0 C D

43 D L} 3L -3 1 F c D

44 E C 30 -3 0 E C D

45 0 D 50 -3 0 E c D

46 1 E 29 -3 E L. c D

47 2 F 28 -3 D c C D

48 3 0 2B -3 D C C D

49 4 1 27 -3 C B C D

s0 5 2 27 -3 C B C D a) o al ts o H Þ, Mantissa in Residue Exponent in Decirnal Residue Nunbers l4antissa in Exponent in Form Residue Form Nuinbers Itfod- 15 Mod- 16 Decinal Forn Decinal Forn Mod- 15 Nlod- 16 Mod-15 lvlod-16

51 6 3 26 -3 B A C D

52 7 4 26 -5 B A c D

53 8 5 25 -3 A 9 C D s4 9 6 25 -3 A 9 c D 55 A 7 24 -3 9 8 c D

56 B 8 24 -3 9 B C D

57 c 9 23 -3 8 7 C D

58 D A 23 -3 8 7 C D

59 E B ¿5 -3 8 7 C D

60 0 C 22 -3 7 6 c D

61 1 D 22 -3 7 6 C D

62 2 E 2t -3 6 5 c D 63 J F 27 -3 6 5 c D 64 4 0 2t -3 6 5 c D r 65 J 1 20 -3 5 4 C D

66 6 2 20 -3 5 4 C D

67 7 3 20 -3 5 4 C D 6B 8 4 20 -3 5 4 C D t) o (-l ts F. t\) o Ê, Nfantissa in Residue Exponent in Residue Nt¡mbers Mantissa in Exponent in Decinal Forrn Residue Fonn Mod-16 Decinal Forn Decimal Forn Numbers Mod-15 Mod-15 N,cd-16 l,lod-15 lvlod-16

69 9 5 19 -3 4 ó C D 70 A 6 19 -3 4 3 c D

7l B 7 19 -3 4 3 c D

72 C 8 18 -3 3 2 c D

t5 D 9 18 -3 3 2 c D

74 E A 18 -3 3 2 c D

t5 0 B 18 -3 3 2 C D

76 1 C 1B -3 J 2 c D

77 2 D T7 -3 2 1 c D

7B 3 E t7 -3 2 1 c D 79 4 F t7 -3 2 1 c D

80 5 0 t7 -3 2 1 c D

81 ó 1 16 -3 1 0 C D

82 7 2 76 -3 1 0 C D

83 8 3 16 -3 1 0 C D

84 9 4 16 -3 1 0 c D

B5 A 5 16 -3 1 0 c D

(-) o cl ts. ts (^ o Ê. Mantissa in P.esidue Exponent in Decinal Residue Numbers Mantissa in Exponent in Forn Residue Forn Numbers Mod-15 Mod-16 Decinal Forn Decinal Form Mod-16 Mod-16 l"lod-15 l"lod-16

B6 B 6 15 -3 0 F C D

87 C 7 15 -3 0 F C D

B8 D B 15 -3 0 F c D

B9 E 9 15 -3 0 F c D

90 0 A 15 -3 0 F C D

91 1 B 15 -3 0 F C D

92 2 C 14 -3 E E c D

93 3 D L4 -3 E E c D

94 4 E t4 -3 E E C D 95 5 F L4 -3 E E c D 96 6 0 74 -3 E E c D

97 7 1 T4 -3 E E c D z 98 8 2 t4 -., E E C D

99 9 3 L3 -3 D D c D

100 A 4 15 -3 D D C D

101 B 5 L3 -3 D D c D

cl rl P. Þ è Èo Mantissa in Residue Exponent in Residue Nunbers Mantissa in Exponent in Decinal Fonn Residue Form Mod- Ilod- 16 Form Decinal Forn Nu:nbers 15 Decinal Mod-15 Mod-16 Mod-15 lvlod-16

t02 C 6 T3 -3 D D c D

103 D 7 73 -3 D D c D

104 E 8 L3 -j D D c D

105 0 9 73 -3 D D c D

106 1 A T3 -3 D D c D

L07 2 B 72 -3 c C c D

108 3 C L2 -3 c c c D

109 4 D L2 -3 c C c D

110 5 E l2 -3 C C c D

111 6 F t2 -3 C C c D

Lt2 7 0 l2 -3 C c C D

L73 8 1 L2 -3 C c C D rt4 9 2 72 -3 C c c D 11s A 3 T2 -3 C C c D

LL6 B 4 11 -3 B B c D

777 C 5 11 -3 B B c D

118 D ó 11 -3 B B C D

119 E 7 11 -3 B B C D 720 0 8 -11 -3 4 5 C D ts (/r A16

APPENDIX - 4

AP4: Error Analysis of Floating Point Addition and Multiplication Operations

In case of floating point additj-on/subtraction, and multiplication, the errors are introduced during rounding process in normal-ì.sation. In floating point division error is introduced from two sources (i) error from floating point, vafue of and (ii) the approximation of ]IJ error from floating point multiplj-cation of FI(A.K). However, errors only due to floating addition and multiplication will be evaluated, assuming the exponents of the operands are zero. aP4 (a) : Error in floatinq point additon

The actual value of Z is given bY

z cz ß + cl (from (4.11) ) .

The positive error occurs if

(cz ß + >R or c a ß R "r) 2

and ", ''V4 if ß is odd.

if ß is even.

Under these condi-ti-ons the normalised rounded Z (Fig 4-6) becomes Z. = (cz + 1)ß A17

Therefore positive error ø+ -- Z' z

(1) ß -c I

Case (i) If ß is odd, then

ß-1 v^ 2

or Ê z .þl*t (1a)

Under error condition since cr > vr, and cl is an j-nteger, therefore the minimum value of cl can be given by

(c,). ( 1b) 'm1n = 9-l*'

(c,) j ¿+ in equation (1), Ís maximj-sed, For cr = ¡ mÌn. therefore

(ø+¡ m ax

(2)

Case (ii) If ß is even, then V, = B/z orß = ,.|9^ (3)

Under error condition since cl > vl and ct is an integer, therefore the minimum value of ct, in this case, is gj-ven by (", )*i' v^ (4)

(c.) , e+ in equation (1), is maxlmised,' For c.r = ¡ ml-lr. therefore AlB

(5)

Therefore in both cases, positive maximum error is same.

The relative positive error U(ø+¡ is given by

(¿+) ?+ U crB+c,

The U(ø+¡ is maximj-sed when Ø* = (¿+ )*r* and cz ß + cr R

Therefore the maximum value of U (¿+) is given by

( ø+¡ max fs ( u*)*"* ^l (6) U R R

The negatj-ve error occurs if

(cz 3 + cr) > R or c2 ß R

and c v^ if ß is odd. or

cr < V,' if ß is even.

Under those conditi-ons the normalised Z becomes ., =czß

Therefore the absolute value of negative error is given by

c lu- | lz' -zl

If ß is odd, lu-l negative error, is given by U(e -)max

U ( ¿- )*r* v^ (7) R A19

If ß iq even, lu-l v^ and maximum I u- | is siven by (since lu-l is an integer.)

The maxi-mum relative negative error, when ß is even, is given by

ø-)*.* v^-' (B) U { R

From (6), (7) and (B), it is clear that the maximum error, ¡lax(¿) is given by (6) or (7) , therefore Max(¿) v^ (e) = U(ø+) .* R

AP4 (b) : Error in .f_-I-e-ati_ng. point multip lication

Actua1 value of Z is given by

I - cg 92 + cz ß + cr (from 4.I4) .

(i) If c3 0, Z is reduced to Z where Case = R ZR=c2ß+cr (10)

In this case, maximum errgr is Same aS the maximum errgr in floating point addition.

Case (ii) If ca and cr are nonzero, then positive error will occur if

(cs + or ce { ß "r) ß]>R and c if ß is odd. 2 vl or c wl if ß is even. A20

In this case the normalised rounded Z (Ffg 4.7) becomes

z (cs + 1)ß2

Therefore positive error 8-+ -- Z' Z

= g'-(cr.ß+cr) ( 11) < g2 (L2) or e+ ""'9

Case (iii) If ca j-s nonzero and c, i" zeto, then positive error will occur if

ca ' ß + cz > R or ca ' ß > R

c2> v^ if ß is od.d. and c if is even. 2 ú,1 ß

Under these conditions, the expresslon for positive error can be derived from (11) as ø'+ ß ..... (13) = 92 "r. From (13) and (tZ), it is seen that ø' > ø- Therefore to evaluate maximum positive error, the expression (13) will be used.

Q.+ j-s maxj-mised if cz = ("rLir, .

If ß is odd cz , Vl (under the error conditions given above). Therefore the minimum value of c2 can be written as

(", Li,, vl., (14)

even c2 theref ore ( c in this case If ß is t V^, 2 m 1n is (under error condition) (", ),ni' v4 (rs¡ A2I

Therefore if ß is odd, the maximum positive error is given by (¿'+Lr* = ß2 (cz)*in' ß from (13) s2 l\rl*rJ o rr.-om (ra¡ = lr.ú,^*'] ' IFzrl.'j l, Wù.') f ,:om ( 1a)

Therefore when ß is odd, (¿'*) "* ( ro¡

When ß is even, the maximum positive error is given by

ß from (13)

ß from (fS¡

Wr' [, 'V^) from (3) (12¡

The negative error occurs if

{ (ce ß + cz) or ca . ß ) > R

c if is odd. 2 v^ 3 and c if ß is even. 2 e,,

(ror c and c are nonzero) 3 t

Under these conditions, the normalised rounded Z becomes

z c g2 3 A22

The absolute vafue of negative error I u- | is given by zl c + c, .....(18) lu-l = 17' 2 3

The maximum value of õ r , (", )*"* = ( 3-1) (ro¡ If ß is odd, under the above condition,

cz <

maxi-mum c can be !.'ritten as Therefore the value of 2

c ) (19a) 2 max vr Therefore the maximum absolute value of negative error, when ß is odd, is given by

(ø-) (c" ) ß + (c,) max - max ¡ max v^ ß + (ß-1) from (19a) and (19) . . .V^+1-1] w^. I' Frr].'] [, vI l' + 3. v^ (20) If ß is even , under the above condition

c 2 w^ Therefore the maximum value of c can be wri-tten as 2

c -1 (2L) 2 max w^ Theref ore the maximum abso.'l-ute value of negative error, when ß is even, is given by lu-L.* = l""l*.* . ß + l.rl*r* vl-,] ß+ (ß-1) from (19) and (2L) 2- + 2'Wl-, wt-, ]. W^ from (3) A:23

= ,[E ù)' 1 (22)

Comparing (16) and (2O') , the maximum error, when ß is odd is given by (20), therefore

2 (ø (o) +3 (23) ) max =2 v^ þ^

Comparing (ZZ¡ and (tl¡, the maximum error, when ß is even, is given by (]-7) , therefore ì 2 (ø(ø) )*r* = 2 w^ (24)

V'lhen c is nonzero, the minimum value of Z is 3 (z') (zs¡ m¡-n =ft

The maximum relative error, when ß is odd, is given (e(o)) by max ([ (øo) )*"* = (z) m1n

2 2 2 +3. 2 R (26) from (23) and (ZS¡

The maximum relative error, when ß is even-, is given by (ø(ø) )max (U (¿¿) )o'"* = ( t) man ( 2 2 t vr) R from (24) ; ,r::'.' A24

APPENDIX - 5

AP5 Mixed Radix Conversion

For a set of moduli *i (i=L,2,3, n) a number X can be expressed j-n mixed radix form Izs ] as

n- I {=a .'fi + +a3m2mr+a2mr*4r..... (1) n 1= I where a. (i=L,2,3, .... Ì n) are the mixed radix digits. The 1 digits can be found by

a lxl*,

a 2

X-e., Rr n ' & 3 m 2 m 3

In this h/ay, by successi-ve subtraction and divislon, all the digÍts can be obtained. Conversion of a number X (residue form) to mixed radi-x fcrm (shown in (1) ) is called mixed radix conversion (MRC) -

Example:

For m, = 16, m2 = 15, mr = 13, find mixed radix digits of X > A25 Solution:

Moduli: 16 15 13

Residue of X 7 5 I 4r B

Subtract a"r 8 B 15 L2

* by lrl 5 7 Multiply 13 | lmt 11 9 &2=9

Subtract a2 9 2 * Multiply by l-5 t+1,, L4 0.. g

From example, it can be shown that total paralleI residue operations required are (i) (n-1) subtractions and (if) (n-1) multiplication. If these operations are carried out with PROMs (by look up table) then subtractions and multiplication can be overlapped (since the multipliers are constant numbers). In this case total operations are (n-1). In other words, delay is (n-1) PRoM-delay (access time).

The decimal value (DV) of X = 14x15x13 + 9x13+8 = 2855

* 1 1 denotes multiplicatj-ve inverse of 13 L3 m. ' 15 ! 1 16 and l-5 with respective to mí (rs and. 16) and 16 respectirr"rv.J A26

APPENDIX 6

PROGRAM LISTÏNGS A-i

Appcndix-6 consists of the program listings for the RAC and is divided into three parts AP6 (a) , AP6 (b) and AP6 (c) . The AP6 (a) contains the program listings for integer arj-thmetic operations together with initialisation of the ports of the microcomputer, decoding of the operation codes etc.; the AP6 (b) contains the program listings for floating point arithmetic operations and the AP6 (c) contains the program listings for the conversion of residue numbers to deci.mal numbers.

The programs are the subroutines nested together. The labe1s of the subroutines and routines, in alphabetical order, are given belor^¡.

Labels Subroutines/Routines Paqe

AD S A30 ADD R A33 AP R A32 AI2 R A33 A30 R A33

BLN s A29

CAD S A38 CAP R A54 CAR S A2B CAT R A39 CBCD S A62

CCHR S A3l_

CNVBN S *

CM S A30 COMS R A33 coMu R A33 A-ii

Labels Subrout S ut Paqe coR A31 COSI A32 COUS A32 COVER A54 CV A30

DAD A38 DI A30 DIV A34 DSV A32

ECHO * EEQ A32 EPT A2B EQ A28 EXP A54 EXPO A43 EXT A57

FAD A45 FA A32 FBCD A62 FD A32 FDI A57 FEND A41 FFC A57 FINTS A40 FTXE A40 FM A32 FMT A59 FMU A49 FS A32 FSU A48

GAT A39 GET A29 GETCH * GGT A31 A-iii

Labels ut S utines Paqe

GT A2B

IBCD A6l_ TNI A2B

JPM A30

KAT A36 KATCH A46 KATH A36 KATR A36 KKK A58

LLT A31 LOAD A29 LT A2B

MAD A47 MM A32 MNT À28 MU A30 MUL A33

NCHRT A65 NEG A28 NEGA A41 Nl"lOUT * NORL A52 NORM A42 oPc A2B OSIGN A31 OUÎPU A45 OVER A44 OVFL A59

PASS A36 PEG A50 PEND A40 A-iv

Labels Subroutines /Routines Paqe

PEl R A34 POS s A28 POVER R A53 PSÏ R A31

QZERO R A56

RRET R A60 RSÏ R A63 RZERO R A56

SAT R A40 SB R A32 SCHRT s A64 SDIV S A34 SDK R A57 SELE s A39 SET R A28 ssc R A37 SSEP S A39 SSSP S A65 SU S A30 SUB R A33 SUM S A64

TAB R A34 TAC R A35 TAD R A35 TAD s A47 TAG R A31 TAKE S A30 TAP s A38 TEST R A32 TOR R A64 TTT R A28 TZERO S A56

XTAR S A29 A-v

Labels Subroutine s,/Routine s Paqe

ZRET R A60 ZERO R A36

Is Subroutine : R Routine l

* Resides in the Monitor Prom of the SDK microcomputer. A21

AP-6(a) : Li-stings .of fnteger Arithmetic operations

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í )'kil()Í{ñIi*tcï{rd;t¡cï-*ll;of f lol,*l'*n,$¡[t¡:ltfr*>|

1 i \c¡T)'l:iliI{ili*}f,hqí()h}i{}h}kt{Ii*{fr/,(l\)$:¡çil{$}r;'F.Y:r}F}lf .tñ}ir)i()ft}.k;ì\Ï{Íi*}liht;ii;'t}$:)l()i(*)fIi}i{}irii{i{ ûT'þlIfi !il.Jlirlltll.JT'l:NH GË'I$ Tl,,J0 ,t$üïï ül"irii:t¡tt'ï[:l'tiì Fl:ttìl'1 íCfll'l$tll.-Ë t¡Ë:Ul:CE: Al'JIr fi0i.lU[:l:iT$ 'Il"lEl'l ]:l,lïCl ûNH IrYTË i ( $-.ß T T'ti þlË.x ) [¡ÉrI'rl .

fiHT' t CAl.-l- GIIT'Cl-l i {.ì[iT' ûl"lË Â$ü I T CH'tlt'ìC'l'[iR . cfìl-.1.- Hcþlü iÏ:rÏ$l:¡1."râY" CALL CNUttN t fiüNV[:ltï' -l T' ï l'{ï0 ]:I'lì . i tJ.L l'IARY Vril.-tJH, RLC f'{Lt RLI: t(L-i: iAlÏütiËI'l'l[:l:t l:OtJl:t LEr[:'T $l{ïF'fü' ,ll,][.3t]ö STrâ '[,J. 360 $ S'f 0ft[: ËtT' l...üC , , Ctrì1.-l- G[iTCl'1 í tu*l::T' Êl.lt]l'l"ltrfI r*r$Ç ï l. t:HARÉ'Cl't{Í( CÉìl-l- ËCþ10 inï$frl.-rqY, CÊl...1.- CNUE{N iC0tlVEliT l:1' INTt} I'r$ i fi l:NÉrltY U'r¡1.-t.lË . ¡'ftlV C¡A il40V[: ïT T'[] ü'-fth:Gl:ãl'ER. L"IlÉr ,[,].3åO iLCl¡âI¡ ¡l- [i[iGïiiT¡:ilt Fl:tLìÞl ;l-CIC.'l'13rå0 Alltr C iËrll[r tl].Tl'J C-ftlIUI$'fHR. F{IiT í )Í{hcs*;*;ri{ilr¡H;ftrliil{r+{**rt*.*il(*}k*I(a+{ì\Í(}iill:il{il{tt,r{iy,r}|(r.l(¡tif )F)Kil(,v}|(ì\:)rt)i{¡rr,t)|t}rtÏi/,c,* I i **l*¡fi***}[.*rfi]f{)+{,ü¡cili,iili<*:lilir{<¡lcti/,ii,çrfi,$;i,{hc¡thcï{;,r\¡cI{rf,ht}ir*,t)i{*;ili}iit{ilr:fl¡t}i{Ï{il(* t'fHl:Sì lilJIrltlJLJl'Ti.lli l-CIÉ¡I¡iì üI¡Ë[tËrl'J[rS ñN[r üF'ËRËrTTUl{ inütrli T'ü filrf:ìïtrLJH 11¡ltITl.'ll.íHI':1.ü lJl'lIT([tÉrLJ)'ql.]il 'I¡-ll:i t üET$ ftE:$LlL..T' t¡UT ü1" T T'" v L..0,lnÍ þlt'rL Ay,[,s0 i ' .ll {i0 ' l:lrì 'l"l-lH Êl1nftfi:$f:i í {lF' T}lt: 1...râT't:l'J r.1fì!ìT[ìi'lHI] Ët50Ët FïH$1', ilFtiltÄ¡.tü {x) " 0LJ'f ,t.1tå i $Hl-ltr Tn fi*[]0l:t'f ( uFfrFfi ) . Lü'â ,lt13É J. i [,f]AIr [:Tfliì1' ilftEl:(rqNI] [j'l:iûl'f i ll-0t:: o {t,l.3d 1. , cllJT' {,14 t $Hlllü L T' l'ü 0f(T . 'â-'F i''lVl: tâ r {.50 i',fi.lio' l:5 l'l.lH ATlllFil::Íi$ t 0F 1'l{H l.-rq'f Cl'l r:rÍlS L Ltl.lËil i F0ft sËc0Nn üF frRÉlNïl ( \') . 0UT,[,J.f.¡ í flËiN[¡ TCI U'-FUF:T ( LIF ÊËlt ) . LIrÄ ,[,]l..5C¡3 i [- 0Ërtt $[;:fi ü]i'.lt¡ 0 [tliRrql{IJ fTl:t 014 i l*t}C.,il,J.3/r.3 ' üLJ'f ,[,J.4 i $[::]itr l:T 'f 0 A'-tiüitT . A30

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$ì'fô'[,13Cr1. iST{]I:(H: ôT .lll.î5C¡1. C'qL.L nlN iGTV[: $FAü[:. fiÉ¡1...t- l'fi.lT í$Ifìh{'âl- '14=" o CAt..L. CìE:T î GliT' ËY'f 'ôhlü'll.lË[t ï: 0[:' [rrtTô. $iïÉ' {,1.:16.T i $'f ilftH AT ,ll 1;Itl.5 . RIiT' i )$l;si{)ii;ü}E*)l(i}i}i()$(iíiT{)'qil(}l(,{(I(S{:io$í*l{tk;{ilf¡k}kh\¡ftcï1ri{Í(,vï{s}kfr{{*\trìc;.&l(ï(ï(ï{i1)fìqhk¡r.t}i{ v û ìf,ili¡\ii(iiir,(*il(fi*)i{Ìi.*ht}8.*¡k*:lrìthtï{,t;r!,{:i<¡t¡a¡¡q4ilili,\\..ti¡trfi$il(;t¡\*}i(g:il¡c*t{t(,1{il<:.*ñil{ tT'þl:LÍi iiLJIjfttll.Jl'l:Nh $iItìNr:ìt..Í:ì 0Uf:[{Fl...0['l ('!') rl::'0$Iï"tUË (.1) y Êl'lH:LìAT:tU[: (-') r/.1Ì.ltt $[rl'lIr$ T'l-lH l:tEÍiLJt-T T0 1'll[:: üüt-l$ilLE Ê nËu:i:cLt . I 0$ItìNi L-trÉr,ll'J.371 il.-0É¡tr lìl:c'jN rlNïr üV[ittl:iLOU i Il'{F'0[iÌ.1'q'ïIfiÌ.1 f:Rü1.1 ,il,].:T7:l . I'IIJU I y A i SÉrVË IT' It,l [r-'Illiü. " 'âNl: {,ûíl ;'f[:liìï Ïfr RHSUL'Ï i üutrttFt...fJ[,J{i JU ü01( iIf: l.luTy ,JUI{F" 'Iil 'C0tt'. CALL. X'f'êR í0'fHl:Ftt^JIii[: -ci:LGl,lÊrl- r¿it/ r C0ttÎ l'TüU ñ¡f¡ ttit{T' li6rtli Il'llîtftl'f'q'fI0N i f:tt0M Il*ft[:tì. . ANï {'0J. ËTHSi'f TF ftEi$tJLT T$ i I'lËCìåT J:V[:: . o JZ. F $I i lti l-l0T ¡ JtJtll:¡ 'f ü 't:,$ï , . C¡+it-L NEG r^0TþlËRLJTSE SIGl.l¡tl.. '-' r o..Fåå= Fsï ; ;ill-r i srrìr.¡,âr.- ,.t., , t_[rft d,]..I70 ; t._ortIt T].tH R î5ut.,1' FltclM ,þ 1370 . Ci*¡l-L Ni.f 0LJT i CtJNUHI:iT' Tl-lFi ttliiiUt..T' t INTCI rqC$:t l: f:01:(1.1. RH]' í T<*ttl¡lrÍt)f<*il(Ì(i$trc¡1í$:;)t¡tìilEg¡q*;stq*:,í(il(*,v**;s)¡iirs¡qx;fi*$)kli(¡c*.àt¡qli:y,(;{í,**I{.ìt}.1r,{

t;:Htlt ü'å1.-1. Hll tSìïtìl'l'tl.- ËË'r ",'. $,T{Ï(,r\}i(}k;$i)i(*)li)lr#*i)i{$ttlçK¡lrilr,ft:Ícs¡crfi}.¡ilfi;üí¡t}ir}¡{}h*ï{)kil(:'kil(¡crfi)i(}fi}i{rfii¡(}ioi{;fi}i(f;}ft I y ¿\lf.4\.¡rr.,'11,ì\ ð. rf..Í.41 /tl d!.f..ï1 4\ + tô ¡F,¿tl.Þ 4\ /ii ¿ì\ /r\,i\ 4\+ + ,,l\ ô,I'.1'41.t.4\,} ¿$/¡\ 4\ 41.+./ß,Þ++ ¡r1ò¿r1rT'J'ô. F'ltüf.iR'1rl'iË: ô!ìlih- Ë'(llï ill:ifiËûl'T{li'l tlt)fi[:$ 'fH5]' iTl-lTti '*'l.lI1 t Tl'ltr 'fYFlI 0F:' UFËRËr'I'l't]l'J liE:[¡tJÏ[tË.I¡' i {:ül.l$üLl;i nHU:1.[[: :tËl;itJlïfiì Tl"li:i Fill.-l-.ü|,il]:i\iü i ËtlIll:fi i -' ôr ( ÉrIrll.t l'.1.üi''l ) v Il ( 5ìLl[r'ï'[trâ0'lï0l.{ ) iü (ì'1U1.-T'ïf:'l...1:{:r'':r1'l;tlN) vt¡ (trTVTfï[il,l] vli: ({1ül'f[]i1rl:tÏEiÏClÌ'l t üF ul{$ I {.ìt,l[::[r l.,ltJl,iIr[iii ) v lî ( fi01.11]rì[t ]:Í:ìilN nF fï:t ü;Nl;:Il il.lt.Ji.ll;{[:r()rtì (F'1...üË¡T']:Ì"1$ Ët]ïÌ{'1" râI1ïll:'il.c)N)vþl (Ë1...ÛÍ\'Il:l¡ti ,^Fnïl'll'$t.J$T'fiÉ\tll'.tüN)vl. (Ë'1.-üÉ¡T'l:i'J{ì Fr(lIl.ll'l'il.ll.-'i'IFl.-ï" r ( } iCAI'Tllt'l ) J l'r'[-ü'lTIi'{tì Füïl.lï' n:iVï$:tOl'J " r TË:$1'I ClÁ[-L t C¡âltIt I rqü[i Il[:'f Ul:ti,{ üâlt 'tl,lü t L- ï NE ËË:tilr . CAL-L tË¡C í$I(ìi'lAl.- fJ;;; Tn G[:'f ; 0F Ëlt¡ì'f I0N üOIrL. . CALI- üETUI-l ißËl' t')Fr[:FfÊrTïC]l'l ü0llË' C/\LL [rüHü i I]:t$Fl-rt'¡,. l40u üyc ;s,qu[: I]. Ë¡T. [r._.t:iÉ.cì. . côL.t- E{[-l.l tGIVli Ë[¡¡lcH þlClU Ë't r Lt AF I üF I ,t,4lL $ T[:$T Tf- 'tt' . .17. Ë¡Ittr i IF 'fl:$ -It_li'lf¡ T'u 'Ërltfr' o $Ill CFI '4'4? it]ïl'lHlttJT$lî,v 'tFfl'I ïlr '$'. Ì,i,.,i dË'ull*' i['lËfi'Íliii"'J,i''Tl;l'0,;, . -lz t1t.JL. irf: Yti$ ,.JtJt'tF TCI 't.1t.J1...'. Ir$V! CF'r {t,44 íCt'rHt:ifttJl:5Ë: T'ËSjT' ïtl,fr',.

c0rr$' dir''lÏ*'Il;"1iiil'iljlln'''ll,''ÏËulü', . J¿ {:0MU iïF \',[igi -lt.li'1Fi Ïu 'cnÌ,il.J'o c{lçiïi cFï,['4d i0Tt.'¡iit(til:t$[:ì-[i$'I-rF'tî" F,âî ,jË'*iii'i['lË,'irf,I|]"u18,'fl;I{Ti:. r¡::f¡fl/ JZ FË¡tl iïF Y[:S -lui'lF ]'U + FS 3 {:F I '1140 î UTt{l::ltlrll:$li T'[i$ì]' ïF 'l"l' * FÈ'r,lfr"lTu'i['l[ü,ìili'nll,,,lT'l;uT':. f:i'it.J ¡IF Yf:r$ Jt.Jl'fi:¡ ïü 'Fl'ftj'. -lL 'IEírì'I FII ; üF I ,[,44 i OT'þlF:fit,J:t $l:i T Ë' ' ul' , :if,."'Ër,' I[,'lllfi'íli';"''J;l],;l;li'''' Ê 0F Ë:l:i¡ôl' T []i{ ü{iIl[:. i ?i{ili¡\)+(}K;fil\:;\t,i(Tr}hT{rc..fiÍ(Tr**)[{ìk$f{Ti,$:firËiFhkrlr:'l{ii{ïir.l:ii(;K;*il{;Ì1il(iir;fi)ii;*&yíÍr,ïift*tctc A33

yc ;Jr }i{ }H )i( :# r+{ }F /,( ik )l{ }h ){( }i( \k }f }h ,\c ri{ hc )k ¡tí ik I( lk ìi( )ii i {i ïr )i: )h hr{ }i{ il1 h"; tk il( }ii il( i( x{ s I{ Ii tk * f It It Ii ii iTþtH t.,l,âl:t.J"{i:,ii [¡Rt)[ìfirtÌ.1[::$ [rL']li Il{I'L:.Ë[:lT Érl'(T]'fii'18'fItl 0llHfiAT'Ïüi'J5' I Atrn I ü'âL.1.. T r\lil: i t.iÊ-T Tl,Jü 0FiË:ttÉrl.ltrÍi . fr^ I I L, f-r t... t- t'.1^ Ir ;ttfJ ËrllttT'fIül.l' rl L:l i ü'ât,.t- C HT\ í C'q¡ÌË( l:Aüü. ÏtH'ILJI:ii'l ñN[¡ û t._ r:[ih.l] fi'JE " Cr.1L..t- Cl$ I riN i$TËl''l'â1."Í; ilVE:RFt..Utl ( l:f: t $ I Ght ,qhlÌ:r [r.l'g;¡:r¡_6t "\l'JY) i'rH[: trH$tJi-T û I N ItHÍi l:[rt.J[: lrüfil'l , -JMl:r ï ErUIr i l.tI í:iF l,-râY Tl"lL: ftli:$l.J1..1' i IN IIE{:T¡'1ñ1.- l::üf(l'f . $lJIi; CÊ'1..t- TÉ¡ltH ; GET 0[r[:RÊrl.lÏ:rli . ilÅ1...1- $LJ i nü sLJË'ïft AcT'l:üi'ì. Jl'lF ôl.r l'f t.Jt,.l üÊrl-.1.- T¡tltl: t 0[:T üF[:Fi'qNIr5ì. ürlL-1.- i'fU i ttU t'lUl.-l T [1[.. T Ërq'I ï 0Ì'l . -Jt.f F' A 1i 00l'f$ ! CÊ'1.-L- TÉrliF: i tìET 0lllirltËrlv'I¡fl . {:'âLL. CV i C0l"fli¡'tl:tl:t'IþlH $jl:[ìlltiil i l.ltJ14fiER$.

ü0r'ru, illl-,-nT,Ï,*,,' tGËî' 0rtiiFiÉ.'t'lt¡$. CÊ1.-t- CÌ"1 ;Cüt'fF'ôRl:1 Tl'lE UN$f üi''ll:iÏl i l,llJi'TIll-:ft$ ' Ër30; U'â1.-l- CrqF{ üÉrl.-t- ccl"lR tSTGt'{flL- ct}¡1r¡A[iT$Ïni-l Ê Ct'lrtFtrì{l'ì-[i Ft " .,1'lF TËST idìSlt Ëüft Cll-'[:RÊ'T'].f:]N i çtlI¡ti. i lT**)FrSï{;ii;tilili;i{}¡tÍíili)i.)+{fr:}¡(àCfrï(;tr{i,$ilXrfi)i{*}'i(*r'l1rir}ii}ii}f ii{,$}ii}i{:.ü}'lt}ii;ìt;fitr;Sil( í${is{i1þ1þtþtl;lli$.+:Þ${iiliiþ:F$lli:ltfli:Flli${;iliiþÍÞiË't's:þiltiF:Fss{tÍlis#l;iFl,ilifilFf' ENn A34

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AP-6 (b) : Listings of Floating Point Operations

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$l'rî¡ ,I,J.3Cr L l'fUI A/,11,$Ii !:ìTrq ,[':1.:TC].3 Cr\1.-1.- i'ft.l t i'f LJl.-'f T F[-Ì' Tl-lH ]t[::f:tJl..1' üF ( [i1...[::U[:i.l) i"\n[r:L]'Tül'l F'",H'¡]l " $TA ;[:l.i("iJ::' i flT'(liit::'fli[i fä I U;',1 rtri{I.r üU[::l:tFl...(]lt i T tl F' il Í( l'l ¡l'I I U ì'-l 0 !:: i'j t.J l- T' I f] [- T ü'l'I T 0 N t râ'f ,['J. il.5f: . Al.lï 0:l û 1'E:f:iT' I F tlU[::ttËf l.-0tJ . JNT ËOUEII t IF YË.5ri v .Jt.J¡'lF'llÜVE.l:i' . i'lClU û r H $ìTA.ü,1.3C)I i $T0l:tl;: 'l'l'l¡:: [iË$tJt..T' Ülr ; MUL'f T[]l-Tü¡*¡'Il:{lN rlT''ll'1.:idl . l.-llrl ,[,t.T7t: í t,.0Í\[r 'f H[: [:0HFF. {JI: i 0-'F'ilU[::l:t üF' 'U,nf:t ( I N F:'F' ) . $Tfl ,[,1.T6:3 Cô'L-1.- ¡6tril T'l'¡H IlFtliUTilt.l$ RH$l.Jl.-1' '1il â 0f:' ¡'1tJl...'f I1"1...I t)râl'T 0l'l i'ü t ZHtiU F llLlFR il[i ;llrlll:{ ( I l'¡ [:' o [:' ) . $TA {,1.$3[: î tìTül:tti'T'1.18: ËiTffil,t ril.tI.r üUE:R[fl.-ütJ í INF0fü4r.1'il:0i{ tilî Êtr[rT'rÏ0N t rl"l' ,ll,J..5,Tl:: . fIN T o? t Tli{il' :t F .0uEFlFl-utJ ' ..tNu ü0Vl::[t iIf '/[ifì¡ ,.JUM[" 'CUU[:[I'. þtclv rl v lit 'I¡"1[: Si'f É,¡ '[..1.37ó t $T0R[r N0Ri'l'tl.- T $tiIt i l'lt.,MIl[::fi rlT '[':[.J,7$ . t-ïtA ,¡,1.3:5li t LtlËr[r 'f Hh. $ I GN rqNIl i 0UH[(fïL.0tl I NF 0Ri'f I0N í F'lt{ll'f ,[,.1..315l:f . "\'f Atl T 0 L i f:;t i'l[r ]'1"¡lî ùri I LìN C]l-' t THti F'l:N'll.- R[:-ÍìlJ[-T' . STA,&J.37F í$T0Ft[i IT AI' Jl'].*17[:'. RTiT t s*)ftÍ1il(il(I(il#ft,*'fi)i('.i(ï(,\()Hlk*àc)H¡'()h)l(il<*,¡cÌ(,fiil()k¡\,$h\,T(,\cx(il(,Ïsrft¡\¡lr.k,Yils.*¡ltf(hci+{htrijil{ ] û ¡\>&¡lç41*¡(,$),k*¡c$¡c,*il(ift)'k¡cil(il(t(il{tc$(t(;Íil(,\kx¡k$tt,$rc$I{)f,yril{h(hk¡c¡Yil()¡cil(s¡\xhcil()f,il(tr t Tl"lT $ l:tütJ'I T t''lH 1'Al{tr$ Ü'tRH üF' [t0l'JNI] I ]'lü tl'lt.lMIflilt. ( ÊF:l'HR F'TltIì'l' 0ft $L:üül'1fi üU[:Fii:iL-0tJ'à i rrËïËüT'I llN r N Tl.l[: siu[r[iiltJT'r NH ' l{0lll* ' ) . ! F()UE,I.i3 t'lUT É¡ r'['llü â'{,iìl' (T'tjfl) IS l'l"lË ; l'ifil'lHl:t'âTlÏll llX[tCIN[rN'I . $iTfi ,t':L:534 í $l'tll:iË: l:T',rt'r :[, I :3:]¡l r L-n'.¡ '[,J.37I] í L0Arr Tl-lH $ r lìN t)[: ]'þll: i r[J[:'Frr o üF ]. ".r¡ü[,Jlilii (ll: i,[,$l'] (TN F'F ) .Fftill"l .[,13îrlt. Íì T' A :l' J.:{5fi i ÍìïilRt: :t T 13li[t . 'IþlH 'â'f 'þ LNA ,9, 1:J7u t L-0¡qIl C0f:F ti . (JF i J..-.F0uHrt CIl:r ;l!li{$ t TN F'.F ) t lrtrül.f ,['1.T7{.] . A54

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ËìN:!' 0t iliTi.l:(l l'l"lH ll.l'{iiN 0[: TllÏ: fi[:llLll.-Ï'.

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