An Alternative to Mainframes for Business Computing

Corporate Business Servers: An Alternative to Mainframes for Business Computing With expandable hardware, PA-RISC architecture, symmetric multiprocessing, a new bus structure, and robust error handling, these systems provide a wide range of performance and configurability within a single cabinet. Standard features include one to twelve symmetric PA-RISC 7100 multiprocessors optimized for commercial workloads, main memory configurations from 128M bytes to 2G bytes, and disk storage up to a maximum of 1.9 terabytes. by Thomas B. Alexander, Kenneth G. Robertson, Dean T. Lindsay, Donald L. Rogers, John R. Obermeyer, John R. Keller, Keith Y. Oka, and Marlin M. Jones, II The overall design objective for the HP 9000 Modelsupporting T500 from one to eight processors with superior value corporate business server (Fig. 1) was to set newfor standards their class. The MPE/iX system is designed to support for commercial systems performance and affordability.businessĆcritical ComĆ data and offers features such as powerful bining expandable hardware, PAĆRISC architecture, symmetricsystem management utilities and tools for performance multiprocessing with up to 12 processors, a new busmeasurement. design, robust error handling, and the HPĆUX* operating system, the In this paper, the hardware platform for both the HPĆUX and Model T500 delivers a costĆeffective alternative to mainframe the MPE/iX systems will be referred to as the Model T500. solutions for business computing. The Model T500 is an update of the earlier HP 9000 Model Users of HP's proprietary operating system, MPE/iX,890/100 also to 890/400 systems, which supported from one to enjoy the benefits of the Model T500 hardware. Thesefour PAĆRISC sysĆ processors operating at 60 MHz. For MPE/iX, tems are designated the HP 3000 Series 991/995 corporatethe Series 991/995 is an update of the earlier Series 990/992 business systems. They provide high performance by systems. Fig. 1. The HP 9000 Model T500 corporate business server (right) is designed as an alternative to mainframe solutions for online transaction processing and other business computing applications. It runs the HPĆUX operating sysĆ tem. The same hardware running the MPE/iX operating system is designated the HP 3000 Series 991/995 corporate business sysĆ tems. The Model T500 SPU (right) is shown here with various peĆ ripherals and expansion modules. 8June 1994 HewlettĆPackard Journal Processor Up to 12Processor Memory Up to 8 Memory PA 7100 PA 7100 256M Bytes 256M Bytes (90 MHz) (90 MHz) Processor Memory Bus (16 Slots) Service Processor Bus Scan Bus 3000 Watts Service Dual Bus Dual Bus 5V, etc. Processor Converters Up to 4 Converters Power System Power Control and BC BC BC BC Monitor DC-to-DC Converter Modules Link Link Link Link Control Panel AC Line HP-PB HP-PB HP-PB HP-PB (200-240V AC Front End BC BC BC BC 1 Phase) Console/LAN Up to Up to M M Card 14 14 Slots Slots Each Each Remote Terminal LAN HP-PB HP-PB HP-PB HP-PB Local HP Precision Buses Terminal Fig. 2. HP 9000 Model T500 system processing unit block diagram. Standard features of the Model T500 include one toT500/400 twelve reaches 38,780 SPECrate_fp92 and 23,717 SPECĆ symmetric PAĆRISC multiprocessors optimized for commerĆrate_int92 with twelve processors. cial workloads and operating at 90 MHz, main memory conĆ The Model T500 provides this high level of performance by figurations from 128M bytes to† 2G and bytes, disk storage up using a balanced bus architecture. The processor memory to a maximum of 1.9 Tbytes (1900 Gbytes). This expandabilĆ bus currently provides the main processorĆtoĆmemory or ity allows the Model T500 to provide a wide range of perforĆ processorĆtoĆI/O interconnect with a bandwidth of 500 mance and configurability within a single cabinet. The Model Mbytes/s and a potential capability up to 1 Gbyte/s. The I/O T500's package minimizes the required floor space, while air buses provide a total aggregate I/O bandwidth of 256 cooling removes the need for expensive mainframeĆtype Mbytes/s. These bandwidths satisfy the high data sharing cooling systems. requirements of commercial workloads. The Model T500 is designed to provide leading price/ performance. The HP 9000 Model T500 with six PAĆRISCSystem Overview 7100 processors operating at 90 MHz has achievedThe 2110.5 key to the Model T500's expandability and performance transactions per minute on the TPCĆC benchmark (U.S.$2115is its bus structure. The processor memory bus provides a per tpmC).†† The SPECrate (SPECrate_int92 and SPECĆ highĆbandwidth coherent framework that ties the tightly rate_fp92) benchmark results show linear scaling withcoupled the symmetrical multiprocessing PAĆRISC processors number of processors, which is expected for CPUĆintensivetogether with I/O and memory. Fig. 2 shows a block diaĆ workloads with no mutual data dependencies. Thegram Model of the Model T500. † Hewlett-Packard Journal memory size conventions: The processor memory bus is a 60ĆMHz bus implemented on 1 kbyte = 1,000 bytes 1K bytes = 1,024 bytes a 16Ćslot backplane with eight slots suitable for processors or 1 Mbyte = 1,000,000 bytes 1M bytes = 1,0242 bytes = 1,048,576 bytes memory boards and eight slots suitable for I/O adapters or 3 1 Gbyte = 1,000,000,000 bytes 1G bytes = 1,024 bytes = 1,073,741,824 bytes memory boards. Each slot can contain as many as four modĆ 1 Tbyte = 1,000,000,000,000 bytes ules, and can obtain its fair fraction of the bandwidth proĆ †† The Transaction Processing Council requires that the cost per tpm be stated as part of the vided by the system bus. Custom circuit designs allow the bus TPC performance results. Cost per tpm will vary from country to country. The cost stated here is for the U.S.A. to operate at a high frequency without sacrificing physical June 1994 HewlettĆPackard Journal9 connectivity. To prevent system bus bandwidth fromAddress becomĆ Bus: ing a bottleneck as the number of processors increases,AiRVAiRVAiRVAiRVAiRV the bus protocol minimizes bus contention and unproductive traffic without adding undue complexity to the bus modules.Address Quad 1 Quad To support such a large number of slots the processor memĆ Data Bus: ory bus is physically large and has an electrical length of 13 Data Quad inches. StateĆofĆthe art VLSI design and mechanical layout D0 D1 D2 D3 allow the processor memory bus to run at 60 MHzĊa very high frequency of operation for a bus of this size. Memory Latency 1 Quad The input/output subsystem links the processors andA memĆ= Arbitration ory on the processor memory bus to I/O devices,i = including I/O a variety of networks. The Model T500 supports attachmentR = Real Address V = Virtual Address of up to eight HewlettĆPackard precision buses (HPĆPB), each of which connects up to 14 I/O cards. TheFig. first 3. Processor HPĆPB memory bus pipeline. is internal to the Model T500 and the other HPĆPBs would be located in adjacent racks. Each HPĆPB connectstransaction to the processing (OLTP) performance and efficient processor memory bus through a linked bus convertermultiprocessor conĆ scaling. sisting of a dual bus converter, a bus converter link, and an HPĆPB bus converter. Under normal operating conditionsBus Protocolthe bus converters are transparent to software. The processor memory bus is a synchronous pipelined bus. The service processor consists of a single card whoseThe pipelinedpurĆ nature of the bus protocol places it between a pose is to provide hardware control and monitoringsplit functions transaction protocol and an atomic transaction protocol. for the Model T500 and a user interface to theseThis functions. allows the processor memory bus to have the To achieve this purpose, the service processor hasperformance connecĆ of a split transaction bus with the lower tivity to many parts of the Model T500. The scanimplementation bus is conĆ complexity of an atomic transaction bus. trolled by the service processor and provides theThe service processor memory bus has separate address and data processor with scan access to all of the processorbuses. memory The address bus is used to transfer address and conĆ bus modules. The scan bus is used for configurationtrol of information proĆ and to initiate transactions. NonĆDMA I/O cessor memory bus modules and for manufacturingdata test. is The also transferred on the address bus. The data bus service processor also provides the clocks used bytransfers processor memory data in blocks of 16, 32, or 64 bytes. The memory bus modules and controls the operation ofprocessor these data bus in the present implementation is 64 bits clocks. The service processor provides data and instructionswide, although the protocol, backplane, and memory system for the processors over the service processor busalso during support 128ĆbitĆwide accesses. For 32Ćbyte transfers on system initialization and error recovery. The servicethe procesĆ data bus, the available bandwidth is 480 Mbytes per secĆ sor connects to the control panel and provides theond. system If processors use all 128 bits of the data bus to perform indications displayed there. The service processor provides64 byte transfers, the bandwidth doubles to 960 Mbytes per its user interface on the console terminals throughsecond. its conĆ nection to the console/LAN card. Fig. 3 shows the processor memory bus pipeline. Four conĆ The service processor also contains the power systemsecutive conĆ processor memory bus states are referred to as a trol and monitor, which is responsible for controllingquad and. A transaction consists of a quad on the address bus, monitoring the Model T500's power and environmentalfollowed sysĆ at some fixed time by a quad on the data bus. tem. The main power system receives 200Ć240V singleĆphase mains ac and converts it to 300Vdc. This 300V supplyAn address is then quad consists of an arbitration cycle, an I/O converted by various dcĆtoĆdc converter modules tocycle, the a real address cycle, and a virtual address cycle.

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