Lecture 28: Process and Device Evaluation

Lecture 28: Process and device evaluation

Contents

1 Introduction 1

2 Electrical measurements 3

3 Thickness measurement 5 3.1 White light interferometry ...... 5 3.2 Spectrophotometer ...... 7 3.3 Ellipsometry ...... 9 3.4 Proﬁlometry ...... 10

4 Contamination and defect detection 11

1 Introduction

Integrated circuit manufacturing is similar to an assembly line manufacturing process, with the wafers moving from one ‘station’ (process step) to the next. The starting point is blank single crystal Si wafer and the various processes to the finished product are carried out in a single fab. There are more than 500 individual steps in current IC manufacturing and the total time for making a single device can be as long as a month. The devices are usually tested (electrical testing) after the process is complete, to check functionality. At this point, it is very hard to trouble shoot the origin of any ‘killer’ defects i.e. a defect that can destroy or significantly reduce functionality. Thus, process control tests are done throughout the process. The disadvantage is that this can can also increase manufacturing time and hence cost. Process or device evaluation is critical to ensure that the chips (or dies) are ‘working correctly’ after each step, without significantly altering total process time and cost. Steps in CMOS manufacturing are shown in figure 1. There

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Figure 1: Various steps in CMOS manufacuturing. The process monitoring steps are marked with M. More the number of monitoring steps, longer is the total process time but error detection and correction will be quicker. Adapted from Semiconductor manufacturing and process control - May and Spanos. are a total of 30 steps in this process, with 14 additional evaluation steps inserted along the process flow. Thus, the overall process involves around 45 steps. Increasing the number of evaluation steps will increase process efficiency but overall time and cost will also increase. On the other hand, less number of evaluation steps can keep cost low but trouble shooting could be difficult and could lead to wastage of time and increased cost, if the process has to be tweaked. The process monitoring is carried out on three types of wafers that are used in the fab 1. Directly on the process wafer

2. On test wafers, which are processed along with the product. There are speciﬁc test dies on the process wafer that are evaluated.

3. On blank wafers, which are used to monitor a particular process. These wafers are process speciﬁc and do not go to other processes in the manufacturing. These are also called test/monitor wafers. This is apart from process evaluation on the ﬁnished wafers. The type of monitoring depends on the nature of the process. For batch processes, like furnace operations, multiple wafers are processed together.

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In such cases, monitoring is carried out on test wafers that are processed together with the process wafers. For serial processes, like etching or polishing, either the process wafers have to be directly monitored or test wafers have to be inserted between runs of process wafers and then the process is monitored using these wafers. Metrology refers to the measurement of physical surface features. In fabrication, some examples of metrology are, measurement of pattern widths, film depth, defect locations, and pattern registry errors (in lithography). Metrol- ogy should provide information on whether the wafers are ‘good enough’ to move to the next step. Hence, the evaluation should be fast and conclusive. Usually, for every step in the flow, a process window is defined. This provides theacceptable range of parameters, for that process. If process evaluation can confirm that the wafers fall within this range, then the wafers can move to the next step in the process flow. For a furnace operation (to grow oxides on Si), the parameters are usually oxide thickness and defect density. These are usually measured on test wafers (since furnace process is a batch process). The product wafers will be ‘waiting’ till the metrology is complete and acceptable. Then the process wafers can move to the next step. There are three main measurement types at each step

1. Electrical testing

2. Physical parameter measurement

3. Defect measurement (contamination)

As device integration increases and size decreases, these measurements will have to made on smaller regions. This can pose lots of technological chal- lenges, especially if the evaluation has to be fast and conclusive.

2 Electrical measurements

Typically, electrical measurements refer to measurement of resistance of the component. Resistance or resistivity can be used to obtain a wide variety of information on the fabrication process. Addition of dopants to the wafer alters electrical conductivity, which can be easily tracked by resistance measurement. Similarly, formation of metal-semiconductor junctions can be probed by I-V and capacitance measurements. These measurements are fast and provide conclusive information on the process and are widely used in the fab. There are also electrical measurements done on the components after the fabrication is done. These tests are more involved and probe a variety

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Figure 2: (a) - (c) Some simple e-test structures for interconnects. These are used for probing effect of defects on the electrical properties of the interconnects. Mostly resistance and capacitance measurements are carried out. Adapted from Semiconductor manufacturing and process control - May and Spanos. of properties than simply resistance or I-V behavior. There are specially de- signed test structures, which are incorporated in the dies, for these electrical measurements. An example of test structures for interconnects is shown in figure 2. The most widely used setup for resistance measurement is the four-point probe technique. The schematic of the setup is shown in figure 3. The inner probes measure the voltage difference while the outer probes are used to pass a known current. By using a four probe technique it is possible to eliminate any resistance effect due to the circuit (wires). For the arrangement shown in figure 3, the resistivity is related to voltage (V ) and current (I) by 2πsV ρ = for t s I (1) πt V ρ = for t s ln2 I The first condition in equation 1 refers to a thin film case or a doped region in a semiconductor, while the second condition corresponds to a shallow junction. When resistance is measured on a thin doped region (which has a much lower resistance than the wafer) an electrical quantity called sheet resistance, Rs, is preferred. The quantity has units of ohms per square (Ω per ). The sheet resistance is give by π V V R = = 4.53 (2) s ln2 I I For metal films on semiconductors or insulators, the sheet resistance can be used to measure thickness since resistivity of the metal is known.

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Figure 3: Four point probe setup for measuring resistance, used on a pn junction. The inner probes measure the potential diﬀerence while current is passed through the outer probes. The probe can be used to measure junction depth by correlating with the resistance. Adapted from Semiconductor manufacturing and process control - May and Spanos.

For pn junctions, resistance measurements can be used to characterize the depth of the junction. This is done by fabricating a bevel structure on the wafer and measuring the resistance as a function of depth. This is shown in ﬁgure 4. Since resistance is related to dopant concentration, this can be used to measure the junction depth. A more reliable technique for dopant concentration as a function of depth, is secondary ion mass spectroscopy (SIMS) but it is time consuming. SIMS has a sub-nm resolution and can also provide chemical information about the dopants and other impurities in the wafer.

3 Thickness measurement

3.1 White light interferometry Measurement of thickness of thin films is an important step in process evaluation. A variety of thin films are grown, oxides, nitrides, metals, Si. Thin layers (less than 500 nm) of oxide and nitrides have a natural color that depends on the thickness. This is due to interference of light reflected from the top and bottom of the film, called white light interference. This is shown in figure 5. The interference color depends on

1. Index of refraction i.e. ﬁlm type

2. Viewing angle

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Figure 4: (a) Bevel structure for measurement of resistance as a function of depth. The bevel has to be fabricated on the wafer and hence, this is a destructive measurement. (a) The resistance is converted and plotted as dopant concentration vs. depth. The dotted lines indicate the junction. Adapted from Microchip fabrication - Peter van Zant.

Figure 5: (a) White light interference from a thin oxide ﬁlm. (b) Changing the thickness changes the color since the path length changes. Adapted from Microchip fabrication - Peter van Zant.

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3. Film thickness

Usually, overhead viewing angle is used. The colors for diﬀerent thicknesses of silicon oxide are tabulated in a color chart in table 1. Using the color

Table 1: Color chart for silica, as a function of thickness. Adapted from Microchip fabrication - Peter van Zant. Film thickness, nm Color (perpendicular illumination, fluorescent light) Order I 50 Tan 75 Brown 100 Violet 150 Light blue 200 Light gold or metallic yellow 250 Orange 300 Blue to violet blue 350 Light green Order II 400 Yellow 450 Violet red 480 Blue violet 500 Blue chart, it is possible to estimate the thickness of the film. This can be used as a rough guide to calculate the time required to grow a specific oxide or nitride layer.

3.2 Spectrophotometer For more accurate calculations of the thickness, a spectrophotometer can be used. This is also based on interference of light, as shown in figure 6. A monochromatic light source (with wavelength in UV region) is used. Fringes are obtained, due to interference of light from the thin film. If the thickness of the film is d, then the path difference between the light reflected from top and bottom is given by λ P ath difference = (2m) ⇒ for constructive interference 2 (3) λ P ath difference = (2m + 1) ⇒ for destructive interference 2

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Figure 6: Schematic of light interference from top and bottom of a ﬁlm. Depending on the path length, there can either be constructive or destructive interference. Source http://www.shimadzu.com/an/uv/support/uv/ap/ﬁlm.html

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Figure 7: Illustration of the components of polarization. Adapted from Semi- conductor manufacturing and process control - May and Spanos. where λ is the wavelength of the light and m is the fringe order (integer). Usually, either wavelength or angle is varied to make another measurement. If wavelength is varied, the thickness is related to the fringes by ∆m 1 d = (4) p 2 1 1 2 n2 − sin θ ( − ) λ1 λ2 where ∆m is the diﬀerence in number of fringes for wavelength λ1 and λ2.

3.3 Ellipsometry Ellipsometry is another widely used technique, which is based on the polarization changes of light when it is reflected or transmitted through a medium. Polarized light that travels through a medium gets rotated by an angle, that is a function of refractive index and thickness. This is shown in figure 7 where an unpolarized light incident on the substrate gets split into different components. In ellipsometry, linearly polarized light is incident on the wafer and the elliptical polarization of the reflected light is analyzed. From

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Figure 8: Step measurement using a stylus profilometer. (a) Wafer level and (b) Step. The horizontal resolution of the profilometer depends on the tip radius, while vertical resolution of the order of nm are possible. Adapted from Microchip fabrication - Peter van Zant. analysis of the polarization of the reflected light, the thickness and refractive index of the film are calculated. The ellipsometry technique can be used for thin films (thickness of the order of a few nm). It is especially useful for measuring thickness in multilayer stacks, where are multiple reflections and transmissions occur due to presence of many individual layers.

3.4 Profilometry Profilometry is a technique for measuring surface topography. It can also be used for measuring film thickness, if a step is introduced in the film. In the original profilometers, a stylus is used that travels along the length of the film (scanning mode) and obtains the surface contours. This is shown in figure 8. Stylus profilometers have now been replaced by optical profilometers. These use a beam of light that scans the surface and the reflection pattern measured. A beam splitter is used and the interference pattern as the light scans the surface is recorded. This is used to calculate the contour information. Optical profilometers have a horizontal resolution of a few hundred nm and vertical resolution (z resolution) as low as 0.1 nm. They can be used to measure thin films with thickness as low as 5 nm and can be used for a variety of films ranging from metals to oxides and nitrides. But, it cannot distinguish individual layers in a multilayer stack.

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4 Contamination and defect detection

Detection of contamination on the wafers is important, because these have the potential to destroy device functionality. As feature sizes are constantly decreasing, the minimum defect size that needs to be detected and controlled is also decreasing. Hence, defect detection and elimination becomes even more important. The following information about defects are needed for process control 1. Size and shape of defects

2. Density of defects i.e. number of defects per unit area

3. Defect location, especially on product wafers

4. Chemical identification of the defect, especially important for metallic defects An overview of surface inspection techniques is shown in table 2. The sim- plest technique is visual inspection (1x). This is mainly used for identifying scratches or chips on edges of wafers. But cannot be used for smaller sized defects. To be able to see smaller defects, microscopy techniques are used. The met- allurgical microscope (optical) can be used for inspection and identification of defects not visible to the naked eye. The microscope can be used in either a bright field or dark field condition, as shown in figure 9. The advantage is that these systems can be automated, to directly identify defect particles (using a thresholding technique by specifying intensity) and provide information on their distribution. An optical particle counter is shown in figure 10. This can be used to find out the density of particle defects and their location on the surface, as shown in figure 11. On bare wafers, these are useful to troubleshoot problems with process equipment and flow. By analyzing the particle patterns on the surface, it is possible to pinpoint the origin of the defect. For example, particles concentrated at a particular edge might mean that the wafers are scrapping against some other component at or near that location. Optical microscopes have a resolution limit of a few hundred nm, since they are limited by the wavelength used. For current IC technologies, minimum defect sizes that need to be detected are a few tens of nm, which cannot be resolved by the optical microscope. Also, chemical identification is not possible with the optical microscope. A newer defect detection tool, that is widely used now, is scanning electron microscopy (SEM). A simple schematic of the SEM is shown in figure 12. The SEM has a resolution of a few nm, so that most defects can be easily

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Table 2: An overview of some of the commonly used surface inspection techniques and their applications. With decreasing device feature size, many of the defects that could be detected by light microscopy have to be detected using scanning electron microscopy. Adapted from Microchip fabrication - Peter van Zant. × × × Critical dimensions (CDs) × Chemical identification × × × × × Alignment × × × × × defects Surface × × × × × Visual contamination Filar SEM Auger ESCA Method UV light Dark field white light 1x incident 1x incident Microscope micrometer Bright field Reflectance

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Figure 9: Optical microscopy under (a) bright/light field and (b) dark field conditions. While bright field conditions provide information on contrast between different areas of the wafers, dark field imaging is useful for identifying precipitates and other point sized defects. Adapted from Microchip fabrication - Peter van Zant.

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Figure 10: An automated optical particle counter. These are used inline for monitoring the purity of the process. Flat wafers are used for measuring defect particles in batch processes, but measurements can also be carried out on product wafers. Adapted from Semiconductor manufacturing and process control - May and Spanos.

Figure 11: A typical surface scan on a bare wafer, showing defect distribution. From looking at the defect density and also the distribution, it is possible to work out the origin of the defects. This is useful for troubleshooting any process ﬂow problems. Adapted from Semiconductor manufacturing and process control - May and Spanos.

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Figure 12: Schematic of the scanning electron microscope. The high resolution and large depth of ﬁeld is useful for studying defects and also for checking patterning (critical dimensions or CDs) on the product wafers. Adapted from Materials characterization - Yang Leng.

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Figure 13: SEM image of a defect due to trapping of an air bubble in lithography. Source http://spie.org/x19264.xml detected. There are also tilting holders that can be used for capturing cross sections and getting three dimensional information. This is important for imaging patterned wafers, especially to check for lithography process errors. A picture of a bubble defect in lithography, as imaged using the SEM, is shown in figure 13. SEM can also be combined with x-ray chemical analysis (energy dispersive spectroscopy) to obtain chemical information of the defect. This is useful for troubleshooting the origin of the defect and for future mitigation. Defect monitoring systems are used as automated in-line systems i.e. they are part of the process flow, with detailed off-line analysis performed, if needed. For in-line device monitoring, optical microscopes were used earlier and they have now been replaced by SEMs. These provide information on the size, location, and density of defects. Chemical information is usually done offline, when required. These in-line monitoring techniques are chosen because they are fast and conclusive. They can be measured on blank wafers (for batch processes) and patterned product wafers. Product wafers are also scanned at specific locations in the process flow to make sure device dimensions are within specifications. Examples of product dies and process control monitors (PCMs) on a product wafer are shown in figure 14. For product wafers, each die is scanned and the image obtained is compared with the stored image of the mask. This is called a die-to-database system. It is useful for product fabrication where the mask image is fixed. Any differences with the database are flagged and marked for further inspection. In the case of development structures and PCMs, comparisons are made to adjacent dies in the wafer. This is

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Figure 14: Dies and PCMs on a product wafer. There are multiple monitors on a given wafer to ensure uniformity of the process. Adapted from Semiconductor manufacturing and process control - May and Spanos.

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Figure 15: TEM and EDS information on Cu interconnects with Co and TaN barrier layers. With miniaturization, the high resolution available in the TEM is essential for measurement of individual layers, which are usually a few nm thick. Source http://dx.doi.org/10.1063/1.4861876 die-to-die inspection and is used for understanding lateral variations in the process. Defect inspection and control is important since it directly affects performance. On line inspections are also supported by other techniques like transmission electron microscopy (TEM). TEM is a slow process (due to sample prepa- ration) but it has the highest resolution. TEM with chemical information (EDS) is an efficient off line tool for product development and troubleshooting. Figure 15 is a high resolution TEM image (with EDS information) of a Cu trench filling (for interconnects) with a Co liner and TaN barrier layer. Due to the high resolution in the TEM, it is possible to identify the locations of the various chemical elements used for forming the interconnects. This is of great help in product development.