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ECE 271 Final Project ECE 271 Final Project These students agreed to their work being shared for the benefit of future course offerings. June 2017 Contents 1 Introduction 3 1.1 Project Deliverables...................................3 2 High Level Description4 2.1 Top Level Hardware Diagram..............................4 2.2 Top Level HDL Schematic................................5 3 Controller Descriptions6 3.1 Button Board Description................................6 3.2 N64 Controller Description...............................6 3.3 VCR Controller Description...............................7 3.4 NES and SNES Input..................................8 3.4.1 NES Controller..................................8 3.4.2 SNES Controller.................................9 4 HDL Components 10 4.1 Top Module Components................................ 10 4.1.1 Active Controller Selector............................ 11 4.1.2 Active Console Selector............................. 12 4.1.3 1MHz Clock Divider Module.......................... 12 4.2 Button Board Top Module................................ 12 4.3 N64 Button Reader (Top Module)........................... 13 4.3.1 N64 Counter Module............................... 13 4.3.2 N64 Flip Data Mode Module.......................... 14 4.3.3 N64 Read Module................................ 14 4.3.4 N64 Send CMD Module............................. 14 4.3.5 N64 Send CMD Trigger Module........................ 15 4.3.6 N64 Button Decoder............................... 15 4.4 VCR Remote Top Module, Remote Translator.................... 16 4.4.1 Negative Counter Module............................ 16 4.4.2 Positive Counter Module............................ 17 4.4.3 Button Identification Module.......................... 17 4.4.4 Signal Interpreter Module............................ 17 4.5 Shared Modules...................................... 18 4.5.1 Shift Register SIPO............................... 18 4.5.2 12-bit Parallel-In-Serial-Out Shift Register Module.............. 18 4.5.3 8-bit Parallel-In-Serial-Out Shift Register Module............... 19 5 Appendix 19 5.1 Design Synthesis and Analysis.............................. 19 5.2 Source Code........................................ 19 5.2.1 top_module.................................... 19 5.2.2 n64_button_reader............................... 21 5.2.3 n64_send_cmd.................................. 22 5.2.4 n64_read..................................... 23 5.2.5 n64_counter................................... 24 5.2.6 flip_data_mode................................. 24 5.2.7 n64_send_cmd_trigger............................. 25 5.2.8 shift_register_SIPO............................... 25 5.2.9 shift_register_PISO............................... 26 5.2.10 shift_register_PISO_12bit........................... 26 5.2.11 remote_translator................................ 27 5.2.12 signal_interpreter................................ 27 5.2.13 positive_counter................................. 28 5.2.14 negative_counter................................. 29 5.2.15 button_identification.............................. 29 5.2.16 active_console.................................. 30 1 5.2.17 active_controller................................. 30 5.2.18 clock_counter_1MHz.............................. 31 5.3 Simulation Results.................................... 32 5.3.1 n64_send_cmd Module Simulation....................... 32 5.3.2 n64_counter Module Simulation........................ 33 5.3.3 flip_data_mode Module Simulation...................... 34 5.3.4 n64_send_cmd_trigger Module Simulation.................. 34 5.3.5 shift_register_SIPO Module Simulation.................... 35 5.3.6 shift_register_PISO_8bit Module Simulation................. 35 5.3.7 remote_translator Module Simulation..................... 36 5.3.8 signal_interpreter Module Simulation..................... 38 5.3.9 positive_counter Module Simulation...................... 39 5.3.10 negative_counter Module Simulation...................... 41 5.3.11 button_identification Module Simulation................... 42 5.3.12 active_console Module Simulation....................... 43 5.3.13 active_controller Module Simulation...................... 43 5.3.14 clock_counter_1MHz Module Simulation................... 44 2 1 Introduction Figure 1: An N64 controller. c Wikipedia, 2017. The purpose of this project is to implement a digital logic design that is capable of using either a remote control, an N64 controller, or an eight push-button board (created in ECE272 lab) and apply functionality for a Nintendo Entertainment System (NES) console or Super Nintendo Entertainment System (SNES) console. Neither of these devices would traditionally be functional with an NES or SNES console, but by designing logic that can shift the inputs of the controller as well as using several decoders and other modules, an output can be given to the system. Two decoders will be implemented to convert the N64 controller data and the remote data respectively into proper NES or SNES logic input. The data sent from the button board will not require such, and all three will be factored into a multiplexer that will, based on input wires, select a controller and send its data to a de-multiplexer which will then select either the NES or SNES console. This project has been offered and completed by several prestigious organizations, such as the University of Michigan[1] and the University of California at Berkeley[2]. The N64 controller, according to the University of Michigan’s design manual, describes the interfacing of an N64 controller as a challenging but intriguing feat because of hardware considerations, data protocol, and overall complexity. The University of California at Berkeley’s lab instructions specify for technical instructions, such as how to serialize data between the N64 controller and the device acquiring it. Mapping the various codes are vital to success, but various signals, such as clock, reset, and the serial data line, are all equally important as they provide transmitting and receiving capabilities. 1.1 Project Deliverables • Supports communication protocol from both the NES and SNES consoles. • Implements button board, N64 controller and VCR remote interface to emulate NES and SNES controller inputs • (Extra Feature) User can select input flow from the listed controllers and forward to console. 3 Figure 2: The Nintendo Entertainment System. c Wikipedia, 2017. 2 High Level Description 2.1 Top Level Hardware Diagram Figure 3: Hardware Diagram of the Button Board, N64 Controller, VCR Remote, FPGA, and NES Console Inputs: This reads signals from a VCR remote, a N64 controller, or a button board Outputs: This is the converted signal from a controller that is read by an NES or SNES con- sole. Description: As shown in the hardware diagram above, the button board, N64 controller, and VCR remote are all connected to the FPGA. The button board and FPGA are connected by pins J8, 4 J7, J6, J5, J4, J3, J2, J1 to pins 107, 106, 105, 104, 100, 99, 98, 97 respectively and GND to GND. Each of the pins on the button board correspond to a button which would be on a simple Nintendo controller: Up, Down, Left, Right, A, B, Start, and Select. The N64 and the FPGA are connected by VCC to 3.3V, Data to pin 69, and GND to GND respectively. The VCR sends a signal that the FPGA receives on pin 120. The FPGA is then connected to the NES console through pins 112, 111, 110, and 109 to Data, Clock, Latch, and Reset respectively. 2.2 Top Level HDL Schematic Figure 4: Top module of the various module components, the button board, the N64 controller, the VCR remote, and the NES console Inputs: This takes data from a VCR remote, a N64 controller, or a button board. Outputs: This is the converted signal from a controller that is read by an NES or SNES con- sole. Description: As shown in the top level HDL schematic above, the N64 controller and the VCR remote go into decoders that process information and prepare it to be read into the multiplexer module. The button board is able to take its raw input and read it into the multiplexer module. The multiplexer reads inputs of 8 bits, which is why the N64 controller and the remote have to be converted but the button board doesn’t (as by default, the button board already gives an 8-bit input). Then, with the selection of various inputs for the A and B wires, a controller will be chosen to be read for the NES or SNES console. A data bus wire is used to connect them together. A 4MHz oscillator is also implemented to account for timing and converted to a 1MHz signal. A clock divider is used to achieve this. 5 3 Controller Descriptions 3.1 Button Board Description The push button board takes in an 8-bit bus, each bit corresponding to a button input. The buttons are active low, thus a 0 is sent to the FPGA when pressed and a 1 when not pressed. The 8-bit input is sent to a parallel-to-serial converter. This type of shift register will load 8 bits in parallel and then under a clock, shift each bit out of the register serially one bit at a time. The shift register has clock input, clk, from the NES, reset input, load input, an 8-bit parallel input, d, and a serial output, Sout [3]. An example of a shift register with a parallel load is shown in Figure 5. Figure 5: Shift Register with Parallel Load, 2012 3.2 N64 Controller Description Figure 6: The black box diagram for the N64 shows how each of the modules are interconnected. The N64 controller connects to the FPGA through three connections: GND, Data, and VCC and can handle a maximum voltage of 3.6V.
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