Gate and Base Circuits and Protection

Table of Contents Page

Chapter 5 Gate and Base Circuits and Protection ...... 235 Objectives of Chapter ...... 235 5.1 Gate and Base Drive Circuits...... 235 Objectives ...... 235 5.1.1 Introduction...... 235 5.1.2 MOSFET Gate Drive Circuits ...... 236 5.1.3 Bipolar Junction Transistor Drive Circuits ...... 238 5.1.3.1 Switch-on Control ...... 239 Activity 5.1 ...... 241 Suggested Answer for Activity 5.1 ...... 241 5.1.3.2 Switch-off Control ...... 242 5.1.3.3 Proportional Base Control ...... 243 5.1.3.4 Anti-Saturation Control ...... 244 Activity 5.2 ...... 247 Suggested Answer for Activity 5.2 ...... 247 Test 5.1 ...... 247 Solution for Test 5.1 ...... 248 5.1.4 Isolation of Gate and Base Drive Circuit ...... 249 5.1.4.1 Pulse Transformer Method ...... 251 5.1.4.2 Optocoupler Isolation Method ...... 251 Activity 5.3 ...... 252 Suggested Answer to Activity 5.3 ...... 252 5.1.5 Thyristor Drive Circuit ...... 253 5.1.6 Unijunction Transistor ...... 255 5.1.7 Programmable Unijunction Transistor ...... 259 Activity 5.4 ...... 262 Suggested Answer to Activity 5.4 ...... 262 Test 5.2 ...... 263 Solution to Test 5.2 ...... 263 5.1.8 Gate Drive Integrated Circuit ...... 264 5.1.9 Summary ...... 265 5.2 Device and Circuit Protection ...... 265 Objectives ...... 265 5.2.1 Introduction...... 265 5.2.2 Cooling and Heat Sinks ...... 266 Activity 5.5 ...... 273 Suggested Answer to Activity 5.5 ...... 273 Test 5.3 ...... 274 Solution to Test 5.3 ...... 274 5.2.3 Thermal Modeling of Power Switching Devices ...... 275 5.2.3.1 Electrical Equivalent Thermal Model ...... 275 5.2.3.2 Mathematical Thermal Equivalent Circuit ...... 277 Activity 5.6 ...... 278 Suggested Answer to Activity 5.6 ...... 278 5.2.4 Reducing Loss with Snubber Circuits ...... 278 - i - Table of Contents Page

5.2.5 Reverse Recovery Transients...... 280 5.2.6 Voltage Protection ...... 283 Test 5.4 ...... 284 Solution to Test 5.4 ...... 285 5.2.7 Current Protection...... 285 5.2.8 Summary ...... 288 Summary of Chapter ...... 288 Reference ...... 289 Glossary ...... 289

- ii - List of Figures Page

Figure 5.1: Fast switch-on MOSFET switching circuit ...... 237 Figure 5.2: Totem pole gate drive circuit with pulse-edge shaping ...... 238 Figure 5.3: The waveform of the base current for a BJT base drive ...... 239 Figure 5.4: (a) Circuit for base current peaking during switch-on and switching-off conditions and (b) the input waveform ...... 240 Figure 5.5: (a) Base current peaking circuit for different switch-on and switch-off requirements and (b) the input waveform ...... 243 Figure 5.6: A circuit shown proportional base current control ...... 243 Figure 5.7: A Baker collector clamping circuit ...... 245 Figure 5.8: Single phase H-bridge inverter (a) Circuit and (b) gate signals ...... 250 Figure 5.9: Gate voltage between gate and ground ...... 250 Figure 5.10: (a) A pulse transformer isolation base drive circuit and (b) pulse signal ...... 251 Figure 5.11: An optocoupler isolation circuit ...... 252 Figure 5.12: A photo-silicon control rectifier isolation circuit ...... 253 Figure 5.13: A pulse transformer isolation circuit for triggering SCR circuit ...... 254 Figure 5.14: (a) Input pulse and (b) output pulse as SCR triggering voltage ...... 254 Figure 5.15: Construction and symbol of unijunction transistor ...... 255 Figure 5.16: Equivalent circuit of unijunction transistor ...... 255 Figure 5.17: Characteristic curve of UJT ...... 256 Figure 5.18: UJT circuit triggering an SCR circuit...... 258 Figure 5.19: Load line of UJT triggering circuit...... 258 Figure 5.20: Waveform at the node E and B1 of UJT circuit shown in Fig. 5.18 ...... 259 Figure 5.21: Programmable unijunction transistor PUT ...... 260 Figure 5.22: Biased circuit of PUT and its characteristic ...... 260 Figure 5.23: PUT relaxation oscillator and its characteristic ...... 261 Figure 5.24: Illustration of gate drive circuit for (a) power MOSFET and IGBT ...... 264 Figure 5.25: Rate of flow of energy in a conductor of different end temperature ...... 266 Figure 5.26: Illustrating heat flows from device through different material to atmosphere ... 267 Figure 5.27: Electrical model of heat transfer from a device ...... 268 Figure 5.28: Thermal resistance characteristics of heat sink 431 and 433 ...... 269 Figure 5.29: Heat pipe of heat transfer ...... 270 Figure 5.30: The instantaneous junction temperature (Tj(t)) of the device when it is pulsed with rectangular power pulses ...... 272 Figure 5.31: (a) Approximation of a power pulses by a rectangular power pulses and (b) the junction temperature (Tj(t)) ...... 273 Figure 5.32: Electrical transmission line equivalent circuit for modeling heat transfer ...... 276 Figure 5.33: Thermal equivalent elements for modeling heat condition of a transistor with solid slab ...... 277 Figure 5.34: Electrical model of heat flow system without considering the internal temperature distribution ...... 278 Figure 5.35: Snubber circuit ...... 279 Figure 5.36: Snubber equivalent circuit during recovery ...... 280 Figure 5.37: Recovery transient: (a) Recovery current and (b) transient voltage ...... 280 Figure 5.38: Voltage protection using selenium diode with different configuration. (a) Polarized configuration, (b) unpolarized configuration, and (c) polarized three- phase configuration ...... 283 - iii - List of Figures Page

Figure 5.39: Fuse used after power supply to protect device and circuit ...... 286 Figure 5.40: Fuse placed in series with device for individual device protection ...... 286 Figure 5.41: Fuse current during melting and arcing ...... 287 Figure 5.42: Current-time characteristic of fuse and device: (a) complete protection and (b) short circuit protection due characteristic cross at time 0.1s ...... 288

- iv - Chapter 5 Gate and Base Circuits and Protection

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Objectives of Chapter

By the end of the chapter, learners should be able to:

 Identifythe gate characteristic and requirements for designing gate drive circuit using BJTs, MOSFET, and thyristor.  Identify the gate characteristic and requirements for designing base drive circuit using BJTs and MOSFET  Develop the isolation techniques between low power drive circuit and high power load circuit to prevent short and protect the operator from high voltage, high current hazard.  Identify the functional requirements and implementation technique of gate drive IC’s.  Apply the electrical analog of thermal models and methods for cooling power device.  Develop the methods for protecting devices from excessive high rate of current flow and high rate of voltage change.  Detemine how to select fast response fuse for protecting power device.

5.1 Gate and Base Drive Circuits Objectives

By the end of this section, learners should be able to:

 Identity the gate characteristic and requirements of BJTs, MOSFET, and thyristor.  Design gate and base drive circuit for converter.  Develop the isolation techniques interface in between low power drive circuit and high power load circuit.  Identify the functional requirements and implementation technique of gate drive IC’s.

5.1.1 Introduction

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The gating circuit is an integral part of a power converter that consists of power semiconductor devices. The output of this circuit is used to control voltage converter. The output of the voltage converter irrespective of whether it is a dc-to-dc or other configuration depends on the switching characteristics of the gating circuit.

The design of gating circuits is very much depending on the understanding of the gate characteristics and knowledge of devices such thryristor, bipolar junction transistor, field effect transistor (MOSFET), insulated gate bipolar junction transistor (IGBT) etc, whereby some of these devices have been leant by learner in the earlier units.

Owing to reverse recovery process of power devices and switching action in the presence of inductance, voltage transient in the voltage converter circuit, short-circuit fault condition can be exist that may cause excessive current flows in the device; resulting malfunction of the device. The heat produced by semiconductor devices need to be dissipated effectively so that the temperature of the device is within the temperature operating limits at all time. Thus, methods for protecting against excessive current consumption, over voltage stress, and temperature heating are the main issues that learner will learn from this unit.

5.1.2 MOSFET Gate Drive Circuits MOSFET is voltage-controlled device and has high input impedance and very low gate leakage. The switch-on time of an MOSFET is depending on its time constant and the external capacitance, whereby the time constant is a function of its switch-on channel resistance, gate capacitance, and drain capacitance. The switch-on time of the MOSFET can be reduced by connecting an RC circuit as shown in Fig. 5.1 to improve the charge time. When the gate voltage

(VG) is just connected, the initial gate current (IG) is equal to

VG IG  (5.1) Rs

where Rs is the internal resistance of the gate signal. At steady state, the gate-to-source (VGS) of the MOSFET is equal to

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RGVG VGS  (5.2) Rs  R  RG

Figure 5.1: Fast switch-on MOSFET switching circuit

In order to achieve switching time below 100ns, which shall mean small time constant, the gate drive circuit ought to have low output impedance and has the capability to source or sink reasonable large current. A totem pole design structure as shown in Fig. 5.2 can achieve these requirements. The totem pole is designed with two bipolar junction transistors (BJT) connected in common drain configuration that has low output impedance and has reasonable high source and sink current to the control n-channel MOSFET.

The bases of the BJTs are controlled by the output of the comparator, whereby the output of comparator is depending on the gate voltage of the n-channel MOSFET and the input voltage

(Vin). The feedback capacitor (C) regulates the rise time and fall time of the gate voltage. Thus, it controls the rate of rise time and fall time the drain current of the MOSFET. When the output switches from low voltage to high voltage, the output at gate of the MOSFET is switched to high voltage rapidly because of low output impedance of the npn BJT and capacitor value. When the output changes from high voltage to low voltage, the output at gate of the MOSFET is switched to low voltage rapidly because of low output impedance of the pnp BJT and capacitor value. The diode connected across the drain and source of the n-channel MOSFET is used to protect the

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MOSFET from damaging due when the output of MOSFET is rapidly switching from high voltage to low voltage.

Figure 5.2: Totem pole gate drive circuit with pulse-edge shaping

5.1.3 Bipolar Junction Transistor Drive Circuits

The switching time can be improved by reducing the switch-on time (ton) and switch-off time

(toff). The switch-on time can be reduced by allowing the base current of the BJT to reach its peak value IB1 during switch-on resulting low forced beta (f) value at the beginning. After switching-on, the beta value can be increased to sufficiently high value so that it can maintain the BJT in the quasi-saturation region. The switch-off time can be reduced by reversing the base current and allowing the base current to reach its minimum peak value (-IB2) and discharge to zero. Increasing the value of reverse base current will decrease the storage time. Basing on the above statement, a typical waveform for the base current of the bipolar junction transistor drive circuit is shown in Fig. 5.3. This waveform of the base current can be implemented using the circuit shown in Fig. 5.4.

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Apart from fixing peak base current shown in Fig. 5.3, the forced beta (f) may be controlled continuously to match the collector current variation. The common methods used for optimizing the base drive for a transistor are listed as follow.

 Switch-on control.  Switch-off control.  Proportional base control.  Anti-saturation control.

We shall discuss each of these methods in details.

Figure 5.3: The waveform of the base current for a BJT base drive

5.1.3.1 Switch-on Control The base current peaking can be provided by the circuit shown in Fig. 5.4(a). The input voltage

(VB) is subjected to the input waveform as shown in Fig. 5.4(b). When the input is just connected to the circuit, the base current (IB1) is equal to

V1  VBE IB1  (5.3) R1

- 239 - where VBE is the voltage drop across base-to-emitter junction of the bipolar junction transistor.

This is because initially the capacitor (C1) is shorted. After the capacitor is fully charged and become open, the final base current (IBS) is

V1  VBE IBS  (5.4) R1  R2

(a) (b) Figure 5.4: (a) Circuit for base current peaking during switch-on and switching-off conditions and (b) the input waveform

After ignoring the VBE voltage, voltage across the capacitor (C1) is final charged to the value approximately equal to

R 2 VC   V1 (5.5) R1  R 2

The charging time constant (1) is approximately equal to

R1R 2C1 1  (5.6) R1  R 2

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Once the base voltage becomes zero that is after the lapse of time t1 as shown in Fig. 5.4(b), the base-to-emitter junction of BJT is reversed biased. At this instant, the capacitor C1 begins to discharge through R2. The time constant (2) of the discharge is C1R2. In order to allow sufficient charging and discharging, the t1 is set to be at least 51 and t2 is to be at least 52. Based on these criteria, the maximum switching frequency (fs) of the is equal to

1 0.2 fs   (5.7) (t1  t2 ) 1  2

Activity 5.1

The base current circuit shown below has VB = 10 V switched-on for 10 s, C1 = 100 nF, and R1

= 100 , and R2 = 200 . Calculate:

(a). The peak base current. (b). The final base current.

(c). The time constant of charging of capacitor C1. (d). Sketch the waveform of the base current.

Suggested Answer for Activity 5.2

VB  Vd1  VBE (a). The collector current without clamping circuit is IC  . , which is equal to RB 15  2.1 0.7 I 16. = 78.08A. C 2.5

(b). The collector current with clamping circuit can be calculated with equation

VCC  VBE  Vd1  Vd2  IL  , and IC  IL  I1 RC 1  100  0.7  2.1 0.9 Thus, = = 65.4A. 1.5

During normal operation, I1 is I1 IB = 78.08/16 = 4.88A. 16 Thus, the collector with clamping circuit is = I  65.4  4.88= C 116 66.15A.

(c). The collector-to-emitter (VCE) with clamping circuit is

VCE  VBE  Vd1  Vd2 = 0.7  2.1 0.9 =1.9V

Test 5.1

The base current control circuit shown below has R1 = 500, R2 = 1,000, C1 = 10nF, and subjected to a VB waveform shown below.

(a). Calculate the time constants of charging and discharging. (b). Calculate the maximum switching frequency of the circuit.

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(c). Are the switch-on time and switch-off time of the input VB sufficient enough to allow

charging and discharging of capacitor C1?

Solution for Test 5.1

R1R2C1 (a). The time constants charging and discharge are calculated with equations 1  and R1  R2 500x1000x10nF   R C respectively. Thus, they are equal to = = 3.33s, 2 2 1 100 1000

and = 1000x10nF = 1.00s. (b). The maximum switching frequency is calculated using equation 0.2 0.2 fs  = = 46.19kHz. 1  2 3.33s 1.00s

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(c). Since t1 is much larger than 1 and t2 is much larger than 2, the switch-on time and switch-

off time of the input VB sufficient enough to allow charging and discharging of capacitor

C1.

5.1.4 Isolation of Gate and Base Drive Circuit For operating a transistor as a switch, an appropriate gate voltage or base current must be applied to drive the transistor into the saturation mode for a low switch-on state. The control voltages are normally applied to the gate-to-source or base-to-emitter terminals of the devices. The power converters generally required multiple transistors and each transistor has to be gated individually such that the single phase dc-to-ac H-bridge topology arrangement consisting of four n-channel power MOSFET supplying high current and high voltage (Vs) to the load (RL) shown in Fig. 5.8(a).

The logic circuit of the design (not shown in the figure) generates for timing pulse as shown in Fig. 5.8(b). Pulse signal Vgs1 and Vgs2 are used to switch-on MOSFET M1 and M2, while Pulse signal Vgs3 and Vgs4 are used to switch-on MOSFET M3 and M4.

These pulses cannot be directly connected to the gates of transistor M1, M2, M3, and M4 without isolation circuit or interface circuit between the logic voltage logic pulse and high voltage power MOSFET.

(a)

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(b) Figure 5.8: Single phase H-bridge inverter (a) Circuit and (b) gate signals

The importance of gating a MOSFET between its gate and source instead of apply the gate voltage directly between the gate and the ground is shown in Fig. 5.9, where there is a load (RL) connecting between the source and ground of the circuit. In the circuit, the effective gate-to- source voltage (VGS) is equal to

VGs  VG  R LIS (5.16)

Figure 5.9: Gate voltage between gate and ground

There are basic ways of floating or isolating the control or gate pulse with respect to ground. They are pulse transformer method and optocoupler isolation method. We shall discuss these methods.

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5.1.4.1 Pulse Transformer Method Pulse transformer has one primary winding transformer and can have one or more secondary windings. Multiple secondary winding allow simultaneous gating multiple series connected transistors or parallel connected transistor. Figure 5.10 shows a pulse transformer isolated gating drive circuit. The transformer must have low leakage and the rise time and fall time of the pulse should be small. The duration of pulsing should not be too long to prevent the transformer go into saturation.

(a) (b) Figure 5.10: (a) A pulse transformer isolation base drive circuit and (b) pulse signal

5.1.4.2 Optocoupler Isolation Method Optocoupler is consists of an infrared light emitting diode (ILED) and silicon phototransistor. The input signal is applied to the infrared light emitting diode. The ILED is then emitting infrared light to the base of phototransistor, which switch-on the transistor. An example of optocoupler isolation circuit is shown in Fig. 5.11.

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Figure 5.11: An optocoupler isolation circuit

The logic signal from logic circuit generator will switch-on the ILED that with emitter infrared light to switch-on phototransistor Q2. The emitter of Q1 shall be at logic 1 after the phototransistor is switched-on. This voltage is more than the base-to-emitter voltage (VBE) of

BJT transistor Q1. Thus, BJT transistor Q1 switches on. As the result, the collector of this BJT is at logic 0, which does not have sufficient voltage to switch on BJT transistor Q3. Since BJT transistor Q3 is switched-off, the VCC voltage shall become the gate voltage (VG) of n-channel

MOSFET that will switch-on the MOSFET because the gate-to-source voltage (VGS) of value

VDD is certainly higher than the threshold voltage (Vt) of the n-channel MOSFET.

When logic 0 is applied at the input, the opposite of what have been described in the above paragraph is true. This will lead to switch-off the n-channel MOSFET.

Activity 5.3 Logic 0 is connected to optocoupler isolation circuit shown in Fig. 5.11. Mark the logic state at output of all transistors.

Suggested Answer to Activity 5.3 The logic states of all transistors are shown in circuit below.

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5.1.5 Thyristor Drive Circuit The power circuit is usually has more than 100 V and the gate voltage is held at low voltage of typical value between 20V and 30V. An isolating circuit is necessary to separate them. A photo- silicon control rectifier (SCR) isolation circuit is shown Fig. 5.12. A pulse will cause ILED to emit infrared light that trigger the SCR (T1) to switch-on. One the SCR (T1) is triggered, it becomes a low resistance and high current device that the VCC voltage via resistance Rg will trigger the power SCR (TL) to connect voltage source (Vs) to the load RL.

Figure 5.12: A photo-silicon control rectifier isolation circuit

A pulse transformer isolation circuit used to trigger power SCR (T1) circuit is shown in Fig.

5.13. A pulse like the one shown in Fig. 5.14(a) is applied to the input. The transistor Q1 would saturate and induce a pulse as shown in Fig. 5.14(b) at the secondary winding of the transformer. - 253 -

This pulse is then used to trigger the power SCR (T1). Once the SCR (T1) is switched on, becomes a low resistance, high current device connecting the load (RL) and power source (Vs).

To shut-off the SCR (T1), it is necessary to do it by forced commutation or simply switch off the connection of voltage source (Vs) to the load (RL).

Figure 5.13: A pulse transformer isolation circuit for triggering SCR circuit

Figure 5.14: (a) Input pulse and (b) output pulse as SCR triggering voltage

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5.1.6 Unijunction Transistor The unijunction transistor UJT is a three-terminal device whose basic construction is shown in Fig. 5.15. The device is not a JFET. Notice it has terminals labeled as base 1 and base 2, and emitter.

Unijunction transistor has one pn junction. Thus, its characteristic is very different from those of BJT or field effect transistor (FET).

(a) Basic construction (b) Symbol Figure 5.15: Construction and symbol of unijunction transistor

The equivalent circuit of UJT is shown in Fig. 5.16.

(a) (b) Figure 5.16: Equivalent circuit of unijunction transistor - 255 -

Unijunction transistor can be represented by a diode, a fixed bulk resistance (rB2) betweeen Base

2 and emitter, a variable resistance rB1 between emitter and base 1, and a diffusion resistance rD.

As the emitter current IE increases, the variable resistance rB1 will decrease. Depending on emitter current IE, rB1 can be varied from several thousand ohm to tens of ohms. The total resistance RBB shall then be equal to sum of rB1 and rB2. Once the UJT is turned-on, the diffusion resistance rD will be decreased as the injection density of hole from p-type into n-type is higher than the density of n-type.

rB1 and rB2 form a voltage divider when the device is biased as shown in Fig. 5.16(b) when emitter current IE = 0. The voltage across the resistance (rB1) V  can be expressed as rB1

 r  V   B1 V (5.17) rB1   BB  rBB  IE 0

The ratio of r /r is an UJT characteristic called intrinsic standoff ratio . Thus, V voltage is B1 BB rB1 equal to V  V . The characteristic curve of UJT is shown in Fig. 5.17. rB1 BB

Figure 5.17: Characteristic curve of UJT

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As long as the applied emitter voltage V  is less than V  V , there is no emitter current EB1 rB1 pn

(IE) because the pn junction is not forward-biased. The value of emitter voltage (VEB1), which causes the pn junction to become forward-biased, is called peak-point voltage (VP) and this voltage is expressed as

Vp =VBB + Vpn (5.18)

When V reaches peak voltage (V ), the pn junction become forward-biased and emitter EB1 p current (IE) begins to increase.

After switching-on, the UJT operates in a negative resistance region up to the emitter current (IE) equals to valley current (IV), whereby the device saturates.

At switch-on, the hole is injected into n-type. The increase of hole causes an increase of free electron. This in turn increases the conductivity between emitter and base B1 resulting decrease in rB1 and rD resistance. This also causes the current to flow in opposite direction and resulting in overall decrease of current. This is the region of negative resistance. When the applied VE voltage reaches valley voltage (VV), the device is saturated. After this voltage point, the increase of VE results a small increase of emitter current (IE).

UJT is often used as trigger device for SCR and triacs. Other application includes non- sinusoidal oscillator, sawtooth generator, phase control, and timing circuit. An application of UJT used as a trigger for SCR circuit is shown in Fig. 5.18.

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Figure 5.18: UJT circuit triggering an SCR circuit

A condition for ensuring UJT to switch-on is to make sure the load line of the circuit is passing through the negative resistance region of the characteristics curve as shown in Fig. 5.19. The

VBB  VV VBB  VP value of resistor R1 should be set such that it is in between and . On top of I V I P this condition, the voltage VR2 at base1 of the UJT should not be greater than the switch-on gate voltage of SCR when it is on turn-off condition. This voltage is calculated based on VR2 = R V 2 BB . R1  rB1  rB2 IE 0

Figure 5.19: Load line of UJT triggering circuit - 258 -

When the UJT circuit shown in Fig. 5.18 is first switched-on, the VBB voltage will begin to charge up the capacitor C through resistor R . When the V voltage reaches the peak voltage 1 EB1

(VP), the UJT switched on. The charge on capacitor C begins to discharge through resistance R2 until VE1 reaches the valley voltage (VV). At this point the UJT switches-off. Thus, another cycle of charging and discharging repeats. The time constant (1) of charging is equal to R1C and the time constant (2) of discharging is equal to R2C. The period (T) of oscillation is

1  1  T   RC ln   (5.19) f 1  

The waveform at node E and B1 of UJT transistor circuit shown in Fig. 5.20 is shown in Fig. 5.19.

Figure 5.20: Waveform at the node E and B1 of UJT circuit shown in Fig. 5.18

5.1.7 Programmable Unijunction Transistor The structure of programmable unijunction transistor PUT is same as SCR except the gate is connected to n-type layer instead of p-type layer in the case of SCR. The structure and symbol of PUT are shown in Fig. 5.21.

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(a) Basic construction (b) Symbol Figure 5.21: Programmable unijunction transistor PUT

When the anode voltage exceeding the gate voltage by approximately 0.7V, the pn junction is forward-biased and PUT would switch-on. The gate can be biased to a desired voltage with an external voltage divider circuit as shown in Fig. 5.22. When the anode voltage exceeds this “programmed” voltage level by 0.7V, PUT is switched-on.

(a) Circuit (b) Characteristic curve Figure 5.22: Biased circuit of PUT and its characteristic

There are many applications for PUT. One of them is the relaxation oscillator as shown in Fig. 5.23.

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(a) Relaxation oscillator (b) Waveform of the relaxation oscillator Figure 5.23: PUT relaxation oscillator and its characteristic

The period T of the relaxation oscillator can be calculated using the universal charging/discharging equation. The charging voltage is from VV to VP and the discharging voltage is from VP to VV. The period T found to be equal to  V  V   V  T =  BB V  +  P  (5.20) R1Cln   R 4Cln    VBB  VP   VV 

R 3 where VP is the peak-point voltage and it is equal to Vp =  VBB + Vpn. The valley R 2  R 3 voltage VV is normally small as compared with supply voltage VBB and R4 is also small as compared with R. The period T of the relaxation oscillator can be approximately equal to

 V   BB  T  R1Cln   (5.21)  VBB  VP 

The instantaneous voltage across the capacitor VC is equal to VP when the PUT is turned on. The voltage drop across resistor R1 is equal to VBB – VP. It would give rise to anode current (IA)

VBB  VP equal to I A  . If the anode current IA is less than the peak current IP, the PUT will not R1 be switched on. Thus, the maximum resistance value of R1 should be

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VBB  VP R1max = (5.22) I P

To ensure there is oscillation, the value of anode current IA should be less the valley current IV.

VBB  VV Since anode current is equal to IA  . The minimum resistance value of R1 should be R1

VBB  VV R1min = (5.23) I V

Activity 5.4 The programmable unijunction transistor PUT relaxation oscillator circuit shown below has turn-on resistance equals to 70 and the forward pn junction voltage equals to 0.70 V. (a). Calculate the voltage value that the capacitor C will begin to discharge. (b). If we assume the full charging and discharging time of the oscillator is separately equal to 3RC, calculate its frequency?

Suggested Answer to Activity 5.4 (a). The gate voltage of the PUT is 15k/25kx20V = 12.0V. Thus, the voltage that the PUT will switch-on, is 12.0V + 0.70V = 12.70V. The capacitor C will begin to discharge when its voltage reaches 12.7V.

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(b). The time constant (1) of charging is R1C1 = 500k(0.2F) = 0.1s. Thus, the charging time is 0.3s.

The time constant (2) of discharging is (R4+RF)C1 = (15+70)0.2F = 17.0s. Thus, the discharging time is 51s. The period T of the oscillator is 0.300051s. The frequency of the oscillator shall be 3.33Hz.

Test 5.2 Reference to the circuit shown in Activity 5.2, if the switch-on resistance PUT is 50, valley voltage (VV) is 1.0V, valley current (IV) = 10mA, and peak current (Ip) = 10A.

(a). Calculate the frequency of the relaxation oscillator.

(b). Check if the resistance R1 complied to the switch-on and switch-off requirements of the PUT.

Solution to Test 5.2

R 3 (a) The peak voltage VP is equal to  VBB + Vpn = 12.7V. R 3  R 2

 V  V   V  The period of the relaxation oscillator is equal to T =  BB V  +  P  = R1Cln   R 4Cln    VBB  VP   VV   20 1  12.7  500x0.2Fln   + (50 15)x0.2Fln   = 1.2869x10-4s.  20 12.7   1.0 

The frequency of the oscillator is equal to 7,770Hz.

(b). The minimum and maximum values of resistance R1 should be R1min =

VBB  VP 20 12.7 VBB  VV 20 1.0 = = 830.0k and R1max = = = 900. I P 10A I V 10mA

Since the value of resistor R1 is equal to 500, it does not comply with the switching requirement of PUT.

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5.1.8 Gate Drive Integrated Circuit The gate driven circuit for an MOSFET and insulated gate bipolar junction transistor (IGBT) is shown in Fig. 5.24. The circuit needs to satisfy the listed requirements.

 Gate voltage needs to be 10V to 15V higher than the source or emitter voltage. It is

because the power drive is connected to the main high voltage rail (Vs), the gate voltage must be higher than the rail voltage.  The gate voltage which is referenced to ground must be controllable from the logic circuit. Thus, the control signal has to be level shifted to the source terminal of the power devices, which in most application swings between rails.  A low side power device generally drives the high side power device, which is connected to high voltage. Thus, there is one high side power and one low side power device. The power absorbed by the gate drive circuitry should be low and it should not significantly affect the overall efficiency of the power converter.

(a) (b) Figure 5.24: Illustration of gate drive circuit for (a) power MOSFET and IGBT - 264 -

5.1.9 Summary In this sub-section, learner has achieved the learning objectives as specified in the objective section of this sub-topic. Learner has identified the gate and base characteristics and requirements of BJTs, MOSFET, and thyristor devices; how to design gate and base drive circuit for converter; learnt the isolation techniques put in between low power drive circuit and high power load circuit to prevent shorting and protect the operator from high voltage, high current hazard; and learnt the functional requirements and implementation technique of gate drive IC’s.

5.2 Device and Circuit Protection

Objectives

By the end of this section, learners should be able to:

 Apply the electrical analog of thermal models and methods for cooling power device.  Develop the methods for protecting devices from excessive high rate of current flow and high rate of voltage change.  Determine how to select fast response fuse for protecting power device.

5.2.1 Introduction Gate and base drive circuits are operating in hazardous condition especially when it interfaces with high power load circuit. It is necessary to find ways to eliminate this problem. Owing to reverse recovery process of power devices and switching action in the presence of inductance, voltage transient in the voltage converter circuit, a short-circuit fault condition can be exist that can cause excessive current flows in the device resulting malfunction of the device or excessive heat dissipation. The heat produced by semiconductor devices need to be dissipated effectively so that the temperature of the device is within the temperature operating limits at all time. Thus, methods for protecting against excessive current consumption, voltage overstress, temperature heating, and identifying the source of electromagnetic interference and method to minimize it are the main issues that learner will learnt from this sub-section.

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5.2.2 Cooling and Heat Sinks Owing to switch-on state and switching losses, heat is generated within the power semiconductor devices. The heat has to be transferred away from the device to a cooling medium so that the junction temperature of the device can be maintained within the defined range. Although heat can be transferred by conduction, convection, and radiation, or natural or forced air, convection cooling is still popular method used in the industry.

Power (PA) or the rate of flow of energy from one end of the material that has higher temperature to the other end material that has lower temperature as illustrated in Fig. 5.26 follows equation (5.24).

AT hbT P   (5.24) A d d where T is the temperature difference between two ends, A is the cross sectional area, d is the length, and  is the thermal conductivity. For 90% pure aluminum, which is the typical material used for making heat sink, its thermal conductivity () is 220 Wm-1oC-1.

Figure 5.25: Rate of flow of energy in a conductor of different end temperature

Thermal resistance (R) of a material is defined as

T R  (5.25) PA

where PA is the average power loss.

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Substitute T from equation (5.24) into equation (5.25), it yields

d R  (5.26)  A

Often heat flow from the device through several different materials, whereby each material has different thermal resistance. Usually heat flows from device to the case and then to the heat sink in the cooling medium such as what is illustrated in Fig. 5.26.

Figure 5.26: Illustrating heat flows from device through different material to atmosphere

If the average power loss (PA) by the device is known, the electrical model of heat transfer for a device, which is mounted on heat sink as shown in Fig. 5.27, can be drawn out. The junction temperature (TJ) of the device is given by equation (5.27).

TJ  PA R JC  R CS  RSA  (5.27)

o where RJC is the thermal resistance from junction to case C/W; RCS is the thermal resistance o o from case to heat sink C/W; RSA is the thermal resistance from heat sink to ambient C/W; TA is

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o ambient temperature C; TJ is junction temperature; TC is case temperature; TS is heat sink temperature; and TA is ambient temperature. From equation (5.24), one can say that for maintaining the junction temperature within a specified range and at the same time large power loss can be dissipated, the total thermal resistance R JC  RCS  RSA  has to be as low as possible.

Figure 5.27: Electrical model of heat transfer from a device

Thermal resistance from device’s junction to case (RJC) and thermal resistance between casing to heat sink (RCS) are normally specified by the manufacturer of the power semiconductor device.

Once the average power loss (PA) is known, the thermal resistance of the heat sink can be calculated for a specified ambient temperature (TA). Knowing the thermal resistance of heat sink to ambient (RSA), the type and size of the heat sink can be chosen to meet this requirement.

The thermal resistance (R) of a material can be calculated using equation (5.28).

t R   0 C / W (5.28)  A where  is the resistivity, t is the thickness and A is the cross sectional area.

A wide range of aluminum heat sinks are available in the market. They use cooling fins to increase heat transfer capability. The thermal resistance characteristic of a Wakefield heat sink 431 and 433 with natural and forced cooling is shown in Fig. 5.28. In Fig. 5.28, the power dissipation against the sink temperature rise is shown for natural cooling (at the left hand side of the graph). In forced cooling, the thermal resistance decreases with the air velocity as it is shown from the right hand side of the graph to close to left hand side of the graph. - 268 -

As it is shown in Fig. 5.28, above certain forced velocity, the decrease of thermal resistance of heat sink to ambient (TSA) is not significant.

Figure 5.28: Thermal resistance characteristics of heat sink 431 and 433

The contact area between the device and heat sink is extremely important to minimize the thermal resistance between the case and the heat sink. The surface should be flat and smooth, and free of dirt, corrosion, and surface oxide. Silicon grease is normally used to improve heat transfer, and minimize the formation of oxide and corrosion.

The power semiconductor device has to be mounted firmly with the right pressure. However, the mounting procedure usually can be obtained from the heat sink manufacturer.

Besides cooling by heat sink method, cooling the device can be achieved using heat pipe, in which the pipe is partially filled with low vapor pressure liquid. The device is mounted on one side of the pipe and a condensing mechanism or heat sink as shown in Fig. 5.29. The cool liquid comes in contact with the device. Heat is transferred to the liquid. While at cooling fin, the hot

- 269 - liquid vaporized dissipating its heat through the cooling fins. Upon releasing the heat, the vapor condenses to become cool liquid that is re-circulated to the device.

Figure 5.29: Heat pipe of heat transfer

In high power operation, the more effective way to cool down the device is liquid, which can be oil or water. Water cooling is efficient. It is three times more effect than oil. When using water, it is necessary to use distilled water that has no contaminant to prevent corrosion.

The thermal impedance of a power semiconductor device is very small. As the result, the junction temperature of the device varies with the instantaneous power loss. The instantaneous junction temperature (Tj(t)) must always be maintained lower than the permitted value. A plot of the transient thermal impedance with square wave pulsing is shown in Fig. 5.30. This plot is usually supplied by the device manufacturer.

The step response of a first order equation can be applied to express the transient thermal impedance. If Z0 is the steady-state junction case thermal impedance then the instantaneous thermal impedance (Z(t)) can be expressed as

t / th Z(t)  Z0 1 e  (5.29)

where th is the thermal time constant of the device. If the power loss is Pd then the instantaneous junction temperature (TJ) is equal to

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t / th TJ  PdZ(t)  PdZ0 1 e  (5.30)

th If tn is the duration of n power pulse, the corresponding thermal impedances at the beginning th and end of n pulse are respectively equal to Z0 = Z(t =0) and Zn = Z(t = tn). If P1, P2, P3,…. are the power pulses with even pulses being zero i.e. P2 = P4 = …. = 0 then the junction temperature at the end of mth pulse can be expressed as

TJ  TJ0  P1Z1  Z2  P3Z3  Z4  P5 Z5  Z6  .... Pm Zm  Zm1 (5.31) or

m TJ  TJ0  Pn Zn  Zn1  (5.32) n1,3,5..

where TJ0 is the initial junction temperature. The negative sign of Z2, Z4, Z6,… signify that the junction temperature falls during the interval t2, t4, t6,…, where there is no power pulse. Fig.

5.30(b) shows the instantaneous junction temperature (TJ(t)) of the device when it is pulsed with the power waveform shown in Fig. 5.30(a).

(a)

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(b)

Figure 5.30: The instantaneous junction temperature (Tj(t)) of the device when it is pulsed with rectangular power pulses

Based on the above analysis, a waveform of any shape can be represented approximately by rectangular pulses of equal or unequal duration, with amplitude of each pulse equal to the average amplitude of the actual pulse over same period such the one shown in Fig. 5.31(a) and its corresponding junction temperature shown in Fig. 5.31(b). For a more accurate representation of any wave, rectangular pulse of small duration should be chosen.

(a)

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(b) Figure 5.31: (a) Approximation of a power pulses by a rectangular power pulses and (b) the

junction temperature (Tj(t))

Activity 5.5 0 The maximum junction temperature of a bipolar junction transistor is TJmax = 150 C and the 0 maximum power dissipation is 2.0 W at ambient temperature TA = 25 C and 40 W at case 0 temperature TC = 25 C.

(a) Calculate the maximum allowable power dissipation of the transistor operating in ambient temperature of 500C in free air environment (b) Calculate the maximum allowable power dissipation of the transistor operating with heat sink that has sufficient large area and with fan forcing convection.

Suggested Answer to Activity 5.5 0 (a). The thermal resistance between junction to ambient temperature of 25 C is RJA = 1500 C  250 C = 62.50C/W. 2W 0 The thermal resistance between junction to case temperature of 25 C is RJC = 1500 C  250 C = 3.1250C/W. 40W

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The maximum allowable power dissipation at ambient temperature of 500C operating in 1500 C  500 C free air environment is Pdmax = = 1.6W. 62.50 C / W (b). Since the heat sink has sufficient large area and with fan forcing convection, the thermal

resistance between the case to junction RJS and between sink to ambient RSA shall be zero. 0 Thus, the thermal resistance RJA = RJC = 3.125 C/W. 1500 C  500 C The maximum allowable power dissipation is Pdmax = = 32.0W. 3.1250 C / W

Test 5.3 The power loss of a semiconductor device is shown in figure below. From data sheet, the o thermal impedance for various time interval are Z(t = t1) = Z1= Z3 = Z5 = 0.035 C/W and Z(t= t2) o = Z2=Z4= Z6 = 0.025 C/W.

(a). Find change of junction temperature for all time intervals.

(b). Plot the instantaneous junction temperature.

Solution to Test 5.3 (a). The change of junction temperature for all time intervals is listed below.

o o TJ (t 1ms)  0.035 C/ Wx800W = 28 C.

o o o o o TJ (t 1.5ms)  0.035 Cx800W  0.025 C/ Wx800W = 28 C – 20 C = 8 C.

o o o o o TJ (t  2.0ms)  8.0 C  0.035 C/ Wx1200W = 8 C + 42 C = 50 C.

o o o o o TJ (t  2.5ms)  50 C  0.025 C/ Wx1200W = 50 C - 30 C = 20 C.

o o o o o TJ (t  3.0ms)  20 C  0.035 C/ Wx600W = 20 C+21 C = 41 C. - 274 -

o o o o o TJ (t  3.5ms)  41 C  0.025 C/ Wx600W = 41 C – 15 C = 26 C.

(b). The plot of instantaneous junction temperature for all time intervals is shown below.

5.2.3 Thermal Modeling of Power Switching Devices The power generated within a power device increases the device temperature, which in turn significantly affects its characteristics such as mobility, threshold voltage, switch-on channel resistance etc. Therefore, instantaneous device heating should be completed directly with the thermal model of the device and heat sink. The instantaneous power dissipation in the transistor is determined at all times and current proportional to the dissipated power should be fed into the thermal equivalent network. Here we shall look at the electrical equivalent thermal model of how heat is flowed from integrated circuit to heat sink and the mathematical thermal equivalent circuit.

5.2.3.1 Electrical Equivalent Thermal Model The heat path from device to heat sink as shown in Fig. 5.26 can be modeled analogous to the electrical transmission line as shown in Fig. 5.32. The electrical power (Pt) represents the power dissipation from the integrated circuit (device). Rth and Cth are the lumped equivalent parameters of the element with the device.

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Figure 5.32: Electrical transmission line equivalent circuit for modeling heat transfer

Figure 5.33 shows the thermal equivalent element of a typical transistor in a package with solid cooling tab. The thermal equivalent elements can be determined directly from the physical structure. The structure is segmented into partial volume usually by a factor of 2 to 8, with progressively larger thermal time constant (RthCth) in the direction of heat flow. If the heat inducing area is smaller than the cross sectional area of heat conducting material, a heat spreading effect occurs as shown as spreading of shaded area.

The thermal capacitance (Cth) is depending on the specific heat (c), the thickness (d), the mass density (), and cross sectional area (A) that follows expression.

Cth  cdA (5.33)

while the expression of thermal resistance (Rth) is shown in equation (5.28), which is t R   0 C / W and it can be re-expressed as  A

d R  0 C / W (5.34) th A where  is thermal conductivity of the material.

The mentioned parameters like thermal conductivity (), specific heat (c), and the mass density () for a material can be obtained from properties table of the respective material.

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Figure 5.33: Thermal equivalent elements for modeling heat condition of a transistor with solid slab

5.2.3.2 Mathematical Thermal Equivalent Circuit The equivalent circuit shown in Fig. 5.32 is often referred to as the natural or physical equivalent circuit of heat transfer via conduction and describes the internal temperature distribution. If the internal temperature distribution is not needed, which is usually the situation, the thermal equivalent circuit as shown in Fig. 5.34 is frequently used to describe the thermal behavior at the input terminals of the block box heat flow system.

The individual RC element represent the terms of a partial fractional division of the thermal transfer function of the system. Using partial fractional representation, the step response of the thermal resistance can be expressed equation (5.35).

1 Z  (5.35) th 1 sC  th1 1 1  sR th1 1 1  .... sCth 2 R th ,n - 277 -

Figure 5.34: Electrical model of heat flow system without considering the internal temperature distribution

Activity 5.6 The thermal resistance of an aluminum heat sink is 25 K/W, its mass is 2 g; cross sectional area is 1.0 cm2; and thickness 0.4 cm. Given that the specific heat of aluminum is 0.95 J/(gK) and the thermal conductivity is 2.7 g/cm3, calculate the thermal constant of the heat sink.

Suggested Answer to Activity 5.6 o Thermal capacitance of heat sink is Cth  cdA = 0.95/2.7x1x0.4= 0.1407J/ C.

Thermal time constant of heat sink is CthRth = 0.1407x25 = 3.158s.

5.2.4 Reducing Loss with Snubber Circuits If a power converter stresses a power semiconductor device beyond its rating, there are two basic ways to overcome them. The ways are either replacing the device with higher rate or using snubber circuit to reduce the stress to a safe level.

The function of the snubber circuit is to reduce the electrical stress found on a device during switching by a power semiconductor converter to the level within the electrical rating of the device. Explicitly, it is used to reduced the switching stress to a safe level by

 Limiting voltage applied to device during switch-off transient.

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 Limiting device current during switch-on transient.  Limiting the rate of current rise (di/dt) flow in the device during switch-on.  Limiting the rate of voltage rise (dv/dt) across device during switch-off or during re- applied forward block voltage across thyristor.  Shaping of switching trajectory of the device as it switches-on and off.

An RC snubber circuit is normally connected across a semiconductor device to limit the rate of change of voltage (dv/dt) within the maximum allowable rating and rate of change of current (di/dt). The snubber circuits could design as polarized, reverse polarized and un-polarized types.

A forward polarized snubber is suitable when a thyristor or transistor is connected with an anti-parallel diode as shown in Fig. 5.35(a). The resistor R limits the forward dv/dt and R1 limits the discharge current (di/dt) of the capacitor when the device is switched-on.

A reverse polarized snubber, which limits the reverse dv/dt, is shown in Fig. 5.35(b). The resistor R1 limits the discharge current (di/dt) of the capacitor (C). The capacitor does not discharge through the device resulting looses in the device.

When a pair of thyristors is connected in inverse parallel, the snubber must be effective in either direction. An example of an un-polarized snubber circuit is shown in Fig. 5.35(c). It limits the voltage across the thyristor and dv/dt at reverse recovery.

(a) Polarized type (b) Reverse polarized type (c) Un-polarized type Figure 5.35: Snubber circuit - 279 -

5.2.5 Reverse Recovery Transients

Owing to reverse recovery time (trr) and recover current (IR), an amount of energy is stored in the inductance of the circuit. As the result, transient voltage appears across the device. In addition to dv/dt protection, snubber circuit also limits the peak transient voltage across the device. The equivalent circuit of snubber circuit is shown in Fig. 5.36. Initially, when the voltage source (Vs) is just connected, the voltage across the capacitor is zero and the current flowed in the inductor is IR. The diode Dm is used to bypass the current during switching from one polarity to another polarity

Figure 5.36: Snubber equivalent circuit during recovery

The RC value of the snubber circuit is chosen such that it is at slight damping condition so that the voltage spike created is not too high. Figure 5.37 shows the recovery current and the transient voltage. Critically damping usually will end with large value of initial reverse voltage

RIR. However, insufficient damping will cause too high overshoot of the transient voltage, which is not good to the device.

(a) (b) Figure 5.37: Recovery transient: (a) Recovery current and (b) transient voltage

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From the circuit shown in Fig. (5.36), with the assumption the recovery is abrupt, the snubber current (i) is expressed as

di 1 L  Ri  idt  v (t  0)  V (5.36) dt C  c s

di v  V  L (5.37) s dt

With initial current at time t = 0 is equal to IR and voltage across capacitor (vc) at time t = 0 is zero. For under damping case, the solution for equations (5.36) and (5.37) yields the reverse voltage across the device, which is

   t IR t v(t)  Vs  Vs  RI R cost  sin te  e sin t (5.38)    C where R   (5.39) 2L

The undamped natural frequency (0) is

1   (5.40) 0 LC

The damping ratio () is

 R C    (5.41) 0 2 L

The natural damping frequency () is

 2 2 2    0    0 1  (5.42) 0

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Differentiating equation (5.38), it yields

dv  2  2   V  RI 2cost  sin tet dt s R      (5.43) I     R cost  sin tet C   

The initial reverse votlage and dv/dt can be found from equation (5.38) and (5.3) by setting t = 0.

v(t  0)  RI R (5.44)

dv IR Vs  RI R R IR  Vs  RI R 2    dt t0 C L C 2  Vs0 2  4d  d

dv 2  Vs0 2  4d  d (5.45) dt t0 where the current factor (or ratio) d is given by

I L I d  R  R (5.46) Vs C Ip

If the initial dv/dt in equation (5.45) is negative, the initial inverse voltage RIR is maximum and

2 this may produce a destructive dv/dt. For a positive dv/dt, Vs0 2  4d  d 0 or

1 1 4d2   (5.47) 4d

and the reverse voltage is maximum at t = t1. The time t1, where it can be obtained by setting equation (5.43) equal to zero, is found as

Vs  RI R 2  IR/ C tan t1  2 2 (5.48) Vs  RI R     IR / C - 282 - and the peak voltage can be found from equation (5.38), which is

Vp  v(t  t1) (5.49)

The peak reverse voltage depends on the damping ratio () and the current factor (d). For a given value of d, there is an optimum value of damping ratio 0, which minimize the peak voltage. However, the dv/dt varies with d and minimizing the peak voltage may not minimize the dv/dt. It is necessary to make compromise between peak voltage Vp and dv/dt.

5.2.6 Voltage Protection Voltage protection can be done using selenium diode and varistor. Selenium (Se) diode can be used to protect again overvoltage transient, The diode has a low forward voltage and good reverse breakdown voltage. Its current-voltage characteristic is same as the normal silicon diode. When it is in used, it is normally connected reverse bias mode where the current flow in the diode is extremely low, which is basically its reverse saturation current. However, when an overvoltage appears, the reverse saturation current flow through this diode increases suddenly that would reduce the transient voltage and limit it to about twice the normal voltage.

(a) (b) (c) Figure 5.38: Voltage protection using selenium diode with different configuration. (a) Polarized configuration, (b) unpolarized configuration, and (c) polarized three- phase configuration

A selenium diode needs to be able to dissipate the surge energy without increase its temperature. Each selenium diode is normally rate at root mean square voltage of 25 V, with clamping - 283 - voltage of typically 72 V. For protection of dc circuit, the polarized suppression circuit as shown in Fig. 5.38(a) is used. In ac circuit, where ac is bi-directional, unpolarized circuit shown in Fig. 5.38(b) is used. This circuit is able to suppress both voltage transient from generated positive cycle and negative cycle of the ac voltage. For three-phase circuit, suppression circuit shown in Fig. 5.38(c) is used, where transient from each phase voltage (a, b, or c) is suppressed individually with selenium d, e, and f.

If a dc circuit has 240 V is to be protected by 25 V selenium diode then approximately ten diodes needs to be used, in which effectively having a clamping voltage of 720 V. To protect a single phase ac circuit of 208 V, 50 Hz, with 25 V selenium diode, approximately nine selenium diodes are needed for each direction. A total of 18 selenium diodes are needed for both directions, which is the unpolarized design. Owing to low internal capacitance of selenium diode, it does not limit rate of change of current (di/dt). It is not as effective as the normal RC snubber circuit.

Varistor is a non-linear variable impedance device consisting of a metal oxide particle separated by an oxide film or insulation. As the applied voltage is increased, the film becomes conductive and the current flow is increased. The current is expressed by

I  KV  (5.50) where K is a constant and V is the applied voltage.

Test 5.4 Selenium diode is used to protect a three phase circuit as shown in figure below. The three phase voltage is 208 V, 50 Hz. If the voltage of each diode is 25 V, determine the number diode needed for voltage protection.

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Solution to Test 5.4 208 The line voltage is V  = 120.0V rms. s 3

The peak line voltage is 120 2 = 169.7V The number selenium diode per line voltage is 169.7/25 = 6.8 The total number of selenium diode required is 6x3 = 18.

5.2.7 Current Protection Power converter may develop short circuits of fault. Fast response fuse is normally used to protect the semiconductor device. When a short circuit occurred, the fuse burnt and the short circuit would be cleared.

The placement of fuse in the circuit can be critical for protecting the circuit particularly the semiconductor. Fig. 5.39 and Fig. 5.40 show the location for placing the fuse. Fig. 5.39 shows placement after ac and dc voltage. However, in Fig. 5.40, the fuses are placed in series with each device.

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Figure 5.39: Fuse used after power supply to protect device and circuit

Figure 5.40: Fuse placed in series with device for individual device protection

Referrence to Fig. 5.41, when there is a short circuit, the excessive current will flow through fuse that rise the temperature until time t = tm, the fuse melts and arc is developed across the fuse. Owing to arching, the impedance of fuse increased reducing the current. When an arc voltage is formed across the fuse, it vaporizes the fuse element and increases the arc length that would further reduce the current. When the arching completes in t = ta, the fault due to shorting is cleared. Thus, the clearing time (tc) of a current fault is equal to the sum of melting time (tm) and arcing time (ta). Melting time (tm) is dependent on the load current and arcing time (ta) is depending on the power factor or parameters of the fault circuit. Figure 5.41 also shows the prospective fault current, which is maximum fault current if there is no fuse.

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Figure 5.41: Fuse current during melting and arcing

If R is the resistance of the fault circuit and i is the instantaneous fault current between the instant of fault occurring and the instant of arc excitation, the energy (We) fed to the circuit can be expressed as let-through energy

W  Ri2dt (5.51) e 

If the resistance R remains constant, the value of i2t is proportional to the energy fed to the circuit. Thus, i2t value is termed as the let-though energy and is responsible for melting the fuse. The fuse manufacturer specifies the characteristic of fuse such as those shown in Fig. 5.42.

In selection of fuse, it is necessary to estimate the fault current and that satisfy the listed requirements.

 The fuse must be able to carry current as rated by the device rated.

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 The i2t let-through value of the fuse before the fault current is cleared have to be less than the rated of the device to be protected.  The peak arc voltage has to be less than the peak voltage rating of the device.

Figure 5.42: Current-time characteristic of fuse and device: (a) complete protection and (b) short circuit protection due characteristic cross at time 0.1s

5.2.8 Summary In this sub-section, learner has achieved the learning objectives as specified in the objective section of this sub-topic. Learner has learnt to apply the electrical analog of thermal models and methods for cooling power device using heat sink and heat pipe; learnt the methods for protecting devices from excessive high rate of current flow and high rate of voltage change using snubber circuit and fuses; and learnt how to select fast response fuse for protecting power device.

Summary of Chapter

In this unit – Gate and Base Drive Circuits and Protection, learner has learnt two main topics which are gate and base drive circuits, and device and circuit protection. Each topic, learner has studied and achieved what have been specified in the learning objectives of each topic via lecture, learning activities, and tests.

In topic one – Gate and Base drive circuits, learner has learnt and achieved the ability and confidence to explain the gate characteristic and requirements of BJTs, MOSFET, and thyristor - 288 - for design the drive circuit, design gate and base drive circuit for converter, learn the isolation techniques interface in between low power drive circuit and high power load circuit, and learn the functional requirements and implementation technique of gate drive IC’s.

In topic two – Device and Circuit Protection, learner has learnt and achieved the ability and confidence to understand the electrical analog of thermal models and methods for cooling power device, learn the methods for protecting devices from excessive high rate of current flow and high rate of voltage change, and learn how to select fast response fuse for protecting power device.

Reference

1. Muhammad H. Rashid, “Power Electronics: Circuits, Devices, and Application”, 3rd edition, Pearson Prentice Hall 2004. New York. 2. J. Machael Jacob, “Power Electronics: Principles & Application”, Delmar Thomson learning 2002. New York. 3. Mohan, Ned., & Undeland, Tore M., & Robbins, William P., “Power electronics: converters, applications, and design”. (3rd ed.). John Wiley. 2003. New York. 4. Thomas L. Floyd, "Electronic Devices", Prentice Hall International, Inc.,1999. New York.

Glossary

Abbreviation/Symbol Descriptions Vd1 Voltage across diode D1 Vd2 Voltage across diode D2 IC Collector current IB Base current IE Emitter current ID Drain current IS Source current BJT Bipolar junction transistor MOSFET Metal oxide semiconductor VCE Collector-to-emitter voltage VBE Base-to-emitter voltage VCB Collector-to-base voltage  Beta RC Collector resistance RD Drain resistance

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RS Source resistance RL Load resistance ILED Infrared light emitting diode Vt Threshold voltage  Intrinsic standoff ratio SCR Silicon control rectifier PUT Programmable unijunction transistor UJT Unijunction transistor IP Peak current IV Valley current IA Anode current IK Cathode current VV Valley voltage VP Peak voltage fs Switching maximum frequency 1 Charging time constant 2 Discharging time constant IGBT Insulated gate bipolar junction transistor PA Average power loss TJ Temperature of device’s junction TA Ambient temperature TC Case temperature TS Heat sink temperature RJC Thermal resistance from device’s junction to case RCS Thermal resistance from case to heat sink RSA Thermal resistance from heat to ambient trr Reverse recovery time IR Recover current  Damping ratio d Current factor  Thermal conductivity Rth Thermal resistance of an element Cth Thermal capacitance of an element tm Melting time ta Arcing time tc Clearing time

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