AN ABSTRACT OF THE THESIS OF
JAMES DANIEL WAGNER for the M. S. in Electrical Engineering (Name) (Degree) (Major)
Date thesis is presented Lay /y /7- Title A CONTROLLED NEGATIVE- RESISTANCE FOR REALIZATION
OF CERTAIN NETWORK FUNCTIONS Abstract approved ajor professor
A circuit which functions as a controlled negative- resistance is described and analyzed; the circuit contains two transistors, a break- down diode, and five resistors connected in a stable feedback config- uration. From the analysis a set of design equations is derived.
An experimental circuit is described and a comparison between measured performance and design objectives is presented.
Several network synthesis procedures are presented to provide background for experimental realizations using the controlled negative - resistance. The problem of biasing is examined for the synthesis techniques presented.
Two experimental realizations, one providing gain and one pro- viding complex zeros of transmission, are described and performance is compared to theoretical specifications; in both cases the agreement is excellent. A CONTROLLED NEGATIVE -RESISTANCE FOR REALIZATION OF CERTAIN NETWORK FUNCTIONS
by
JAMES DANIEL WAGNER
A THESIS
submitted to
OREGON STATE UNIVERSITY
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
June 1965 APPROVED:
Pro scor of Elect, cal Engineering
In Charge of Major
ad of Depart e t :f i'ectrical Engineering
Dean of Graduate School
Date thesis is presented iY, /96r Typed by Lucinda M. Nyberg ACKNOWLEDGMENTS
Appreciation is gratefully extended to the Department of Electri- cal Engineering of the School of Engineering, Oregon State University, and to Professor Leland C. Jensen for encouragement and assistance with this project. Acknowledgment is also extended to the following individuals and organizations: Mr. Keith Taylor, Instrument Design Engineer at Tektronix, Beaverton, Oregon, for initial suggestions about the negative- resis- tance circuit; Accessories Design Group at Tektronix for making available in-
struments for measuring the high- frequency characteristics of the negative resistance;
Mr. Stuart Eide for writing a computer program used in the analysis of the high -frequency characteristics of the negative re- sistance. TABLE OF CONTENTS
Page
I. INTRODUCTION 1
II, NEGATIVE -RESISTANCE DEVICES 2
III. A CONTROLLED NEGATIVE -RESISTANCE .. . 5 3. 1 Basic Circuit Analysis 5 3. 2 Detailed Circuit Analysis 9 3. 3 Design Procedure 19
IV. EXPERIMENTAL CONTROLLED NEGATIVE- RESIS- TANCE 23 4. 1 Design 23 4. 2 Performance 24 4. 3 Secondary Considerations .. 26
V. NEGATIVE RESISTANCE SYNTHESIS TECHNIQUES. . 31 5. 1 Background 31 5. 2 Larger RC- Ladder Gain Realizations . 33 3 5. Nonminimum -Phase RC-Transfer Functions . . 37 5. 4 Arbitrary Zero of Transmission 40 5. 5 Biasing 42
VI. EXPERIMENTAL NETWORK REALIZATIONS . 47 6. 1 RC- Ladder with Gain ...... 47 6. 2 Arbitrary Zeros of Transmission . . . 51
SUMMARY AND CONCLUSIONS 57
BIBLIOGRAPHY 59
APPENDIX I 61 Measurement of Negative Resistances 61 LIST OF FIGURES
Figure Page
2. 1 Negative resistance types ...... 3
2. 2 Typical tunnel diode characteristic curve . . 4
2. 3 Tunnel diode equivalent circuit . 4
3. 1 A portion of the controlled negative- resistance cir- cuit 5
3. 2 Simplified transistor equivalent circuit 6
3. 3 Region I equivalent of Figure 3. 1 6
3. 4 Region II equivalent of Figure 3 1 6
3. 5 Region III equivalent of Figure 3. 1 . 7
3. 6 Current amplifier 8
3. 7 Input voltage- current characteristics 8
3. 8 Controlled negative- resistance circuit . 9
3. 9 Component large - signal equivalent circuits - . . 9
3. 10 Large- signal equivalent circuit of Figure 3. 8 . . 10
3. 11 Region A equivalent of Figure 3. 10 11
3. 12 Region B equivalent of Figure 3. 10 . . . . 11
3. 13 Region C equivalent of Figure 3. 10 13
3. 14 Region D equivalent of Figure 3. 10 . 14
3. 15 Region E equivalent of Figure 3. 10 . . 16
3. 16 Region F equivalent of Figure 3. 10 18
3. 17 Detailed input characteristic curve 19 Figure Page
4. 1 Experimental characteristic curve . . . . 25 dI 4. 2 Terminal conductance as a function of terminal voltage for circuit designed in Section 4. 1 . . 27
4. 3 Terminal admittance, G + jB, as a function of fre- quency (circuit similar to Section 4. 1) 28
4. 4a Negative impedance converter equivalent . . . . 29
4. 4b A reorientation of Figure 3. 8 to emphasize negative impedance converter form. . . 29
4. 5a Effect of high frequency oscillation on the charac- teristic curve . . . . 30
4. 5b Same circuit as Figure 4. 3a with addition of sup- pressor beads 30
5. la Negative resistance equivalent circuit 32
5. lb Passive parallel RC circuit 32
5. 2 Pole -zero configurations illustrating procedure for
realizing RC transfer functions with gain . . . . 36 E 5. 3 Network form for realizing RC G12 with = É gain i 37
5. 4 Pole zero plot for example of section 5. 3 . . 39
5. 5 General form for nonminimum -phase transfer . . 39
5. 6 Network form for arbitrary zero realization . . . 40
5.7 Biasing of negative resistance ...... 42
5. 8 Bias scheme for Figure 5. 3 . . . 43
5. 9 Illustration of first step to realize zero at s = a . 44
5. 10 Network realization of transmission zero at s = a after first two steps . 44 Figure Page
5. 11 Derivation of bias feasibility 46 H 6. 1 Realization for with gain . 49 G12(s) = (s +1) s +10)
6. 2 Network realized from Figure 6. 1 . . 49
6. 3 Frequency response curve for network shown in Figure 6. 2b 50 2 6. of G 53 4 Illustration realization for '
6. 5 Modification of N to equalize transmission coef- ficients .a . . 54 (s2 +1) 6. 6 Network for realization of G12 = s +4 s +16 scaled to 1 kc ...... (. .)(. . ) 55
6. 7 Frequency response curve for network shown in Figure 6. 6 56
I. 1 Simple curve tracer for two -terminal devices . 61
I. 2 Bridge for measuring negative resistance . . . .. 62
I. 3 Circuit for measuring negative resistance . . . . 63 A CONTROLLED NEGATIVE -RESISTANCE FOR REALIZATION OF CERTAIN NETWORK FUNCTIONS
I. INTRODUCTION
Since the advent of the tunnel diode in 1958, several procedures
of synthesizing networks using tunnel diodes have been developed. Tunnel -diode networks have several advantages over conventional
resistance- capacitance (RC) networks; a tunnel -diode network can provide greater gain than can a pure RC network, and a tunnel diode
and RC network in ladder form can realize transmission functions im- possible to realize with an RC ladder without tunnel diodes. Tunnel diodes, however, have characteristics which limit their usefulness as network elements; the magnitude of the negative- resistance is highly nonlinear, the capability of handling signals great- er than a few hundred millivolts is greatly limited, there is limited choice of values of negative -resistance which can be provided, and the repeatability of negative- resistance values for diodes of the same type is generally poor.
The controlled negative- resistance to be described overcomes many of the limitations of tunnel diodes. The magnitude of the negative -resistance is quite linear over a large portion of the oper- ating range, signal handling capability is the choice of the designer, and almost any value of negative resistance may be obtained with good repeatability. 2
II. NEGATIVE- RESISTANCE DEVICES
Negative resistance is an electrical characteristic defined as
either a decrease in current with increasing voltage if voltage is the independent variable or, conversely, a decrease in voltage with in- creasing current if current is the independent variable.
A number of electrical devices and circuits exhibit negative re-
sistance. Some devices have been known for many years; examples are the electric arc (1, p. 492) and the dynatron (2, p. 5). Vacuum - tube negative- resistance circuits have been built for telephone re- peater applications (1, p. 506; 7, p. 98). Advances in solid -state technology have produced a number of devices and numerous circuits exhibiting negative resistance; these include the tunnel diode (9, p.
1203), the unijunction transistor (3, p. 2), the four -layer diode (8, p. 9), negative -impedance converters (5, p. 726), and various other composite circuits (10, p. 326; 11, p. 25).
A negative resistance may be classified according to the shape of its characteristic curve. The two basic types are shown in Figure
2, 1.
Figure 2.1(a), an N -type negative- resistance, is considered cur- rent controlled since voltage is a single- valued function of current.
Figure 2.1(b), an S -type negative resistance, is considered voltage controlled since current is a single- valued function of voltage. 3
Voltage Voltage
Current Current
( a) N- Type (b) S-Type
Figure 2.1. Negative resistance types.
A positive- resistance, by definition, dissipates energy; convers- ely, a negative resistance supplies or converts energy. Since no physical device can supply an infinite quantity of energy, any negative- resistance must be bounded by two positive -resistance regions in a manner similar to the characteristic curves indicated in Figure 2.1. In general, negative- resistances are not pure resistances but have some associated reactances. There is, at least, always some shunt capacitance which is inherant to all physical devices.
An example of limitations present in negative resistances is pro- vided by the tunnel diode; a typical tunnel diode characteristic curve is indicated in Figure 2,2 and an equivalent circuit is given in Figure 2. 3
(9, p. 1203). 4
Milli amp s L5 Rs
o
1 0 2 0 3 0 Mil.livolts
Figure2.2. Typical tunnel diode Figure2.3. Tunnel diode equiva- characteristic curve. lent circuit.
Negative resistances have many practical applications. Negative - impedance telephone repeaters have already been mentioned. Several network -synthesis methods have been developed using negative-imped- ance converters (4, p. 555 -64; 15, p. 140 -44). Tunnel diodes are used extensively as microwave oscillators, amplifiers, and convert- ers, as logic elements, and as network synthesis elements (9, p.
1201 -6; 6, p. 357 -62; 13, p. 80 -87; 14, p. 116 -20). 5
III. A CONTROLLED NEGATIVE -RESISTANCE
3. 1 Basic Circuit Analysis
A simple analysis of the circuit in Figure 3. 1 will reveal three regions of operation as the voltage, V, increases from zero. These
regions will be designated Regions I, II, and III in order of increasing voltage. In the following analysis, all voltages and currents are
static unless otherwise indicated. A
V Figure 3. 1. A portion of the con- trolled negative re- sistance circuit.
Region I is characterized by the breakdown diode, D, in Figure
3. 1 not conducting..: Using the simplified equivalent circuit for the transistor, Q1, given in Figure 3. 2, the equivalent circuit of Figure
3. 1 which applies in Region I is given in Figure 3. 3. As V increases, the base current, IB1' increases causing an increase in both the collector current, ßIB1, and the net input current, I. The lower limit of V for this region is at V = 0 and the upper limit occurs when the diode, D, breaks down.
Region II is characterized by conduction in the diode and all active elements. For these conditions the circuit in Figure 3. 1 has 6
c Collector
1B Base
IB
Emitter
Figure 3. 2. Simplified transis- Figure 3. 3. Region I equiva- tor equivalent circuit. lent of Figure 3. 1. the simple equivalent circuit shown in Figure 3.4. Referring to Fig- ure 3.4 the base of Q1 is kept at a constant voltage, VD, by the con- ducting breakdown diode. The transistor tries, within gain limitations,
I F--- 0
V Figure 3. 4. Region II equiva- lent of Figure 3.1.
to keep its emitter voltage, VE1, constant since the base voltage is constant; a constant VE1 implies a constant current through R0. But as V increases, the voltage drop R, V - increases, in- across VE1' creasing the current through R. Since the current through R0 is the sum of the current through R, and IEl, the emitter current of 01, the emitter current must decrease if VE1 is to remain constant. The 7 upper boundary of this region occurs when IEl decreases to zero and
Q1 becomes cut off.
Region III is characterized by conduction of the breakdown diode
and the cutoff of all active elements. For these conditions, the cir- cuit in Figure 3. 1 has the simple equivalent shown in Figure 3. 5.
In this region the only current is through Rb and through the series
combination of R and Ro. o
Figure 3. 5. Region III equivalent of Figure 3. 1.
Since the collector current of a transistor is approximately the emitter current and is proportional to the base current, the net re- sult is that the collector current increases in Region I, decreases in
Region II, and is zero in Region III. At the same time the input cur- rent, I, increases in Region I and in Region III, but remains almost constant in Region II.
A negative resistance results in Region II if the amplifier shown in Figure 3. 6 is added to the circuit in Figure 3. 1. In Figure 3. 6 the input current, I', is the sum of I and of 1E2. IE2 is proportional 8
A' 0
Figure 3. 6. Current amplifier. to the collector current of Q1' 'Cl' according to the values of RC and RE. If a portion of circuit values are chosen so that IE2 is large I', the I' will increase in Region I, decrease in Region II and increase again in Region III. The input current vs. voltage characteristics as indicated by this simplified analysis is shown in Figure 3.7 and the complete circuitis given in Figure 3. 8.
V
Region I Region II Region III Figure 3. 7. Input voltage- current characteristics. 9
Figure 3. 8. Controlled negative resistance circuit.
Control of the negative -resistance region is achieved by changing
RE. Since the value of RE controls only the gain of the current ampli- fier, changing RE will change the currents in Region I and II without changing the voltages which bound these regions.
3. 2 Detailed Circuit Analysis
A more detailed analysis is necessary to explain some of the ob- served circuit characteristics and to provide accurate performance equations for design purposes. This analysis will be based on the large - signal equivalent circuits shown in Figure 3. 9. Using these circuits, the equivalent circuit of Figure 3. 8 is shown in Figure 3. 10.
Collector s Collector _ ß lb Cathode r' ßr lb ' Base Base _b. V lb v.lb D ¡' V v Emitter b Emitter Anode I PNP NPNT Breakdown Transistor Transistor Diode Figure 3. 9. Component large - signal equivalent circuits. 10
Figure 3. 10. Large - signal equivalent circuit of Figure 3. 8.
The following analysis will be divided into regions; the regions will be considered in the order of increasing terminal voltage and will be labeled sequentially with subscripted upper -case letters. The upper boundary of a region is labeled by upper -case letters in parenthesis. Subscripts in lower -case letters and /or numbers indicate circuit lo- cations. Upper -case -voltages and currents refer to the input ter- minals; lower -case, to internal circuit locations. Examples are: IA is input current in Region A; V(C) is input voltage at upper limit of
Region C; vbl is the base voltage of Q1. In addition, incremental re- sistance, dV /dI, will be designated R'.
Region A, which begins at V = 0, is defined by neither D, Q1, nor
Q2 conducting; since Q1 is not conducting, there is no voltage across
Rc and Q2 cannot conduct. Upper boundary for the region occurs when
Q1 conducts. Figure 3. 11 shows the equivalent for this region; Q1 is included to determine V(A). 11
V Figure 3. 11. Region A equiva- lent of Figure 3.10.
The only current flowing is through R and R so that 0
IA = VA/(R + Ro) (Eqn. 3. 1)
RA = (R + Ró (Eqn. 3. 2)
Q1 will begin to conduct when vbl Since no current - vel = vl. flows in Rb, vbl = VA, and = VARo + R . Then V(A) occurs vel /(R ó R o when VA(1 - or R + R) -v1, o R V(A) = v1 (1 + Tt ) (Eqn. 3. 3)
Region B is defined by conduction of Q1 but cut off of D and Q2; after Q1 begins to conduct, icl must increase until the voltage drop across Rc exceeds v2 before Q2 can conduct. Figure 3. 12 shows the equivalent circuit for this region.
Figure 3. 12. Region B equivalent of Figure 3. 10. 12
The equations relating the currents and voltages in Figure 3. 12 are:
= + 1) + i I = io io ib1 (Pi o
i _ vl + v = i R vbl vel el o o
i = - (VB vbl) = ib1( Rb + rbl) (VB vei) /R B bl
Solving these equations for IB and RB gives: VB[ R( ß 1+ 1) + Ro + rb1] - v1R( ß 1+ 1) (Eqn. 3. 3) IB Ro (RR o) +RRo( ß + 1)
(Rb +rbl) (R + Ro) + RRo (ß + 1) RB (Eqn. 3. 4) R(ß + 1) + (Rb + r41)
V(B) occurs when ib1Rc = v2; substituting and solving for V(B) and
1(B):
V(B) = vi (1+RR) + (Rb + riz/ii)( 1+ )1-Ro( R 1+1) ] (Eqn. 3. 5) lZ?cß1 [ Ro i I(B) = + b (Eqn. 3. 6) R Rß 1131+1+ RR ] 1
Region C is defined by both Ql and Q2 conducting but D not con- ducting; V(C) occurs when D starts to break down. The equivalent circuit is shown in Figure 3. 13. 13
Ia- Vc "Ci o1 uCl 1 Yel 10 A ß Figure 3. 13. Region C equivalent of Figure 3. 10.
The equations relating voltages and currents in Figure 3. 13a are:
= i + ib1 i + ((31 -B 0 1 + 1)lbl
= vbl = V -Rblbl vbl vl + vel
V -vel = iR vel = ioRo
vbl-vbl = rblib and for Figure 3. 13b are:
= IB + ß Rc ('cl ± ib2) IB B icl+ 21b2 vb2 =
y + RE(r 2 + 1)ib2 vb2 -vb2 = ib2 rb2 vb2 -
Solving the proceeding two sets of equations for IC and RC gives:
VC[ Rby + +R(ß +1) +13 2yR] +Ro ß ß 2y +R(13 +1) ] rbl -vl [ (R IC (R.+rbi (Ro+ R) + ((31+ 1)RRb
yv1ß2 (Eqn. 3. 7) R c 14
( Rb + rbl) + (p + 1) R 1 R' _ (Eqn. 3. 8) C ß 1 ß +Rb +rbl ß 1+1)R where: R c (Eqn. 3. 9) y - ((3 2+1)RE+Rc+rb2
V(C) occurs when vbl = vd Solving for V(C) and the correspond- ing current, I(C), gives:
vd( (Rb+rbl)(R+Ro)+(ß l+1)RRo] - v1Rb(R+Ró V( C) _ (Eqn. 3.10) rbl(R+Ro)+RbRo+RRo (ß1+1)
( Rb+rbl)+R(ß2y+ßl+1)] -vl(Rb+R2Ytß+RQ)+(ß1+1)R1 P2 2y 1(C) _ rbl (R+Ró + RbRo + RoR (p1 + 1) Rc (Eqn. 3. 11)
These first three regions, Region A, B, and C, are equivalent to
Region I of the simplified analysis.
Region D is defined by conduction of Q1, Q and D; V(D) occurs when Q2 becomes cut off. Figure 3. 14 shows the equivalent circuit which applies in this region.
A B Figure 3. 14. Region D equivalent of Figure 3. 10. 15
The circuit equations for Figure 3. 14b are identical to those given for
Region C; for Figure 3. 14a the equations are the same except that: V-v It = i+i' and i' R
Solving the new set of equations for ID and RD gives:
VD[ rbl(R+Ro Rb) +RRo (ß l+l)+RoRb (1-ß 1 (32-y) ] ID + RRo +1) Rb[ rbl( (P1 ] ri; l(R+Ro)+RRo(ß1+1)-ß iE32yRb(R+Ro)-Rb(ß 1R-R) + RRo (P1+1) Rb[ rbl (R+Ro) vi R+Ro) ß2v2y [ ( ß l R 2y+Rb( ß l R-Ró (Eqn. 3. 12) rbl (R+Ro)+RRo(ß 1+1) Rc +RRo(ß Rb[ rIbl(R+R.o 1+1) ] R' - (Eqn. 3. 13) D rbl ( R+Ro+Rb) +RRo( ß +1)+RoR (1-P ß 1 2y)
where y is given by Equation 3. 9.
From the equivalent circuit, it can be seen that, with the diode con- ducting, the dynamic resistance, Rb, would be composed of Rb in parallel with a second resistance. Using the notation II to indicate
"in parallel with ", Rb may be written as:
r' (R +Ro) + RRo(P +1) R' Rb (Eqn. 3. 13a) - II _ Ro( pip 2y- 1) -rbl
The upper boundary of the region occurs at V(D) where the collector V current of Ql has dropped to ibl R and Q2 is cut off. Solving ßl c for V(D) and the corresponding current, 1(D), gives: 16
v R 2 V(D) = d-v1)(1+ Ro) - [ R( R 1+1)+rbl(1+ Ró ] (Eqn. 3. 14) ß Rc p 1 c
v T( D) = { vl( +R), vl ( R+Ro+Rb) - [ rbl( R+Ro+R.b) b Rc RoRb ß c
+ Ro(Rb+R( ß 1+1) ] } (Eqn. 3. 15)
Region E is defined by conduction of D and Ql but 02 cutoff. The upper limit of V occurs when Q1 is cut off. Figure 3. 15 shows the equivalent circuit for this region. The circuit equations for Figure
l'E f' i
°d
A ' B Figure 3. 15. Region E equivalent of Figure 3. 10.
3. 15a are identical to those for Region D; those for Figure 3. 15b are the same, also, except that
ib2 = 0 I = I' + lcl
Solving the appropriate equations for IE and RÉ gives:
+Ro +Rb) +RoRb +Ro(ß +1)R] -vlRb(ß VE[ rbl(R 1 lR -R) IE _
Rb[ 1(R +Ro) +((3 1 + 1) RRo ] 17
+RRO(ß 1RRb + RbRo] Td[ rbl(R+Ró l+1)-p (Eqn. 3. 16) Rb[ rbl(R+Ró +( ß 1+1)RRo]
Rb[ rb1(R+R0)+( R 1+1)RRo] ' = (Eqn. 3. 17) E rbl(R+Ró Rb)+RoReRRo((31+1) l+1)
Again, expecting RÉ to be composed of Rb in parallel with another resistance, RÉ can be written as:
rbl( R+Ró +RRo( ß 1+ 1) _ ( Eqn. 3. 17a) RE Rb rbl + Ro
V(E), the upper boundary of the region occurs when the base current of Q1 drops to zero and Q1 is cut off. Solving for V(E) and the cor- responding current, I(E), gives:
V(E) = ( ) (1+R-) (Eqn. 3. 18) 0 R+Rb 1 I(E) = -V1) (Eqn. 3. 19) RoRb vl Rb o
Region F is defined by conduction of D and cutoff of both Q1 and
Q2; there is no upper bound except as restricted by component break- down or diode power dissipation. The equivalent circuit for the region is given by Figure 3. 16. The equations relating the voltages and currents for Figure 3. 16 are:
I = i+i' V = (R+Ró i (V-vd)- i' Rb 18
F v d
A Figure 3. 16. Region F equivalent of Figure 3. 10.
Solving these equations for IE and RÉ gives:
V -Vd V E (Eqn. 3. 20) IE Rb + R + Ro
RF,r = Rb (R + Ró (Eqn. 3. 21)
There is no V(F) or I(F).
Region E and Region F are equivalent to Region III of the simpli- fied analysis.
The results of this analysis may be represented by the input characteristic curve shown in Figure 3. 17. 19
Voltage V(A) V(B) V(C) V(D) V(E)
Figure 3. 17, Detailed input characteristic curve.
3. 3 Design Procedure
Usually the region of primary interest will be the negative -re- sistance region, Region D. Consequently, the circuit parameters would be determined from one of the following five sets of specifica- tions: V(C), RD, V(D), 1(D) or
V(C), I(C), V(D), 1(D) or
V(C), 1(C), V(D), RD or
V(C), 1(C), RD , 1(D) or
RD , I( C) , V(D) , 1( D)
These five sets, however, are all equivalent because the five para- meters are all related by the expression
V(D) - V(C) R' = (Eqn. 3. 23) - D 1(C) - 1(D) 20
The most useful set of specifications from the design standpoint is
V(C), RD , V(D), and I(D) because of the nature of the equations in- volved.
If it is assumed that rbl is small enough to be neglected, (its value is usually less than 1000i2), and that ß and f32 are large enough so that (ß +1)z ß, then Equations 3. 10, 3. 13a, 3. 14, and 3. 15 may be written approximately as:
d[ Rb(R+R© +ß 1RRol -v1Rb(R+Ro) V(C) (Eqn. 3. 10') RR + RR
ß +1 R' -R 1 (Eqn. 3.13'a) D Rb (I ß12Y -1
V(D) v (v d-vi) (1+ - v2 (Eqn. 3. 14') R ) R o c R I(D) Ñ [v Rb+R) -v1( R+Rb+Ro) - RIR b+ 1R) o b 2ß1Rc (Eqn. 3. 15')
To insure that transistor Ql never becomes saturated, the limi- tation, Rb > R , must be placed on Rc. If the equality is assumed, b- P l c c the solution of the preceeding four equations yields:
V(G)-vd Rb = { V(D) +[ V(D) -v d+v -v21 } I(D) [v(D))_ ) ] [ V(D)-V(C)1 (Eqn. 3. 24) Rb (Eqn. 3. 25) Rc ^ ßl 21 V(D) - V(C) R = R (Eqn. 3. 26) c V(C) - v d-vl
[ V(D) -V(C) ] [(v d-vi) Ro = Rc (Eqn. 3, 27) [V(C)- ] [ V(D) -vd-v2] +vl[ V(C) - -v2] Rc c R+rsb2 (Eqn. 3. 28) ß R 1 RE (1+ Rb 2 R ( R' ) b o ßl
Using the design equations, Equations 3. 24 through 3. 28, the design procedure would follow the following steps:
Step 1: Choose the breakdown diode Its breakdown voltage must be less than V(C) because V(C) is always greater than vd. The diode should also have a sharply defined break down; otherwise, the transi- tion at V(C) will be rounded instead of sharp.
Step 2: Choose the transistors, one NPN and one PNP. Their selection will determine v1, v2, pi, ß rbl, and rb2. Guidelines for choosing Q1 and 02 are:
(a). Breakdown voltage of 02 larger than V(D).
V(D). -V(C) (b). Current rating of Q2 at least I(D) + ' D (c). Breakdown voltage of Ql at least V(D) - vd.
Step 3: Using specifications and component parameters from pre - ceeding step, determine component values from Equations 3. 24 through 3. 28.
Step 4: Minimum value of Rb is limited by maximum power 22
dissipation of the breakdown diode since the power dissipated, Pd(D),
at V(D) is R [ V(D) -v d] . If the power is greater than the rated power of the diode, a larger Rb must be used; it is usually easiest to reduce
I(D) to make Rb larger. This completes the design procedure.
The magnitude of the negative resistance may easily be controlled by changing RE since RE effects only I(C) (or Rb). 23
IV. EXPERIMENTAL CONTROLLED NEGATIVE RESISTANCE
4. 1 Design
The design procedure presented in Section III is illustrated by the realization of the following set of specifications:
A negative resistance of - 200012 is to be produced. Break points are to be at 11 volts and 20 volts. It is to be biased midway between breakpoints at 5 milliamps.
The specifications should first be restated in standard form by determining I(D) which is 5 ma. - or I(D) = 2.75 ma. 2 Step 1: Choose a 10.0 volt, 100 milliwatt zener diode.
Step 2: Choose a 2N706 for Q1 and an ST8034 for Q2. The first is an NPN transistor; the second, a PNP. The ST8034 is 600 mw,
25 volt silicon transistor with a beta of 90 at 10 volts and 7. 5 ma. ; the 2N706 is a silicon 300 mw, 20 volt transistor with a beta of 90 at 9 volts and 1 ma. There will be no problem on either power limi- tations or voltage breakdown for either transistor.
Step 3: Design equations give:
Rb = 50.0 K
R = 556 ohms c
R = 12.5K
Ro = 5.13 K
RE = 69. 4 ohms 24
Step 4: There will be no problem with zener power dissipation since power dissipation at V(D) will be 2 mw.
4. 2 Performance
A circuit using the components listed in the preceeding section was constructed in the laboratory. Actual circuit values and circuit performance is tabulated in Table 4. 1 and typical characteristic curves for the circuit are shown in Figure 4. 1.
TABLE 4. 1. CIRCUIT DESIGN AND PERFORMANCE. Quantity Design Realized Values Values
Rb 50. 0 K. 50. 0 K, 1%
R 556 554 1% c R 12.5K 12.5K 1%
Ro 5.13K 5.13K 1% 0
RE 69. 4 70. 0 Si 1%
V 10.0 v 10. 05 v z V(C) 11.0v 11.0v
V(D) 20. 0 v 20.0v
I( D) 2. 75 ma 2. 1 ma
RD -2. 0 K -2. 3 K 25 ió IMO MIMI EWA"
l A 1111/Mill LJNM 111 Figure 4. 1. Experimental characteristic curve.
The error in I(D) is due primarily to the assumption . that rb is zero; this assumption had to be made to obtain useful design equa- tions and it is a reasonable assumption when significant base current
flows, as, for example, at V(C). At V(C) with the circuit designed,
rb1 is about 500SZ which is quite insignificant compared to Rb. But,
as the base current decreases while changing V from V(C) to V(D), rbl increases considerably, particularly as the base- emitter voltage approaches vl.
A second major factor contributing to errors is the variation of
ßl and ß2; both are functions of the collector current and the collector - emitter voltages of the respective transistors. For example, in a typical 2N706, beta increases from 110 to 153 when the collector cur- rent is increased from 0. 1 to 1.0 ma at a collector voltage of 4 v. 26
4. 3 Secondary Considerations
The linearity of RD (Equation 3. 13a) can be of major importance in network applications, particularly when large signals are to be handled. For the reasons indicated in the preceeding section, linearity is best near V(C). Decreases in both 131 and 13 and increases in both rb1 and rb2 contribute to nonlinearity at low currents. Linearity could undoubtedly be improved by a different choice of transistors. Figure
4. 2 shows the variation of GD = (RD) -1 for the circuit designed in
Section 4. 1.
The variation of RD with frequency is also a major consideration in network applications. Figure 4. 3 shows measured values of
GD = (RD) -1 and its associated susceptance, jBD, for a circuit similar to that designed in Section 4. 1; while the measured circuit was not absolutely identical, similar results could be expected.
Shunt capacitance may, or may not, be a problem in network ap- plications. Most negative- resistance synthesis techniques take into account shunt capacitance. At frequencies below about 500 kc. , the circuit measured in Figure 4. 3 has an equivalent shunt capacitance of approximately 100 pf. Usually the shunt capacitance required for network synthesis is greater by several orders of magnitude than that supplied by the circuit and shunt capacitance must be added. If the required shunt capacitance is less than that provided, it may be 27
. i , I ,i - -1 - t 1 1 y.. Y t _ , ; -r- ._ .. i :ü.a- - . : ._.' . . : ú : 1 _.... H:. Figure 4. 2. Terminal conductance J1- _, dI as a function of terminal voltage ME . -1-4 di- -,-,' IIII dv for (circuit designed in Section 4. 1 mg ::::.-' _MEN ...1 ::::: _ -'rY-
11111! EMII r Ill :: ohm . ii I: 1 WINOMMINIM mumr-val Au EuN um logronslom MINA 9.1 1 i
::: MAU MIRE 11/1111111111111111111111111 I I
11111111111111/111111111111111111111111111111/1111 III
1111111111111111111111111141111111111111111111111 III 1111 IIIIIIIIIIIIIIIIIIIIIIIIIINIIIIIIIIIIIIIIIIIIIIII IR. RI 111111. 1 1 11111111 EMI 1 ILI Ill . limo
1111 1111111111111111111111111111111111111111111111111 _:::::::::::i:_ _ g= S=1u=1CG EEE::Ca1 ...... L. % ::::::
w.:;Elm ::::::::::::::: ii i :.üEEE
NM¡III ii 111111111111141111111111111118111119111111im AA6 m Inalignammallmll : II :111111041111011111111111111111111111111111 :: -- ::i:::: :::iiïi:iüiii i:::: : i IL ::::::::::::::::::: ::=::::a:::: ::::: : ::' : 1 :':::1:::1"::: :: 1 ,--- :::::::"
:: ':::::::: ::::::.:::i:::.íi::::::::::: ::i.:: 1 Terminal voltage, volts mom +} a- +ni"1im`hpc I 1 n Figure 4. 3. Terminal admittance, G + jB, as a function of frequency Ylllrm 1111 _ !_ circuit similar to Section 4. 1. Inset: - _ -{ 4-
low frequency admittance. i !
.... II
.. .
O trlc I , 111111NMIISM : 5Ú tt c tl w11111111111 . .C. ,------, -üsG . . w PmiiiEiiiiiii=iw.=s..n.u. nLI. L MA -
- ---. ..N="'m ==IIIMINIOM ; ---{ -,--- O1110 -----_-F--i .1 ... 0NMINIS - ---' ...... _.. . . -. .i. +1, nii . H= I
l ! ' nnnnn .n...nn - . 0.nsp ' n nmn.n iúi.ni w;__ LJ _. ' Eli iII li II o.'i a4' II 1>> 29
cancelled out, but only for a small frequency range, by shunting the
resistor R, (see Figure 3. 8, p.9 ), with a capacitance. That this will cancel the output capacity may be seen from Equation 3. 13a:
rbl( R+Ro)+1tRo( ß 1+ 1) RD = Rb - Ro(131132Y-1)-rb1 which indicates that the circuit may also be considered as a negative impedance converter of the form given in Figure 4. 4. R r' rbl Ro r + Ro(r31+ 1) °
Figure 4. 4a. Negative- impedance Figure 4. 4b. _A reorienta- converter equivalent. tion of Figure 3. 8 to em- phasize nega- tive- impedance converter form
The compensation of the input capacitance will occur at only one fre- quency because of the "stray" resistance in series with R; although this undesired resistance cannot be removed by compensation as in many NIC's, it can be made small by making 131 large.
Oscillation may occur in the upper part of Region C, particularly in breadboard circuits, where layout and lead lengths often are less 30
than ideal,especially if high frequency transistors are used. This
condition may usually be prevented by placing a ferrite "suppressor"
bead on either or both the collector and base leads of Q2. Although
the oscillation is usually too high to be seen on a curve tracer, it is
revealed by a distortion of the traced curve with the distortion being
effected by hand capacity near the circuit. Figure 4. 5a shows the
distortion produced by such oscillation and Figure 4. 5b shows the
curve after application of the suppressor beads.
11111111111M11111 MINE 1111111E.0111= lommismoomm! MIME
R
Figure 4. 5a. Effect of high frequency Figure 4. 5b. Same circuit as oscillation on the char- Figure 4. 3a with acteristic curve. addition of sup- pressor beads. 31
V. NEGATIVE RESISTANCE SYNTHESIS TECHNIQUES
5. 1 Background
Synthesis with negative resistances gives several advantages over
conventional passive network synthesis; higher gain constants may be realized than possible with transformerless networks, and pole -zero arrays impossible with passive synthesis may be realized with negative resistances.
A considerable number of negative -resistance synthesis tech- niques have been developed but most are either quite complex or re- quire a large number of negative resistances. A paper by Losee and
Mitra (6, p. 357 -62) presents a set of realization techniques using simple adaptations of RC- ladder synthesis methods. Several of those techniques are outlined to provide a background for the experimental realizations presented in Chapter VI. As previously indicated, all negative- resistance devices also exhibit a shunt capacitance; sometimes it is small enough to be ne- glected, but in RC- ladder synthesis it is an advantage. 32
ZB
c -R c R T
Figure 5. la. Negative resistance Figure 5. lb. Passive parallel RC equivalent circuit. circuit.
The negative- resistance equivalent shown in Figure 5. la has an impedance, Za(s), of: a
1 Za(s) = sC- R
1 1 ( E qn. 5. la) C s - 1 RC while the parallel RC circuit in Figure 5. lb has an impedance,
Zb( s), of:
= Zb( s) 1 sC + RC
1 1 s+RC (Eqn. 5. lb) s+RC
The comparison of Equations 5. la and 5. lb indicate that the circuit 33 of Figure 5. la can be used to realize positive real impedance poles in the same way parallel RC combinations are used to realize nega- tive real impedance poles.
5. 2 Larger RC Ladder Gain Realizations
The use of a negative resistance to realize transfer functions usually realizable with passive RC-ladders gives larger gain factors than possible with the passive ladder; sometimes a net gain may even be realized. The procedure is outlined in the following steps and is illustrated in Figure 5. 2, page .
Step 1: Given an RC open- circuit voltage -transfer function, m n N(s) = T (s + 6 (s + Z). Since G12 = /P(s) i .)r i G12(s) = Eout /Ein is an RC- transfer function, 6 . and Z. are real, positive and m 4.n. i 1 The following procedure requires a transmission zero at infinity, making the condition on m and n a strict inequality, m L n.
Step 2: Using the relationship between open- circuit voltage- trans- fer functions and the of a G12 = "z" parameters network, z12 /z11' form z11 = P(s)/Q(s) and z12.=- N(s)/0(s) with Q(s) of the form: n-1 Q(s) = (s- a) (s + pk) such that a and pk are real positive and that 0< z 1< pl Step 3: Subtract a 1SL resistor from z11. According to the assumed form for z11, the leading coefficients of both P(s) and Q(s) are unity; thus, z (00) is unity and removal of 111. z the 11 from shifts highest zero of z11 to infinity. This operation is shown in Figure 5. 2b. The remainder impedance, z , is given by: 0 n i-Ï j = 1(s + z;) - - 1 zo - zll 1 - (s -a) n.... (s+pk) k =1 n n -1 Tr 1 (s +zi) - (s -a) k=1 (s+p n-1 (s-a) (s+pk) Step 4: Form y = l/z and shift the zero of y at a to the origin o 0 o by removing G = y(o); 0 0 n-1 -a pk 1 Go = o zo (o) ajT z Pk j=1 J +äk=1 Note that Go is negative. The pole plot this is 0 -zero for step shown in Figure 5. 2c. The remainder admittance, y' = y - G , is given o o o by: 35 n-1 n-1 (s-a) (s+pk) -a k 1 Pk Y' - n n-1 o - n n-1 :1T1 (s+zj)-(s-a) (s+pk) jiTIT zj + a k 1 Pk n-1 n n-1 Li.... zj) +a( 1 (s+zj) (s-a): (s+pk)(j Pk) j n n-1 n n [ Tll ( s+z ) -( s - a) ( s+pk) T1 z. + a - ] [ pk] J= J J- J k- Step 5: Remove the pole of y' at infinity to realize the shunt o capacity associated with Go. The need for this capacitance shunting Go is the reason for requiring a transmission zero at infinity. Ex- 0 panding both the numerator and denominator of y' in polynomial form, o the coefficient of the term of the highest degree of the numerator, an, is n-1 ¡It z. + a -n- an = pk j=1 J k=1 and the coefficients of the two highest degree term of the demoninator, bn and bn are: n n-1 n n-1 bn = zi + -n- [TT z. + a Tf i a pkk - IT pk]k = 0 j=1 k=1 j=1 J k=1 n n-1 n n-1 Pk][FiZ- ú Pk+ a] bn-1- [z.+aj=1 k=1 y=1 k=1 Carrying out only the first step of the synthetic division of the numera- tor by the denominator of y' and calling the remainder y (s): o r 36 c.O cr- P. 3 °y O in. cr. Its ls) PA FI`. 5.2a. %NITIALPoL 2Eo CoNFIGUeATWa volt, R -C TRAWaFER WISH GAtÑ, Safi STEP Z. P.V ... 1 I s a.CC) 1 ;:. A. \r P r ._ - as 1 \ 9 17. N \ FIGUR6 S.Zb. R6OyoVAL or IA F/co To . FORM Z. MAMA A 2Eto AT I6iGIN1T7 y; cal I I 1 / 1 / X O ^V _.p I f Ft4tAtE 5.2C REMOVAL OF FROr, yo d,fol = e 7o FORM Yo AN) To REALne Cw' 2e (0) aI /i O 0 FwURe 5.2o 1?(nOVAL oF ?OLE AT INFWITy To REAIIS e Co FIG(As 5.Z POLE-ZERO CONFI4UR.ATIONS ILWbTRATIw1(i PROCEDURE FOR REAL l2\NG RC TRANSFER FuNCTtONS WC-r H GAIN 37 s - + yr(s) yo n- z . a Pk J =1 - k =1 n n -1 so that a shunt capacitance, Co = (£1 + a) -1, may be J= z. - 1 pk realized. This step is shown in Figure 5. 2d. Step 6: Realize the remaining transmission zeros with conven- tional RC- ladder procedure. The remainder admittance, y r (s), is usually most easily determined numerically at this point from y = y - G - sC . The network form at this step is given. in Figure r o 0 0 5. 3. 112 Passive RC E i Ladder E o E Figure 5. 3. Network form for realizing RC G12 = Éo with gain. 5. 3 Nonminimum -phase RC Transfer Functions Nonminimum -phase RC- transfer functions are characterized by having positive real zeros. Realization is directly analogous to standard RC- ladder techniques, and is best described by example: Step 1: Given G12 = Eo/Ei ( (s +2)(s)( +4)) Step 2: Using the open- circuit transfer relationship or 38 choose -y12 and y22 with negative real poles inter- G12 = -y12/y22, laced with zeros of y22: (s+ 2) (s +4) y22 ( s+3) ( s+6) -y (s- 1)(s +5) Y12 (s +3)(s +6) Pole -zero plots are given in Figure 5. 4. Step 3: Shift the most positive zero of y22 to coincide with one of the positive zeros of -y12, at 6 This is accomplished by re- 1. moving y22 (o- y22(o- is l) from y22; it should be noted that l) greater than y22 (o); removal of y22(o) will shift the zero to the origin but removal of a conductance greater than y22(o) is required to shift a zero to the positive real axis. In this case, the zero at 6 = -2 is shifted to = +1 by removal of 15/28 mhos. Step 4: Realize the positive transmission zero as a pole of Z ) ] -1 by removing a parallel combination of a = [ y22(s) - y22( negative resistance and a capacitance. In this example: 364 85. 124 (s+3)(s+6) 59 13. 33 Z (s-1)(s+ 46) ( s - 1) + (s + 13 13 ) The pole at s = 1 is then realized by a capacitor of 59/364 farads in parallel with a -364/59 ohm resistor. Step 5: The procedure outlined in steps 3 and 4 is repeated for 39 each positive transmission zero; the remaining zeros are realized conventionally. Obviously this procedure requires one negative re- sistor for each positive zero. The resulting network form is given in Figure 5. 5. -6 -4 -2 X a X Y12 _A i 1 > Y22 r If I k ¡ ., 1) . o Y = Y22-Y22( 1 Y -.o ; o-= _ --- X > Z 1 : t 1 ; 1 X ° >Y' = -' it PA.eTIRL Re M CNA L. / .n yn 1 e 1 Z" ti--- I 364 yI E. in E out Figure 5. 4. Pole zero plot for example of section 5. 3. -R -- -R 1NVr IN Figure 5. 5. General form for nonminimum -phase transfer. 40 5. 4 Arbitrary Zero of Transmission Arbitrary zeros of transmission with negative real poles may be realized by two parallel two -ports of the form shown in Figure- 5. 6. r - - I e -R I RC r ~- RC I n 1 Ladder J co Ladder I I T-I ------° N a__ _ J RC Ladder -bi Figure 5. 6. Network form for arbitrary zero realization. The technique is based in the fact that any arbitrary polynomial with a positive leading coefficient may be written as the sum of one poly- nomial with negative real zeros only and one polynomial with one posi- tive real zero and all other zeros negative real (6, p. 361). Or, ex- pressed algebraicly: k n n n-1 a s = (s-a) 1T(s+6 ) + 1T (s+6 i) ak;g,;v ;areal positive (Eqn. 5. 2) Since, for two parallel two -ports, Na and Nb, with admittance parameters [ ya] and [ yb] , the admittance [Y] of the combined net- work, N, is the sum of the admittances of the parallel networks, 41 [Y] = [ ya] + [ yb] , the open- circuit voltage -transfer function of the network, N, may be written: a b -Y12 -y12 -y12 G12 = Y a b 22 y22 + y22 From the assumed configuration shown in Figure 5. 6, -y12 has one positive zero. Thus if G12 is specified with a denominator having only negative real zeros and with a numerator restricted only to having a positive leading coefficient, the numerator may be separated into two polynomials of the form given in Equation 5. 2 and the terms may be associated with the admittance parameters of Na and Nb. The procedure may be outlined as follows: k n n r a s Step 1: Given - G = H with a >0 and p.> 0 12 ( s+p) k Step 2: Separate the numerator of G12: (s -a)11 (s +o .) +1T(s i) H G12 TT(s + p.) Step 3: Associate terms with admittance parameters: ( s- a) T` ( s+z. ) a -¡T( s+zi) a a -y12 Q(s) -y12 Q(s) 11 ( s+pj) d b 1 y22 + y22 H Q(s) If the coefficient, H, is chosen so that H is two, then y22 and y22 may be easily identified as: 42 s+p.) a b TÌ( y22 - y22 - Q(s) Step 4: Actual synthesis of Na follows the pattern outlinedd in Section 5. 3; synthesis of Nb follows standard procedure. 5.5 Biasing One factor seldom considered in the negative resistance synthesis problem is that ,of biasing. Current R,c l- R -R r Operating point Voltage Figure 5. 7. Biasing of a negative resistance. To achieve stable bias for a negative- resistance device, the DC load -line must intersect the characteristic curve of the device only once and that intersection must be in the negative resistance region, as indicated by the line Rol in Figure 5.7. Otherwise, the circuit will be stable in one of the two positive resistance regions, as indi- cated by the RL2 in Figure 5. 7. The criterion of one intersection only in the negative resistance region can be met only when the effec- tive load resistance is smaller in magnitude than the negative re- sistance; an equivalent condition is that the bias supply must "see" a 43 net negative resistance. From a network synthesis standpoint it is desirable to be able to use a portion of the network for biasing although sometimes it is most convenient to add components for biasing. A simple example is pro- vided by networks realized from the technique presented in Section 5. 2. The DC driving -point impedance, z11(0), is negative as indi- cated in Figure 5. 2a. Biasing may be provided by supplying bias current through a resistor of value less than z11(0) to the input terminals as shown in Figure 5. 8. Z11 1R RC Ladder Bias f- Figure 5.8. Bias scheme for Figure 5. 3. The ladder form of Figure 5. 5 may be biased quite easily. Con- sider, first, synthesis of a ladder with one positive zero at s = a, a >0, from a y22 partially diagrammed in Figure 5. 9. Following the procedure previously outlined, the most positive zero is shifted to s = a by removal of y22(a) which is greater than y22(0), leaving a y1(0) which is negative. After realizing the transmission zero as a pole with residue Ka, the network has the form shown in Figure 5. 10. 44 ------5P"- Cr. Figure 5. 9, Illustration of first step to realize zero at s = a. 1 t ka a_ G ka Z'2 y1(0) Figure 5. 10. Network realization of transmission zero at s = a after first two steps. Now, if the shunt arm y22 (a) in Figure 5. 10 is broken, the lad- der may be examined for biasing possibilities. To allow biasing at this point, the resistance seen at the break must be negative, or, 1 y22(a) + As indicated in Figure 5. 9 which represents an arbi- 1 l(0 )). trary admittance function, y22 (a) + y1(0))0 and y1(0) <0. Then mani- pulating the inequality: y22 (a)?- Yi(0) 1 I Y22 ( a)<- y1(0) since - y1(0) > 0 ) 1 y22 (a) + yl(0) 0 45 Thus the resistance at the break is negative and bias may be applied at that point. The procedure for biasing a ladder with a single positive trans- mission zero may be extended to ladders with more than one positive zero. The steps demonstrating this feasibility are shown in Figure 5. 11. Figure 5. l la shows a ladder with an arbitrary number of arbi- trary positive transmission zeros, recalling that after each realiza- tion of a positive zero, the remaining impedance is positive at o- =0. Figure 5. llb shows the network after breaking the first shunt leg and inserting the bias voltage. Figure 5.11c shows the result of combin- ing the first shunt resistance and the first negative resistance; the result of this combination is negative as indicated in the preceeding paragraph. Figure 5. lid indicates the result of taking the Norton equivalent of the bias supply and the combination of the first two re- sistances. Figure 5. lle gives the result of finding the Thevenin equivalent of the bias source of Figure 5. i id. Since the driving -point impedance presented to the bias source does not change under succes- sive Thevenin- Norton transformations, the driving -point impedance in Figure 5. lle is still negative and biasing is achieved. This procedure can be continued for all of the negative resistances in the network, in- dicating that each negative resistance may be biased through the net- work preceeding it. 46 -R2 -R1 -R3 -R1 Ra E A. Arbitrary ladder. B. Addition of bias to A. -R2 -R=-RI+Ra -R2 E -R C. Combining -Rl and Ra D. Norton equivalent ofbl. of C. -R Rb Rb E' =E -RRWRa ! - E Rb-R E. Thévenin equivalent of D. Figure 5. 11. Derivation of bias feasibility. It should be noted that a considerable portion of the bias current will be lost in the shunt arms and that the DC voltage drop across each shunt arm is always larger than the voltage required to bias the next negative resistor. It is thus advantageous to design the negative resistances for as small a bias voltage as possible. The network of Section 5. 4 may be biased in the same manner as the networks with positive real zeros since the portion of the net- work resulting from that technique is simply a ladder with one posi- tive zero. 47 VI. EXPERIMENTAL NETWORK REALIZATIONS 6. 1. RC Ladder with Gain Following the procedure outlined in Section 5. 2, a network with transfer poles at s = -1 and at s = -10 with no finite transfer zeros is desired. The synthesis proceeds in the following steps and is out- lined in Figure 6. 1; the completed network is given in Figure 6. 2. Step 1: Given - H N(s) G12(s) (s+l)(s+10) P(s) All poles and zeros are real negative and the degree of the numerator is less than the degree of the denominator so that all criteria are met. Step 2: Choose - Q(s) = (s- 2)(s +5) then _ (s +1)(s +10) z11(s) (s- 2)(s +5) H and z _ 12(s) (s-2)(s+5) Step 3: Subtract one ohm from z11 (s+2)(s+5) - z11 1 - 8 (s-2) (s+5) -1 Step 4: Remove Go = yo(0) from yo = (z11 -1) 48 1 (s-2)(s+5) Y o 8 (s+2.5) 1 ( -2) (5) 1 and G - 0 8 (2.5) - - 2 n n -1 -1 Step 5: Remove C = X1 - pk + a) in parallel with o ( J= Z'J k - l G o Co = (1+10-5+2)-1 = 8 Step 6: Determine y = yo - Go - sC and continue remainder of r o synthesis as normal RC- ladder - 9 s Y r 16 (s+2. = = (1+ 2s5) Zr Y r 9 The network resulting from the proceeding synthesis has a net gain of two at 2 = 0 as determined by the first two resistors in the network (Figure 6. 2a). This gives a value of 20 for the gain constant, H, in Step 1; the maximum possible value of H for a passive ladder is 10. Figure 6. 3 shows a graphical comparison of the measured fre- quency response and the theoretical frequency response for the net- work shown in Figure 6. 2b. 49 -p° 2 zeros -10 -8 -6 -4 -2 +2 0- - - - ;---- X z12 -- il 2 X y11- 1JL O- 1 u7 . o yll-11L Yo= Yo( 2) 1 yr= 2) -Cos yo-yo( 1 z = -yr z - z ( -oo) r 1 z -z r (-co) H Figure 6. 1. Realization for G12(s) _ (s +1)(s +10) with gain. 1 16/9 1, 000 16/9 x 103 A. Unscaled network. B. Network amplitude scaled 103; frequency scaled to 1 KC with bias. Figure 6. 2. Network realized from Figure 6. 1. ll ;:4- ...... lll ...... -^ ...... - ...... 71E:Eiiii ...... 4:iF ...... 4. - ...... MOM 44.."4../m. .... 2 174 . 4 .. 111111 11,1lllli-- . - u::P:n.munnunn:' . 11111 1/1111111111 u111111II11111IIIIIIIIII... y'1il1hI114..,,nU111111111111111.w ... ;;;;;;;.flÖ111.iÌ::::;;1,oÓIÌÌi ,.,q,h,,,O;;i^i:::;;;;;;ÜÖi;ipi === 1111111111111111111111111111111111I1101111111... 11111111111111111111111111111.1111111.11111111...... IIIIIIIIr111111111111111111111111111. .. 11111111iÌ111111I1f1111111b.: ".j 11111111. 11111111111111111101111 p 1011111111111111111111111111111111111.. 11111111111111111111111111111111111Ì....'.111. IIIIIL.... umuU11 11 11111111 m..mn11111 111111101.. . 1/11111111I111 11111111 11 11111 11111 1111111111 1 0 11= ... IIIII111N1111011111 1111111111111111111111111...1110 11111II11111111111t11111111l111111111111111111.. t. I1111111111111111111t1111I1111111111111! 11111111111111111111111111IIIII1111111111110111...I ...... 11 1111111111111 1 1 1111 1111111111 MEIN IIIIIIIIIII IIIIIIUlu111u1n1u111n1n11111...... Min u III11111110111111111111111111111111111111111116aCM111 ..... 1111111111111111111111111111111111111111111111... IIIII11111111111111/111111111111111n11111...NUlli 1111111111111111111111111 1111111111111111111111. 1111111111111111111111111111111111111111111111111111.\: ...O 11111111111111111111111111111111111111111111 111111111111111111111I111111111111111111111111111.. p ..mnnnnunnunuunuununununnumuummlmiinnnmuuuuumnmmuom uuumuluiummnainynnmmuuuunnnnnnnnnnnnuunumnonnnununuuuunu11muuuunnnunnuulnul - ...... lll ...... ll ...... 1.1 ...... ^ ...... lllllllll ...... . ... ts M.N. lllllllllllll 1111 llllllllllllll 111141 Figure 6. 3. Frequency response curve for .,. IIIM 1411441 ...... 114.111I ;;;;.mmi....iiiï uulluual . I1 1ñ . °Ó°lÓ1Ó°1° i°Ón11uunnu11r..úüm. uu11 ' ...... 1111;i1...... 1 Ì;.IÌ.. 111111111.. Yt network shown in Figure 6. 2b. lllllllllll 1 11 1111111111 11I/1111/111111111 11111.. 111111111111111111111111111011/11111111111111111.. tt 1111I1111111111111111111 Ill 1111, 11. 'Il1 1111111111111111111111111111111111111111111111... 1/1111111u11111111111111111111111111111111111. .411.. 1111111111111111111111111111111111111111111111....11lI1llt IIIIIIIIIIIIIIIIIIInII1111111II1111I11nn111n,v3u IIIIIIIII1111111111I11111111111111111NIIIIIIIIIIII...IBftlll 11111111111111111111111111111111111111111111111111111111v.1' 1111111111111111111111111111111111111111111111111111... 1 1111111111111111I11111111111111n1111111I111111111111111 \.11111111111111111111111IIIIIIIIIIIInn111111111111111111111MMEl11111 0. 1 theoretical response 1un1uwummnnNlumnmminnnlmunu11111:11..n1 umnul nnnmummm11ulmmnuummnllnmu - -...... ll asymptotic approximation to ll ll theoretical response lll o ® o measured response _----- ...... g lllllllllllll ...... 1.1111.1,11--- ...... 1 " ;;,;e..,...:...,¡....,,...,,,,;,,;,,,¡__ t ... 1; 11Ì.Ì.Ì ;l,1l1111u11P111aI11111I1yy 1011i1111-.m illl II.11111t11111111111/111I IlI0.1111I111111111.. 11111111111111111 11Ìh111u111... IIIIII111111h111111110110 III 11i111111111.. 1111IIIi,V11111111111X111111111t11I11111111h11.. U II1111111111111111111111I1/1111111111111111111111.. VIIIIIIIIIIIIIIGIIIItl1 11111 1 0 11 11111.. uununulIIIUnnnumuuumllIlmmi.. IIIt11111111111111Illllllllllllln111u11u1n. lll IIUIII11111111111111111u1uII111n111u. u IuI11111uII111n111u11.11W1I11111111111111..... 111111111IIIIIIIInIIt111NP1111111111111N11.. n ...ammuummlDNNn11mN11mnnnnNmmmmltt.nmummm11IIIIIIIIIIIIIIIIIIIIU1111111111111111nn111u.. lll 11111111111111111111111111111111111111111111MINE Illlllllldn111n1111111IIIt1I11111tINIn111.....O2u lmnun 1111mm1mmunnnmm11m1mnnnnmmmmumn11mNlnnanllmu 11111 mu111...tf II1f111U11q1111111111IIIIIII1I111III11111111111111I emunmlmmmnN:V111111111n11111I1111IlINIIIINMnnm1 0.01 IIIIIIIIIIIIIII1t1111nnM11111111nI11111I1I1nIm11111111l1 mnn11n1111nlnlIE111111111111111111111IIIIg111111m111111111111I1111I1I1IMINE111111111111111111IIIIIIIIID111111111111111111111IIIIIIIIIII111111e.U1U1 10 100 10 10 10 Frequency, cycles per second 0 51 6. 2. Arbitrary Zeros of Transmission Following the procedures outlined in Sections 5. 3 and 5. 4, a net- work with zeros at s = + jl and any convenient RC poles is desired. The procedure is outlined in Figure 6. 4 and is detailed in the follow- ing steps. Step 1: Given - - (s2 -I- 1) G12(s) (s+a) (s+13) Step 2: Separate the numerator of G12(s) into one term with only negative real zeros and one term with one positive real zero. 3 s2 + 1= Zs2 + 2- + 1 2 s+2s = Zs (s-3) + 2 (s2 + 3s + 2) = Zs (s-3) + (s+2)(s+1) 2 At this point, the poles of G12(s) may also be chosen. To easily identify the poles in the resulting response curve, they should be at least two octaves apart and two octaves away from the notch. Thus, a convenient denominator for G12(s) may be (s +4)(s +16). Step 3: Associate terms separated in with G12 admittance para- meters and choose poles for those parameters. The identifications are : - 52 a s(s-3) b (s+2) (s+1) -Y12 - Q(s) -Y12 Q(s) a b (s+4)(s+16) Y22 Y22 = 2 Q(s) + Q(s) must be chosen so that ya and y22 are RC functions. It is con- venient in this case to choose the two y22's equal. Thus, an approp- riate Q(s) is (s +8)(s +20). Step 4: Realization of Network B is a conventional RC- ladder procedure and is only outlined in Figure 6. 4a. Realization of Network A is outlined in Figure 6. 4b and proceeds as follows: a A. s(s-3) a (s+4)(s+16) -y12 ( s+8)( s+20) y 22 ( s+8)( s+2o) B. Remove y22( +3) from y22(s). 7 19 133 y22(+ 3) = 11 23 = 253 8( 15 s+ 212)Cs -3) _y Y22 -Y22(3) 253(s +8)(s +16) C. Realize the zero at s = +3 as a pole of z = 1 . Y 253 z (s+8)(s+16) 8 (15s + 212) (s-3) 253 253 ( 257 s + 417 2) 8 257 (s-3) + 257 (15s + 212) 253 253 253 257s + 4172 1 z' - z 8 257 (s-3) 257 8(15s + 212) y' D. Shift zero of y' to s = 0 by removal of y' (0) 53 -20 -8 -2 -1 -Y12 (o-) 1 }tJ -16 -4 X C\ x_ c Y22 (ff ) r -14.8 I y =y22-Y24 -1) ! .I, 1 J }. o . -17. 8 Y z1-z- k-1 -í` /'\ 3+1 , I f1 1 y'= !z q - 9--- - Y"=y'-y'(-d I 1 -o X z"= - , 1 z!! k-2 (s+2) A. Realization of Nb. -20 -8 +3 ,x X-- o- -Y12(Q ) 1 -16 4 K © t f --- Y24') N -14. 1 a 1 --, 0-- k , 0- yT-Y22-Y24 e 4 1 1 1 \ . - . OV - X- z= - N -16.2 Y Lo v '-z-z(s-3)k+3 1 1 I Y°-- -, 0-- Y'- p - - 1 -- - - - y"=Y' -y'(0) ! -----O z"= 1 Ylk z11!--11_ il R Ran1;,7mtinr, f 1\T O a Figure 6. 4. Illustration of realization for s2 + 1 G12 (s +4)(s +16) 54 257 424 Y' (0) 253 1043 8096 514 s Y' - y'(0) - t I 1043 253 ( 257 s + 417 2) 1 E. Realize the zero at s = 0 as a pole of z" = -! Y 253 1043 257s + 4172 z 514 8096 s 253 1043 4172 257 + ) 514 8096 ( -s At this point, the coefficients of realization for -y12 and -Y12 must be examined since the result is obviously not valid unless the two -y12's are realized within the same factor. If they are not the transmission of the network with the higher coefficient must be re- duced. For the two networks just realized, ka = 0. 06134 and kb = 0. 0977 so that attenuation must be added to Nb so that kb = ka; the attenuation required is ka /kb. The easiest point to insert the attenuation is to use the last resistance realized in Nb; it may be ac- complished as shown in Figure 6. 5 using a T -pad attenuator. o--/V/W- 10. 31 G 12(oc) = 0. 0977 1.814 2. 9562 t o 1. 11851 8. 470.51 5. 00 0--Atv\,-t° - o G12(0o) = 0, 0613 14. 2984. 1. 118i). o + o 10. 319A Figure 6. 5. Modification of Na to equalize a transmission coefficients. 55 The resulting network from the preceeding realization after scal- ing s = jl to s = j1000 cps and scaling impedance by 100 is shown in Figure 6. 6; graphical comparison between computed and measured frequency response is shown in Figure 6. 7. 846.96A. 500.0J2-M/\ A4` 1 .,7.9245k l. 4 5 lk o )(__. 0.01004 f 0. 109 23µf IN OUT 1. 429811 181. 4211 295. 56 -1. 0377k 1. 6297k NW-7 t . 006016µf .0/ 1214f 242. 161L 190. 23A Bias (s +1) Figure 6. 6. Network for realization of G12 (s+4) (s+16) scaled to 1 kc. Figure 6. 7. Frequency response curve rM-- ...... : __ ...... ,1 .X11, for network shown in Figure ..1.111111111111i....-4ÁÌIÌÌÌÌÌÌÌÌÌ ,11111111 II 111i111 2MMM... IIIIHNIIHIIIIIIIII.liHllllllllnllllnlin IIIl11,lI,IIIIIIlIIH11111111H111u111111111111 mono M_l... IIIIIIIIIIIIIIIIIM..'7 1111 11111 1UI1UI11/M InunnlUnnnnnll 11111111// 6. 6. IIIIIIIIIn111H15I/ I1H111111111111111// 1111111111/11111111111111M1111111111111111111111//MM 1111IIIIIUIIIIPiM/11/1111111I1111U1111//MM IIIIIIIIIIIIIIIINIIIIIIIIIIIIIIIIIIUIIIUIIMMMMM IIIIIIIIIIIUIP.AllllllllllllllllllllUllIMIMM :IIIIIIIIIUIUIIIIUIIIIUIIIIIIIIIIilllllullllllll/M 111111111111111111,.11011111111111111111111111111111111 oauounnnunnnrnslmmuununnuunnnnlmmmnooumnuuunnnuunnmunnnumnnumnmmmmanaol11111111111111111f1111111111111111111111111 oununnuuumelwimuunnnnnumunmmmmmoumnunnunnunuununuuuumnmmmmmmunm o Theoretical response curve ,I,,::_,-:;Y --:::::-_ ___:::_- o o o o Measured response 11 '1"l' MM ' HI 111. "'1X iINI 1 11-IIn1Ï111111N-NNÑ I'"Ixll.0 x x =- 1 -Ï'1ÌllÌÌ111ÌIÌIIÌÌiNNNI11111111111pÌÌpi22NNN-N 1 YIÌÌ 111 ,N11:ÌI1111Ñ11NIN 'x11:11ÌI1ÑR111X.1111111111n11 Ì1I 1 IlIIt1.\NNNH NNNN NIN111MI1IIIIn....IIIIIIIIIIIIIIIIIInNI N.Y..1INIIIIIInI111111NI1...111111IIIIIIInp11I11NININNN 1111111111 ,n11nIN1MInnIN 111111nNImnNHII11111n11I1Ì11111NINNNMp NIN IIIINIIIIIIIIIIIIINI.INIIIIIIn111I11111111ININNNNNN NIIIIIIIIIININMM1IIINIIl1111n1111111.111NINNNNNI",M INnlNnnuulNlnmmlNNmmnnXM ppIIIIUIIIIH1.t11111111111111NNMNINI NN 1111p1q111Mn.111/.N11111111111111111n1ININNNNNM NIIIIIIMIIMWIRII N11nIIIN.NINNNI N IIIIIIIl111111R1II11111U11111I.1111111111NXNIN IIIIINIINIIIIIIIIIIIt1111I111111111IINNNI NUN MMIMIII111111111/111111111111111UIN IIIIIIInm11MIMMM111H1111111IIIIIIIIIN111NNNNN/N IIII/IIII minim g111Hp11111111111NUnN n1111111IIIIIHUIIINIIIINIIIIIIINIININNNNNMM NN In1111111111111111111111111111111111111n1111111NN IIIIHIIIIMI1111111111111111111111MI1I11111111NNNN11/, IIIIIIIIIIIIIIIIIIIIH1111111111111111111111111111NN 1/11111111011.11111111111111111111111111111111111111111N111111111111110111 NNMaa1111111111111 NIM IINI MINNNI IIIII IIIII IIIII IIIII IIIII aN1111111111111111IIIMII IIIIN11111111111111111111111 NIII NNaa'/a1111111111111111111111111111H11111111111111111111111 NIN alalNNa 111111111111111111111111111111N1111111111111111111mMH1NNNNaa1111 n11111alalaa111NIMNI111111111111IIIIIIIIIIIIII Maaaaa1111111111111111111111HNNIN aMaaan IIIII IIIIIIIItI IIIII NIII aM11aU111O1111111111111111IMIININ IIIIIIIIIIIIIIIIINI INII nu1111111111I IIIIIIHII IIIIINNI IIIII IIIII I111HIIIInm aaHl 1w111uxlanalaluwul 1 111 M1UM I 1 IN nnuunnmwlu_--__--__. u nlluunnwu- --_.-.--.- n II _unummn nm I ;,OiIIIII111aI1aI1111MI1111MpII11IaaI1HIIINIi1116aU1111111111111a1111IMINIlIN11111tlIII11111MW111nIunl ___-_ w M . . . _::T: . ----- _ - -- a --- y a 10 -- -- ~------: ==°_--==== _ -_N.=------______=::.-r;á>,_=__=°=_-° ._ --..--_ -__;--_. -.- - ____: 1W - __- ---- . .E__ ..I n >: :ä w:=.=__----- , - »... ,iM: ...... a------..... :w N"NWt vÌi mi::ii::::::ii::iÑiPñÌÌ_= n.1x .....N,IM. 1-MI . -lU.wu1.:::iM"11:: SE ., '__-_. 11 I,ÌÑÌMiE- ::Ìi:Ñ,Ì1NÌ- m MItYÌ MIIIIMIINIIIIH-IIM1111H1111Ñ11111fl111MIHIM I MN IM.NIIUHIMUIII/IWiIINIHIMIMI ,ïi: Ilp.xi,ii :::Ì -.. H HHINIn1NllU1NII.IUIIIHIIIINIIN111// nHII11MNIHHlnn1MHH.M11111 MMI.UUIIIII1111HMIMl111/IIIIM11111111u11//M .M1nHIM1M . 1IIIU1111111n11N11 // / //MMM M11nn1111NNIMMHM111n11M11//M 1/IIIIMIIIIIIMUIIIMIIIIIIIt11111111111111// UIn1U1NIN IIIIUIINI//MMMMMH Mn111111u11U111IIUMINIIMII//MMMM MIIIIn11n1MNMMtlOIIIUIIUMI/1WWW// UnH1111UUNIMIl1111111111111111111N1//MMM nmaummnunmnnwYnIWN//MMUN.M llIlM111H111111111UH111//UIIIIIIIINHINNIII/ IIIIIIUIINIHNIWNIU1111111HHIMMINI/ IIIIIIIII MINIM ltl1111111111111111111UIMl/MM qIIIIIIIIIIIIIMIUI/IIIIIIIIImiIInMM//MM 11M111111111NIIINIIINMIIIIHIIIIH1111NN111//M IIIIIHIIIMINN111111111111HIHHIIIdI// 11111111111111H111111M11111111111111111111111111 IIIIIHIIIHIIIIIIUIIIIIYIHHIIIHNIUNIMIMIMMM , mmMMaaO l[IIIM1111111111111ffim111111111111111111011111MmM 1111111111111111111N11111111111111111fnWm111 mman111111111111m111mmu1uummmanl[m11uHnmmm1mm1nmmÁmmNann[m1nn11mnlunumuumunlumMMmmmmmnunmmmmnnnmummnmmmmnn[11[1111111111H1H1111111111NI11111111111111111111111111111MMM 1p11111111NmmNIM11mHH1MNN11M [N 10 mmmnnnnnmunnunmlqmmnunumounmummmmmnnumnnnoumnnumnnunnnlmmnimmmmnummmaunumunnmumnnnuunuummoouonmunnuumimmmmnunnnlummnnmmmann[ 10 l00 l03 l04 10 Frequency, cycles per second 57 SUMMARY AND CONCLUSIONS The circuit of Figure 3. 8, page 9, exhibits five distinct regions of operation; the one of particular interest occurs after the zener diode begins to conduct and a negative resistance is generated at the terminals. A set of design equations, Equations 3. 24 through 3. 28, is pre- sented which allows the circuit component values to be determined from any set of specifications. Table 4. 1 compares a set of specified circuit parameters to parameters measured in a circuit designed to those specifications. Several negative- resistance synthesis techniques proposed by Losee and Mitra (6, p. 357 -62) are outlined for the purpose of demon- strating applications of the controlled negative resistance to actual problems in network synthesis; two such networks are actually realized and the measured frequency response is compared to the theoretical response. The problem of including biasing within the network is discussed and it is demonstrated that biasing may always be included within a + RC network without otherwise modifying the network. The principal conclusion is that the device presented is a practi- cal device for use in network synthesis where negative resistances are required. It's practicality arises from the ease of design, the 58 ability to handle large signals, and the ease with which the negative resistance may be controlled. 59 BIBLIOGRAPHY 1. Crisson, George. Negative impedances and the twin 21 -type repeater. The Bell System Technical Journal 10:484 -513. 1931. 2. Hull, Albert W. The dynatron. Proceedings of the Institute of Radio Engineers 6:5 -35. 1918. 3. Lesk, I. A. and V. P. Mathis. The double -base diode: a new semiconducting device. In: Convention Record of the Institute of Radio Engineers, New York, 1953. pt. 6. 2 -8. 4. Linvill, J. G. R. C. active filters. Proceedings of the In- stitute of Radio Engineers 42 :555 -564. 1954. 5. . Transistor negative impedance converters. Proceedings of the Institute of Radio Engineers 41 :725 -729. 1953, 6. vosee, D. L. and S= K. Mitre.. Transfer function synthesis of tunnel diode networks. Institute of Electrical and Elec- tronics Engineers Transactions on Circuit Theory 11:357 -362. Sept. , 1964. 7. Merrill, J. L. Jr. Theory of the negative impedance converter. The Bell System Technical Journal 30:88 -109. 1951. 8. Shockley, W. and J. F. Gibbons. Introduction to the four - layer diode. Semiconductor Products 1:9 -13.. January Feb- ruary, 1958. 9. Sommers, H. S. Jr. Tunnel diodes as high frequency devices. Proceedings of the Institute of Radio Engineers 47 :1201 -1206. 1959. 10. Strauss, Leonard. Wave generation and shaping. New York, McGraw -Hill, 1960. 509 p. 11. Todd, Carl David. A composite circuit exhibiting S -type negative resistance. Semiconductor Products 5 :24 -28. October, 1962. 60 12. . Measurement of tunnel diode negative re- sistance. Review of Scientific Instruments 32 :338 -342. 1961. 13. Weinburg, Louis. Designing passive and tunnel diode networks, part 1. Electrical Manufacturing 66:80 -87. 1960. 14. . Designing passive and tunnel diode net- works, part 2. Electrical Manufacturing 66:116 -120. 1960. 15. Yanagisawa, Takesi. R. C. active networks using current in- version type negative impedance converters. Institute of Radio Engineers Transactions on Circuit Theory 4:140 -144. Sept. , 1957. APPENDIX 61 APPENDIX I MEASUREMENT OF NEGATIVE RESISTANCES The problem of measuring the magnitude of negative resistances presents several difficulties, particularly because of the bias require- ments. The simplest approach is to use a curve tracer; this proved to be most useful during experimental work on the negative resistance cir- cuit where highly accurate measurements of negative resistance are not required. A curve tracer such as the Tektronix 575 or the circuit shown in Figure I. 1 proved adequate. +35v 11.11 100. 01L . 01v/m Oscilloscope vertical (in- . 10v/ma o verted) AC coupled or DC 60 cy lOk2N498 offset. 30v peak 2N1613 °Oscilloscope external horiz. negative 100 k r,sistance (1 megohm) i Figure I. 1. Simple curve tracer for two -terminal devices. When greater accuracy is required, a different approach is re- quired. One such approach is to modify the standard Wheatstone Bridge to accept bias as shown. in Figure I. 2; two of the resistive arms 62 are replaced with equal capacitors to prevent bias current from cir- culating in the bridge. Stable biasing of the negative resistance is possible only if r - R <0; fortunately, this condition presents a posi- tive resistance to the bridge and it may be easily measured by nulling the bridge with R'. The method is not direct since the value of -R must be computed from the known value of r and the calibrated value of R.'. Audio generator Bias Audio detector Figure I. 2. Bridge for measuring negative resistance. Another approach used is a modification of a method suggested by Todd (12, p. 338). The principle is direct; when R' = -R , an infinite resistance occurs in the signal path and a null occurs. The circuit shown in Figure I. 3. The only difficulty with this technique is that DC current must flow through the calibrated resistor. 63 Audio detector Audio generator Figure I. 3. Circuit for measuring negative resistance.