DOCSLIB.ORG

DDR5 Speci- Fication As a New WRITE Pattern Command

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
DDR5 Speci- Fication As a New WRITE Pattern Command Solid State Technology Association 3103 North 10th Street Arlington, Virginia 22201 TEL: (703) 907-7560 COMMITTEE LETTER BALLOT Committee: JC42.3 Committee Item Number: xxxx.yy Subject: DDR5 Full Spec Draft Rev0.1 Background: All red and black items are for ballot, red text identifies the updates from the previous ballot. Items in grey are not part of the ballot material and are for reference only Keywords: DDR5, Full Specification Ballot Template Version draft rev. 8/11 © JEDEC 2011 DDR5 Proposal Item 1845.31A P R O P O S E D R O P P Page 2 of 2 REVISION HISTORY Revision Author Date Status and Description Rev0.1 C.Cox 12/5/17 Initial Format Rev0.1 - Includes all ballots through Q3’17 Document Formating Legend Colors used in this Document and what they mean: RED - All Red text is defined as something that is NEW BLACK - Is considered the standard or the current Ballot. LIGHT GREY - All Light Grey text is defined as something that should be considered TBD. The content may be accurate or the same as previous technologies but has not yet been reviewed or determined to be the working assumption. Special NOTE: Some legacy diagrams that have not been updated may be BLACK or RED but that does not indicate that they are new or current working assumption. In the case where there is a digram that is BLACK or RED, it is important to look at the section for reference. If the section/heading is BLACK or RED, then it is as intended. If the section/heading is GREY, then assume its only an artifact of the old diagram that could not easily be changed. Proposed DDR5 Full spec (79-5) Item No. xxxx.yyy Page 1 1. Scope ................................................................................................................................................................................... 1 2. DDR5 SDRAM Package, Pinout Description and Addressing ............................................................................................. 2 2.1 DDR5 SDRAM Row for X4, X8 - Q3’17 Ballot#1830.69B ............................................................................................... 2 2.2 DDR5 SDRAM Ball Pitch - Q3’17 Ballot#1830.69B ........................................................................................................ 2 2.3 DDR5 SDRAM Columns for X4, X8 - Q3’17 Ballot#1830.69B ........................................................................................ 2 2.4 DDR5 SDRAM X4/8 Ballout using MO-xxx - Q3’17 Ballot #1830.69B ............................................................................ 3 2.5 DDR5 SDRAM X16 Ballout using MO-xxx - No Ballot .................................................................................................... 4 2.6 Pinout Description - Q4’16 Ballot #1830.69 .................................................................................................................... 5 2.7 DDR5 SDRAM Addressing - Q2’17 Item#1830.36B ....................................................................................................... 7 3. Functional Description.......................................................................................................................................................... 8 3.1 Simplified State Diagram - No Ballot ............................................................................................................................... 8 3.2 Basic Functionality - No Ballot......................................................................................................................................... 9 3.3 RESET and Initialization Procedure - Q1’17 Ballot ......................................................................................................... 10 3.3.1 Power-up Initialization Sequence ....................................................................................................................... 10 3.3.2 TBD - VDD Slew rate at Power-up Initialization Sequence ................................................................................ 13 3.3.3 TBD - Reset Initialization with Stable Power ...................................................................................................... 14 3.4 Mode Register Definition - Q1’17 Ballot #1845.17 .......................................................................................................... 15 3.4.1 Mode Register Read (MRR) ............................................................................................................................... 15 3.4.2 Mode Register WRITE (MRW) ........................................................................................................................... 16 3.4.3 Mode Register Truth Tables and Timing Constraints ......................................................................................... 16 3.5 Mode Registers - Q1’17 Ballot #1845.17 (OUT OF DATE) ............................................................................................. 20 3.5.1 Mode Register Assignment and Definition in DDR5 SDRAM............................................................................ 20 3.5.2 MR0 (MA[7:0]=00H) - Q3’17 Ballot #1845.35B .................................................................................................. 22 3.5.3 MR1 (MA [7:0] = 01H) - PDA Mode Details - Q3’17 Ballot #1845.35B............................................................... 23 3.5.4 MR2 (MA [7:0] = 02H) - DQS Training - Q3’17 Ballot #1845.35B ...................................................................... 24 3.5.5 MR3 (MA[7:0]=03H) - Functional Modes - Q3’17 Ballot #1845.33B................................................................... 25 3.5.6 MR4 (MA[7:0]=04H) - Refresh Settings - Q1’17 Ballot #1845.32B w/Editorial update ....................................... 26 3.5.7 MR5 (MA[7:0]=05H) - IO Settings - Q2’17 Ballot #1845.31A ............................................................................. 27 3.5.8 MR6 (MA[7:0]=06H) - Write Recovery Time & tRTP - Q2’17 Ballot #1845.31A ................................................. 28 3.5.9 MR7 (MA[7:0]=07H) - Q2’17 Ballot #1845.31A .................................................................................................. 29 3.5.10 MR8 (MA[7:0]=08H) - Preamble / Postamble - Q2’17 Ballot #1845.31A.......................................................... 30 3.5.11 MR9 (MA[7:0]=09H) - VREF Config - Q2’17 Ballot #1845.30A - w/Editorial Updates ...................................... 31 3.5.12 MR10 (MA[7:0]=0AH) - Vref DQ Calibration Settings - Q2’17 Ballot #1845.30A..............................................32 3.5.13 MR11 (MA[7:0]=0BH) - Vref CA Calibration Settings - Q2’17 Ballot #1845.30A ..............................................32 3.5.14 MR12 (MA [7:0] = 0CH) - tCCD_L - No Ballot .................................................................................................. 33 3.5.15 MR13 (MA [7:0] = 0CH) - Blank - No Ballot ...................................................................................................... 34 3.5.16 MR14 (MA[7:0]=0EH) - ECC Configuration - Q1’17 Ballot #1845.40 ............................................................... 35 3.5.17 MR15 (MA[7:0]=0FH) - ECS Threshold - Q1’17 Ballot #1845.40 ..................................................................... 35 3.5.18 MR16 (MA [7:0] = 10H) - Reserved for Transparency 1 - Q1’17 Ballot #1845.40 ............................................ 36 3.5.19 MR17 (MA [7:0] = 11H) - Reserved for Transparency 2 - Q1’17 Ballot #1845.40 ............................................ 36 3.5.20 MR18 (MA [7:0] = 12H) - Reserved for Transparency 3 - Q1’17 Ballot #1845.40 ............................................ 36 3.5.21 MR19 (MA [7:0] = 13H) - Reserved for Transparency 4 - Q1’17 Ballot #1845.40 ............................................ 36 3.5.22 MR20 (MA [7:0] = 14H) - Reserved for Transparency 5 - Q1’17 Ballot #1845.40 ............................................ 37 3.5.23 MR21 (MA [7:0] = 15H) - Reserved for Transparency 6 - Q1’17 Ballot #1845.40 ............................................ 37 3.5.24 MR22 (MA [7:0] = 16H) - Reserved for Transparency 7 - Q1’17 Ballot #1845.40 ............................................ 37 3.5.25 MR23 (MA [7:0] = 17H) - PPR Settings - Q1’17 Ballot #1845.41 ..................................................................... 38 3.5.26 MR24 (MA [7:0] = 18H) - Blank - No Ballot....................................................................................................... 39 3.5.27 MR25 (MA[7:0]=19H) - Read Training Mode Settings - Q1’17 Ballot #1845.42 ............................................... 40 3.5.28 MR26 (MA[7:0]=1AH) - Read Pattern Data0 / LFSR0 - Q1’17 Ballot #1845.42 ............................................... 41 3.5.29 MR27 (MA[7:0]=1BH) - Read Pattern Data1 / LFSR1 - Q1’17 Ballot #1845.42 ............................................... 41 3.5.30 MR28 (MA[7:0]=1CH) - Read Pattern Invert DQL7:0 (DQ7:0) - Q1’17 Ballot #1845.42................................... 42 3.5.31 MR29 (MA[7:0]= DH) - Read Pattern Invert DQU7:0 (DQ15:8) - Q1’17 Ballot #1845.42 ................................. 42 3.5.32 MR30 (MA[7:0]=1EH) - Read LFSR Assignments - Q1’17 Ballot #1845.42..................................................... 43 3.5.33 MR31 (MA[7:0]=1FH) - Read Training Pattern Address - Q1’17 Ballot #1845.42 ............................................ 43 3.5.34 MR32 (MA[7:0]=20H) - CK ODT - Q2’17 Ballot #1845.43 ...............................................................................
Load more

Recommended publications
  • Improving DRAM Performance by Parallelizing Refreshes
    Improving DRAM Performance by Parallelizing Refreshes with Accesses Kevin Kai-Wei Chang Donghyuk Lee Zeshan Chishti† [email protected] [email protected] [email protected] Alaa R. Alameldeen† Chris Wilkerson† Yoongu Kim Onur Mutlu [email protected] [email protected] [email protected] [email protected] Carnegie Mellon University †Intel Labs Abstract Each DRAM cell must be refreshed periodically every re- fresh interval as specified by the DRAM standards [11, 14]. Modern DRAM cells are periodically refreshed to prevent The exact refresh interval time depends on the DRAM type data loss due to leakage. Commodity DDR (double data rate) (e.g., DDR or LPDDR) and the operating temperature. While DRAM refreshes cells at the rank level. This degrades perfor- DRAM is being refreshed, it becomes unavailable to serve mance significantly because it prevents an entire DRAM rank memory requests. As a result, refresh latency significantly de- from serving memory requests while being refreshed. DRAM de- grades system performance [24, 31, 33, 41] by delaying in- signed for mobile platforms, LPDDR (low power DDR) DRAM, flight memory requests. This problem will become more preva- supports an enhanced mode, called per-bank refresh, that re- lent as DRAM density increases, leading to more DRAM rows freshes cells at the bank level. This enables a bank to be ac- to be refreshed within the same refresh interval. DRAM chip cessed while another in the same rank is being refreshed, alle- density is expected to increase from 8Gb to 32Gb by 2020 as viating part of the negative performance impact of refreshes.
    [Show full text]
  • Load Management and Demand Response in Small and Medium Data Centers
    Thiago Lara Vasques Load Management and Demand Response in Small and Medium Data Centers PhD Thesis in Sustainable Energy Systems, supervised by Professor Pedro Manuel Soares Moura, submitted to the Department of Mechanical Engineering, Faculty of Sciences and Technology of the University of Coimbra May 2018 Load Management and Demand Response in Small and Medium Data Centers by Thiago Lara Vasques PhD Thesis in Sustainable Energy Systems in the framework of the Energy for Sustainability Initiative of the University of Coimbra and MIT Portugal Program, submitted to the Department of Mechanical Engineering, Faculty of Sciences and Technology of the University of Coimbra Thesis Supervisor Professor Pedro Manuel Soares Moura Department of Electrical and Computers Engineering, University of Coimbra May 2018 This thesis has been developed under the Energy for Sustainability Initiative of the University of Coimbra and been supported by CAPES (Coordenação de Aperfeiçoamento de Pessoal de Nível Superior – Brazil). ACKNOWLEDGEMENTS First and foremost, I would like to thank God for coming to the conclusion of this work with health, courage, perseverance and above all, with a miraculous amount of love that surrounds and graces me. The work of this thesis has also the direct and indirect contribution of many people, who I feel honored to thank. I would like to express my gratitude to my supervisor, Professor Pedro Manuel Soares Moura, for his generosity in opening the doors of the University of Coimbra by giving me the possibility of his orientation when I was a stranger. Subsequently, by his teachings, guidance and support in difficult times. You, Professor, inspire me with your humbleness given the knowledge you possess.
    [Show full text]
  • NON-CONFIDENTIAL for Publication COMP
    EUROPEAN COMMISSION Brussels, 15.1.2010 SG-Greffe(2010) D/275 C(2010) 150 Subject: Case COMP/C-3/ 38 636 Rambus (Please quote this reference in all correspondence) […]* 1. I refer to Hynix' complaint to the Commission of 18 December 2002 lodged jointly with Infineon pursuant to Article 3 of Council Regulation No. 17/621 against Rambus Inc. ("Rambus"), an undertaking incorporated in 1990 in California and reincorporated in Delaware, USA, in 1997, with its principal place of business in Los Altos, California, regarding alleged violations of Article 101 and Article 102 of the Treaty on the Functioning of the European Union ("TFEU")2 in connection with computer memory chips which are known as synchronous DRAM chips ("the Complaint"). I also refer to the letters listed here below, by which Hynix provided additional information/explanations on the above matter, as well as the Commission’s letter of 13 October 2009 ["Article 7 letter"] addressed to Hynix in that matter and the response to the Article 7 letter of 12 November 2009. […] 2. For the reasons set out below, the Commission considers that there is no sufficient degree of Community interest for conducting a further investigation into the alleged infringement and rejects your complaint pursuant to Article 7(2) of the Commission Regulation (EC) 773/20043. * This version of the Commission Decision of 15.1.2010 does not contain any business secrets or other confidential information. 1 Regulation No. 17 of the Council of 6 February 1962, First Regulation implementing Articles 85 and 86 of the Treaty (OJ No. 13, 21.2.1962, p.
    [Show full text]
  • Refresh Now and Then Seungjae Baek, Member, IEEE, Sangyeun Cho, Senior Member, IEEE, and Rami Melhem, Fellow, IEEE
    IEEE TRANSACTIONS ON COMPUTERS 1 Refresh Now and Then Seungjae Baek, Member, IEEE, Sangyeun Cho, Senior Member, IEEE, and Rami Melhem, Fellow, IEEE Abstract—DRAM stores information in electric charge. Because DRAM cells lose stored charge over time due to leakage, they have to be “refreshed” in a periodic manner to retain the stored information. This refresh activity is a source of increased energy consumption as the DRAM density grows. It also incurs non-trivial performance loss due to the unavailability of memory arrays during refresh. This paper first presents a comprehensive measurement based characterization study of the cell-level data retention behavior of modern low-power DRAM chips. 99.7% of the cells could retain the stored information for longer than 1 second at a high temperature. This average cell retention behavior strongly indicates that we can deeply reduce the energy and performance penalty of DRAM refreshing with proper system support. The second part of this paper, accordingly, develops two practical techniques to reduce the frequency of DRAM refresh operations by excluding a few leaky memory cells from use and by skipping refreshing of unused DRAM regions. We have implemented the proposed techniques completely in the Linux OS for experimentation, and measured performance improvement of up to 17.2% with the refresh operation reduction of 93.8% on smartphone like low-power platforms. Index Terms—SDRAM, refresh operation, power consumption, performance improvement. ✦ 1 INTRODUCTION again. Refresh period, the time interval within which we RAM is commonly used in a computer system’s main must walk through all rows once, is typically 32 ms or D memory.
    [Show full text]
  • A Modern Primer on Processing in Memory
    A Modern Primer on Processing in Memory Onur Mutlua,b, Saugata Ghoseb,c, Juan Gomez-Luna´ a, Rachata Ausavarungnirund SAFARI Research Group aETH Z¨urich bCarnegie Mellon University cUniversity of Illinois at Urbana-Champaign dKing Mongkut’s University of Technology North Bangkok Abstract Modern computing systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) data movement, especially off-chip to on-chip, is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost. The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, proliferation of different main memory standards and chips, specialized for different purposes (e.g., graphics, low-power, high bandwidth, low latency), and the necessity of designing new solutions to serious reliability and security issues, such as the RowHammer phenomenon, are an evidence of this trend.
    [Show full text]
  • Memory & Storage Challenges and Solutions
    Memory & Storage Challenges and Solutions G S A 2 0 1 9 Jinman Han Senior Vice President, Memory Product Planning & Application Engineering Legal Disclaimer This presentation is intended to provide information concerning SSD and memory industry. We do our best to make sure that information presented is accurate and fully up-to-date. However, the presentation may be subject to technical inaccuracies, information that is not up-to-date or typographical errors. As a consequence, Samsung does not in any way guarantee the accuracy or completeness of information provided on this presentation. The information in this presentation or accompanying oral statements may include forward-looking statements. These forward-looking statements include all matters that are not historical facts, statements regarding the Samsung Electronics' intentions, beliefs or current expectations concerning, among other things, market prospects, growth, strategies, and the industry in which Samsung operates. By their nature, forward- looking statements involve risks and uncertainties, because they relate to events and depend on circumstances that may or may not occur in the future. Samsung cautions you that forward looking statements are not guarantees of future performance and that the actual developments of Samsung, the market, or industry in which Samsung operates may differ materially from those made or suggested by the forward-looking statements contained in this presentation or in the accompanying oral statements. In addition, even if the information contained herein or the oral statements are shown to be accurate, those developments may not be indicative developments in future periods. Abstract Memory-centric system innovation is the overarching theme of modern semiconductor technology and is one of the crucial driving forces of the future IT world.
    [Show full text]
  • (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics
    Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics Minesh Pately Jeremie S. Kimzy Taha Shahroodiy Hasan Hassany Onur Mutluyz yETH Zurich¨ zCarnegie Mellon University Increasing single-cell DRAM error rates have pushed DRAM entirely within the DRAM chip [39, 76, 120, 129, 138]. On-die manufacturers to adopt on-die error-correction coding (ECC), ECC is completely invisible outside of the DRAM chip, so ECC which operates entirely within a DRAM chip to improve factory metadata (i.e., parity-check bits, error syndromes) that is used yield. e on-die ECC function and its eects on DRAM relia- to correct errors is hidden from the rest of the system. bility are considered trade secrets, so only the manufacturer Prior works [60, 97, 98, 120, 129, 133, 138, 147] indicate that knows precisely how on-die ECC alters the externally-visible existing on-die ECC codes are 64- or 128-bit single-error cor- reliability characteristics. Consequently, on-die ECC obstructs rection (SEC) Hamming codes [44]. However, each DRAM third-party DRAM customers (e.g., test engineers, experimental manufacturer considers their on-die ECC mechanism’s design researchers), who typically design, test, and validate systems and implementation to be highly proprietary and ensures not to based on these characteristics. reveal its details in any public documentation, including DRAM To give third parties insight into precisely how on-die ECC standards [68,69], DRAM datasheets [63,121,149,158], publi- transforms DRAM error paerns during error correction, we cations [76, 97, 98, 133], and industry whitepapers [120, 147].
    [Show full text]
  • Computer Architectures
    Computer Architectures Processor+Memory Richard Šusta, Pavel Píša Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.00 2019 1 The main instruction cycle of the CPU 1. Initial setup/reset – set initial PC value, PSW, etc. 2. Read the instruction from the memory PC → to the address bus Read the memory contents (machine instruction) and transfer it to the IR PC+l → PC, where l is length of the instruction 3. Decode operation code (opcode) 4. Execute the operation compute effective address, select registers, read operands, pass them through ALU and store result 5. Check for exceptions/interrupts (and service them) 6. Repeat from the step 2 AE0B36APO Computer Architectures 2 Single cycle CPU – implementation of the load instruction lw: type I, rs – base address, imm – offset, rt – register where to store fetched data I opcode(6), 31:26 rs(5), 25:21 rt(5), 20:16 immediate (16), 15:0 ALUControl 25:21 WE3 SrcA Zero WE PC’ PC Instr A1 RD1 A RD ALU A RD Instr. A2 RD2 SrcB AluOut Data ReadData Memory Memory A3 Reg. WD3 File WD 15:0 Sign Ext SignImm B35APO Computer Architectures 3 Single cycle CPU – implementation of the load instruction lw: type I, rs – base address, imm – offset, rt – register where to store fetched data I opcode(6), 31:26 rs(5), 25:21 rt(5), 20:16 immediate (16), 15:0 Write on rising edge of CLK RegWrite = 1 ALUControl 25:21 WE3 SrcA Zero WE PC’ PC Instr A1 RD1 A RD ALU A RD Instr.
    [Show full text]
  • Low Power DRAM Evolution Osamu Nagashima Executive Professional Micron Memory Japan
    Low Power DRAM Evolution Osamu Nagashima Executive Professional Micron Memory Japan JEDEC Mobile Copyright © 2016 Micron Technology, Inc & IOT Forum How We Got Here • Low Power DRAM evolved from a lower- voltage, lower-performance version of PC-DRAM designed for mobile packages to become one of the highest bandwidth-per-pin DRAMs available • High resolution displays, high-resolution cameras, and 3D rendered content are the primary drivers for increased bandwidth in mobile devices Mainstream DRAM Datarate by Type and Year of Introduction 4500 4000 3500 3000 2500 2000 1500 1000 500 0 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 LPDDR PC-DDR Evolution of Mainstream DRAM Energy Power Evolution 50.00 DDR2 DDR3 DDR4 LPDDR2 LPDDR3 LPDDR4 ENERGY, PJ/BITENERGY, 0.00 500 1000 1500 2000 2500 3000 3500 4000 4500 DATA RATE, MBPS Typical Mobile Device Usage 2% 8% 100% 4% 4% • The percentage of 20% 80% active usage has 20% 24% greatly increased in 60% recent years, driving 22% 13% an increase in 40% 12% memory bandwidth 20% 37% 34% • This has shifted 0% limitations from Heavy user Light user standby battery life to active battery life and Read Energy Write Energy Activate Energy thermal limits Standby Energy Refresh Energy Self Refresh Energy Near-Term Future • This evolution of system limitations is driving future LPDRAM architectures, beginning with the evolution of the LPDDR4 standard • Responding to the need for lower power, JEDEC is developing a reduced-I/O power version of LPDDR4, called LPDDR4X • LPDDR4X will reduce the Vddq level from 1.1v to 0.6v • Signaling swing will remain similar to LPDDR4 – This allows the same receiver designs and specifications to be used for both LPDDR4 and LPDDR4X LPDDR4X: I/O Energy Reduction • Reducing Vddq from 1.1v to 0.6v produces about 40% I/O energy savings LPDDR4 vs.
    [Show full text]
  • SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer
    Primer SDRAM Memory Systems: Architecture Overview and Design Verification SDRAM Memory Systems: Architecture Overview and Design Verification Primer Table of Contents Introduction . 3 - 4 DRAM Trends . .3 DRAM . 4 - 6 SDRAM . 6 - 9 DDR SDRAM . .6 DDR2 SDRAM . .7 DDR3 SDRAM . .8 DDR4 SDRAM . .9 GDDR and LPDDR . .9 DIMMs . 9 - 13 DIMM Physical Size . 9 DIMM Data Width . 9 DIMM Rank . .10 DIMM Memory Size & Speed . .10 DIMM Architecture . .10 Serial Presence Detect . .12 Memory System Design . .13 - 15 Design Simulation . .13 Design Verification . .13 Verification Strategy . .13 SDRAM Verification . .14 Glossary . .16 - 19 2 www.tektronix.com/memory SDRAM Memory Systems: Architecture Overview and Design Verification Primer Introduction Memory needs to be compatible with a wide variety of memory controller hubs used by the computer DRAM (Dynamic Random Access Memory) is attractive to manufacturers. designers because it provides a broad range of performance Memory needs to work when a mixture of different and is used in a wide variety of memory system designs for manufacturer’s memories is used in the same memory computers and embedded systems. This DRAM memory system of the computer. primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview Open memory standards are useful in helping to ensure for memory design improvement through verification. memory compatibility. DRAM Trends On the other hand, embedded systems typically use a fixed There is a continual demand for computer memories to be memory configuration, meaning the user does not modify larger, faster, lower powered and physically smaller. These the memory system after purchasing the product.
    [Show full text]
  • LPDDR4 Is Expected to Crossover LPDDR3 in 2018
    S32 DDR Tools Suite Radu Ivan, Jacques Landry Presenter title goes here Second line title goes here October 2019 | Session #AMF-AUT-T3843 Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2019 NXP B.V. Agenda • Industry Trends • Basic DDR SDRAM Structure • Next Generation of DDR Subsystems • S32 DDR Tool COMPANY PUBLIC 1 Industry Trends COMPANY PUBLIC 2 Industry Trend • DDR4 DRAM pricing is lower or same as DDR3\3L. The pricing crossover occurred around Q4 of 2015. Similarly, LPDDR4 is expected to crossover LPDDR3 in 2018. • Production DDR4 DRAM, DIMMs and LPDDR4 are available from most DRAM vendors. • The first NXP device with DDR4 support, T104x product, taped out in Q42013.The LS1043A also supports DDR4. Nearly 4 years of product experience with DDR4. − Many current and all future QorIQ products including T1, LS1, and LS2 products will support DDR4. • The first NXP device with LPDDR4 support is the i.MX8 Family. COMPANY PUBLIC 3 DDR3, DDR4 and LPDDR – Major Vendors Supported by all major memory vendors COMPANY PUBLIC 4 DRAM Migration Roadmap 100% 80% 60% DDR4 DDR3 40% DDR2 DDR 20% 0% 2016 2017 2018 2019 2016 2017 2018 2019 DDR 1% 1% 1% 1% DDR2 2% 1% 1% 1% DDR3 32% 20% 14% 8% DDR4 65% 78% 84% 91% COMPANY PUBLIC 5 DDR3/DDR3L/DDR4 Power Saving • DDR3 DRAM provides 20% power savings over DDR2 • DDR3L DRAM provides 10% power savings over DDR3 • DDR4 DRAM provides 37% power savings over DDR3L COMPANY PUBLIC 6 LPDDR2/LPDDR3/LPDDR4 Power Saving Reductions in operating voltage – LPDDR • LPDDR2 DRAM 1.8V (LPSDR, LPDDR) provides 36% power 1.2V (LPDDR2, LPDDR3) savings over LPDDR1 1.1V, 0.6V (LPDDR4/LPDDR4X) • LPDDR3 DRAM provides 10% power savings over LPDDR2 • PLDDR4 DRAM provides 37% power savings over LPDDR3 COMPANY PUBLIC 7 DDR SDRAM Highlights and Comparison Feature/Category DDR3 DDR4 LPDDR4 Package BGA only BGA only BGA.
    [Show full text]
  • Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh
    Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh Michael Jaemin Kim, Jaehyun Park, Yeonhong Park, Wanju Doh, Namhoon Kim, Tae Jun Ham, Jae W. Lee, and Jung Ho Ahn Seoul National University [email protected] Abstract—Since its public introduction in the mid-2010s, the computer system. RH-induced bit-flip can be abused in various Row Hammer (RH) phenomenon has drawn significant attention attack scenarios. For example, the RH can be utilized to from the research community due to its security implications. modify an unauthorized memory location or enable other Although many RH-protection schemes have been proposed by processor vendors, DRAM manufacturers, and academia, they attack techniques such as privilege escalation and cross-VM still have shortcomings. Solutions implemented in the memory attacks [1], [11], [12], [17], [41], [49], [53]. controller (MC) pay an increasingly higher cost due to their The criticality of this problem motivated many RH protec- conservative design for the worst case in terms of the number tion solutions. There exist several software-based solutions [5], of DRAM banks and RH threshold to support. Meanwhile, the [9], [19], [30], [49], but such solutions often incur a high- DRAM-side implementation has a limited time margin for RH protection measures or requires extensive modifications to the performance cost and have limited coverage (i.e., only ef- standard DRAM interface. fective against a specific attack scenario). For these reasons, Recently, a new command for RH protection has been intro- architectural solutions have emerged as promising alternatives. duced in the DDR5/LPDDR5 standards, called refresh manage- By providing the RH mitigation at the DRAM device level, ment (RFM).
    [Show full text]