Symposium Time Table and Program
Keynote I
Trend of Multi-/Many-core for Embedded Systems
Fumio Arakawa Chief Professional, Renesas Electronics Corp. Japan
Date : 9:20 A.M.- 10:20 A.M., Thursday, September 20, 2012 Place : Lecture Theater
Abstract A multi-/many-core is one of the most promising approaches to realize high-efficiency, which is the key factor to achieve high-performance under some fixed power and cost budgets. A cloud system enables thin clients in many cases relying on high-performance of severs remotely connected by network; however, it is still desirable to accomplish a real-time or dependable operation locally by an embedded system. This is because some critical operation does not allow slow or unpredictable response caused by network delay or disconnection. Such a disadvantage of network should be concealed from a user. Therefore, embedded systems will employ multi- /many-core architecture more and more to realize various cool functionalities with/without network. A heterogeneous multi-core chip, RP-X integrates eight SH-X4 CPU cores, four flexible engine (FE) cores, two matrix processor (MX) cores, and a video processing unit (VPU). The SH- X4 cores run at 648MHz and achieve totally 13.7 Dhrystone GIPS and 36.3 peak GFLOPS. Overall, the RP-X achieves 114.7GOPS with 3.07W, and the power-performance ratio is as high as 37.3 GOPS/W.
Biography: Fumio Arakawa is a chief professional in the System Core Development Division of Renesas Electronics. His research interests include architecture and micro-architecture of low- power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He’s a program committee co-chair of the Cool Chips conference series, a guest editor of COOL Chips Special Section/Issue of IEEE Micro, a program committee member of the VLSI Circuits Symposium, and the chairman of Microprocessor Technical Committee and Multi-/Many-core Application Research Committee of Japan Electronics and Information Technology Industries Association. He’s a member of IEEE and IEICE.
1 Keynote II
An NoC Architecture for Inductive Coupling Wireless Interconnect
Hideharu Amano Professor, Keio University, Japan
Date : 1:30 P.M.- 2:30 P.M., Thursday, September 20, 2012 Place : Lecture Theater
Abstract The initial cost of LSI for design and mask is growing in advanced technologies, and developing various types of SoC (System-on-a-Chip)s for required application has become difficult. SiP (System in Package) or 3-dimensional implementation techniques can address the problem by connecting multiple dies. Various scales and functions can be realized from various combination of dies. Especially, inductive coupling wireless 3-D connection is attractive because of its flexibility. An NoC architecture which enables to replace and add dies is proposed. By using a simple ring topology and bubble-flow control, dies can be connected and switched without deadlock. The experience using a prototype chip Cube-0 is reported.
Biography: Hideharu Amano received the Ph.D degree from Keio University, Japan in 1986. He is now a Professor in the Department of Information and Computer Science, Keio University. His research interests include the area of parallel architectures and reconfigurable computing.
2 Keynote III
System-on-Chip Design Verification: Challenges and State-of-the-art
Sofiène Tahar Professor, Concordia University, Montreal, Canada
Date : 9:40 A.M.- 10:40 A.M., Friday, September 21, 2012 Place : Lecture Theater
Abstract We address an important area of System-on-Chip R&D activity, namely "Design Verification". Verification today is known to cost about 70% of industrial electronics design projects, in terms of human, computer and budget. Many product delays are caused by verification taking longer than expected, and despite multiple efforts, products are delivered with uncaught bugs. We present the different kinds of verifications used today in an industrial design flow, namely design, implementation and fabrication verification. We then focus more on design verification from high level specification to gate level implementation. Several technologies will be displayed and compared, drawing a picture to still open problems and possible research issues. Among them "formal verification" is one of the most active areas that is carried out since recently and which make use of computerized mathematical reasoning to verify system properties. Example applications of this technology used in industry scale projects will be presented and discussed.
Biography: Sofiene Tahar received in 1990 the Diploma degree in computer engineering from the University of Darmstadt, Germany, and in 1994 the Ph.D. degree with "Distinction" in computer science from the University of Karlsruhe, Germany. Currently he is Professor in the Department of Electrical and Computer Engineering at Concordia University, Montreal, Quebec, Canada, where he is holding a Senior Research Chair in Formal Verification of System-on-Chip. Prof. Tahar is founder and director of the Hardware Verification Group at Concordia University, which focuses on developing verification technologies in the fields of microelectronics, telecommunications, security, aviation, etc. He has received several awards and distinctions, including in 2010 a National Discovery Award, given to Canada's top 100 researchers in engineering and natural sciences. Prof. Tahar is senior member of IEEE and member of the Order of Engineers of Quebec, ACM, IEEE Computer and IEEE Communications Societies.
3 Keynote IV
Cool System: A Scalable and Energy-Efficient 3D Heterogeneous Multi-Chip System with Cool Interconnect, Cool Chip, and Cool Software
Yukoh Matsumoto President, TOPS Systems Corp., Japan
Date : 1:20 P.M.- 2:20 P.M., Friday, September 21, 2012 Place : Lecture Theater
Abstract “Smart” Information Systems, such as next-generation Smart Phones, Tablets, Smart-TVs, Automotive safety systems, etc. drive evolution of SoC architecture to meet these system requirements such as high performance with scalability and flexibility of functionality, with low- power and low-cost in short time-to-market, that currently limited by SOCs integrating multiple processor cores and a number of hardwired accelerator IPs. 3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. In this presentation, I introduce a vision and architecture of Cool System that consists of three fundamental technologies, such as 1) Cool Chip, to make a high performance microprocessor chip to be low-power enough to avoid heat issue, 2) Cool Software, to increase processor core utilization with distributed processing software, and 3) Cool Interconnect, to enable low-power and scalable 3D Multi-Chip stacking of heterogeneous LSIs. Cool System architecture takes an approach to drastically reduce the operating clock frequency, but keep the high performance with several hardware-software techniques and optimizations through architecture-and-algorithm co-design. 1) Cool Chip architecture has features such as, a heterogeneous Multi-Core with stream processing cores, distributed parallel processing with zero-overhead message passing mechanisms, application domain specific heterogeneous Multi- Core configurations in Instruction Set Architecture and , etc. 2) Cool Software is a distributed parallel processing software based on Kahn Process Network Model with stream processing scheduling. 3) Cool Interconnect is a common interface to enable scalable and heterogeneous Multi-Chips stacking with low-power wide bandwidth communication.Example application domains, such as next generation DTV and Video Mining, and their domain specific architectural solutions will be presented. In addition, the architectural details and characteristics of Cool Interconnect test chip and Cool System test chips will be presented. 4 Biography: Dr. Yukoh Matsumoto is the chief architect, and president and CEO of TOPS Systems Corp. He led “Cool System : Ultra-Low-Power 3D stacked heterogeneous Multicore / Multichip” project supported by NEDO and “Ultra-Android : Distributed Processing embedded software platform” project supported by METI. Currently, he is working on “Low-Power Many-Core Architecture and Compiler Technology” project supported by NEDO. In his 26 years of carrier, he has architected and designed over 10 advanced microprocessors such as, Embedded Multicore processors, x86 microprocessors, and DSPs. He funded TOPS Systems Corp. in 1999, and received the Takeda Techno-Entrepreneurship Award, Tsukuba Venture Award, and ET Award in hardware in 2001, 2010, and 2011 respectively. Prior to TOPS Systems, he has held several positions within Texas Instruments and its R&D organization in US and Japan, and within V.M. Technology, a microprocessor start-up in Japan. He received the Dr. of Information Sciences (the Ph.D.) degree from the Graduate School of Tohoku University, Sendai, Japan, in 2007, and participated in the MOT (Management of Technology) program at the Graduate School of Engineering in Tokyo University from 2004 through 2005. He is also President & CEO of Cool Soft Corp., and a member of Microprocessor Technical Committee, Multi/Many- core Application Research Committee, Information System Disruptive Technology Research Committee, and 3D Semiconductor Sub-Committee of JEITA.
5 Keynote V
Scalable Many-core Acceleration for Image Understanding - is CPU+GPU the answer?
Luca Benini Professor, University of Bologna, Italy
Date : 2:20 P.M.- 3:20 P.M., Friday, September 21, 2012 Place : Lecture Theater (Video-session)
Abstract Image understanding is becoming the next "killer app" for mobile and embedded platforms and devices. Visual search, face and gesture recognition, SLAM, 3D reconstruction are computationally intensive and complex algorithms which will have to run in real-time with a very modest power budget in next-generation smart phones, tablets, TVs... The hunt for the best computational engine for image understanding is now open. Some serious contenders are already emerging, high-frequency SMP-style embedded CPUs and GP-GPUs being the main ones. In this talk I would discuss the pros and cons of these architectures in running image understanding applications, and I will give my view and experience in designing an alternative scalable computational fabric to hit the sweet spot in terms of GOPS/mm2/W while preserving a standard-based software API for ecosystem build-up and application integration.
Biography: Lca Benini is Full Professor at the Department of Electrical Engineering and Computer Science (DEIS)of the University of Bologna, Italy. He also holds a visiting faculty position at the Ecole Polytechnique Federale de Lausanne (EPFL) and he is currently serving as Chief Architect for the Platform 2012 project in STmicroelectronics, Grenoble. He received a Ph.D. degree in electrical engineering from Stanford University in 1997. Dr. Benini's research interests are in
6 energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. He has published more than 500 papers in peer-reviewed international journals and conferences, four books and several book chapters. He has been general chair and program chair of the Design Automation and Test in Europe Conference. He has been a member of the technical program committee and organizing committee of several conferences, including the Design Automation Conference, International Symposium on Low Power Design, the Symposium on HardwareSoftware Codesign. He has been Associate Editor of several international journals, including the the IEEE Transactions on Computer Aided Design of Circuits and Systems and the ACM Transactions on Embedded Computing Systems. He is a Fellow of the IEEE, a member of the Academia Europaea, and a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.
7 Keynote VI
Architectures, Protocols, and Applications of Internet of Things (IoT): What are the Essential Factors to Create a True IoT System? Zixue Cheng Professor, The University of Aizu, Japan
Date : 9:20 A.M.- 10:20 A.M., Saturday, September 22, 2012 Place : Lecture Theater
Abstract At first, we will give a survey on Internet of Things (IoT), which is being rapidly developed and will change our daily life greatly in the near future. IoT began with the proposal of Auto-ID-Center by MIT in 1999, and then was developed by various institutions in variety of Countries, e.g. A Smarter Planet by IBM, Roadmap for the future –Internet of Things in 2020, the concept of Sensing China in China, and NIT (Network Information Technology) at USA in a report to the president and congress and etc. IoT has become a national research topic in many countries. For example, in China, there are 973 national projects for deep research on architecture and main technologies in IoT. In IoT, various kinds of intelligent communication model have been researched, e.g., Person to Person (P2P), Person to Machine (P2M), Machine to Machine (M2M). To quickly promote research and industrialization of IoT, some consolidations have designed and published various standards for IoT, especially for M2M, e.g., ETSI in Europe, TIA in USA, CCSA in China, and so on. Based on IoT technology, variety of future applications can be created to serve in various fields in daily life, e.g., smart homes and elderly care by detecting detail situation around the elderly people and sending services to remote family/care center quickly through networks. Based on the survey mentioned, we will discuss the essential factors of IoT, to make clear what is different between IoT and other paradigms, such as ubiquitous networks. In addition, we will propose a new architecture of IoT, a communication model called Situation-to-Situation (S2S), and show some applications based on the architecture and the model.
8 Biography: Dr. Zixue Cheng got his Master and Doctor Degrees in Engineering from the Tohoku University Japan in 1990 and 1993, respectively. He joined the University of Aizu in Apr. 1993 as an assistant professor, became associate professor in 1999, and has been a full professor since 2002. His interests are design and implementation of protocols, distributed algorithms, distance education, ubiquitous computing, ubiquitous learning, embedded systems, functional safety, and Internet of Things (IoT). He served as the director of University-business innovation center during Apr. 2006-Mar. 2010, and has been the head of the Division of Computer Engineering, University of Aizu, since Apr. 2010. He is a member of ACM, IEEE, IEICE and IPSJ.
9
Program at a Glance Sept. 20 Sept. 21 Sept. 22 8:30 Registration 8:30 - Registration 8:30-9:20 Registration 9:00-9:20 Opening 9:40
9:20- 9:40- Keynote 1 Keynote 3 9:20-10:20 Keynote 6 10:20 10:40
10:20- 10:40- Coffee Break Coffee Break 10:20-10:40 Coffee Break 10:45 11:00 General- Purpose GPU Numerical Network GPGPU and 10:45- 11:00- Computing for Computation on Chip & Architecture I Applications Programming 10:40-12:20 12:00 12:20 and Auto- Multicore Biomedical Environment Researches tuning Tech.
12:20- 12:20- Lunch Lunch 12:20-12:30 Closing 13:30 13:20
Keynote 4 13:30- 13:20- Keynote 2 ------14:30 15:20 Keynote 5
14:30- 15:20- Coffee Break Coffee Break 14:50 15:30 MCSoC-12 Social Event Networked (Lunch and Excursion) - Buffer Issues 12-40:16:30 Embedded Fee: Free for registered 14:50- & Multi- 15:30- Architecture Task Allocation Systems for participants. 16:30 Processor 17:10 II & Scheduling Internet of Systems Things
17:00- 18:30- Welcome Reception MCSoC-12 Banquet 19:00 20:30
10
Time-Table & Program
Thursday 20
Start End Duration Session(Room) Details 8:30 9:00 30min Registration 9:00 9:20 20min Opening Welcome & Opening Remarks (Lecture Theatre) Keynote Presentation 1 “Trend of Multi-/Many-core for Embedded Systems” 9:20 10:20 60 min Session 1 Fumio Arakawa (Renesas Electronics Corp., Japan) (Lecture Theatre) Session Chairs: Stanislav Sedukhin, Shigeru Kanemoto (The University of Aizu, Japan) 10:20 10:45 25min Break Application Session Co-Chairs: Gi-Ho Park (Sejong University, South Korea) and Yoshiki Yamaguchi (University of Tsukuba, Japan)
“An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System” Takuya Otsuka, Takashi Aoki, Eiichi Hosoya, Akira Onozawa (NTT Microsystem Integration Laboratories, Japan) 10:45 12:00 75min Session 2-1 (Room: S6) “Hardware Implementation of Accumulated Value Calculation for Two- Dimensional Continuous Dynamic Programming” Junko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, Kenichi Kuroda (The University of Aizu, Japan)
“Hardware Accelerator for BLAST” Shizuka Ishikawa, Asuka Tanaka , Toshiaki Miyazaki (The University of Aizu, Japan)
Architecture I Session Co-Chairs: Hiroki Matsutani (Keio University, Japan) and Junji Kitamichi (The University of Aizu, Japan)
“FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations” Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters , Gerd Ascheid (Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany) 10:45 12:00 75min Session 2-2 (Room: S7) “Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router” Takeo Nakamura, Hiroki Matsutani (Keio University, Japan), Michihiro Koibuchi (National Institute of Informatics, Japan), Kimiyoshi Usami (Shibaura Institute of Technology, Japan), and Hideharu Amano (Keio University, Japan)
“Segmented Bus based path setup scheme for Distributed Memory Architecture” Muhammad Adeel Tajammul, Muhammad Ali Shami ,Ahmed Hemani (Royal Institute of Technology, Stockholm, Sweden)
12:20 13:30 70min Lunch The University of Aizu Restaurant (Cafeteria Rat-a-tat) Keynote Presentation 2 “An NoC Architecture for Inductive Coupling Wireless Interconnect” 13:30 14:30 60min Session 3 Hideharu Amano (Keio University, Japan) (Lecture Theatre) Session Chair: Toshiyaki Miyazaki (The University of Aizu, Japan) 14:30 14:50 20min Break
11 Buffer Issues and Multi-processor Systems Session Co-Chairs: Sofiène Tahar (Concordia University, Canada) and Tsutomu Yoshinaga (The University of Electro-communications, Japan)
“DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP” Xiaoping Huang, Xiaoya Fan, Shengbing Zhang, (Northwestern Polytechnic University Xi’an, China), Yuhui Chen (XI'AN Guide Technology, LTD, China)
14:50 16:30 100min Session 4-1 “On-Chip Communication Buffer Architecture Optimization Considering Bus (Room:S6) Width” Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan)
“Throttling Control for Bufferless Routing in On-Chip Networks” Yicheng Guan , Ahmadou Dit Adi Cisse , Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie , Tsutomu Yoshinaga (The University of Electro-Communications , Japan)
“Transputer-like Multicore Digital Signal Processing on the Array of ARM Cortex-M0 Microprocessors” Kunio Takaya (University of Saskatchewan, Canada)
Networked Embedded Systems for Internet of Things Session Co-Chairs: Zixue Cheng (The University of Aizu, Japan), Song Guo (The University of Aizu, Japan) and Hong Yao (China University of Geosciences, China)
“Multi-decision Making Based PSO Optimization in Airborne Mobile Sensor Network Deployment” Xuanya Li, Linlin Ci (Beijing Institute of Technology, China), Minghua Yang (Beijing Institute of Information Technology, China) , Chengping Tian (Beijing Institute of Control and 14:50 16:30 100min Session 4-2 Electronic Technology, China), Bin Cheng (Beijing Institute of Technology, China) (Room: S7) “A novel data transfer scheme of Smart Grid and DTN” Hong Yao, Zheng Zhao, Huawei Huang, Lei Cong (China University of Geosciences, Wuhan, China)
“Design of a Communication System Integrating Wireless Sensor Network and Smart Phones for a Disaster” Junbo Wang, Zixue Cheng , Isao Nishiyama , Yinghui Zhou (University of Aizu, Japan)
“Accurate Coverage of Complex Targets in Three-Dimensional Mobile Sensor Networks” Xiang Li, Xuanya Li (North University of China, Shanxi, China)
17:00 19:00 120min Welcome Reception Venue: The University of Aizu Restaurant (KEYAKI)
12 Friday 21
Start End Duration Session(Room) Details 8:30 9:40 70min Registration Keynote Presentation 3 “System-on-Chip Design Verification: Challenges and State-of-the-art” 9:40 10:40 60min Session 5 Sofiène Tahar (Concordia University, Montreal, Canada) (Lecture Theatre) Session Chair: Hideharu Amano (Keio University, Japan) 10:40 11:00 20min Break General-Purpose GPU Computing for Biomedical Researches Session Co-Chairs: Xin Zhu (The University of Aizu, Japan)
“Early Stage Chick Embryonic Heart Outflow Tract flow Measurement Using High Speed 4D Optical Coherence Tomography” Zhenhe Ma, Tao Xu (Shenzhen Academy of Metrology and Quality Inspection, Shenzhen, 11:00 11:50 50min Session 6-1 China) , Linlin Du , Zhongdi Chu, Jiangtao Lv , Fengwen Wan (Northeastern University at (Room:S6) Qinhuangdao, Hebei, China)
“Load-prediction Parallelization for Computer Simulation of Electrocardiogram based on GPU” Wenfeng Shen, Liang Wang, Jie Li, Weimin Xu, Daming Wei (Shanghai University, China), Xin Zhu (Tohoku University, Sendai, Japan)
GPGPU and Programming Environment Session Co-Chairs: Takahiro Katagiri (The University of Tokyo, Japan)
Invited Speaker 1 "Software Evolution for System Architecture Revolution" 11:00 12:20 80min Session 6-2 Hiroyuki Takizawa (Tohoku University, Japan) (Room: S7) "Tuning Block Size for QR Factorization on CPU-GPU Hybrid Systems" Yaohung Tsai (National Taiwan University, Taiwan), Ray-Bing Chen (National Cheng-Kung University, Taiwan), and Weichung Wang (National Taiwan University, Taiwan)
"Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU" Kazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin (The University of Aizu, Japan)
12:20 13:20 60min Lunch The University of Aizu Restaurant (Cafeteria Rat-a-tat) Keynote Presentation 4 “Cool System: A Scalable and Energy-Efficient 3D Heterogeneous Multi-Chip 13:20 15:20 120min Session 7 System with Cool Interconnect, Cool Chip, and Cool Software” (Lecture Theatre) Yukoh Matsumoto (TOPS Systems Corp., Japan)
Keynote Presentation 5 "Scalable Many-core Acceleration for Image Understanding - is CPU+GPU the answer?" Luca Benini (University of Bologna, Italy)
Session Chair: Ryuichi Oka (The University of Aizu, Japan) 15:20 15:30 10min Break
13 Architecture II Session Co-Chairs: Shinichi Yamagiwa (University of Tsukuba, Japan), Satoshi Nishimura (The University of Aizu, Japan) and Hideyuki Kawashima (Tsukuba University, Japan)
“GRAPE-MPs: Implementation of an SIMD for quadruple/hexuple/octuple- precision arithmetic operation on a structured ASIC and an FPGA” Naohito Nakasato (The University of Aizu, Japan), Hiroshi Daisaka (Hitotsubashi University, Japan), Toshiyuki Fukushige (High Energy Accelerator Research Organization, Japan), Atsushi Kawai (Tokyo Institute of Technology, Japan), Jun'Ichiro Makino, Tadashi Ishikawa, Fukuko Yuasa (High Energy Accelerator Research Organization, Japan)
15:30 16:45 75min Session 8-1 “Design and Implementation of a Merging Network Architecture for (Room: S6) Handshake Join Operator on FPGA” Yasin Oge (University of Electro-Communications, Japan, Japan) , Takefumi Miyoshi, Hideyuki Kawashima (University of Tsukuba, Japan), Tsutomu Yoshinaga (University of Electro-Communications, Japan)
“Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor” Masayuki Kimura, Hideharu Amano (Keio University, Japan)
Task Allocation and Scheduling Session Co-Chairs: Ikki Fujiwara (National Institute of Informatics, Japan) and Hiroshi Saito (The University of Aizu, Japan)
“Task Scheduling for Voltage-Frequency Islands applied NoC-based MPSoC considering Network Congestion” Sho Ninomiya, Keishi Sakanushi , Yoshinori Takeuchi, Masaharu Imai (Osaka University, Japan)
“Optimal Assignment for Tree-structure Task Graph on Heterogeneous 15:30 17:10 100min Session 8-2 Multicore Systems Considering Time Constraint” (Room: S7) Li Wang, Jing Liu (Hunan University, Wuna, China) , Jingtong Hu (University of Texas at Dallas, USA), Qingfeng Zhuge (Chongqing University, China), Edwin H.-M. Sha (Hunan University, China)
“An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip” Hiroshi Saito (The University of Aizu, Japan), Tomohiro Yoneda (National Institute of Informatics, Japan) , Yuichi Nakamura (NEC , Japan)
“Scheduling for Multi-core Processor under Process and Temperature Variation” Zheng Zhou, Junjun Gu, Qu Gang (University of Maryland, College Park, USA)
18:30 20:30 120min MCSoC-12 Banquet (with Tsuruga-jo Taiko Traditional Dance + Yosakoi Dance Performance) Venue: Washington Hotel
14 Saturday 22
Start End Duration Session(Room) Details 8:30 9:20 10min Registration Keynote Presentation 6 “Architectures, Protocols, and Applications of Internet of Things (IoT): 9:20 10:20 60 min Session 9 What are the Essential Factors to Create a True IoT System?” (Lecture Theatre) Zixue Cheng (The University of Aizu, Japan)
Session Chair: Qiangfu Zhao (The University of Aizu, Japan) 10:20 10:40 20min Break Numerical Computation and Auto-tuning Session Co-Chairs: Hiroyuki Takizawa (Tohoku University, Japan) and Kenichi Kuroda (The University of Aizu, Japan)
Invited Speaker 2 "Automatic Tuning for Parallel FFTs on Clusters of Multi-Core Processors" Daisuke Takahashi (University of Tsukuba, Japan)
"An Auto-Tuning Technique of the Weighted Jacobi-Type Iteration used for Preconditioners of Krylov Subspace Methods" Akira Imakura, Tetsuya Sakurai(University of Tsukuba, Japan), Kohsuke Sumiyoshi (Numazu 10:40 12:20 100min Session 10-1 College of Technology, Japan), and Hideo Matsufuru (High Energy Accelerator Research (Room: S6) Organization, Japan)
"SSG-AT: An Auto-tuning Method of Sparse Matrix-vector Multiplication for Semi-Structured Grids -An Adaptation to OpenFOAM-" Satoshi Ito, Satoshi Ohshima, and Takahiro Katagiri (The University of Tokyo, Japan)
Invited Speaker 3 "Bridging the Productivity-Performance Gap with Selective Embedded Just-in- Time Specialization" Shoaib Kamil (University of California at Berkeley, USA)
Network-on-Chip and Multicore Technology Session Co-Chairs: Hitoshi Oi (The University of Aizu, Japan) and Michihiro Koibuchi (National Institute of Informatics, Japan )
“Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels” Nicola Caselli, Alessandro Strano , Daniele Ludovici, Davide Bertozzi (University of Ferrara, Italy) 10:40 11:55 75min Session 10-2 (Room: S7) “LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture” Akram Ben Ahmed, Abdderazek Ben Abdallah (The University of Aizu, Japan)
“Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems” Yu-Hsin Kuo, Po-An Tsai,Hao-Ping Ho,En-Jui Chang,Hsien-Kai Hsin,An-Yeu Wu (National Taiwan University, Taipei, Taiwan)
12:20 12:30 10min Closing (Lecture Theatre) Social Event (Lunch & Excursion) 12:40 16:30 230min Session 11 Fee: Free for all registered participants.
Co-Chairs: Y. Kohira and A. Vazhenin
15 Campus Map Lecture Hall 2F
WiFi is available though the campus
Opening Ceremony &
Keynote Speech Research Quadrangles 2F (Lecture Theater)
Student Hall 1F
LAN room Staff room I (North Lounge) (S4)
Lunch Coffee server Sep. 20-21 12:20-13:30
University Shop Sep. 20- 21 Open : 8:00-20:00 Sep. 22 Closed Break room (S5) Student Hall 2F Session 1 (S6) Session 2 (S7)
II Welcome Reception Staff room (S8) Sep. 20 17:00-19:00 Registration desk & (Keyaki) Cloakroom (South Lounge)
16 Shuttle Bus & Registration Schedule
Shuttle Bus Stop ① ② ③④
17
Banquet
・ Date : From 6:30 P.M., Friday, September 21, 2012 ・ Place : Aizu-Wakamatsu Washington Hotel (2F) 0242 – 22 – 6111 ・ Shuttle Bus : Avaiable from the University to Aizu - Wakamatsu Washington Hotel.
University → Washington Hotel 17:30 → 17:40 17:45 → 17:55
Shuttle Bus Stop
University of Aizu
18 Excursion September 22 (Sat.) Time Event Place Gather around the Shuttle 12:40 Tour start Bus stop (Check: Shuttle Bus Schedule) Lunch & shopping Tsuruga-jo Kaikan 13:00-14:10 (Restaurant) 14:10-15:00 Tsuruga-jo Castle
15:15-16:15 Going to look at places Aizu Buke Yashiki of interest & shopping (Samurai House)
16:30 Hotel arrival Washington Hotel 16:40 University arrival The University of Aizu
Tsuruga-jo Castle History
The prototype of the castle was built here by the head of a powerful family clan called the Ashinas about 600 years ago. In 1591 Ujisato Gamō became lord of the area, and built a seven storey tower. He was also the one who named it “Tsuruga-jō”. But, as the result of a big earthquake in 1611, the castle tower was damaged, and began to lean. In 1627, Yoshiaki Katō became the new lord of the region, and repaired the tower. He also made it five stories.(Aizu was a location central in importance to the control of Eastern Japan, and many famous generals from all over the country came and ruled the area.) During the Edo Period (1600— 1867), Japan was controlled by the Tokugawa Shogunate. When the younger brother of the third Tokugawa Shogun became head of the Aizu clan, close relations developed between the clan and shogunate. As a result, though many clans severed their ties to the Tokugawas during the Meiji Restoration, the Aizu clan came to their aid and fought to the last as samurai against the Meiji governmental forces (1868) at the latter half of the Edo Period. This battle between the Meiji governmental forces and samurai is called the Boshin War. Using the latest weapons, the Meiji governmental forces sieged the castle and inflicted suffering on the 3000 people taking refuge inside. The Aizu clan resisted the ruthless attack for a month, but was finally defeated, and proclaimed an end to the samurai age. After this, on orders from the Meiji government, the castle was destroyed and all that was left was its stone walls. The castle was first inspected for reconstruction in 1965 as a result of local enthusiasm to rebuild it. A picture of the castle in the latter half of the 19th century—said to have been taken by a Frenchman—was used in consultation for the restoration.
Aizu Buke Yashiki (Samurai House) This is a tourist spot where the Buke Yashiki (Samurai house), which had burned down during the Boshin War, was restored. On this site, which encompasses around 23,100㎡ of land, a hidden atmosphere of the past can be found in the many historical buildings lined in a row.
19 Local Bus Schedule ☆：No bus services available on Saturdays, Sundays, and national holidays
¥170 ¥170 Bus Aizu- Aizu- Univ. of Univ. of terminal wakamatsu wakamatsu Aizu Aizu 4 st. st. ☆ 6:10 6:15 8:11 8:25 6:40 6:45 8:56 9:10 ☆ 7:10 7:15 ☆ 9:26 9:40 7:40 7:45 9:56 10:10 ☆ 8:10 8:15 ☆ 10:26 10:40 9:00 9:05 11:11 11:25 ☆ 9:40 9:45 ☆ 11:56 12:10 10:30 10:35 12:41 12:55 ☆ 11:10 11:15 ☆ 13:26 13:40 12:00 12:05 14:11 14:25 ☆ 12:40 12:45 ☆ 14:56 15:10 13:30 13:35 15:41 15:55 ☆ 14:10 14:15 ☆ 16:26 16:40 15:00 15:05 16:51 17:05 ☆ 15:40 15:45 ☆ 17:31 17:45 16:10 16:15 18:21 18:35 ☆ 17:10 17:15 ☆ 19:01 19:15 17:40 17:45 19:41 19:55 ☆ 18:15 18:20 ☆ 20:11 20:25
The front enterance Please note there are two different bus stops: one from the University to the station (outside campus), the other from the station to the University (on campus)
Local Bus stop Univ. of Aizu → s Aizu-wakamatsu st. t r Local Bus stop e Aizu-wakamatsu st. e → Univ. of Aizu t
20 Aizu-wakamatsu city map Bakery & Cafe
＜FURUKAWA BAKERY> Around the hotel Aizu-wakamatsu Open 8:30.- 18:30 station
Italian restaurant
Aizu-wakamatsu Angelo Bianco> Washington Hotel １ Open 11:00.- 21:30
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Ramen Fujinoyu 3 Hot Spring ＜Korakuen> Open 11:00.- 2:00 a.m.
Japanese style bar
Japanese style bar
Japanese style bar
Open 10:00.- 24:00 Adults ¥390 (without towel) 0242-32-1126 21