THEFUTURE OF MICROPROCESSORS Albert Yu Tn my role as head of Intel’s micro- The bad news is that producing advanced pro&or products, I am often asked to microprocessors involves much higher cap- Intel Corporation 1paint a picture of the microprocessor of ital cost than anyone ever expected. At Intel, the future. Even if our newest processor has we’ve augmented Moore’s law (the number just hit the streets and has not even come of transistors on a processor doubles approx- close to full use, people naturally crave imately every 18 months) with Moore’s law information about where they’re going 2. Law 2 says that as the sophistication of rather than where they’ve been. chips increases, the cost of fabrication rises My colleagues and I have been trying for exponentially (see Figures 1 and 2). In 1986, about 10 years now to identify trends about we manufactured our 386 containing 250,000 the microprocessor of the future. While transistors in fabs costing $200 million. these are based on a wide variety of Today, the Pentium Pro processor contains unknown factors inherent in developing 6 million transistors but requires a $2 billion new technology, for the most part, we have facility to produce. been close to the mark. However, before Looking ahead, the important technolog- making statements about microprocessor ical fact that emerges is that Moore’s law trends 10 years out-Micro 2006-it might continues to reign, with the number of tran- be useful to revisit our past statements’J sistors per chip increasing exponentially. about the microprocessor of today and tge Today’s performance trend can continue, microprocessor of 2000. Then we can see thanks to microarchitecture and design inno- where we have been right and where vations beyond raw transistor count. The wrong. This retrospective will reveal impor- personal computer market, by far the biggest tant trends that promise to give some insight market for microprocessors, continues to into the microprocessor of the next decade. grow at a healthy rate. It can provide the vol- ume markets needed to absorb the huge Performance, capital costs manufacturing capital costs. To be sure, we Over the last 10 years, evolving micro- have a number of key technology barriers processor performance increased at a high- to overcome as device geometry migrates er than envisioned rate; unfortunately, so did well below the submicron range. However, manufacturing capital costs. Table 1 lists our all indications are that the microprocessor 1989 predictions for today’s microprocessor of 2006-and beyond-will be well worth performance at speeds of 100 MIPS (millions the wait. of instructions per second), which is equiv- alent to an ISPEC95 rating of 2.5 and clock Micro 2000 revisited rates of 150 MHz. Surprisingly, today’s per- As Table 1 shows, we anticipated in 1989 formance dramatically exceeds this. The Intel that in 2000 a processor would carry 50 mil- Pentium Pro processor runs at 400 MIPS, with lion transistors in a 1.Zin. (square) die. The Intel’s head of an ISPEC95 rating of about 10 and a ZOO-MHz industry is mostly on track to deliver a 40- clock rate. This great performance boost has million-transistor chip on a l.l-in. die in microprocessor stimulated a huge range of applications for 2000. This 20 percent offset is not a tech- business, home, and entertainment, from nology limitation but an economic one, products looks 10 mobile computers to servers. As a result, the necessitated by creating a reasonable die PC market segment is a lot larger today than cost (see Figure 1). years ahead to 2006. we anticipated years ago. Silicon technology. Our visions about 46 IEEE Micro 0272.1732/96/$5.000 1996lEEE silicon process line width Table 1. Visualizing trends for the microprocessor of the future. were right on the money, ‘as Intel is currently in produc- 1989 1989 1996 1996 tion with 0.35micron tech- predictions 1996 predictions predictions predictions nology for the Pentium and Characteristic for 1996 actuals for 2000 for 2000 for 2006 Pentium Pro. I believe that line width will continue to Transistors (millions) 8 6 50 40 350 drop to 0.2 micron in 2000 Die size* (inches) 0.800 0.700 1.2 1.1 1.4 and to 0.1 micron in 2006 Line width (microns) 0.35 0.35 0.2 0.2 0.1 (see Figure 3). Also, the Performance: dielectric thickness and the MIPS 100 400 700 2,400 20,000 voltage supply will have ISPEC95 2.5 10 17.5 60 500 decreased correspondingly. Clock speed (MHz) 150 200 250 900 4,000 This incredible shrinkage will continue unabated for the *Length of single side of square die. forseeable future. The num- ber of metal interconnects has increased from two to five over the last 10 years and will increase ^ . turther as we need more intercon- nects to hook up all the devices.3 In fact, this is one of the biggest per- formance-limiting factors we con- tend with (see later discussion). In addition, the problem of inter- connects from the chip to the pack- age and eventually to the system board is another major limiting factor 1971 1976 1981 1986 1991 1996 2001 2006 for performance. Actually, we want Year to build single chips to avoid per- formance loss when sending signals Figure 1. Chart showing Moore’s law. off chip. We added cache and float- ing-point units on the 486 processor mostly for that reason, For the Pentium Pro processor, we of microprocessors exceeds our 1989 vision by quite a lot. placed the second-level cache and the processor in the same There are several reasons for this. Although the silicon package to achieve the bandwidth needed between the two. process advances were pretty much on target, we have The future trend will be to incorporate more performance achieved higher frequency out of these advances with novel and bandwidth-sensitive elements on chip and to continu- microarchitecture and circuit techniques. In addition, the ously improve the package interconnect performance. number of instructions per clock has increased faster, and Several companies are investigating MCM (multichip module) we have exploited superscalar architectures and greater technology to eliminate chip packaging altogether, and I degrees of parallelism. There have also been significant inno- believe this will be an important trend for future high-per- vations in compiler technology that boost performance even formance processors. higher. I see these trends continuing.*a5 Performance. It is amazing that the actual performance 0.011 : / 1966 1974 1982 1990 i 998 2006 1971 1976 1981 1986 1991 1996 2001 2006 Year Year Figure 2. Chart showing Moore’s law 2. Figure 3. Chart showing line width versus time. December 1996 47 We will see clock speeds of about 700 MHz with a 60 nology provided software compatibility, compact code size, ISPEC95 rating in 2000. Such tremendous clock rates place and future RISC-matching performance. great demands on the resistance and capacitance of the chip’s Today, the architecture debate has pretty much become a metal interconnects for power and clock distribution. These nonissue. Both the debate and the competition have been multimillion-transistor devices also face new hurdles in pack- good for the industry, as both sides learned a great deal from aging and power management. the other, which stimulated faster innovation. There is really ,&rchitecture. In the late 1980s there was much debate no perceptible difference between the two in either perfor- about which microprocessor architecture held the key to mance or cost. Pure RISC chips like the IBM ROMP, Intel fastest performance. RISC (reduced instruction set comput- 80860, and early Sun Spare, as well as pure CISC chips like ing) advocates boasted faster speeds, cheaper manufactur- the DEC VAX, Intel 80286, and Motorola 6800, are gone. Smart ing costs, and easiest implementation. CISC (complex chip architects and designers have incorporated the best ideas instruction set computing) defenders argued that their tech- from both camps into today’s designs, obliterating the differ- 48 IEEE Micro ences between architecture-specific implementations. What in the entry of various circuit-logic data, verify the global counts most in designing the highest performance, lowest chip timing, and extract the actual layout statistics and veri- cost chip today is the quality of implementation. fy them,against the original simulation assumptions. One of Seven years ago in IEEE Spectrum, r our vision was that the the rapidly developing areas is synthesis, first in logic syn- microprocessor of 2000 would have multiple general-purpose thesis but progressing to data path synthesis. These capa- CPUs working in parallel. What has instead happened is not bilities have improved design productivity enormously. separate CPUs on the same chip but a greater degree of par- Future advances will improve the layout density (to reduce allelism within a single chip. The Pentium processor employs product cost) and raise performance (to enable new applica- a superscalar architecture with two integer pipes, and the tions). This is particularly challenging as interconnects are Pentium Pro processor design expanded that to three. Other becoming greater performance limiters than are transistors. In processors such as the HP PA and IBM PowerPC have used addition to electrical simulation, thermal and package simula- similar superscalar architectures. I see the trend to exploit tion will be the norm by 2000. Beyond the chips, the trend is more parallelism continuing well into the future. to expand simulation to encompass the whole system, includ- Human interface. The number of transistors devoted to ing processor, chip sets, graphics controller, VO, and memory. the human interface is increasing too.