Reverse Engineering the Cognitive Brain in Silicon

Home , Neuromorphic engineering, Reverse engineering

Gert Cauwenberghs

Department of Bioengineering Institute for Neural Computation UC San Diego

http://inc.ucsd.edu

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] BRAIN Initiative Brain Research through Advancing Innovative Neurotechnologies

–! Interdisciplinary collaborative initiative engaging broad participation in the sciences, engineering, arts, and humanities alongside neuroscientists in advancing our understanding of the circuits and function of the healthy and diseased brain –! Initial investments with contributions from industry (NIH, NSF, Salk Institute, Allen Brain Institute, etc.)

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] https://www.whitehouse.gov/ blog/2015/10/15/ nanotechnology-inspired- grand-challenge-future- computing

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Lee Sedol vs. AlphaGo Go World Champion vs. Google DeepMind ~ 25 W ~ 1 MW

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Neuromorphic Engineering “in silico” neural systems design

g g1 0

g g2 g2 1 Neuromorphic g 2 g0 Engineering g0 g1

Neural Learning & VLSI Systems Adaptation Microchips

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Analysis by Synthesis

Richard Feynman Carver Mead

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Computational Systems Neuroscience

Brain 1 m Systems

Maps 1 cm Networks

Analysis Neurons 100 µm Multi-scale levels of VPre investigation in analysis E V of the central nervous Reversal Post system (adapted from Synapses Churchland and 1 µm Sejnowski 1992) and Pre CMembrane Synthesis Post corresponding neuromorphic synthesis Gate Source of highly efficient silicon Drain cognitive microsystems. Membrane Channels Boltzmann statistics of 10 nm MOSFET ionic and electronic channel channel transport Ion channel provide isomorphic physical foundations. Carriers

1 Å Energy G. Cauwenberghs, Gate “Reverse Engineering voltage the Cognitive Brain,” PNAS, 2013 Neuromorphic Systems Engineering

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Physics of Neural Computation Silicon and Lipid Membranes Mead, 1989

Gate SiO2 Source Drain poly Si + + p p-Channel p n- well p- Si substrate Gate voltage Energy

Squid giant axon (Hodgkin and Huxley, 1952) Voltage-dependent p-channel Voltage-dependent conductance + + –! Hole transport between source and drain –! K /Na transport across lipid bilayer –! Gate controls energy barrier for holes –! Membrane voltage controls energy barrier across the channel for opening of ion-selective channels –! Boltzmann distribution of hole energy –! Boltzmann distribution of channel energy produces exponential decrease in channel produces exponential increase in K+/Na+ conductance with gate voltage conductance with membrane voltage

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Event-Coding Silicon Retina Zaghloul and Boahen, 2006

–! Models coding and communication of visual events in the mammalian retina and optic nerve ! •! Integrated photosensors (rods) •! On and off transient and sustained ganglia cell outputs –! Spatiotemporal compressed coding and communication in optic nerve! –! Address-event coding of spikes!

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Change Threshold Detection APS CMOS Imager Chi, Mallik, Clapp, Choi, Cauwenberghs and Etienne-Cummings (2007)

–! Event-driven video compression! • Change detection and threshold encoding DDS / Event Coding ! on the focal plane –! 6T pixel combines APS and change event 90 x 90 coding ! TD-APS Array –! 4.3mW power at 3V and 30fps! FIFO

Fast Rotation Slow Rotation pos. neg.

Video Out Change Events Out

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Reconfigurable Synaptic Connectivity and Plasticity From Microchips to Large-Scale Neural Systems

Address-Event Representation

Neural Synaptic Multi-Chip Systems Plasticity & Systems Wiring

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Address-Event Representation (AER) Lazzaro et al., 1993; Mahowald, 1994; Deiss 1994; Boahen 2000

–! AER emulates extensive connectivity between neurons by communicating spiking events time-multiplexed on a shared data bus. ! –! Spikes are represented by two values:! •! Cell location (address) •! Event time (implicit) –! All events within "t are “simultaneous”!

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Address-Event Synaptic Connectivity Goldberg, Cauwenberghs and Andreou, 2000

2 Receiver

1 Sender transceiver (IFAT) (DRAM) –! ‘Virtual’ synapses! •! Dynamically reconfigurable •! Wide-ranging connectivity •! Rewiring and synaptic plasticity –! Quantal release: R = n p q •! n: multiplicity (repeat event) •! p: probability of release (toss a coin) •! q: quantity released (set amplitude) IFAT2 (2000)

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Hierarchical Vision and Saliency-Based Acuity Modulation Vogelstein, Mallik, Culurciello, Cauwenberghs, and Etienne-Cummings, NECO 2007

IFAT Cortical Model Octopus Silicon Retina 4800 silicon neurons 80 x 60 pixels 4,194,304 synapses AER spiking output

OR image Simple cell response Saliency map

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Spike Timing-Dependent Plasticity

Bi and Poo, 1998

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Spike Timing-Dependent Plasticity in the Address Domain

Causal Anti-Causal

Vogelstein et al, NIPS*2002

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Scaling of Task and Machine Complexity Deep digital search Rule-based cognition [log]

Collective analog Machine Deep learning computation Complexity Learned/habitual cognition Throughput; Memory; Human brain Power; 1015 synOP/s; 15W Size Neuromorphic engineering

[log] Task Complexity Search tree breadth ^ depth Achieving (or surpassing) human-level machine intelligence will require a convergence between:! •! Advances in computing resources approaching connectivity and energy efficiency levels of computing and communication in the brain; •! Advances in deep learning methods, and supporting data, to adaptively reduce algorithmic complexity. G. Cauwenberghs, “Reverse Engineering the Cognitive Brain,” PNAS, 2013

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Scaling and Complexity Challenges

•! Scaling the event-based neural systems to performance and efficiency approaching that of the human brain will require: –! Scalable advances in silicon integration and architecture! •! Scalable, locally dense and globally sparse interconnectivity – Hierarchical address-event routing! EE ! 12 15 NanoE •! High density (10 neurons, 10 synapses within 5L volume) Phys –! Silicon nanotechnology and 3-D integration! •! High energy efficiency (1015 synOPS/s at 15W power) –! Adiabatic switching in event routing and synaptic drivers! –! Scalable models of neural computation and synaptic plasticity! Neuro •! Convergence between cognitive and neuroscience modeling CS •! Modular, neuromorphic design methodology CogSci •! Data-rich, environment driven evolution of machine complexity

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Long-Range Configurable Synaptic Connectivity

Comparison of synaptic connection topologies for several recent large-scale event-driven neuromorphic systems and the proposed hierarchical address-event routing (HiAER), represented diagrammatically in two characteristic dimensions of connectivity: expandability (or extent of global reach), and flexibility (or degrees of freedom in configurability). Expandability, measured as distance traveled across the network for a given number of hops N, varies from linear and polynomial in N for linear and mesh grid topologies to exponential in N for hierarchical tree-based topologies. Flexibility, measured as the number of target destinations reachable from any source in the network, ranges from unity for point-to- point (P2P) connectivity and constant for convolutional kernel (Conv.) connectivity to the entire network for arbitrary (Arb.) connectivity. MMAER: Multicasting Mesh AER; WS: Wafer-Scale.

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Hierarchical Address-Event Routing (HiAER)

w2,10 w6,13 w6,16 w6,3 w2,12 w6,1 w9,16 w2,8 Example network with 16 neurons w9,14 w w2,5 1,4 w w1,2 w2,3 w6,5 w6,7 w9,10 11,10 w11,12 w13,14 w15,14 and weighted synaptic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 connections. () () L31 1 2 L21 2 3 L22 Example partitioning into 1 2 1 hierarchical neural network with 5 L11 5 L12 5 L11 5 6 L12 ascending and descending projections through inserted relay 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 neurons. ()

PRE POST PAR 1 L3 1 22 d1,2:2 2 23 d2,2:3 22, 23 PRE POST PAR 1,2 PRE POST PAR 1 25 d1,2:5 1 1 26 d1,2:6 2 1 1 d1,1 L2 L2 2 15 d2,1:5 Corresponding edge-vertex-dual 2 2 d2,2 3 25 d3,2:5 2 15 d2,1:5 HiAER implementation with 15 25 15 25, 26 1 2 1 synaptic routing tables (SRT) at 1 2 1 2 L1 L1 L1 L1 each level in the hierarchy.

IFAT IFAT IFAT IFAT

PRE POST PAR PRE POST PAR PRE POST PAR PRE POST PAR

1 2 w1,2 2 1 w2,1 1 2 w1,2 1 2 w1,2 1 4 w1,4 2 3 w2,3 1 1 d1,1 3 2 w3,2 2 1 d2,1 2 2 d2,2 3 2 w3,2 5 1 w5,1 2 3 w2,3 5 1 w5,1 3 4 w3,4 5 4 w5,4 5 1 w5,1 5 4 w5,4 5 2 w5,2 6 2 w6,2 5 3 w5,3 5 4 w5,4 6 4 w6,4 Joshi et al, 2010; Park et al, 2011, 2015

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] (a) (b)

2 Receiver

1 Sender transceiver (IFAT) (DRAM)

(c) SRT SRT (d) (e) Level 1 Level 1 IFAT 0.13µm CMOS (c) distal IFAT IFAT col 0 col 1 synapse 0,1 neuron GL EL Gcomp SRTHiAER SRT HiAER compartment Level 1 SRT Level 1 SRT IFAT SRT SRT IFAT Erev0,1 Vm1 HiAER HiAER row 0 V SRT SRT u0,1 Level 1 SRT Level 1 SRT V C IFAT SRT SRT IFAT τ0,1 HiAER HiAER Level 1 Level 1 IFAT Csyn IFAT SRT HiAER SRT HiAER IFAT Level 1 SRT Level 1 SRT IFAT HiAER HiAER Level 1 SRT Level 1 SRT IFAT IFAT SRT SRT HiAER SRT HiAERSRT proximal 5 mm synapse 2,3 Level 1 neuron Level 1 SRT SRT IFAT compartment IFAT SRT HiAER SRT HiAER Level 2 HiAER Erev2,3 Vm0 Isyn Level 1 SRT Level 1SRT SRT IFAT SRT row 1 IFAT HiAER HiAERLevel 2 Vu2,3 HiAER Vτ2,3 C SRT SRTSRT SRT Level 2 ! Csyn HiAER Level3 SRT SRT HiAER Level 2 +! 5 mm HiAER SRT SRT SRT !

Hierarchical Address-Event Routing (HiAER) Integrate-and-Fire Array Transceiver (IFAT) for scalable and reconfigurable neuromorphic neocortical processing [Park et al, 2012; Yu et al, 2012]. (a) Dynamic reconfigurable synaptic connectivity across IFAT arrays of addressable neurons is implemented by routing neural spike events through DRAM synaptic routing tables (SRT). (b) The IFAT neural array multiplexes and integrates (top traces) incoming spike synaptic events to produce outgoing spike neural events (bottom traces). (c) Full-size HiAER-IFAT network with 4 boards, each with 4 IFAT modules, serving 1M neurons and 1G synapses, and spanning 4 levels in connection hierarchy. (d) Each IFAT chip module comprises a 65k-neuron Tezzaron 130nm CMOS IFAT microchip, Xilinx Spartan-6 FPGA (Level 1 HiAER), and two 2Gb DDR3 SDRAM SRTs serving 65M synapses. (e) Each neural cell models conductance based membrane dynamics in proximal and distal compartments for synaptic input with programmable axonal delay, conductance, and reversal potential. IFAT chip measured energy consumption is 48 pJ per spike event, several orders of magnitude more efficient than emulation on CPU/GPU platforms.

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] IFAT Thermodynamics of Neural Excitability Yu, Park, Joshi, Maier, Cauwenberghs, BioCAS 2012

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Large-Scale Reconfigurable Neuromorphic Computing

–! Integrate-and-fire array

2 transceiver (IFAT) as digitally Receiver programmable analog neural

1 supercomputer Sender transceiver (IFAT) –! Biophysical detail in neural (DRAM) and synaptic continuous- time dynamics –! Record high density: 65k two-compartment neurons with 65M reconfigurable conductance-based synapses –! Record low energy: 22 pJ per synaptic event –! Real-time at 73M spikes per 2 Power second Linear Fit of Power

1 J. Park et al, “A 65k-Neuron 73- Mevents/s 22-pJ/event Asynchronous

Power (mW) Micro-Pipelined Integrate-and-Fire Array Transceiver”, Proc. IEEE BioCAS 2014. 20 40 60 80 Event rate (Mevents/s)

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Large-Scale Reconfigurable Neuromorphic Computing Technology and Performance Metrics

Stromatias 2013 Merolla 2014 Schemmel 2010 Benjamin 2014 Park 2014 SpiNNaker SyNAPSE TrueNorth FACETS/BrainScaleS NeuroGrid IFAT Manchester IBM Heidelberg Stanford UCSD Technology (nm) 130 28 180 180 90 Die Size (mm2) 102 430 50 168 16 Analog Analog Analog Digital Digital Neuron Type Conductance Shared-Dendrite 2-Compartment Arbitrary Accumulate & Fire Integrate & Fire Conductance I&F Conductance I&F # Neurons 5216 1 1M 2 512 65k 65k Neuron Area (µm2) N/A 1 3325 (14) 2 1500 1800 140 Peak Throughput 5M 1G 65M 91M 73M (Events/s) Energy Efficiency 8n 26p N/A 31p 22p (J/SynEvent) 1 Software-instantiated neuron model 2 Time-multiplexed neuron (256x)

Benjamin, B., P. Gao, E. McQuinn, S. Choudhary, A. Chandrasekaran, J. Bussat, R. Alvarez-Icaza, J. Arthur, P. Merolla, and K. Boahen, “Neurogrid: A mixed analog-digital multichip system for large-scale neural simulations,” Proc. IEEE, 102(5):699–716, 2014. Merolla, P.A., J.V. Arthur, R. Alvarez-Icaza, A S. Cassidy, J. Sawada, F. Akopyan, B.L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S.K. Esser, R. Appuswamy, B. Taba, A. Amir, M.D. Flickner, W.P. Risk, R. Manohar, and D. S. Modha, “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, 345(6197):668–673, 2014. Park, J., S. Ha, T. Yu, E. Neftci, and G. Cauwenberghs, “65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver,” Proc. 2014 IEEE Biomedical Circuits and Systems Conf. (BioCAS), 2014. Schemmel, J., D. Bruderle, A. Grubl, M. Hock, K. Meier, and S. Millner, “A waferscale neuromorphic hardware system for large-scale neural modeling,” Proc. 2010 IEEE Int. Symp. Circuits and Systems (ISCAS), 1947–1950, 2010. Stromatias, E., F. Galluppi, C. Patterson, and S. Furber, “Power analysis of largescale, real-time neural networks on SpiNNaker,” Proc. 2013 Int. Joint Conf. Neural Networks (IJCNN), 2013.

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Phase Change Memory (PCM) Nanotechnology

(a) (b) (c)

(d) (e) (f)

Intel/STmicroelectronics (Numonyx) 256Mb multi-level phase-change memory (PCM) [Bedeschi et al, 2008]. Die size is 36mm2 in 90nm CMOS/Ge2Sb2Te5, and cell size is 0.097µm2. (a) Basic storage element schematic, (b) active region of cell showing crystalline and amorphous GST, (c) SEM photograph of array along the wordline direction after GST etch, (d) I-V characteristic of storage element, in set and reset states, (e) programming characteristic, (f) I-V characteristic of pnp bipolar selector.

–! Scalable to high density and energy efﬁciency! •! < 100nm cell size in 32nm CMOS •! < pJ energy per synapse operation

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Kuzum, Jeyasingh, Lee, and Wong (ACS Nano, 2011) (a)

(b) Vi AER I&Fi OUT

I&Fi

Input Lines M5 PCM Crossbar GST/TiN “Via” Output Lines M4 Standard Via M3 AER I&F Element IN (3M CMOS)

wij Vj Hybridization and nanoscale integration of CMOS neural arrays with phase change memory (PCM) synapse crossbar arrays. (a) Nanoelectronic PCM synapse with spike-timing dependent plasticity (STDP) [Kuzum et al, 2011]. Each PCM element implements a synapse with conductance modulated through phase transition as controlled by timing of voltage pulses. (b) CMOS IFAT array vertically interfacing with nanoscale PCM synapse crossbar array by interleaving via contacts to crossbar rows. The integration of IFAT neural and PCM synapse arrays externally interfacing with HiAER neural event communication combines the advantages of highly flexible and reconfigurable HiAER-IFAT neural computation and long-range connectivity with highly efficient (fJ/synOP range energy cost) local synaptic transmission.

Gert Cauwenberghs Reverse Engineering the Cognitive Brain in Silicon [email protected] Deep Learning in Spike-Based Neuromorphic Systems

Neural Sampling: Integrate & Fire (I&F) neurons can perform MCMC • sampling of a Boltzmann distribution Restricted Boltzmann Machines can be trained using STDP •

!3! %+% 0 '()&&$*+,-./

"##$%& 92% accuracy on MNIST hand-written digit recognition task •