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A Hybrid CMOS-Memristor Neuromorphic Synapse Mostafa Rahimi Azghadi, Member, IEEE, Bernabe Linares-Barranco, Fellow, IEEE, Derek Abbott, Fellow, IEEE, Philip H.W

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A Hybrid CMOS-Memristor Neuromorphic Synapse Mostafa Rahimi Azghadi, Member, IEEE, Bernabe Linares-Barranco, Fellow, IEEE, Derek Abbott, Fellow, IEEE, Philip H.W IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 1 A Hybrid CMOS-memristor Neuromorphic Synapse Mostafa Rahimi Azghadi, Member, IEEE, Bernabe Linares-Barranco, Fellow, IEEE, Derek Abbott, Fellow, IEEE, Philip H.W. Leong, Senior Member, IEEE Abstract—Although data processing technology continues to of synapses and their role in large-scale learning, there is advance at an astonishing rate, computers with brain-like pro- still a need to implement a versatile memristive synapse cessing capabilities still elude us. It is envisioned that such that is capable of faithfully reproducing a larger regime computers may be achieved by the fusion of neuroscience and nano-electronics to realize a brain-inspired platform. This paper of experimental data that takes into account conventional proposes a high-performance nano-scale Complementary Metal STDP [12], frequency-dependent STDP [13], triplet [14], [15] Oxide Semiconductor (CMOS)-memristive circuit, which mimics and quadruplet [15], [16] plasticity experiments. In a recent a number of essential learning properties of biological synapses. study, Wei et al. replicated the outcome of a variety of synaptic The proposed synaptic circuit that is composed of memristors and plasticity experiments including STDP, frequency-dependent CMOS transistors, alters its memristance in response to timing differences among its pre- and post-synaptic action potentials, STDP, triplet, and quadruplet spike interactions, using a TiO2 giving rise to a family of Spike Timing Dependent Plasticity memristor [17]. (STDP). The presented design advances preceding memristive This paper proposes a new hybrid CMOS-memristive circuit synapse designs with regards to the ability to replicate essential that aims to emulate all the aforementioned experimental data, behaviours characterised in a number of electrophysiological with minimal errors close to those reported in a phenomeno- experiments performed in the animal brain, which involve higher order spike interactions. Furthermore, the proposed hybrid logical model of Triplet STDP (TSTDP) rule presented in [15]. device CMOS area is estimated as 600 µm2 in a 0:35 µm Similar to many previous studies that devised memristive process—this represents a factor of ten reduction in area with synaptic devices/circuits with STDP, SRDP, or other synaptic respect to prior CMOS art. The new design is integrated properties, our aim is a circuit that implements the TSTDP with silicon neurons in a crossbar array structure amenable to learning algorithm of [15]. To the best of our knowledge, large-scale neuromorphic architectures and may pave the way for future neuromorphic systems with spike timing-dependent this has not been previously achieved using memristors. The learning features. These systems are emerging for deployment in proposed TSTDP memristive circuit advances the synaptic ca- various applications ranging from basic neuroscience research, pabilities of previous designs to be more biologically realistic, to pattern recognition, to Brain-Machine-Interfaces. and promotes our understanding of synaptic alteration mech- Index Terms—Neuromorphic, Synaptic Plasticity, Learning, anisms, believed to play a key role in learning and memory. Memristor, Crossbar, STDP, Triplet, Quadruplet. Furthermore, the proposed design significantly decreases the silicon real estate required for implementing and utilizing a variety of learning rules. I. INTRODUCTION Spiking neural networks with memristive synapses incorpo- EMRISTORS, due to their special features including rating the proposed compact and biologically plausible triplet M non-volatility, nanoscale dimensions, low power con- learning circuits, will be an important contribution to the sumption, and the ability to be programmed while operat- neuroscience research, where a more faithful synaptic plas- ing [1], have attracted attention for implementing an in-situ ticity rule, compared to traditional STDP, can be implemented architecture [2], [3], [4]. These emerging nanoscale devices and simulated in a large-scale network. An interesting feature can implement and mimic the synaptic plasticity character- of memristive synapses that distinguishes them from their istics of well-known learning algorithms such as pair-based traditional pure Complementary Metal Oxide Semiconductor STDP and Spike Rate-Dependent Plasticity (SRDP) [5], [6], (CMOS) counterparts is the feasibility of arranging them in a [7], [8]. Attempts have also been made to mimic experimental dense crossbar structure [1] integrated with CMOS circuitry. outcomes of higher order spike-based synaptic plasticity rules We also show how the proposed CMOS-memristive circuit can such as the suppressive STDP rule of Froemke and Dan [9] or be used in this fashion, to facilitate large-scale integration. Local Correlation Plasticity (LCP) rules to reproduce higher In order to promote reproducible research, Matlab and order synaptic plasticity in memristors [10], [11]. In order Cadence files to generate the experimental data and reproduce to advance our understanding of the fundamental properties the results in this paper are made publicly available through Github.1 M. Rahimi Azghadi was with the School of Electrical and Information Engi- neering, The University of Sydney, NSW 2006, Australia. He is currently with the College of Science and Engineering of James Cook University, Townsville, II. MEMRISTIVE SYNAPSE WITH SPIKE TIMING QLD 4814, Australia (e-mail: [email protected]). DEPENDENT PLASTICITY (STDP) B. Linares-Barranco is with the Microelectronics Institute of Seville, Seville 41092, Spain (e-mail: [email protected]). Spike Timing Dependent Plasticity (STDP) is a well- D. Abbott is with the School of Electrical and Electronic Engineering of known synaptic plasticity rule that modifies the synaptic the University of Adelaide, Australia (e-mail: [email protected]). P. Leong is with the School of Electrical and Information En- weight according to the exact timing relationship of pre- gineering, The University of Sydney, NSW 2006, Australia (e-mail: [email protected]). 1https://github.com/MostafaRahimiAzghadi/MemristiveSynapse IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2 claimed to be physically implemented in [19] can be written pre as: iMR = g(w; vMR)vMR (2) dw = f(w; v ); (3) post dt MR where iMR and vMR are the current passing through and the voltage across the device, w denotes a memristor physical state variable, and g represents the nonlinear conductance of the device. According to [21], this memristor is voltage/flux driven, because its structural parameter depends on vMR. Fig. 1. Synaptic weight changes, at the time of each spike, as a function of the timing difference between pre- and post-synaptic spikes, their temporal Considering this model for a memristive device, one should order, and their synaptic amplitude parameters, i.e. A+ and A−. Here, the define the function f, so that account for the memristive potentiation time constant (τ+), is assumed smaller than depression time behaviour observed in physically implemented devices. Here constant (τ−), hence for the same ∆ts between pre and post spikes, different weight changes are induced, even if A+ = A−. Here, ‘o’ denotes the we utilize a simple function similar to the one employed exponentially decaying potentiation potential, while ‘r’ represents depression in [20]. This function is written as potential. ( jvMRj vth I0sign(vMR)[e v0 − e v0 ] if jvMRj > vth f(vMR) = 0 otherwise; and post-synaptic spikes and brings about Long Term Po- (4) tentiation (LTP) or Long Term Depression (LTD) [15]. In where I0 and vo are some physical parameters of the device some electrophysiological experiments performed in cultured and vth is its threshold, beyond which the conductance of hippocampal neurons in 1998, the hypothesized dependence of the device changes exponentially. This behavioural model of the synaptic efficacy to the spike timing was experimentally a memristive device can be illustrated as shown in Fig. 2(a). confirmed [12]. Consequently, computational neuroscientists Note to the two thresholds and the exponential growth of the developed a model to approximate the findings of the exper- conductance. These are the features that we exploit to devise iment [18]. This model is today known as pair-based STDP a memristive synapse with STDP. (PSTDP) and is usually represented as Fig. 2(b-c) demonstrate the current-voltage and resistance ( −∆t characteristics of the utilized device, which is simulated us- + + ( τ ) ∆w = A e + if ∆t > 0 ing the memristor macromodel used in this paper and was ∆w = ( ∆t ) (1) ∆w− = −A−e τ− if ∆t ≤ 0; presented in [20]. This macromodel depicts a thresholding be- haviour similar to a commercially available ion-based physical where ∆t = tpost − tpre is the timing difference between a memristor [24] with a current-voltage characteristic as shown single pair of pre- and post-synaptic spikes. As demonstrated in Fig. 2(d). in Fig. 1, the amount of potentiation/depression will be deter- mined as a function of the timing difference between pre- and III. MEMRISTIVE SYNAPSE WITH TRIPLET STDP post-synaptic spikes, their temporal order, and their relevant amplitude parameters (A+ and A−). In 2002, Froemke and Dan presented a modified STDP rule, that takes into account a suppressive mechanism among Since the report of the first memristor, various attempts spikes. This mechanism was hypothesized to account for non- have been made to devise artificial memristive synapses with linearities
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