Chapter 6: Power Amplifiers and Output Stages

Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan CHAPTER 6: POWER AMPLIFIERS AND OUTPUT STAGES

6.0: INTRODUCTION The analysis and design of small-signal amplifiers were discussed so far. These amplifiers operate in the linear range, and the output will normally be undistorted. The operation of the transistors is confined to the active mode. This permitted the use of small-signal models to analyze these circuits. Such small-signal amplifiers have inherently low power output capability and are not expected to drive low impedance loads such as speakers and motor drives.

Requirements of Power Amplifiers In this chapter, we consider power amplifiers. Both discrete and IC power amplifiers will be examined. These amplifiers usually constitute the output stages in a multistage amplifier. There are some specific requirements of such amplifiers. Some important ones are: 1. Power amplifiers must have low output impedance so they can drive low impedance loads with no reduction in the voltage gain. 2. Power amplifiers must deliver a large amount of power while dissipating only a low amount of power internally; i.e., they must have a high power efficiency. There are two important reasons for this: (a) While the amplifier is expected to deliver a specific amount of output (load) power, the input power to the amplifier comes essentially from the dc power supply (Section 1.4) Therefore, if the amplifier is inefficient, there will be a large drain on the power supply. (b) The difference between the battery power and the power delivered to the load must be dissipated by the transistors. If the amplifier is inefficient, the power dissipation ratings of the transistors must be higher, and large size heat sinks will be required to prevent any damage to the transistors. High power transistors are expensive, and the size and cost of the amplifier will escalate. These reasons clearly suggest the importance of efficiency. 3. Power amplifiers handle large voltage and current signals since they are the final stages of multistage amplifiers. Therefore, the distortion of the output signal is also an important consideration. These amplifiers should deliver power to a specific load with acceptably low levels of distortion. A measure of the distortion in the output signal is the total harmonic distortion (THD). In a good power amplifier, THD should be less than 0.1 %. 4. Since the power amplifiers handle large signals, the small-signal approximations are not generally

479 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

valid in the analysis of power amplifiers. Instantaneous values of the signals should be used instead. However, as mentioned earlier, we cannot accept large distortion either. Therefore, linearity is also an important consideration in power amplifiers. In this chapter, we first consider the classification of power amplifiers using the signal-swing considerations. Then, power amplifiers under the different classifications starting with the simplest configuration of the emitter follower circuit are discussed. Thermal considerations due to the power dissipation in the transistors are included. Also examined are short-circuit protection and current-limiting features. We conclude the chapter with a discussion on power MOSFETs.

6.1: CLASSIFICATION OF POWER AMPLIFIERS Power amplifiers are classified according to the waveform of the collector current (drain current if FETs are used). They are Class-A, Class-AB, Class-B, and Class-C amplifiers. While the first three types of amplifiers find wide use in the audio power applications, the Class-C operation is usually employed in the RF (radio frequency) power amplifiers. In this chapter, we focus on the first three categories only.

In the Class-A operation, the BJT is biased with a dc bias current ICQ so the instantaneous value of the collector current never becomes zero. The waveform of the collector current under the Class-A operation is shown in Fig. 6.1.1(a) using a sinusoidal signal1 as an example. The transistor conducts during the entire cycle, and the collector current never goes to zero. This is like any other small-signal amplifier addressed in the earlier chapters. All small-signal linear amplifiers belong to the Class-A category. Therefore, in a Class-A power amplifier, the distortion will be the least. The value of ICQ is typically chosen to be equal to half the maximum expected value of the collector current. This provides the maximum symmetrical signal-swing and maximum efficiency in this category.

In the Class-B operation, the transistor is biased to operate with a zero bias current; i.e., ICQ = 0. With sinusoidal inputs, the collector current exists during either the positive or negative half cycles only. Therefore, the waveform of the collector current of a npn transistor will be as shown in Fig. 6.1.1(b). With the same input, a pnp transistor will conduct during the negative-half cycles of the input only. Since the input voltage has to overcome the cut-in voltage of the base-emitter junction, the collector current will be distorted near the zero crossings. This situation is exactly similar to what exists in a half-wave rectifier. If only one transistor is used to amplify signals with Class-B operation, the output will be heavily distorted. Fortunately,

1 Sinusoidal signals are used to study and assess the properties of many electrical and electronic circuits. The properties of the power amplifiers are studied using a single frequency sinusoidal signal. Therefore, unless otherwise specified, both input and output signals will be sinusoidal throughout this chapter.

480 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

iC(t)

iC(t) ICQ

0 0 π 2π 3π 4π ωt π 2π 3π 4π ωt (a) (b)

iC(t)

iC(t) Im

ICQ 0 0 π 2π 3π 4π ωt π 2π 3π 4π ωt (c) (d) Fig. 6.1.1: Collector current waveforms of the npn transistors operating in (a) class-A, (b) class-B, (c) class-AB, and (d) class-C power amplifiers. both halves of the input signal can be amplified using the complementary symmetry (push-pull) arrangement. With this arrangement, the power amplifier will be highly efficient because there is no dc power dissipation under the quiescent conditions, i.e., with no input signal. To avoid the distortion during the zero crossings, each transistor in the push-pull arrangement can be biased with a small dc bias current so that the conduction angle is more than 180E as shown in Fig. 6.1.1(c). This is called the Class-AB operation because this operation is intermediate between the Class-A and Class-B operations. Of course, the efficiency will reduce in comparison to the Class-B operation because of the quiescent dc power dissipation but the distortion during the zero-crossings can be avoided. However, in all types of power amplifiers, whether it is Class-A, -AB, -B, the distortion due to the transistor saturation cannot be avoided. Therefore, the maximum signal-swing should be limited to the transistor saturation levels, and we assume this to be the case throughout this chapter.

481 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

In the Class-C operation, the transistor is biased to conduct for less than half a cycle as shown in Fig. 6.1.1(d). This type of operation is used in RF power amplifiers (in radio and TV transmitters), where efficiency is required to be very high. The output waveform is almost pulsating. The output is fed to an LC tank circuit, which essentially operates as a tuned amplifier (see Fig. 1.9.3) and selects the fundamental component for further amplification. Although the Class-C amplifier is very efficient, it is only used in some special applications where high power is delivered to the load. The analysis of the Class-C amplifier is tedious and beyond the scope of this book.

6.2: CLASS-A POWER AMPLIFIERS The simplest power amplifier is an emitter(or the source) follower. A Class-A power amplifier using a constant-current source biasing, along with its transfer characteristic, has been reproduced here in Fig. 6.2.1 (see Fig. 3.6.9). Emitter- and source-followers have been analyzed in the earlier chapters for their small-signal behavior. Now we consider their large-signal operation and power efficiency. This circuit may be used in a discrete design also. To keep the analysis simple, it is assumed that α . 1 for the BJTs in this and future sections.

vO +VCC Q 1 V -V +vI CC CES1 + v BE1 i - E1 i +v R L O IREF v v I BE1 I Q BIAS RL Q3 2

-IBIASRL

-(VEE -VCES2 ) -VEE Fig. 6.2.1: (a) A class-A power amplifier with a constant-current source biasing, and (b) its transfer characteristics.

Power Dissipation and Efficiency A power amplifier is designed to deliver a specified maximum value of the average amount of power to a given load. It is convenient to assume the output signal to be a sinusoid and develop all the equations in terms of its amplitude. Thus, let

482 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

vO (t) ' Vm sin ωt , (6.2.1) where Vm # VCC. Then, we find that

vCE1 ' VCC & vO ' VCC & Vm sinωt,andiC1 . iE1 ' IBIAS % (Vm /RL )sinωt . (6.2.2) The input current from the signal source is very small in comparison to the collector currents of the transistors. Therefore, in power calculations, the power input from the signal source is ignored, and the input power to the circuit is assumed to be the power supplied by the power supplies only (see (1.4.1)). The power dissipation in a transistor, also known as the collector-dissipation, is mainly due to the collector current (see

(1.4.2)). The instantaneous value of the power dissipation in Q1 is

2 2 pD1 ' vCE1 iC1 ' VCC IBIAS & (Vm /RL )sin ωt % ( VCC /RL ) & IBIAS Vm sinωt . (6.2.3)

If VCC = IBIASRL, the above equation reduces to

2 2 pD1 ' VCC IBIAS & (Vm /RL )sin ωt. (6.2.4)

The maximum power dissipation equal to (VCC IBIAS) occurs in Q1 at t = 0 or if Vm is zero (there is no signal). Therefore, Q1 must be able to dissipate this power without any increase in its junction temperature.

However, if RL 6 4 (when no load is connected to the amplifier), we find from (6.2.3) that the maximum power dissipation can be as much as (VCC + Vm )IBIAS, when sin(ωt) = -1. Since such a special condition exists only at specific instants of time and is not sustained, the design need not be this conservative; it is sufficient if the transistor power dissipation rating is greater than (VCC IBIAS). Another possible extreme condition is RL

= 0 (short-circuit). Under this condition, the transistor Q1 may draw a large current, and consequently, its junction temperature will start increasing. If this condition persists even for a small period, the transistor will be damaged. Therefore, most power amplifiers are provided with a short-circuit protection (see Fig. 6.4.7).

The collector current of Q2 has a constant value of IBIAS. Taking VCC = VEE, its maximum collector- dissipation is [(VCC + Vm )IBIAS] and occurs when vO(t) reaches Vm. This again is only an instantaneous maximum but not the average. The average power dissipation in Q2 is

t ' T 1 P ' ( V sinωt % V )I dt ' V I . (6.2.5) D2 T m m CC BIAS CC BIAS t ' 0

The (average) power dissipation in Q1 is

t ' T 2 2 1 Vm Vm P ' V I & sin2 ωtdt' V I & . (6.2.6) D1 T m CC BIAS R CC BIAS 2R t ' 0 L L

The power conversion efficiency is calculated as the percentage of the useful (average) power PL

2 supplied to the load to the total power PS drawn from the dc sources (see (1.4.4)). We can find the latter as

2 In calculating the total power drawn from the power supplies, we neglect the average power drawn from the negative power supply by the bias resistance R. We discuss its influence soon.

483 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

PS ' PD1 % PD2 % PL , where

t ' T 2 2 2 1 Vm sin ωt Vm P ' dt ' . (6.2.7) L T m R 2R t ' 0 L L

Therefore, PS = (2VCCIBIAS), and the efficiency is

2 2 PL 1 Vm 1 Vm η ' ' ' . (6.2.8) P 4 V ×I R 4 2 S CC BIAS L VCC

The efficiency is maximum if Vm = VCC, and the maximum attainable efficiency is only 25%. Since the biasing resistor R also draws a current approximately equal to I from the negative power supply, we have to add another (VCCIBIAS) to PS. If so, the maximum power efficiency will only be 16.7%, when this biasing scheme is used. If the amplitude Vm of the output signal is close to the value of VCC, considerable distortion of the output can occur due to saturation of the transistors. Therefore, the value of Vm should be less than VCC. Then, the efficiency will be even lower than 16.7% in this circuit.

A Transformer coupled Class-A Power Amplifier In the audio power applications, one uses mostly a single power supply scheme, and the load resistance is capacitively coupled to the emitter follower (see Fig. 3.8.5). However, with the use of a transformer coupling, the maximum efficiency can be increased to almost 50%. The emitter follower circuit with a transformer coupling and its load lines are shown in Fig. 6.2.2. The transformer can also serve the purpose of providing impedance matching between the load and the output resistance of the amplifier, which is an added advantage. This helps to transfer maximum power to the load. The resistance of the transformer primary coil is negligible and is almost a short-circuit for dc. Therefore, the dc load line will be almost vertical. However, for sinusoidal signals, the effective resistance on the primary side is

2 RLeff ' a RL , (6.2.9) where a is the turns-ratio (n1/n2). Therefore, the slope of the ac load line will be (-1/RLeff). Let the output voltage be

vO (t) ' Vm sin ωt.

Then, the sinusoidal signal across the collector-emitter terminals will have an amplitude of (aVm) around VCC. The maximum and dc bias values of the collector current are

(VCC % aVm ) aVm Vm ICmax ' ,andICQ ' ' . (6.2.10) 2 2 aR a RL a RL L

484 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

+VCC R i B1 Q C ∞ +vI ICmax dc load line, +v slope ≈ ∞ n :n O i 1 2 E I ac load line, R CQ B2 i R -1 L L slope = RLeff 0 VCC VCC + aVm vCE (a) (b) Fig. 6.2.2: (a) A transformer-coupled power amplifier and (b) its load lines.

To obtain the maximum symmetrical signal-swing, ICQ must bisect the ac load line (see Fig. 3.8.3); i.e., the following conditions must be fulfilled:

ICmax VCC VCC ' aVm ,andICQ ' ' . (6.2.11) 2 2 a RL

The average current drawn from the power supply is ICQ. Therefore,

2 VCC P ' V I ' . (6.2.12) S CC CQ 2 a RL (6.2.7) gives the load power in this circuit also. Therefore, the efficiency is

2 2 PL 1 a Vm η ' ' . (6.2.13) P 2 2 S VCC

Since Vm # (VCC /a), the maximum attainable efficiency is 50%. In this calculation, the power dissipation in

RB1 and RB2 has been ignored. Therefore, the actual efficiency will be lower than 50%. However, in comparison to the previous Class-A amplifier, the efficiency has doubled for the same supply voltage and the amplitude of the output signal.

If Vm = (VCC /a), the collector-dissipation is equal to the power dissipation in the load because the efficiency is 50%. The average power dissipation in the BJT is then

PD ' ( VCC ICQ /2). However, with no input signal, the maximum average collector-dissipation is

PD ' VCC ICQ . Therefore, transistor power dissipation rating should exceed twice the maximum power dissipation in the load; i.e.,

485 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

PD $ 2PLmax , (6.2.14) where PLmax occurs for Vm = (VCC/a).

Example 6.1 (Design) Using the circuit of 6.2.2, design a power amplifier to supply a maximum load power of 2 W to a 4-Ω load. Assume that VCC = 12 V. SOLUTION Using (6.2.9),

Vm' 2PL RL ' 4V.

For maximum efficiency, the transformer turns-ratio is a ' (VCC/Vm ) ' 3. Next, using (6.2.11), we find that

VCC 12 1 I ' ' ' A. CQ 2 9×4 3 a RL

The current rating of the transistor should exceed 2ICQ = (2/3) A, and its power rating should exceed (VCC ICQ)

= 4 W. The maximum signal-swing across the collector-emitter terminals is (2VCC), which is 24 V. Since we need a relatively low current device, a general purpose transistor such as 2N2270 may be used in this circuit.

It has VCEO = 45 V, and ICmax = 1 A. Usually, a general purpose transistor cannot be used in power applications without a heat sink. With a heat sink provided, the maximum power dissipation rating for this transistor is 5 W. Thus, the power dissipation rating is also satisfied.

The typical value of the base-emitter voltage is about 0.88 V at IC = 150 mA, and hFE = 135 at this current for this transistor. Therefore, we use the same value in this design, although we require (1/3) A.

Allowing (ICQ /10) through RB2, since the dc voltage drop across RB2 should be 0.88 V, a standard value of

RB2 ' 27 Ω may be selected. The current through RB1 should be (IB + ICQ /10) = 35.8 mA, and the voltage

drop across RB1 should be about 11.12 V. Therefore, RB1 should be 310.6 Ω. We select a standard resistance of RB1 ' 330 Ω .

Let us calculate the efficiency of this design including the power dissipation in RB1 and RB2. The total power dissipated in these two resistors is about 403 mW. Then, including this power dissipation, the efficiency is

2 η ' ' 45.4 %. 4 % 0.403

486 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan Power Dissipation and Thermal considerations The power dissipated in a transistor generates heat and causes an increase in its collector-base junction temperature. In an improper design, the temperature increase may damage the transistor permanently. Therefore, the designer should choose a power transistor with appropriate power rating and should also consider the details of the heat sink that may be necessary for a given application. Let us now address the effect of the power dissipation on the junction temperature. The junction temperature of a transistor should be kept below the maximum allowable junction temperature TJmax. For silicon transistors, the value of TJmax is about 150 to 200EC, and the manufacturers usually specify this value. The heat is transmitted from the junction to the case and then to the environment. Unless this heat is taken away from the case as fast as it reaches, the case temperature and the temperature at the environment will also increase. If so, for a given amount of power dissipation, the junction temperature increases. The ambient temperature decides how fast the heat can be transferred away from the case, and therefore, how much power can be dissipated in a transistor.

PD P Dmax -1 slope = θJC

0 TCO TJmax TC Fig. 6.2.3: The typical power derating characteristic of a transistor.

The manufacturers usually provide the maximum power dissipation and the power derating curve, similar to the one shown in Fig. 6.2.3, for a transistor. In this plot, TC is the case temperature, and TCO is typically about 25EC. The value of TJmax can be read from the point where the curve (a straight line) cuts the temperature axis; i.e., if TC = TJmax, the transistor cannot transfer any heat from the junction to the case and hence cannot dissipate any power. Nonzero power dissipation is possible, only if TC < TJmax. For TC < Tjmax, we can find the maximum permissible power dissipation level of the transistor at a specified case temperature

TC from this curve. The manufacturers also give the slope of this curve, known as the power derating factor, the unit of which is W/EC. The linear portion of the power derating curve can be described by

TJmax & TC ' θJC PD , (6.2.15) where PD is the permitted power dissipation at a case temperature TC and θJC is called the thermal resistance expressed in EC/W. The value of the thermal resistance value can be computed from the inverse of the slope

487 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan of derating characteristic. Usually, the manufacturers provide the thermal resistance θJC from the junction to the case. Sometimes, they also provide the value of θJA, which is the thermal resistance from the junction to the ambient without any heat sink added. With a heat sink, one has to take the thermal resistance of the heat sink also into account. Including all the effects, we can write that

TJmax & TA ' (θJC % θCS % θSA )PD ' θJA PD , (6.2.16) where θCS is the thermal resistance from the case to the heat sink, and θSA is the thermal resistance of the heat sink to the ambient. Without a heat sink, θJA = θJC + θCA. It should be noted that the thermal resistance from the case to the ambient without a heat sink would be much greater than the effective thermal resistance (θCS

+ θSA) with a heat sink. Hence the need is for a heat sink.

Example 6.2 A 200-W power transistor is operated at a case temperature of 100EC with no heat sink. Its maximum allowable junction temperature is 200EC and θJC = 0.875EC/W. (a) Find the maximum allowed power dissipation. (b) If TC = 70EC, and the transistor dissipates 100 W, find the junction temperature. SOLUTION

(a) Using the values of θJC in (6.2.15),

(TJmax & TC ) 100 PD ' ' ' 114.3 W. θJC 0.875

Obviously, the maximum power dissipation should not exceed 114.3 W, although its maximum power rating of the transistor is 200 W. (b) Using (6.2.15) again, we find that

TJ' TC % 0.875×100 ' 157.5E C.

Although the thermal resistance from the junction to the case is typically small, the thermal resistance from the junction to the ambient θJA is usually high with a typical value of 60EC/W. Assume that a transistor has a maximum power rating of 60 W, θJA = 60EC/W, and TJmax = 150EC. If it is to be operated at a room temperature of 25EC, the transistor can only dissipate 2.1 W.

Example 6.3 (Design)

A 200-W power transistor has TJmax = 200EC and θJC = 0.875EC/W. It has a typical value of θCS =

488 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

1EC/W. It is operated with a heat sink. If the transistor power dissipation is 50 W and the ambient temperature is 25EC, what can be the maximum value of the thermal resistance of the heat sink to the ambient? SOLUTION Using (6.2.16), we find that

(TJmax & TA ) 200 & 25 θJC % θCS % θSA # ' ' 3.5EC/W. PD 50

Substituting the values for θJC = 0.875EC/W and θCS = 1EC/W, the thermal resistance of the heat sink should be limited to

θSA # 3.5E/W & 0.875EC/W & 1EC/W ' 1.625EC/W.

Therefore, any heat-sink with a thermal resistance less than 1.625EC/W is acceptable.

6.3: CLASS-B POWER AMPLIFIERS A maximum efficiency of 50% is obtained in a transformer-coupled Class-A power amplifier. This circuit configuration, however, cannot be realized in an IC because of the presence of the transformer. The efficiency can be improved considerably with Class-B operation both in IC and discrete circuits. Virtually, in all practical applications, either the Class-B or its modification, Class-AB operation, is used.

A Class-B Power Amplifier using a Complementary pair of BJTs The basic Class-B circuit, using a complementary pair of npn and pnp transistors, is shown in Fig.

6.3.1(a). This circuit is essentially a combination of two emitter follower circuits. If vI is zero, both Q1 and

Q2 do not conduct, and iL = vO = 0. We can prove this using the contradiction principle. Assume that vI = 0 and Q1 conducts. If so, iL > 0 and vO > 0. If vI = 0 and vO > 0, vBE1 < 0. For Q1 to conduct, vBE must be positive because it is an npn transistor. This contradicts our original assumption. Using a similar argument, it can be proven that, if vI = 0, the pnp transistor does not conduct either. Since both transistors do not conduct, vO ' 0. Circuit Operation Each transistor operates in the Class-B mode and conducts during alternate half cycles of the input signal. At the output, the half cycles are combined to obtain the replica of the input signal. During the positive half cycle, the npn transistor pushes the current iE1 into the load, and the pnp transistor pulls the current iE2 from the load during the negative half-cycle. Therefore, another name for this amplifier is the push-pull amplifier. Q1 and Q2 operate as emitter followers during the positive and negative half cycles respectively.

If vI goes positive, Q1 conducts for vI $ Vγ, whereas Q2 does not. If Q1 conducts, the load draws current from

489 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

vO +VCC Q1 VCC + v i +v BE1 E1 +v I - O -V - γ v i V v BE2 E2 R i γ I + L L

Q2 -V CC -VCC (a) (b) Fig. 6.3.1: A class-B power amplifier and its transfer characteristic.

the positive power supply, and vO increases positively. Thus, during the positive cycle of vI,

vO . vI & Vγ , vI $ Vγ . (6.3.1) vO can only reach a maximum value of VCC because the transistor Q1 will saturate for a sufficiently large positive input. If vI goes negative, Q2 conducts and Q1 does not; vO also goes negative. For a sufficiently large negative value of vI, vO will reach a negative maximum of -VCC if Q2 saturates. Therefore, the transfer characteristic will be as shown in Fig. 6.3.1(b). Since the transistors do not conduct for *vI* # Vγ, where Vγ stands for the cut-in voltages of the transistors, there is a dead zone in the transfer characteristic around vI =

0. If vI is a sinusoidal signal, the waveform of the output voltage will be as shown in Fig. 6.3.2(a). The waveforms of the emitter and output currents are also shown in this figure. The distortion near the zero-crossing of the output signal is called the zero crossover distortion.

Reducing or eliminating the distortion is possible. Ignoring the crossover distortion and approximating vO(t) as a sinusoid, the load power is same as the one given by (6.2.9); i.e.,

2 PL ' (Vm /2RL ). (6.3.2) Efficiency The average current drawn from the positive power supply is

t'T/2 1 I ' (V / R )sin(ωt) dt ' V /(πR ). (6.3.3) C1 T m m L m L t'0 The average current drawn from the negative power supply (In fact, the current sinks into the negative supply) has equal value in magnitude but is negative, and therefore,

IC2 ' Vm /(πRL ). (6.3.4) Therefore, the total power drawn from the power supplies is

490 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

vO(t) iE1(t) Vm Vm RL

0 0 T T 3T t T T 3T t 2 2 2 2

-Vm -V m R (a) L (c)

iL(t) iE2(t) Vm Vm

RL RL

0 0 T T 3T t T T 3T t 2 2 2 2

-Vm -Vm R R L (b) L (d)

Fig. 6.3.2: The waveforms of varuous signals in the class-B amplifier of Fig. 5.3.1. (a) vO(t), (b) iL(t), (c) iE1(t), and (d) -iE2(t).

PS ' VCCIC1 % VCC (%IC2 ) ' (2VCCVm )/(πRL ). (6.3.5) Using (6.3.2) and (6.3.5), we find that

PL π Vm η ' ' . (6.3.6) PS 4 VCC

If the amplitude of the sinusoid Vm equals the value of VCC, the efficiency reaches its maximum of 78.5%. The corresponding load power is

2 VCC PLmax ' . 2RL Clearly, the efficiency of the Class-B amplifier is much higher than the efficiency of the Class-A power amplifier. This is the most important reason for its popularity in both IC and discrete circuits. Furthermore, if vI = 0, the quiescent power dissipation in the transistors is zero. Another advantage of the Class-B operation also exists. If Vm is less than VCC, the efficiency decreases linearly in a Class-B amplifier whereas being

491 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

2 proportional to ( Vm/VCC ) , it decreases quadratically in a Class-A amplifier. For values of Vm less than VCC, the percentage decrease in the efficiency of the Class-B amplifier will be lower than the percentage decrease in the efficiency of the Class-A amplifier.

Power Dissipation in the Transistors Because of the symmetry, the power dissipation in both transistors should be equal. Therefore, if we subtract the load power from the total power drawn from the power supplies, it should be twice the power dissipated in each transistor. Thus, the power dissipation in each transistor is

2 1 VCC Vm 1 Vm PD ' PD1 ' PD2 ' (PS & PL ) ' & . (6.3.7) 2 πRL 4 RL

Unlike in Class-A amplifiers, the average power dissipation depends on the value of Vm in a Class-B amplifier. The plot of PD as a function of Vm is shown in Fig. 6.3.3.

PD η = 50%

PDmax

η = 78.5%

0 2V V CC CC Vm π Fig. 6.3.3: The collector dissipation as a function of the amplitude of the output sinusoid in the class-B power amplifier.

Under the quiescent conditions (Vm = 0), the collector-dissipations are zero. For some value of Vm, the collector-dissipation reaches a maximum value. To find the condition for the maximum collector- dissipation, we can differentiate PD with respect to Vm and equate it to zero. Solving such an equation, it can be shown that PD reaches the maximum value, if

Vm ' (2VCC)/π. (6.3.8)

Substituting this value of Vm in (6.3.7), the value of PDmax is

2 2 VCC 2VCC 1 2VCC 1 VCC 2 P ' & ' ' P , (6.3.9) Dmax πR π 4 π R 2 2 Lmax L L π RL π where PLmax = PL when Vm = VCC. Therefore, to select the transistors in this circuit, the above equation is used

492 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan to specify their power dissipation rating. In the Class-A amplifier with the transformer coupling, the collector power dissipation should be greater than 2PLmax (see (6.2.16)). This means that, for the same load power delivery, the collector-dissipation of the transistor in a Class-B amplifier should only be approximately 10% of what it is in a Class-A amplifier. In the design Example 6.1, the same 2-W power could have been delivered with transistors having only about 0.4 W power dissipation rating had we used the Class-B configuration. If the amplitude Vm of the sinusoid is equal to the value given by (6.3.8), the efficiency will only be 50%. Typically, the efficiency of the Class-B amplifiers is somewhere between 50% and 78.5%.

Example 6.4 (Design) Design the push-pull Class-B amplifier to deliver a maximum power of 20 W to an 8-Ω load. SOLUTION The amplitude of the sinusoidal signal at the output can be computed from

2 PL ' Vm /(2RL ) ' 20 W .

Using the value of RL = 8 Ω, we find that Vm = 17.89 V. To avoid the distortion of the output due to saturation, we choose

VCC ' 20 V .

The maximum collector-dissipation can be found using (6.3.9), and thus,

2 2 PDmax ' VCC /(π RL ) ' 5.066 W . The maximum current through the transistors is

ICmax ' ( Vm / RL ) . ( VCC / RL ) ' 2.5 A .

If vO(t) reaches -VCC, the maximum value of VCE in Q1 is about 38 V. Similarly, the maximum value of VEC in Q2 should also be about 38 V. Therefore, we select a complementary pair of transistors, MJE180 (npn) and MJE170 (pnp) from Motorola, which satisfy the required power, current, and voltage ratings. These transistors have a continuous current rating of 3 A, and VCEO = 40 V. With a heat sink provided, their power dissipation rating is 12.5 W, which is more than twice the required value. Single Supply Schemes A Class-B power amplifier can also be designed with transformer coupling using a single power supply. This circuit is shown in Fig. 6.3.4. One should note that the center-tapped secondary of the transformer at the input enables the use of the npn-type for both transistors. This amplifier works in about the same way as the previous circuit does. The load current reconstructed with the use of the center-tapped transformer at the output will be similar to the one shown in Fig. 6.3.2(b). All the waveforms will be similar

493 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

+2VCC

Q1 iC1

+ +v ∞ ∞ +v v + I O BE1 VCC - i L R L vO - RL iL vBE1 + - Q2

Q2 iC2

Fig. 6.3.4: A class-B power amplifier with Fig. 6.3.5: A class-B power amplifier transformer coupling. using a single power supply.

to the ones shown in Fig. 6.3.2 except that of iC2. The waveforme of iC2 will be the negative of the waveform of (-iE2), shown in Fig. 6.3.2, i.e., iC2 and iE2 will have the same waveform. Therefore, all the power calculations given for the previous circuit hold for this circuit also. This circuit has the advantage in that the transformer can be used for impedance matching at the output. Another single supply scheme without an elaborate arrangement of transformers is shown in Fig. 6.3.5. This circuit uses a pair of large-valued coupling capacitors just as in other ac-coupled amplifiers. The operation of this circuit is similar to that of the circuit of Fig. 6.3.1 except that the low frequency components will be attenuated. The choice of the coupling capacitors can be made to meet a specific value of 3-dB frequency in the low frequency range (Chapter 8). If the amplifier is designed with a symmetrical signal- swing, the maximum signal-swing at the output should be limited to VCC. This circuit can be designed using the same method used to design the circuit in Fig. 6.3.1 with two power supplies except that the supply voltage in this circuit should be (2VCC).

Total Harmonic-Distortion The output voltage waveform in Fig. 6.3.2(a) is not purely sinusoidal. An accurate description of this waveform during one period is

vO (t) ' 0, 0 # (ωt) # θ, ' Vm sin(ωt) & Vγ , θ # (ωt) # π & θ, ' 0, π & θ # (ωt) # π % θ, (6.3.10) ' Vm sin(ωt) % Vγ , π % θ # (ωt) # 2π & θ, ' 0, 2π & θ # (ωt) # 2π, where Vγ is the cut-in voltage, and

494 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

Vγ θ ' sin&1 . (6.3.11) Vm vO(t) is an odd function since vO(-t) = -vO(t). Also, vO(t) has half-wave symmetry in that vO(t+T/2) = -vO(t) for all t. The Fourier series representation of an odd function with half-wave symmetry will have the fundamental and odd harmonic sine terms only. Therefore, vO(t) can be represented in terms of its fundamental and odd harmonics as follows:

4 ' vO (t) j Vmnsin(nωt). (6.3.12) n'1 n odd

In the above sum, n = 1 corresponds to the fundamental, and the other components are the harmonics. Vm1 is the amplitude of the fundamental, and its effective value is (Vm1/%2). The effective value (rms) value of all the harmonics put together is

4 1 2 VHeff ' j Vmn . (6.3.13) 2 n'3 n odd

The total harmonic-distortion is defined with

4 2 j Vmn n'3 (6.3.14) effective value of all harmonics VHeff n odd THD ' ' ' . effective value of the fundamental V Vm1 / 2 m1

Using Parseval's theorem,

T 2 2 1 2 Vm1 V ' v (t)dt & . (6.3.15) Heff T m O 2 t ' 0

Using the above in the definition for THD,

T 1 2 2 THD ' v (t)dt & 1. (6.3.16) 2 T m O Vm1 t ' 0

The percentage THD can be found by multiplying the above result with 100. The value of the term inside the square-brackets in (6.3.16) is nothing but twice the amount of power dissipated by the output voltage vO(t) in a 1-Ω resistor. The amplitude of the fundamental component of vO(t) described in (6.3.10) is

495 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

T 2 2θ sin(2θ) 4cosθ V ' v (t)sinωtdt' V 1 & % & V . (6.3.17) m1 T m O m π π π γ t ' 0

Also, for the same vO(t),

T 2 2 2 2 2 2θ Vm sin(2θ) 8Vm Vγ cosθ v (t)dt ' (V % 2V ) 1 & % & . (6.3.18) T m O m γ π π π t ' 0

For a given set of values for Vm and Vγ, the value of θ can be computed using (6.3.11). We can then find the values of Vm1 and the square-bracketed term in (6.3.16) using (6.3.17) and (6.3.18) respectively. Knowing these values, the value of THD can be calculated. As an example, if Vm = 5 V and Vγ = 0.7 V, θ = 0.1405 radians. Using this value of θ, we find that

T T 2 2 2 V ' v (t)sin(ωt)dt ' 4.11 V, and v (t)dt ' 17.04 m1 T m O T m O t'0 t ' 0 Using these values in (6.3.16), THD = 8.9%. In an inexpensive audio power amplifier, this may be tolerable. However, in a good high-fidelity system, the THD should be less than 1%, and the crossover distortion in the Class-B power amplifier may be unacceptably high.

+VCC

+v I R + +vX B +vO Ad - RL iL

-VCC

Fig. 6.3.6: A scheme to reduce the crossover distortion in a class-B power amplifier.

The zero crossover distortion can be reduced significantly using an op amp with negative feedback as shown in Fig. 6.3.6. In this circuit, the output signal is compared with the input signal in the same way as in the voltage follower circuit of Fig. P1.43. The operation of this circuit is similar to the regular Class-B amplifier except that the dead zone is greatly reduced. Let Ad be the difference-mode gain of the difference amplifier. If vI = 0, then vO = 0, and vX = 0. Neither Q1 nor Q2 conducts. If vI increases positively, vX increases positively; Q1 starts to conduct when vX = Vγ or vI = (Vγ/Ad), and vO starts to increase thereafter. Similarly, if vI goes negative, vO also goes negative except when *vI* = (Vγ/Ad). Clearly, the dead zone is now limited to time intervals during which *vI* = (Vγ/Ad), rather than *vI* = Vγ if the op amp is not used. Let us now relate

496 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan vO and vI when either Q1 or Q2 conducts Neglecting the base-bias currents of Q1 and Q2 and the voltage-drop across RB,

vO ' vX K Vγ , where Vγ is the cut-in voltage of the base-emitter junctions of Q1 and Q2. The "-" sign holds, if vO is positive, and the "+" holds, if vO is negative. Since vX = Ad (vI - vO),

vO ' Ad (vI & vO ) K Vγ . Solving the above equation, the output voltage is

Ad Vγ vO ' vI K . (6.3.19) 1 % Ad 1 % Ad

If Ad = 10,000 and Vγ = 0.7 V,

vO . vI K 70 µV . Clearly, the op amp works in the buffer mode of Fig. P1.43, and the dead zone becomes insignificant in the transfer characteristic. Therefore, the crossover distortion is almost be eliminated at the output. However, such an elaborate arrangement is not a practical solution to reduce the distortion. A better solution is to use the Class-AB operation, where a small nonzero bias current is used.

6.4: CLASS-AB AMPLIFIERS

By operating the transistors in the push-pull amplifier with a small dc bias collector current ICQ, the distortion caused by the dead-zone can be eliminated. Therefore, the Class-AB operation is very popular in both IC and discrete designs. A Class-AB Power Amplifier using a Diode-scheme A Class-AB amplifier and its transfer characteristic are shown in Fig. 6.4.1. The two diode-connected transistors D1 and D2 are biased by a constant-current source IBIAS. Even if vI = 0, a part of the current IBIAS flows through the diodes generating the bias voltage VBB. This bias voltage keeps Q1 and Q2 on. Therefore, there is no "dead zone" in this characteristic; the crossover distortion will be absent. The various current waveforms are shown in Fig. 6.4.2. There is an important advantage in this scheme. An increase in the collector current increases the power dissipation, which, in turn, increases the junction temperature of the output BJTs. Any increase in the temperature causes a decrease in the diode voltage and a decrease in VBB , since the diode-connected transistors are in the same neighborhood in an IC. A decrease in VBB causes a reduction in the collector currents of the power transistors. Thus, there is a thermal tracking, and the output transistors are protected from the thermal runaway.

Assume that both Q1 and Q2 have the same junction areas, and the junction areas of D1 and D2 are also

497 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

+VCC

vO VCC IBIAS

Q1 + -V slope ≈ 1 D γ 1 +v O v vBB I

D2 i - RL L

+ Q v 2 I - -VCC

-VCC (a) (b) Fig. 6.4.1: A class-AB power amplifier using a diode scheme, and (b) transfer characteristic.

Amplitude of the current

ICQ1 iCQ1 iL 0 π 2π ωt i CQ2 ICQ2

Fig. 6.4.2: Waveforms of collector and load currents in a class-AB power amplifier. The collector currents and the load current are concident except near the zero crossing. Observe that the load current is not distorted as in class-B operation. equal. However, the junction areas of the diodes need not be as large as the junction areas of the output transistors because the diode-connected transistors need to carry only a low bias current in the order of base- bias current of Q1. Let the junction area of the power transistors be n-times the junction area of the diode- connected transistors. If so, the saturation current of the output transistors will be n-times the saturation current of the diodes. The voltage VBB provides the bias for the output transistors. The dc component of vI is usually such that the dc component of vO is zero. Therefore, under the quiescent conditions, assume that vO

498 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

= 0. There is a collector bias current ICQ in Q1 and Q2, and the current through the diodes will be [IBIAS -

(ICQ/βdc1)]. Therefore,

VBB ' 2VT ln [IBIAS &(ICQ/βdc1 )]/IS ' 2VT ln[ICQ /(nIS )], (6.4.1) where IS is the saturation current of the diodes. Solving the above, the value of ICQ is

IBIAS ICQ ' . nIBIAS,ifβdc1 » n. (6.4.2) 1/n % 1/βdc1

For a given value of ICQ, which is usually less than 10% of the maximum load current, the value of

IBIAS can be made as small possible (not zero, of course) by choosing a large value for n. However, there is a limit to the minimum value of IBIAS, which limits the maximum value of n. If the base-bias current in Q1 becomes a substantial portion of IBIAS , the diode current will reduce. This, in turn, will reduce the value of

VBB. There should be a minimum diode current to maintain the output transistors in the active-mode.

Therefore, there is a need for a minimum value for IBIAS. For a given ICQ, the value of n cannot therefore be arbitrarily large, and the junction area of the diode-connected transistors cannot be too low.

Because of the collector-bias current in Q1 and Q2, there is a quiescent power dissipation. The equations derived in Section 6.3 for the total power drawn form the power sources and the collector- dissipation must be modified to account for the quiescent power dissipation. The equation (6.3.5) for PS should be modified to

PS ' 2VCC [ Vm /(πRL ) % ICQ ]. (6.4.3) The power dissipation in each transistor also increases to

2 1 Vm 1 Vm PD1 ' PD2 ' (PS & PL ) ' VCC % ICQ & . (6.4.4) 2 πRL 4 RL The maximum power dissipation in the output transistors will be

V P ' V CC % I . Dmax CC 2 CQ (6.4.5) π RL

Example 6.5 (Design)

In the Class-AB power amplifier of Fig. 6.4.1, VCC = 12 V, RL = 100 Ω, and vO(t) = 10sin(ωt) V. The input bias voltage is such that the dc output offset is zero. The power transistors have IS = 0.1 pA, βQ1 = 100, and VA1 = 100 V. The diode-connected transistors have a the junction area of the power transistors. If a minimum diode current of 1 mA is required, find the minimum value for the bias current IBIAS. Find the value of ICQ through the transistors. Also, calculate the efficiency of the power amplifier and the required power

th rating for the power transistors. Find the harmonic components in vO(t) up to 10 harmonic using PSPICE

499 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan simulation. The transient analysis is required for this purpose. Find the percentage of THD assuming that the amplitudes of components beyond 10th harmonic are insignificant. SOLUTION

Under the quiescent conditions, VO = 0, and βdc1 = 112. The maximum collector current in Q1 is

ICmax ' ILmax ' (12/0.1) ' 120 mA .

Since the minimum diode current should be 1 mA, the value of IBIAS should be at least

IBIAS ' (ICmax / βdc1 ) % 1 ' 2.071 mA .

Then,

I I ' BIAS ' 6.051 mA . CQ 1/3% 1/112

In this scheme, once the value of IBIAS is chosen, there is no control on ICQ except through the value of n. To lower the value of ICQ, we have to lower the value of n. This emphasizes the point that we cannot increase n to a high value. The power absorbed by the load is

2 2 Vm 10 PL ' ' ' 0.5 W. 2RL 2×100 Using (6.4.3), we find that

PS ' 2×12×( 31.83 % 6.051) ' 909.1 mW. Therefore, the efficiency is 55 %. Using (6.4.5), we find that the maximum power dissipation in the output power transistors is 0.219 W. Therefore, a 1/4&W transistor should be adequate in this application.

The transient analysis was carried out with a sinusoidal input signal with an arbitrarily chosen amplitude of 10 V and a frequency of 1000 Hz. The plot of the output signal is shown in Fig. 6.4.3. There was an output offset voltage of about 6.299 mV. Otherwise, the output is very close to a sinusoidal signal. The Fourier analysis was also carried out, and the amplitudes of the harmonics up to the 10th were obtained. These values are available in the output file along with the value of THD and are listed here in Table 6.1. The THD is about 0.15%. The total harmonic distortion is indeed very small as anticipated in a Class-AB amplifier.

500 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

10.0 V O v 5.0 V

0 V

-5.0 V Output voltage -10.0 V 0 0.5 1.0 1.5 2.0 2.5 3.0 Time in ms Fig. 6.4.3: The waveform of the output signal in Design Example 6.5 Table 6.1: The amplitudes of the fundamental and the other harmonics in Example 6.5. HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG) 1 1.000E+03 9.903E+00 1.000E+00 8.178E-04 0.000E+00 2 2.000E+03 7.682E-03 7.756E-04 9.276E+01 9.275E+01 3 3.000E+03 1.183E-02 1.194E-03 -1.790E+02 -1.791E+02 4 4.000E+03 6.888E-04 6.955E-05 7.912E+01 7.911E+01 5 5.000E+03 4.430E-03 4.474E-04 1.789E+02 1.789E+02 6 6.000E+03 3.247E-04 3.279E-05 9.920E+01 9.919E+01 7 7.000E+03 2.049E-03 2.069E-04 -1.790E+02 -1.790E+02 8 8.000E+03 1.767E-04 1.784E-05 8.094E+01 8.094E+01 9 9.000E+03 1.098E-03 1.108E-04 1.792E+02 1.792E+02 10 1.000E+04 6.602E-05 6.666E-06 9.125E+01 9.125E+01 TOTAL HARMONIC DISTORTION = 1.512880E-01 PERCENT

A Class-AB Power Amplifier using a VBE-multiplier Circuit

To keep the value of VBB relatively constant, a VBE-multiplier circuit may be used instead of the diodes. This scheme is shown in Fig. 6.4.4, which is more flexible than the diode scheme and is also popular in IC amplifiers. Q3 has relatively a smaller area because its collector current needs to be in the order of the maximum value of the base-bias current of the output transistor Q1. For a given value of the bias current IBIAS, the ratio (R1 / R2) can be adjusted to produce the required value of VBB that sets a specified value of ICQ in the output transistors. Under the quiescent conditions, neglecting the base-bias current of Q1,

IBIAS ' IC3 % IR . (6.4.6) where IR is the current through R1. Neglecting the base-bias current of Q3, we find that

VBB ' VBE3 (1 % R1 / R2 ), (6.4.7) where

VBE3 ' VT ln ( IC3 / IS3 ). (6.4.8)

Since VBB is obtained by multiplying VBE3 with a factor, this scheme is called the VBE-multiplier scheme. The advantage of the scheme is that a specific value of ICQ can be set by controlling the resistance ratio. Besides,

501 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

+VCC

IBIAS

Q1 + I R I R 1 Q C3 3 +vO

vBB

R2 i - RL L

+ v Q2 I -

-VCC

Fig. 6.4.4: A class-AB power amplifier using a VBE - multiplier sheme.

the change in VBB will be very small even if there is a large increase in the collector current of Q1. An increase in the collector current of Q1 causes an increase in the base-bias current of Q1. Then, the collector current of

Q3 decreases. However, if Q3 remains in the active-mode, a large change in IC3 causes only a very small change in the value of VBE3 keeping the value of VBB relatively constant.

Example 6.6 (Design)

In the Class-AB amplifier of Fig. 6.4.4, VCC = 15 V, and RL = 100 Ω. The saturation current of the power transistors is 0.1 pA and that of the small-signal transistor Q3 is 0.01 pA. It is required to establish ICQ

= 10 mA. The maximum amplitude of the output signal is expected to be 15 V. VA = 100 V and β = 100 for

Q1. Design the circuit. SOLUTION

βdc1 = 115. The maximum expected collector current of Q1 is 150 mA, and the maximum base current of Q1 will be approximately 1.3 mA. Therefore, IBIAS should be more than 1.3 mA. The value of VBB required under the quiescent condition is

VBB ' 2VT ln(10mA/0.1pA) ' 1.317 V. Under the quiescent conditions, we also find that

IBIAS & VBB /(R1 % R2 ) & ICQ/115 VBB ' (1% R1 /R2 ) VBE3 ' (1% R1 /R2 ) VT ln . IS3

502 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

There is only one equation with three unknowns, R1, R2, and IBIAS. Therefore, some unknowns can be arbitrarily selected. We can choose IBIAS ' 2.5 mA, which is greater than 1.3 mA, the maximum base

current of Q1. This allows us to provide a minimum 1.2 mA for (IC3 + IR). Allowing IR = 0.5 mA and noting that VBB is relatively constant,

R1 % R2 ' ( 1.317 / 0.5 ) ' 2.634 kΩ.

Neglecting the base-bias current of Q1 under the quiescent conditions, IC3 will be 2 mA. Therefore, using (6.4.7) and (6.4.8),

R1 1.317 1 % ' ' 1.947. R2 0.026 ln (2mA / 0.01 pA )

Solving for R1 and R2 from the above two equations, the values of R1 and R2 can be found to be

R2 ' 1.353 kΩ,andR1 ' 1.281 kΩ.

The closest standard values for R1 and R2 may be picked in a discrete design. However, using a variable resistor, the value of VBB can be adjusted for a specific value of ICQ. In an IC, the initial design can be set for the required values. This completes the design. If the load current reaches the maximum of 150 mA,

IC1 VBB 150 1.317 IC3 ' IBIAS & & ' 2.5 & & . 0.7 mA. βdc1 R1 % R2 115 2.634

We have used an approximate value for VBB in the above equation. However, using the new possible value of IC3, a correct estimate for the value of VBB is

VBB ' 1.947×0.026× ln(0.7 mA/0.01 pA ) ' 1.282 V.

Clearly, the value of VBB remains relatively constant in this scheme, as the collector current of the output transistor changes.

Small-Signal Analysis of Class-AB Amplifiers Under the Class-AB operation, the power amplifier becomes almost a linear amplifier. Since the Class-AB power amplifier is also the output stage of a multi-stage amplifier (for example, an op amp), it is also necessary to know how to estimate its primary parameters, such as the voltage gain. During this analysis, we assume that the input source is a voltage source vs with a source impedance Rs. While the input signal is directly fed to the base-node of Q2, the signal path to the base-node of Q1 has an additional resistance of the base-bias circuits for small signals in both configurations of Figs. 6.4.1 and 6.4.4. Fortunately, this additional resistance is very small in comparison to the input resistance looking into the base-node of Q1 and can be neglected. This is essentially equivalent to the assumption that the biasing part of the amplifier can be short-

503 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

Ri i i Ro i r o +v Rs ee o + + + r vs vi kbeio 1×vi oe RL - - -

Fig. 6.4.5: The small-signal equivalent circuit of class-AB amplifier. The boxed-part shows the

model of the composite (parallel combination of Q1 and Q2) BJT in a power amplifier. The parameters are defined in (6.4.9). circuited for small-signals. With this excellent approximation, the amplifier becomes a parallel connection of the two output transistors, and one can obtain the small-signal equivalent in the form of Fig. 3.5.3(b) to represent this circuit as shown 6.4.5, where the small-signal parameters of the composite BJT are

ree ' (re1 2re2 ), rπe ' (rπ1 2rπ2 ), kbe ' (ree /rπe ), and roe ' (ro1 2ro2 ). (6.4.9) The small-signal parameters of the individual transistor can be easily calculated using the usual formulas at the corresponding collector-bias currents (ICQ1 and ICQ2 for Q1 and Q2 respectively). Using the equivalent circuit of Fig. 6.4.5, one can easily find the amplifier’s primary parameters. As an example, consider the situation in Example 6.5. Assume that the input source has an internal resistance of 2 kΩ. In addition to the parameters given in Example 6.5, assume that VA1 = 100 V, and VA2 = 50 V, and βQ2 = 50. Since

VCE1 = VCE2 = 12 V, βdc1 = 112, and βdc1 = 62. Since IEQ1 = IEQ2 . ICQ1 = 6.501 mA, re1 = re2 = 4.3 Ω, and ree =

2.15 Ω. rπ1 = 485.9 Ω, rπ2 = 270.9 Ω, and rπe = 173.9 Ω. Therefore, kbe = (2.15/173.9) = 0.01236. Furthermore, ro1 = 18.51 kΩ, ro2 = 10.25 kΩ, and roe = 6.6 kΩ. This leads to (RL2roe) = 98.51 Ω. Using these parameters,

vi vi io ' ' . ree % (RL 2roe ) 100.7 Using KVL,

vs ' kbe io Rs % vi , Y vi ' 0.8029 vs . Clearly then,

0.8029 vs ×98.51 vo vo ' ' 0.7854vs , Avs ' ' 0.7854 V/V. 100.7 vs The input resistance is

Rs Ri ' . 8.147 kΩ. (vs /vi ) & 1 Since the load resistance is relatively small, input resistance is also relatively small. Clearly, most of the attenuation of the signal occurs at the input of the amplifier. Of course, the output resistance of the amplifier

504 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan is

Ro . ree % kbe Rs ' 26.87 Ω. Clearly, it is very simple to evaluate the amplifier’s parameters using the equivalent circuit of Fig. 6.4.5.

+VCC

IBIAS Q1

R1 Q3

+vO R2

Q5 R iL + Q L v Q4 6 I -

-VCC Fig. 6.4.6: A class-AB power amplifier using the compound transistors. Class-AB Amplifier using Darlington Pairs To reduce the base-bias currents of the power transistors, the Darlington pair and composite transistors may be used for Q1 and Q2 in the circuits of Figs. 6.4.1 and 6.4.4. An example circuit is shown in

Fig. 6.4.6. In this circuit, the base-bias current of Q1 will be approximately (iL/β1β2). The compound transistor, formed by Q4, Q5, and Q6, behaves as a pnp transistor with an effective value of β . (β4β5β6). In IC technology, the pnp transistor is usually a lateral pnp transistor having a low β-value (. 5 to 10) (see

Appendix-A). Since (β1β2) is likely to be very high, the use of two npn transistors Q5 and Q6 in conjunction with Q4 permits a similar effective current gain to be achieved. This is necessary to keep the positive and negative signal-swings approximately equal. The lateral pnp transistors also have poor frequency response. If this scheme is used in a discrete circuit design, it may be sufficient to use only one npn transistor in the compound pnp transistor. In the recent past, vertical pnp transistors have been realized in IC technology (see Fig. A.8(b) in Appendix-A), and they may also be used to realize current mirror circuits. Vertical pnp transistors, with high frequency responses closely matching those of npn transistors, may also be used in the IC designs. There is an inherent stability problem in the circuit of Fig. 6.4.6. Because of the internal feedback

505 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan in the composite connection of Q4 and Q5, there could be high frequency oscillations. This problem can be handled with a proper frequency compensation (Chapter 9).

Short-circuit Protection

If there is an accidental short-circuit (RL = 0), the collector current in the output transistors can become excessively high causing a thermal runaway. If the junction temperature increases beyond TJmax, the transistors will be damaged. Therefore, it is critical to provide the output transistors with a short-circuit protection. A modification of the Class-AB power amplifier of Fig. 6.4.4 with a short-circuit protection is shown in Fig. 6.4.7. Besides the usual components as in the circuit of Fig. 6.4.4, this circuit has four additional components, namely Q3-R3 and Q4-R4 combinations. These combinations provide the short-circuit protection to the amplifier. The transistors, Q3 and Q4, need only be small-size transistors as they are expected to carry collector currents in the order of the base-bias currents of the power transistors.

+VCC

IBIAS Q1

Q3 +VDD R1

Q I 5 R3 BIAS iD1 +vO

M3 M1 R4 RL iL R2 + +vO Q 4 VGG R - iL L Q + 2 M4 M2 vI i - -VCC D2 -V +vI SS Fig. 6.4.7: A class-AB power amplifier with Fig. 6.5.1: A class-AB MOSFET output short-circuit protection. amplifier.

The resistance values of R3 and R4 are small (usually a fraction of an ohm to a few tens of ohms depending upon the maximum collector current). Under the normal operating conditions, the voltage drops across these resistances are adjusted to be less than Vγ (about 0.5 V), and therefore, Q3 and Q4 will be under

506 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan the cutoff conditions normally. However, if the collector currents in Q1 and Q2 become excessively large due to accidental short-circuits, the voltage drops across these resistors turn on the transistors Q3 and Q4 starving the bases of Q1 and Q2. This process, in turn, virtually shuts the collector currents through the power transistors protecting them from the thermal runaway.

6.5: MOSFET CONFIGURATIONS

A Class-AB MOSFET output amplifier is shown in Fig. 6.5.1. This configuration is very similar to that of the BJT amplifier of Fig. 6.4.1. The diode-connected MOSFETs M3 and M4 provide the bias voltages for M1 and M2. The operation of this circuit is also very similar to that of its BJT counterpart, and indeed this circuit can be operated either as a Class-B or a Class-AB amplifier. However, the signal-swing and biasing considerations are different because MOSFETs suffer from body effects. When the gate-node potential of M1 can be taken to the level of VDD, the output signal reaches the maximum positive signal vOmax. Let the corresponding drain current of M1 be (vOmax/RL). We can find the value of vOmax using (4.7.11). Typically, (VDD

+ VSS - Vt1) »(iOmax / K1 ). Neglecting this excess gate voltage (iOmax / K1 ),

2 2 vOmax ' VDD & Vtn % (γn /2)& γn VDD % VSS & Vtn % (γn /4). (6.5.1)

Following similar steps, assuming that the gate-node potential of M2 can be lowered to the level of -VSS and that only M2 conducts under this condition, we can show that the minimum possible output signal (negative value) is

2 2 vOmin '&VSS % Vtp & (γp /2)% γp VDD % VSS & Vtp % (γp /4). (6.5.2)

The maximum and minimum possible output currents are

iOmax ' (vOmax /RL ), and iOmin ' (vOmin /RL ). (6.5.6) However, these currents are also given by

2 2 iOmax ' K1 ( VDD & vOmax & Vt1 ) ,andiOmin '&K2 ( VSS % vOmin & *Vt2 *) , (6.5.7) where Vt2 is the threshold voltage of M2 corrected for its body effect.

Example 6.7 (Design) The fundamental parameters of the n-channel MOSFETs in the circuit of Fig. 6.4.6 are: KP =

2 -1 1/2 51.17 µA/V , Vtn = 0.7339 V, λn = 0.03122 V , γn = 0.4823 V , and (2φf) = 0.7 V. The parameters of the p-

2 -1 1/2 channel MOSFETs are: KP = 16.53 µA/V , Vtp = -0.7776 V, λp = 0.04349 V , γp = 0.6727 V , and (2φf) =

507 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

0.7 V. Assume that VDD = VSS = 5 V, IBIAS = 10 µA, and RL = 1 kΩ. Assuming that the gate-node potentials of

M1 and M2 can be taken to VDD and -VSS respectively, find the possible output voltages and the corresponding output currents. Since γp > γn, by comparing (6.4.12) and (6.4.13), it may be noted that

vOmin < vOmax.Assume that the load current is limited to &2mA, when the gate-node potential of M2 reaches -VSS. Obtain the sizes of M2 and M1. It is also required to have vO = 0, and ID1 = ID2 = 0.1 mA, if the signal input vi is zero. Find the required input dc bias voltage and the sizes of M3 and M4. Choose the minimum length of L = 2 µm for all the MOSFETs and neglect the channel-length modulation. Verify the signal-swings of the design using PSPICE simulation. Also, use Fourier analysis in PSPICE by applying a sinusoidal signal of 1000 Hz frequency and of suitable amplitude to avoid saturation and find the THD. SOLUTION Using (6.5.4) and (6.5.5), we find that 0.48232 v ' 5 & 0.7339 % & 0.4823 5 % 5 & 0.7339 % (0.48232 /4) ' 2.91 V, Omax 2 and 0.67272 v '&5 % 0.7776 & % 0.6727 5 % 5 & 0.7776 % (0.67272 /4) '&2.393 V. Omin 2

Clearly,

vOmax vOmin iOmax ' ' 2.91 mA, and iOmin ' '&2.393 mA. RL RL

If iO = -2 mA, vO = -2 V. At this voltage,

Vt2 ' 0.7776 % 0.6727 5.7 % 2 & 0.7 ' 2.081 V. Therefore, ignoring the channel-length modulation,

2 2mA' K2 (5& 2 & 2.081) .

From the above equation, we find the required value of K2 and hence the required width choosing L2 = 2 µm. This results in the aspect ratio of

W 574 ' . L 2 2

Since M1 should carry the same level of current at the same output voltage, we choose

W 16.53 574 186 ' × . . L 1 51.17 2 2 With these choices,

508 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

51.17 186 16.53 574 K ' × ' 2379.4 µA/V 2 ,andK ' × ' 2372.1 µA/V 2 . 1 2 2 2 2 2

At vO = 0,

Vt2 ' 0.7776 % 0.6727 5.7 % 0 & 0.7 ' 1.821 V.

Since ID2 = 100 µA under this condition, 100 V ' V % ' 2.026 V. SG2 t2 2372.1

Therefore, the dc input bias voltage should be VI '&VSG2 '&2.026 V. At the zero output bias voltage,

the bias currents of M1 and M3 are in the ratio of (1/10) and those of M2 and M4 are also in the ratio of (1/10).

Besides, the same gate-to-source voltages of M1 and M3 and those of M2 and M4 are equal. Therefore, the aspect ratios of M3 and M4 can be found to be

W 1 W 19 W 1 W 58 ' × . ,and ' × . . L 3 10 L 1 2 L 4 10 L 2 2 4

Output in V -2

-4 -6 -4 -2 0 2 4 6 Input in V Fig. 6.5.2: The transfer characteristic of the class-AB amplifier designed in Example 5.7

The circuit was simulated in PSPICE, and the transfer characteristic is shown in Fig. 6.5.2 with a dc input bias voltage of VI = -2.026 V. From this characteristic, the output offset was found to be -6.7 mV, which is indeed very small. Besides, at vI = -2.026, VGG = 3.7 V. When the gate-node potential of M1 becomes 5.72 V, the output voltage reached a level of approximately equal to +2.91 V. In our original design, we calculated this output level at the gate-node potential of M1 at +5 V. However, in this calculation, we ignored the excess gate-to-source voltage. Similarly, when the gate-node potential of M2 reached a level of -5.48 V, the output reached the level of -2.39 V. Again, in our original calculation, at the output level of -2.39 V, the gate-node potential of M2 should be at -5 V. The error is again due to the excess gate-to-source voltage. From the

509 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

PSPICE simulation, we found that, at the output levels of +2 V and -2 V, the inputs were required to be +1.144 V and -5.021 V respectively. With an input of 0 V, the output offset voltage was 1.2806 V, and an input voltage of -2.1174 V was required to offset this and bring the output to zero. Finally, it should be noted that the nonlinear transfer characteristic is not only due to the square-law characteristic of the MOSFETs but also because of the nonlinear body effect which depends on the output voltage. A sinusoidal signal with an amplitude of 3 V and a frequency of 1000 Hz was applied at the input. The input offset was set to -2.1174 V. The transient response, obtained from the PSPICE, is shown in Fig. 6.5.3. Even though the input offset was set to be the required value, one can observe the fact that the positive and negative peaks are not identical. The Fourier analysis showed that the fundamental component was 1.939 V. The second harmonic, as was pointed out in Chapter 4, was the next dominant term with an amplitude of 55.86 mV. The third and fourth harmonics were respectively 13.17 mV and 9.753 mV. We found the amplitudes of the harmonics up to 10th harmonic. The THD was found to be 3.01%. Clearly, a Class-AB MOSFET power amplifier suffers from considerably more distortion than its BJT counterpart.

2.0V 1.5V 1.0V O v 0.5V 0V -0.5V -1.0V

Output voltage -1.5V -2.0V -2.5V 0 0.5 1.0 1.5 2.0 2.5 3.0 Time in ms Fig. 6.5.3: The waveform of the output signal in the Design Example 6.7.

Although the output amplifier of Fig. 6.5.1 has a low output impedance, since the MOSFETs M1 and

M2 suffer from body effects, the signal-swings of the output are severely limited. The gate-node potentials of M1 and M2 can not even reach the levels of +VDD and -VSS in a practical realization of circuit shown in Fig. 6.5.1. An alternate scheme is to use the inverter configuration of Fig. 6.5.4, which can source current from a high output impedance node without wasting any current. This circuit can also be operated either in Class-B or Class-AB by adjusting the gate voltages of M3 and M4. If it operates in Class-B, as the input goes positive,

510 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

+VDD

M5 M7 M M 1 3 iD7

+VG1 io +v +v I +VT2 -VT1 O

RL +VG2 iD8 M2 M4 M M6 8

-VSS Fig. 6.5.4: Push-pull inverting CMOS output amplifier with a high impedance output.

the current in M1 increases, and M2 is turned off. This current in M1 is reflected as the drain current in M8, which is the load current because the current in M7 should be zero. Similarly, if vI goes negative, the current in M2 increases and is reflected as the current in M7, which will be load current because M8 is now cutoff. It can be noted that the output voltage can swing almost to the supply voltages. However, the circuit constitutes a voltage-controlled current source because the output resistance, at the quiescent conditions, is (ro72ro8), which is relatively high. Such an output stage can be used in an operational transconductance amplifier (OTA). This circuit is very attractive from all points of view except possibly the output resistance. Consider a design example on the sizing of the MOSFETs and the calculation of the required bias voltages VG1 and VG2.

Example 6.8 (Design) The process parameters of the MOSFETs in the circuit of Fig. 6.5.4 are the same as those in Example

6.7. Assume that VDD = VSS = 5 V, and RL = 1 kΩ. The load current is limited to ±4 mA. It is also required to have vO = 0, and ID1 = ID2 = 0.4 mA, if vI = 0. Obtain the sizes for all MOSFETs. Choose the minimum length of L = 2 µm for all the MOSFETs. Verify the signal-swings using PSPICE simulation. SOLUTION At the maximum possible output current of +4 mA, the output voltage should be +4 V. The MOSFET

M7 should remain in the pinch-off mode at least until this level. Therefore, it is required that

511 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

vO 2 VDD & vO $ Y K7 $ 4000 µA/V . K7 RL

Therefore, the aspect ratio of M7 must satisfy the condition of KP W W $ 4000 µA/V 2 Y $ 484. 2 L 7 L 7 We choose

W 970 ' . L 7 2

The size of M8 is given by W 16.53 970 313.4 ' × . , L 8 51.17 2 2 and we choose

W 314 ' . L 8 2 With these aspect ratios, we find that 16.53 970 51.17 314 K ' × ' 4008.5 µA/V 2 ,andK ' × ' 4016.8 µA/V 2 . 7 2 2 8 2 2

At any output current level, the current through M3 and M5 (similarly in M4 and M6) need not be that high. We choose a current scaling ratio of 10 in the current mirrors formed by M5-M7 and M6-M8 pairs and design the circuit to operate as a Class-AB amplifier with the drain currents ID7 = ID8 = 0.1× 4 mA = 400 µA, if vI = vO = 0. If the current scaling ratio of 10 is used, then the current through M5 and M6 should be 40 µA, when vI = vO = 0. With ID8 = 400 µA, the required bias voltage VGS6 = VGS8 can be calculated to be 400 V ' V ' 0.7339 % ' 1.0274 V. GS6 GS8 4016.8×( 1 % 0.03122×5)

Next,

51.17 W 2 W 36 40 µA ' × ( VGS6 & Vtn ) (1% 0.03122×VGS6 ) Y ' . 2 L 6 L 6 2

Proceeding in the same way, we find that

400 V ' V ' 0.7776 % ' 1.0639 V, SG5 SG7 4008.5×( 1 % 0.04349×5) and 16.53 W 2 W 113 40 µA ' × (VSG5 & *Vtp *) (1% 0.04349×VSG5 ) Y . . 2 L 5 L 5 2

512 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

VT1 and VT2 depend on the threshold voltages of M1 and M2, which, in turn, depend VT1 and VT2 because of the body effect. We do not know the sizes of M1 and M2 yet, and therefore, we can only evaluate the approximate values of VT1 and VT2. First, consider M1 with vI = 0. Its threshold voltage is

Vt1 ' Vtn % γn ( &VT1 % VSS % 0.7 & 0.7) . Vtn % γn &VT1 % VSS . and the equation for VT1 is

VT1 ' Vt1 % ID1 / K1 .

Since Vt1 »ID1 / K1 , as first order approximation, we can neglect the second term in the above equation and get the following approximate equation for VT1:

VT1 . Vtn % γn &VT1 % VSS . Solving the above equation, we obtain

2 2 VT1 . Vtn & γn /2% γn VSS & Vtn % γn /4' 1.6205 V.

Using the above value of VT1, an approximate value of Vt1 is

Vt1 ' Vtn % γn &VT1 % VSS % 0.7 & 0.7 ' 1.3045 V. Then,

KP W 2 W 26 ID1 ' 40 µA ' VT1 & Vt1 1 % 0.0312 VDS1 Y ' . 2 L 1 L 1 2

2 With the above choice of the aspect ratio for M1, K1 ' 332.6 µA/V . Since we now know the values for

drain current of M1 and its conductivity parameter, we can find the accurate value of VT1 and its threshold voltage using

2 2 VT1 ' Vtn % ID1 / K1 & γn /2& γn 0.7 % γn VSS & Vtn & ID1 / K1 % 0.7 % γn 0.7 % γn /4' 1.648 V, and

Vt1 ' Vtn % γn ( &VT1 % VSS % 0.7 & 0.7) ' 1.3012 V. The approximate values found earlier and the above accurate values agree very well. Proceeding further, we find that VBS4 = 6.648 V, VSD4 = 2.3246 V, and

*Vt4 * ' *Vtp * % γp ( 6.648 % 0.7 & 0.7) ' 2.0383 V.

The value of VG2 should be less than&(VT1 % *Vt4 *), and we choose VG2 '&4V. Next using the drain

bias current of 40 µA in M4, we find the size of M4 using

KP W 2 W 90 ID4 ' 40 µA ' (&VG2 & VT1 & *Vt4 * ) (1% 0.04349 VSD4 ) Y ' . 2 L 4 L 4 2

Proceeding further to find the required sizes of M2 and M3, we first find the approximate value of VT2 using

2 2 VT2 .*Vtp * & γp /2% γp VDD & *Vtp* % γp /4 ' 1.952 V.

Next, the threshold voltage of M2 can be found to be

*Vt2 * ' *Vtp * % γp ( VDD & VT2 % 0.7 & 0.7 ) ' 1.5159 V.

Also, VSD2 = 6.952 V. Since ID2 = 40 µA,

KP W 2 W 36 ID2 ' 40 µA ' VT2 & Vt2 1 % 0.04349 VSD2 Y ' . 2 L 2 L 2 2

2 With the above choice of the aspect ratio of M2, K2 ' 148.75 µA/V . We can refine the value of VT2 using

2 2 VT2 ' *Vtp *% ID2 /K2 &γp /2&γp 0.7%γp VDD &*Vtp *& ID2 /K2 %0.7%γp 0.7%γp /4' 2.023 V.

Therefore,

Vt3 ' Vtn % γn ( VT2 % VSS % 0.7 & 0.7 ) ' 1.6707 V.

VG1 should be greater than (VT2 + Vt3), and we can choose VG1 '%4V. We also find that VDS3 = 1.913 V.

Finally, we find the size of M3 using

KP W 2 W 32 ID3 ' 40 µA ' (VG1 & VT2 & Vt3 ) (1% 0.03122 VDS3 ) Y ' . 2 L 3 L 3 2 The above design was simulated in PSPICE. The transfer characteristics are shown in Fig. 6.5.5.

From these characteristics, at vI = 0, the output current was found to be 37.5 µA (the output offset). The drain currents of M7 and M8 were 469.9 µA and 432.4 µA respectively. Besides, the bias voltages VT1 and VT2 were

1.635 V and 2.002 V respectively, which are very close to the predicted values. The drain bias currents of M1 and M3 were 44.23 µA and 47.16 µA respectively. This imbalance causes the differences in the drain currents of output MOSFETs and hence the offset voltage. By scaling M2 and M3 to

W 34 W 29 ' ,and ' , L 2 2 L 3 2 the imbalances can be reduced considerably reducing the output offset current to 4.9 µA.

5.0

2.5 iO iD8 0

-2.5 currents in mA iD7

-5.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5

Input voltage vI in V Fig. 6.5.5: The transfer characteristics of the output stage designed in Example 6.8. 40 +VDD

i 20 D1 iD1 i M D2 A 1 + - io 0 iO +vO +vI +

- -20

R currents in mA A L M i 2 D2 -40 -4.0 -2.0 0 2.0 4.0

-VSS Input voltage vI in V Fig. 6.5.6: Push-pull inverting CMOS output amplifier with feedback to reduce the output impedance and the transfer characteristics of a typical design.

One can increase the output resistance of the circuit of Fig. 6.5.4 using the cascode mirror at the expense of decreased signal-swing for the output voltage. Feedback can be employed to the circuit of Fig. 6.5.4 to decrease the output resistance (Chapter 7). A circuit arrangement using such feedback is shown in Fig. 6.5.6.

Assume that the output MOSFETs are biased with an IQ such that

iD1 ' IDQ1 ,andiD2 ' IDQ2 , vO ' 0 vO ' 0

where IDQ1 and IDQ2 are the quiescent bias currents, which are usually a fraction of the maximum load current. From the circuit, it can be found that

vSG1 ' VDD & A(vO & vI ), and vGS2 ' A(vO & vI ) % VSS.

Since vO is expected to be less than vI in the circuit, the MOSFETs never reach ohmic mode but they may

515 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan reach cutoff depending the bias currents and the gate-to-source voltages. When the MOSFETs operate in the pinch-off mode, the drain currents are given by

2 2 iD1 ' K1 VDD & A(vO & vI ) & Vt1 ,andiD2 ' K2 VSS % A(vO & vI ) & Vt2 .

Since iD1 = iD2 +iO and iO = (vO/RL), we get

2 2 vO K1 VDD & A(vO & vI ) & Vt1 & K2 VSS % A(vO & vI ) & Vt2 & ' 0. RL

Assume that we choose the aspect ratios of the MOSFETs such that K1 = K2 = K and the supply voltages such that VSS = VDD. Then, using these equalities in the above equation and solving for vO,

2 AKRL 2 VDD & Vt1 & Vt2 KRL 2 VDD & Vt1 & Vt2 Vt2 & Vt1 vO ' vI % . (6.5.8) 2 AKRL 2 VDD & Vt1 & Vt2 % 1 2 AKRL 2 VDD & Vt1 & Vt2 % 1

It is clear that vO has a linear relationship with vI except for the unavoidable but a small output offset due to the difference in the threshold voltages of the MOSFETs. Since at vI = 0, vO is nearly zero, the zero-input bias currents are

2 2 IDQ1 ' K1 VDD & Vt1 ,andIDQ2 ' K2 VDD & Vt2 . Using the above in (6.5.8),

2 ARL KIDQ1 % KIDQ2 (IDQ1 & IDQ2 ) RL vO ' vI % , 2 AR KI % KI % 1 2 AR KI % KI % 1 L DQ1 DQ2 L DQ1 DQ2 (6.5.9) A(gm1 % gm2 ) RL IO RL ' vI % , A(gm1 % gm2 ) RL % 1 A(gm1 % gm2 ) RL % 1 where gm1 and gm2 are the small-signal transconductances of the MOSFETs. If [A(gm1+gm2)RL] » 1, it is clear that vO closely follows vI. Furthermore, we can show that, for small-signals, the output resistance of the circuit is

&MvO 1 Ro ' / . , (6.5.10) Mi 0 A(g % g ) O 0 Q m1 m2 which will be much lower than the output resistance without feedback.

As vI increases to a sufficiently large positive or negative value, one of these MOSFETs enters the cutoff mode. For example, if vI > vO + (VSS - Vt2)/A, M2 enters the cutoff, and iO = iD1. For such values of input, the output current has square law characteristic, which increases the harmonic distortion. Furthermore, as vO increases to a large positive value, vSD1 falls below the value to keep M1 in the pinch-off mode, and M1 may enter the cut-off mode. Therefore, the increase in the value of iO is reduced. A similar situation occurs for the negative inputs also, and M2 may enter the cut-off mode for large negative inputs. However, we can choose a larger value of IDQ to increase the linear range and reduce the distortion but at the risk of lower efficiency.

516 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan 6.6: IC POWER OPERATIONAL AMPLIFIERS IC op amps are versatile and find a very wide range of applications. This is the most important reason for their popularity. Their output current, however, is limited to a few tens of mA, and their maximum power output is also limited. For example, if an op amp, energized with a ±15 V dc source, can supply a maximum output current of 50 mA and the output is sinusoidal, the maximum output power is limited to 375 mW. This amount of power is sufficient in most small-signal applications but it is quite low in power applications. Current boost transistors are therefore added to increase their power handling capability, and they are then called power operational amplifiers. There is a wide range of commercial IC power amplifiers. These amplifiers essentially consist of a preamplifier with a Class-AB output stage or a simplified form of an op amp with an internal feedback. The main difference between a normal op amp and a power operational amplifier is in the power handling capability of the output power transistors. The IC power amplifiers typically have a voltage gain of 30-50 dB with moderately high (but not as much as in a regular op amp) input impedance. They can usually handle power output of 5-20 W without any current boost. Their current handling capability can be increased by adding Class-AB power stages externally. IC power amplifiers can be used for most audio and video power applications and are also available in the dual-in-line packages for stereo systems. The application areas of the IC power op amps include phonographs, intercoms, alarms, AM- FM radios, TV, etc. An example of the IC power amplifier is LM384 from National Semiconductor corporation. This is a 5-W audio power amplifier whose schematic is shown in Fig. 6.6.1. The input stage is a difference amplifier

(Chapter 6) with Darlington pairs at the input. The difference amplifier is biased by (R1 + R2) and R3. Q2 is a high gain CE-amplifier. The 10-pF capacitor provides frequency compensation to achieve adequate stability margins (Chapter 9). The output of the CE-amplifier is fed to a Class-AB power amplifier with short-circuit protection. R3 also provides feedback, which reduces the closed-loop gain to about 50. LM384 can be used with a maximum supply voltage of 28 V. It can be noted that [R3 /(R1 % R2 )]' 0.5. Therefore, the

approximate value of the dc output voltage is about (Vs /2), and there is a maximum symmetrical swing at the output. If the amplifier is used with a single-ended supply, a coupling capacitor is required to remove the dc at the output. One end of the input may be left open in the circuit because there is a dc path for the base-bias currents through R5 and R6. This power amplifier comes in a dual-in-line package. The total harmonic distortion is only 0.25% when an output power of 4 W is delivered to an 8-Ω load. If a 5-W power is drawn, the THD increases to 10% because of the saturation of the output transistors. The junction-to-ambient thermal resistance of LM384 is 85EC/W, and the maximum junction temperature should be limited to 150EC. Therefore, if it is operated without a heat sink at a room temperature

Vs (14)

R1 = 25k 0.5 R3 = 25k BYPASS (1) Output (8) 0.5 R2 = 25k 1k 10 pF

-IN (6) +IN (2)

R5 = 150k R6 = 150k GND (3,4,5,10,11,12) GND (7) Fig. 6.6.1: The schematic of the IC power amplifier LM384 (Courtesy of National semiconductor Corporation) +22 V

0.1 µF V I + 500 µF N 8 6 1 10k - 2.7 Ω 3,4,5,7,1 5 µF 8 Ω 0,11,12 0.1 µF

Fig. 6.6.2: A typical application of the IC power amplifier LM384. (Courtesy of National Semiconductor Corporation) of 25EC, the internal power dissipation of the IC should be limited to 1.5 W. With a maximum efficiency of about 70%, the output power should be limited to 1 W. With all the ground points soldered to a total copper foil area of 6 in2 on a printed circuit board, the thermal resistance can be reduced to 35EC/W, which increases the maximum power output capability to 2.5 W. However, with a larger heat-sink, the output power can be as high as 5 W. The type of heat sink to be used is suggested by the manufacturer in the application notes. A typical audio application of LM384 is shown in Fig. 6.6.2.

518 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan Current Boosting The power output from IC power amplifiers may not be sufficient in some applications. Greater output power can be obtained with the use of external power transistors in Class-AB operation driven by IC power amplifiers or operational amplifiers with feedback similar to the circuit shown in Fig. 6.3.6 or a modification of this scheme. This is effectively achieved by increasing the maximum current that can be drawn from the power supply, and this is why the process is called current boosting. LM391 from National Semiconductor is an audio power driver, which is an example of this type of amplifier. It can drive a Class-AB power stage in 10-100 W power amplifier circuits. Its supply voltage can be as high as ±50 V (100 V with a single ended supply). This also comes in dual-in-line package for stereo applications. It has many applications, and the interested readers can find its applications from the manufacturer's data book.

6.7: POWER MOSFETS Power MOSFETs are available from several manufacturers, and they have distinct advantages over the BJTs. Some of them are: 1. The transfer characteristic in the pinch-off mode is linear for currents over a small current range (usually a fraction of an ampere) in some power MOSFETs. This means that the harmonic distortion of the output will be negligible. 2. The breakdown voltages between the drain and source terminals may be as high as 500 V. 3. Power MOSFETs are majority carrier devices. Consequently, switching speeds are high. This enables one to use power MOSFETs in the high frequency applications. 4. Because of the inherent high input impedance at the gate terminal, very small input power is required. Of course, the power gain is extremely high.

5. For low voltage devices, rDS in the ohmic region is very low.

6. In the ohmic mode, rDS has positive temperature coefficient. However, in the pinch-off mode, there is an operating region where the drain current has negative temperature coefficient, and the current becomes self-limited, if the device heats up. 7. Power MOSFETs have extremely low noise figures. Because of the above advantages, power MOSFETs are very popular and are widely used not only in the output stages but also in switching power supplies, motor control, etc. Therefore, in this section, the structures of power MOSFETs will be addressed. MOSFET power amplifiers can be developed by replacing the BJTs with power MOSFETs in most circuits.

The cross-sectional view of the enhancement type MOSFET is shown in Section 4.1 (see Fig. 4.1.1). The structure of Fig. 4.1.1 is not suitable for high current applications. To examine this, consider the equations (4.2.4)-(4.2.8). To increase the current capacity, there should be an increase in the value of KP with an increase in the width and a decrease in the length. Reducing the length results in the reduction of the breakdown voltage between the drain and the source. Therefore, the conventional short-channel devices cannot handle high voltages, which are typical of power circuits. However, with a change in the structure of the MOSFET, it became possible to fabricate short-channel devices (with L . 1 to 2 µm) having high breakdown voltages using double diffusion.

G G S oxide S oxide

n- + n+ n+ n+ n

p p n- n-

n+ n+

D D Fig. 6.7.1: The structure of the V-groove Fig. 6.7.2: The structure of the DMOS. MOSFET with a short vertical channel.

The initial concept used a V-groove MOSFET (VMOS) shown in Fig. 6.7.1. The drain terminal at the bottom has a large area and can be placed in direct contact with the heat sink for removal of the heat dissipated in the device. The fabrication starts with the n+-substrate. The n--epitaxial region is grown on top of the substrate. Then, two diffusions take place, the first with p-type and the second with n-type impurities. The channel length is the vertical length of the p-region. However, the breakdown voltage depends on the thickness and the resistivity of the n-epitaxial region. It is a lightly doped n--region, and therefore, its resistivity is high making it possible to have large breakdown voltages between the drain and source terminals. The breakdown voltages can be many hundreds of volts. The low power MOSFETs described in Chapter 4 are symmetrical between the drain and source, and therefore, they are interchangeable. However, VMOS is unsymmetrical, and the drain and source terminals are not interchangeable. These devices can be

520 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan connected in parallel to increase the current capacity. Due to the nonplanar structure of the VMOS, the cost of manufacturing was high, and for this reason, this structure has been replaced by a vertical planar structure shown in Fig. 6.7.2. Because of the double diffusion, this device is called the DMOS. This device operates in exactly same way as the VMOS. Again, because of the n--epitaxial region, the breakdown voltage between the drain and the source is high for the DMOS. The transfer characteristic of a typical DMOS in the pinch-off mode is shown in Fig. 6.7.3. Note that, for larger currents, iD-vGS characteristic is linear. At higher values of vGS, because of the short channel length, the electric field in the channel becomes high. This causes the velocity of the charge carriers to reach an upper limit (about 6 × 104 m/s for electrons in silicon), known as the velocity saturation. Under this condition in the saturation mode, iD becomes proportional to (vGS - Vt). In this region of operation, an approximate equation for the drain current of a short-channel device is 1 i ' C WU v & V , (5.7.1) D 2 OX sat GS t where Usat is the saturated velocity. gm becomes independent of VGSQ in the linear region and is proportional to the width of the device. This is in contrast to the low power device where gm is proportional to square root of W. Since W is usually large in the high power devices, power MOSFETs have relatively high transconductance values.

Linear

25° C -55° C 100° C

square law 0 vGS Fig. 6.7.3: The transfer characteristics of a typical DMOS in the pinch-off mode at various temperatures.

We observe from the transfer characteristics of Fig. 6.7.3 that there is a value of vGS at which the temperature coefficient of iD is zero. At values of vGS above this point, the temperature coefficient is negative. Therefore, if the MOSFET is operated above the zero temperature coefficient point, the device does not suffer from the thermal runaway because of the self-limiting of the current. However, at low operating currents, the

521 Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan thermal runaway can occur because of the positive temperature coefficient, and therefore, heat sinks are necessary. The third MOSFET structure that has been commercialized in the 1990s is the UMOS, which is similar to VMOS. The name for this structure comes from the U-shaped groove formed in the gate area as opposed V-groove in the VMOS. The fabrication of UMOS is also similar to that of VMOS. However, UMOS has higher channel density than either of VMOS and DMOS, which causes a considerable reduction in the on-resistance of the channel, which is in the order of 0.05 µΩ&m 2 . Siliconix has lately introduced power MOSFETs based on UMOS technology with an on-resistance of 0.01 µΩ-m2.

6.8: CONCLUSIONS In this chapter, we discussed several types of power amplifiers, which are usually the output stages in amplifier configurations. The detailed analyses of Class-A, B, and -AB power amplifiers were provided. In most practical applications, the Class-B or Class-AB power amplifiers are used at the output stage because of their high efficiencies. The distortion of the output signal is also of concern in power amplifiers, and in a good high fidelity system, the THD should be less than 1%. Therefore, except in the inexpensive circuits, Class-AB is preferred as a compromise between high fidelity and high efficiency. We also addressed the power dissipation in the transistors along with the related thermal considerations with illustrative examples in this chapter. Low power IC monolithic power amplifiers are available from many manufacturers. We discussed some IC power amplifiers in Section 6.6.

BIBLIOGRAPHY 1. B. Jayant Baliga, Power Semiconductor Devices, PWS Publishing Company, Boston, MA, 1996.

PROBLEMS SECTION 6.1

6.1. In Fig 6.1.1(a), assume that ICQ = 10 mA, and Im = 5 mA. What is the average power dissipated by

iC(t) in a 1-kΩ resistor?

6.2. Repeat Problem 6.1, if ICQ = 5 mA, and Im = 5 mA.

6.3. In Fig. 6.1.1(b), if Im = 5 mA, what is the average power dissipated by iC(t) in a 1-kΩ resistor?

6.4. In Fig 6.1.1(c), if ICQ = 0.5 mA, and Im = 5 mA, what is the average power dissipated by iC(t) in a 1- kΩ resistor?

6.5. In Fig. 6.1.1(b), assume that the waveform of iC(t) is triangular with a peak value of Im = 5 mA. What

is the average power dissipated by iC(t) in a 1-kΩ resistor? SECTION 6.2

6.6. In the circuit of Fig. 6.2.1, VCC = VEE = 9 V, R = RL = 1 kΩ. All the transistors are identical. Assume

that VBE = 0.7 V, VCES . 0.3 V, and α . 1. What are the upper and lower limits of the output signal and the corresponding inputs, if there should be no distortion due to saturation?

6.7. Repeat Problem 6.6, if the junction area of Q3 is (a) half the junction areas of Q1 and Q2; (b) twice

the junction areas of Q1 and Q2. 6.8. Repeat Problem 6.6, if all the parameters remain the same except that R = 2 kΩ. 6.9. Find the efficiency in Problem 6.6 including the power loss in R. Also find the power dissipation ratings for the transistors. Assume that (a) the output is a sinusoid with an amplitude of 5 V and (b) the output is a symmetrical triangular waveform having a peak-to-peak value of 10 V with a zero average value. 6.10. Repeat Problem 6.9 if the output is a symmetrical square wave with an amplitude of 5 V and a zero average. 6.11. The circuit shown in Fig. P6.11 uses a depletion-type MOSFET to realize the constant-current

source. Assume that VCC = VSS = 9 V, VBE = 0.7 V, and VCES = 0.3 V for the BJT. The MOSFET has

2 K = 10 mA/V and Vt = -2 V. (a) In the linear range of operation, what is the range of output

voltages obtained with RL = 4. (b) Repeat (a) if RL = 1 kΩ. (c) What is the smallest value of RL, if the output should be an undistorted sinusoidal signal? What is the corresponding efficiency?

+VCC Q1 +vI

+vO +5 V M1 iD +vI iL RL M2 +vO

M2 iL -3 V RL = 10 kΩ

-VSS -5 V Fig. P6.11. Fig. P6.12.

2 6.12. The n-channel MOSFETs in the Class-A amplifier of Fig. P6.12 have (µnCOX) = 51.17 µA/V , Vtn =

-1 1/2 0.7339 V, λn = 0.03122 V , γn = 0.4823 V , and (2φf) = 0.7 V. The aspect ratios are (W/L)1 = (20/2)

and (W/L)2 = (80/2). Assuming that M1 can be driven by an input vI ranging from +1 V to +5 V, find the peak-to-peak output signal. D6.13. In the circuit of Fig. 6.2.1, it is desired to have an undistorted sinusoidal output with a minimum

amplitude of 8.5 V. Assume that all BJTs are identical with VBE = 0.7 V and VCES = 0.3 V. Select the

power supply voltage and the value of R to establish the appropriate bias current I, if RL = 1 kΩ. Determine the efficiency of your design including the power dissipation in R, if the output is a sinusoidal signal with an amplitude of 8.5 V. Also obtain the power dissipation ratings for the transistors.

D6.14. RL = 100 Ω, a = (n1/n2) = 3, and vO(t) is a sinusoidal signal having an amplitude of 3 V in the circuit

of Fig. 6.2.3(a). Find the required dc bias current ICQ. Obtain the values of RB1 and RB2 to establish

this bias current. Find the efficiency of your design including the losses in RB1 and RB2.

6.15. A power transistor operating at an ambient temperature of 50EC has a thermal resistance θJA of 1EC/W and dissipates 50 W. What is the junction temperature? 6.16. A 100-W power transistor has its maximum junction temperature of 150EC. Its thermal resistance

θJC is 1.5EC/W. If the case temperature should not exceed 50EC, what is the maximum power dissipation allowed? If its power dissipation is reduced to half the level, what could be the maximum case temperature?

D6.17. A power transistor has TJmax = 150EC and θJC = 1.5EC/W. It operates with a heat sink for which θCS

= 0.5EC/W and θSA = 1EC/W for each cm of heat sink length. The overall θSA is inversely proportional

to the heat sink length. For example, if the heat sink length is 10 cm, then θSA = 0.1EC/W. If the transistor dissipates 50 W, the ambient temperature should not exceed 25EC. What should be length of the heat sink? If the heat sink length is doubled, how much increase can we achieve in the power dissipation level for the same ambient temperature? SECTION 6.3

6.18. If VCC = 15 V, RL = 100 Ω, and vO(t) is a sinusoidal signal with an amplitude of 15 V in the circuit of Fig. 6.3.1, find the load power and the power drawn from the power supplies. Determine the efficiency and the power dissipation ratings for the transistors.

6.19. Repeat Problem 6.18, if vO(t) = 10sin(ωt). D6.20. Design the circuit of Fig. 6.3.1 to deliver an output power of 50 W into a 4-Ω load, if the output signal is a sinusoid. The power supply voltage should be at least 2 V more than the peak amplitude of the sinusoid to avoid distortion due to saturation. Find the requirement of the dc power supply. Determine the peak current through the transistors, power dissipation ratings for the transistor, and

the efficiency of your design. 6.21. In the circuit of Fig. 6.3.1, if the output is a symmetrical triangular waveform with a peak to peak

value of 2Vm and zero average, find the load power, supply power, and the maximum attainable

efficiency. For what value of Vm, will the power dissipation in the BJTs reach maximum? What is the efficiency of the circuit under this condition?

6.22. In Problem 6.18, assume that Vγ = 0.7 V. Find the amplitude of the fundamental component and the percentage of THD.

6.23. If Ad = 1000 and Vγ = 0.7 V in the circuit of Fig. 6.3.6, sketch the transfer characteristic. Assume that

the output saturates at VCC.

6.24. In the Class-B amplifier using MOSFETs shown in Fig. P6.24, VDD = VSS = 5 V. The fundamental parameters of the MOSFETs are the same as those in Example 6.7. Find the transfer characteristics

if (a) RL = 4 and (b) RL = 1 kΩ. Are they linear? Identify the dead zone. Verify your results using PSPICE simulation. SECTION 6.4

D6.25. IBIAS = 0.1 mA in the circuit of Fig. 6.4.1. If the output resistance seen by the load should be less than 10 Ω, what should be the minimum value of n?

D6.26. VCC = 15 V, IBIAS = 0.5 mA, n = 2, RL = 100 Ω, VA1 = 100 V, and βQ1 = 100 in the circuit of Fig. 6.4.1.

(a) What is the value of ICQ? (b) What are the maximum positive and negative output signal levels

without saturation being reached? (c) What is minimum value of IBIAS to achieve equal values for positive and negative peaks? (d) Repeat (c), if the current through the diodes should be at least 1 mA.

D6.27. The Class-AB power amplifier of Fig. 6.4.1 should deliver 50 W output into a load of RL = 4 Ω. n = 3 and the output is sinusoidal. The power supply voltage should be at least 2 V more than the

peak amplitude of the sinusoid. The diode current should be at least 1 mA. VA1, and βQ1 = 50. Find

the power supply requirement and the value of IBIAS. Determine the efficiency of your design and the power dissipation ratings of the transistors.

6.28. In the circuit of Fig. 6.4.4, R1 = R2 = 1 kΩ, VCC = 15 V, and RL = 100 Ω. VBE3 = 0.6 V @ IC3 = 1 mA.

Similarly, VBE1 = 0.6 V @ IC1 = 100 mA. βQ1 = 100. Q1 and Q2 are matched. What is the minimum

value of IBIAS for a maximum output signal?

D6.29. In the circuit of Fig. 6.4.6, R1=R2=1 kΩ, VCC = 15 V, IBIAS = 4 mA, and RL = 100 Ω. The transistors,

Q3, Q4, and Q5 have β 6 4. In these transistors, VBE = 0.6 V @ IC = 1 mA. The output transistors Q1

and Q2 have β = 100. If the load current exceeds 150 mA, the power transistors Q1 and Q2 should shut

down. Find the required values for R3 and R4. Verify your design using PSPICE simulation.

+VDD M1 1 Ro i gm1 + gm2 o +vI +vO + + i + 1 L RL v i 1×vi (ro12ro2) vo RL - gmb1 + gmb2 M 2 iD2 - -

-VSS Fig. P6.24. Fig. P6.30.

SECTION 6.5 D6.30. Assuming the diode-connected MOSFETs to be short-circuits in the circuit of Fig. 6.5.1, show that the small-signal equivalent circuit of Fig. P6.30 can be used to find the primary parameters, such as the voltage gain, of this Class-AB amplifier. Find the voltage gain and the output resistance in the design Example 6.7.

2 -1 6.31. The n-channel MOSFETs in the circuit of Fig. 6.5.1 have KP = 50 µA/V , Vt = 1 V, λn = 0.025 V ,

1/2 2 and γn = 0.5 V . The parameters of the p-channel MOSFETs are: KP = 17 µA/V , Vt = -1 V, λp =

-1 1/2 0.03 V , and γn = 0.6 V . (2φf) = 0.7 V in both cases. While all MOSFETs have the same length,

M1 and M2 have 20-times the width of M3 and M4 respectively. RL = 1 kΩ. It is desired to establish

IDQ1 = IDQ2 = 4 mA. Ro should be less than 100 Ω for small signals. What should be the value of IBIAS? Find the aspect ratios of the transistors. Verify your design using PSPICE simulation.

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