DOCSLIB.ORG

Lecture 7: Static and Pass Transistor Logic

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

EE241 - Spring 2005 Advanced Digital Integrated Circuits Lecture 7: Logic Families for Performance Admin Homeworks due on We. New assignment on your way. Will get feedback on the projects within a week. 2 1 Logical Effort: Summary Stage Path Logical Effort g = G ∏gi Electrical Effort (Fanout) f = C /C = out in F Cout /Cin = Branching Effort n/a B ∏ bi Effort h = fg H = FGB Effort Delay h = DH ∑ hi Number of Stages 1 N Intrinsic Delay p = P ∑ pi Delay d = h + p D = DH + P 3 Increasing Performance Scaling technology Circuit/logic level: 1. Logic optimizations 2. Transistor sizing, buffering 3. Wire optimization, repeaters 4. Supply voltage 5. Threshold voltage 6. Logic styles 7. Timing, latches Microarchitecture level 4 2 Design Techniques Performance does not come for free Design Dynamic custom Effort Custom design Structured ASIC ‘Enhanced’ ASIC ASIC/RTL Performance 5 RTL Design Flow HDL RTL Manual Module Synthesis Design Generators a 0 d netlist q Library b 1 s clk logic optimization a 0 d q netlist b 1 s clk physical design layout [from K. Keutzer] 6 3 RTL/ASIC Design Design description in Verilog/VHDL RTL Synthesized logic Standard cells Pre-defined macros Static timing verification, pre- and post-layout Statistical vs. extracted wire loads Physical design Top-level floorplan Automatic place and route Clock tree synthesized Post layout optimization, verification 7 Logic Optimization a 0 d q netlist b 1 Perform a variety of s clk transformations and optimizations logic Structural graph transformations Library optimization Boolean transformations Mapping into a physical library a 0 d q 1 netlist b s clk smaller, faster less power [from K. Keutzer] 8 4 Combinational Logic Optimization Input: • Initial Boolean network • Timing characterization for the module - input arrival times and drive factors - output loading factors • Optimization goals - output required times • Target library description Output: • Minimum-area netlist of library gates which meets timing constraints A very difficult optimization problem ! [from K. Keutzer] 9 Logic Optimization 2-level Logic opt netlist tech multilevel independent Logic opt logic Library optimization tech dependent Generic Library netlist Real Library [from K. Keutzer] 10 5 Modern Approach to Logic Optimization Divide logic optimization into two subproblems: • Technology-independent optimization - determine overall logic structure - estimate costs (mostly) independent of technology - simplified cost modeling • Technology-dependent optimization (technology mapping) - binding onto the gates in the library - detailed technology-specific cost model Orchestration of various optimization/transformation techniques for each subproblem 11 Logic Level Optimizations Logic Depth or Techniques: Restructuring, pipelining, retiming, technology mapping R R Well covered by today’s logic and sequential synthesis 12 6 Logic Optimizations (2) Late arriving Fanout Tp = O(FO) also effects wiring capacitance Technique: Removal of common sub-expression Start from tree structure/output 13 Technology mapping 4.0 Fanin tpHL 3.0 2 Tp = O(FI ) ! 2.0 quadratic tp Observation: only true if FI (nsec) p t translates in series devices - 1.0 t otherwise linear linear pLH e.g. NAND pull-down 0.0 13579 NOR pull-up fan-in AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4) 14 7 Technology Mapping for Performance Alternative coverings Use low FI modules on critical path(s) Library composition? 15 CMOS Logic Styles CMOS tradeoffs: Speed Power (energy) Area Design tradeoffs Robustness, scalability Design time Many styles: don’t try to remember the names – remember the principles Changing the logic style – can it be done without breaking the synthesis flow? 16 8 CMOS Logic Styles Complementary VDD Pass Transistor Logic A B PUN C A B LOGIC OUT OUT C NETWORK A B PDN C simple and fast GND not always very efficient versatile robust scales large and slow 17 CMOS Logic Styles Ratioed Logic Dynamic Logic VDD VDD φ LOAD Out GND OUT CL In1 In2 PDN A B RPDN << In C PDN 3 RLOAD φ GND small & fast Small & fastest! static power Noise issues Scales? 18 9 Others Current-mode logic Adiabatic logic 19 Pulsed Static CMOS RH – Reset high RL – Reset low Fast pull-up Fast pull-down Chen, Ditlow, US Pat. 5,495,188 Feb. 1996. 20 10 PS-CMOS Evaluation and reset waves: reset is 1.5x slower 21 PS-CMOS Advantages: No dynamic nodes – good noise immunity Reset delay slower than evaluation No data dependent delay (worst case gets better) No false transitions Disadvantages Width of reset wave limits logic depth Margin in design 22 11 Skewing Gates Different rising and falling delays W W LE = 23 Skewing Gates 4W W LE = 24 12 Ratioed Logic VDD VDD VDD Resistive Depletion PMOS Load RL Load VT < 0 Load VSS F F F In1 In1 In1 In2 PDN In2 PDN In2 PDN In3 In3 In3 VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS 25 Pseudo-NMOS 3.0 VDD 2.5 PMOS load 2.0 W/Lp = 4 F 1.5 , V W/Lp = 2 out 1.0 In1 V In W/L = 0.5 2 PDN p W/Lp = 1 0.5 In3 W/Lp = .25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin , V Trade-off between performance and power + noise margins 26 13 Differential Logic 27 Differential Logic Differential Cascode Voltage Switch (DCVS) Differential Split-Level Logic (DSL) Regenerative Push-Pull Cascode Logic (PPCL) Pass transistor logic families Dynamic logic families 28 14 Differential Logic + implicit invert, higher logic density 29 Cascode Voltage Switch Logic VDD VDD M1 M2 Out Out A A B PDN1 PDN2 B VSS VSS Cascode Voltage Switch Logic (CVSL) Sometimes called Differential Cascode Voltage Switch Logic (DCVSL) 30 15 CVSL VDD -Vth 2. 5 Out Out Out 1. 5 Out A M 1 M M A,B A 3 B 4 Voltage,V 0. 5 A, B B M2 -0.5 0 0.2 0.4 0.6 0.8 1.0 Time, ns Fast (but hysteresis due to latch function) No static power dissipation BUT: large cross-over current! 31 CVSL Full adder design How to design for reduced transistor count? 32 16 Karnaugh Map Technique 33 Karnaugh Map Technique x2x3 00 01 11 10 x1 0 0 001 1 0 111 LOAD LOAD Q Q Q Q Build shared x1 x1 x1 x1 cubes first! x1 x2 x2 x2 x2 x2 Add other cubes next x3 x3 x3 x3 34 17 Example Q = x1x2x3x4 + x1(x2+x3+x4) 35 Push-Pull Cascode Logic Gieseke et al, U.S. Patent 5,023,480 June 1991. 36 18 DSL Differential Split-Level Logic 37 Simulation Results for Different Adders 38 19 Pass-Transistor Logic B Switch Out A ts Out u p n Network B I B • N transistors • No static consumption B A • Transistor implementation B F = AB using NMOS 0 39 Pass-Transistor Logic Performance of PTL: Advantage over CMOS in implementing XOR, MUX Disadvantage in implementing AND, OR. Datapaths, arithmetic circuits are examples of use: Adders and multipliers use XOR, MUX Advantage of complementary implementation Comparisons: When a new logic family is introduced, the examples are chosen to show its advantages; (not disadvantages). Comparison papers sometimes point to the disadvantages Full-custom design 40 20 Examples of PTL Styles Complementary Pass-Transistor Logic NMOS-only pass-transistor network Transmission-gate logic NMOS+PMOS pass gates Double Pass-Transistor Logic NMOS+PMOS network Numerous other logic families 41 NMOS-only switch 3.0 In C =2.5V C =2.5 V Out 2.0 M2 x A =2.5V A =2.5 V B Mn B V Voltage, 1.0 CL M1 0.000.511.52 Time, ns Threshold voltage loss causes static power consumption 42 21 Solutions Transmission gates – adding complexity Low-threshold switches – leakage! Level-restoration V DD Level Restorer V DD M r B M 2 X A M n Out M 1 43 Single-Ended Level Restoring Level Restoration Transistor Output Inverter Input Output Feedback Inverter 44 22 Differential Level Restoring f f Differential NMOS Logic Tree Inputs Inputs Different level restoration leads to different logic families 45 Different Restoration Schemes Swing-Restored Pass-Transistor Logic f f Differential NMOS Logic Tree Inputs Parameswar, et al Inputs CICC’94, JSSC 6/96 46 23 Other Level-Restoring Schemes f f f f Differential NMOS Logic Tree Differential NMOS Logic Tree Inputs Inputs Inputs Inputs Energy Economized Pass-Transistor DCVS with Pass Gates Logic (DCVS-PG) 47 Pass-Transistor Logic Families 48 24 Complementary Pass-Transistor Logic (CPL) A Pass-Transistor A B Network F B A Complementary A Pass-Transistor F B Network B • Complementary functions • Reduced number of logic levels • Less transistors than CMOS • Fast – reduced load • Complementary inputs – complementary outputs • VT drop – several solutions 49 CPL Level restoration Yano et al, CICC’89, JSSC 4/90 50 25 CPL Same topology of networks Just different signal arrangements 51 Complementary Pass-Transistor Logic (CPL) A A A A B nFET logic n1 n2 B B network n3 n4 B -Fast C - V drop T C - Efficient QQb S S (a) (b) implementation S S of arithmetic XOR Sum 52 26 CPL Karnaugh Maps B A B A C 2 C1 C2 C 0 0 1 A A B 0 1 A A C1 C2 A⋅ B A⋅ B 53 CPL vs. CMOS 54 27 Skewing Output Inverter 55 Differential vs. Single-Ended 56 28 Leap Cell Library Yano et al, CICC’94, JSSC 6/96 Goal: Implement full logic functionality with small library Rely on automated design methodology 57 Various Logic Functions of the Leap Library 58 29 LEAP Comparison 59 Double Pass-Transistor Logic (DPL) VDD A B B A AND/NAND A B B B A A O O A B A B A B A B A B B A XOR/XNOR A B B A A B O O 60 30 Designing DPL Gates B A A C4 C2 C A B 0 0 1 A×B B 0 1 C 2 A B C1 C3 C4 C3 61 Designing DPL Gates (2) A A C C A 1 2 B B C 0 1 2 AÅ B 1 0 A A B C C C1 4 3 B B C C 3 A 4 A A C2 C C3 4 0 1 B B B 1 0 AÅ B C4 B B C C3 C1 C2 1 A A 62 31 Applications of DPL Full adder: 1.5ns 32-bit ALU in 0.25µm CMOS Suzuki, ISSCC’93 JSSC 11/93 63 Comparison of Logic Styles Zimmermann, Fichtner, JSSC 7/97 64 32 Comparison of Logic Styles 65 Comparison of Logic Styles 66 33 Results 67 Results 68 34 Results 69 35.
Recommended publications
  • Optimization of Combinational Logic Circuits Based on Compatible Gates

    Optimization of Combinational Logic Circuits Based on Compatible Gates

    COMPUTER SYSTEMS LABORATORY STANFORD UNIVERSITY STANFORD, CA 94305455 Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani Jerry Chih-Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September 1993 This research is sponsored by NSF and DEC under a PYI award and by ARPA and NSF under contract MIP 9115432. Optimization of Combinational Logic Circuits Based on Compatible Gates Maurizio Damiani * Jerry Chih- Yuan Yang Giovanni De Micheli Technical Report: CSL-TR-93-584 September, 1993 Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University, Stanford CA 94305-4055 Abstract This paper presents a set of new techniques for the optimization of multiple-level combinational Boolean networks. We describe first a technique based upon the selection of appropriate multiple- output subnetworks (consisting of so-called compatible gates) whose local functions can be op- timized simultaneously. We then generalize the method to larger and more arbitrary subsets of gates. Because simultaneous optimization of local functions can take place, our methods are more powerful and general than Boolean optimization methods using don’t cares , where only single-gate optimization can be performed. In addition, our methods represent a more efficient alternative to optimization procedures based on Boolean relations because the problem can be modeled by a unate covering problem instead of the more difficult binate covering problem. The method is implemented in program ACHILLES and compares favorably to SIS. Key Words and Phrases: Combinational logic synthesis, don’t care methods. *Now with the Dipartimento di Elettronica ed Informatica, UniversitB di Padova, Via Gradenigo 6/A, Padova, Italy.
  • Logic Optimization and Synthesis: Trends and Directions in Industry

    Logic Optimization and Synthesis: Trends and Directions in Industry

    Logic Optimization and Synthesis: Trends and Directions in Industry Luca Amaru´∗, Patrick Vuillod†, Jiong Luo∗, Janet Olson∗ ∗ Synopsys Inc., Design Group, Sunnyvale, California, USA † Synopsys Inc., Design Group, Grenoble, France Abstract—Logic synthesis is a key design step which optimizes of specific logic styles and cell layouts. Embedding as much abstract circuit representations and links them to technology. technology information as possible early in the logic optimiza- With CMOS technology moving into the deep nanometer regime, tion engine is key to make advantageous logic restructuring logic synthesis needs to be aware of physical informations early in the flow. With the rise of enhanced functionality nanodevices, opportunities carry over at the end of the design flow. research on technology needs the help of logic synthesis to capture In this paper, we examine the synergy between logic synthe- advantageous design opportunities. This paper deals with the syn- sis and technology, from an industrial perspective. We present ergy between logic synthesis and technology, from an industrial technology aware synthesis methods incorporating advanced perspective. First, we present new synthesis techniques which physical information at the core optimization engine. Internal embed detailed physical informations at the core optimization engine. Experiments show improved Quality of Results (QoR) and results evidence faster timing closure and better correlation better correlation between RTL synthesis and physical implemen- between RTL synthesis and physical implementation. We elab- tation. Second, we discuss the application of these new synthesis orate on synthesis aware technology development, where logic techniques in the early assessment of emerging nanodevices with synthesis enables a fair system-level assessment on emerging enhanced functionality.
  • Basic Boolean Algebra and Logic Optimization

    Basic Boolean Algebra and Logic Optimization

    Fundamental Algorithms for System Modeling, Analysis, and Optimization Edward A. Lee, Jaijeet Roychowdhury, Sanjit A. Seshia UC Berkeley EECS 144/244 Fall 2011 Copyright © 2010-11, E. A. Lee, J. Roychowdhury, S. A. Seshia, All rights reserved Lec 3: Boolean Algebra and Logic Optimization - 1 Thanks to S. Devadas, K. Keutzer, S. Malik, R. Rutenbar for several slides RTL Synthesis Flow FSM, HDL Verilog, HDL Simulation/ VHDL Verification RTL Synthesis a 0 d q Boolean circuit/network 1 netlist b Library/ s clk module logic generators optimization a 0 d q Boolean circuit/network netlist b 1 s clk physical design Graph / Rectangles layout K. Keutzer EECS 144/244, UC Berkeley: 2 Reduce Sequential Ckt Optimization to Combinational Optimization B Flip-flops inputs Combinational outputs Logic Optimize the size/delay/etc. of the combinational circuit (viewed as a Boolean network) EECS 144/244, UC Berkeley: 3 Logic Optimization 2-level Logic opt netlist tech multilevel independent Logic opt logic Library optimization tech dependent Generic Library netlist Real Library EECS 144/244, UC Berkeley: 4 Outline of Topics Basics of Boolean algebra Two-level logic optimization Multi-level logic optimization Boolean function representation: BDDs EECS 144/244, UC Berkeley: 5 Definitions – 1: What is a Boolean function? EECS 144/244, UC Berkeley: 6 Definitions – 1: What is a Boolean function? Let B = {0, 1} and Y = {0, 1} Input variables: X1, X2 …Xn Output variables: Y1, Y2 …Ym A logic function ff (or ‘Boolean’ function, switching function) in n inputs and m
  • The Basics of Logic Design

    The Basics of Logic Design

    C APPENDIX The Basics of Logic Design C.1 Introduction C-3 I always loved that C.2 Gates, Truth Tables, and Logic word, Boolean. Equations C-4 C.3 Combinational Logic C-9 Claude Shannon C.4 Using a Hardware Description IEEE Spectrum, April 1992 Language (Shannon’s master’s thesis showed that C-20 the algebra invented by George Boole in C.5 Constructing a Basic Arithmetic Logic the 1800s could represent the workings of Unit C-26 electrical switches.) C.6 Faster Addition: Carry Lookahead C-38 C.7 Clocks C-48 AAppendixC-9780123747501.inddppendixC-9780123747501.indd 2 226/07/116/07/11 66:28:28 PPMM C.8 Memory Elements: Flip-Flops, Latches, and Registers C-50 C.9 Memory Elements: SRAMs and DRAMs C-58 C.10 Finite-State Machines C-67 C.11 Timing Methodologies C-72 C.12 Field Programmable Devices C-78 C.13 Concluding Remarks C-79 C.14 Exercises C-80 C.1 Introduction This appendix provides a brief discussion of the basics of logic design. It does not replace a course in logic design, nor will it enable you to design signifi cant working logic systems. If you have little or no exposure to logic design, however, this appendix will provide suffi cient background to understand all the material in this book. In addition, if you are looking to understand some of the motivation behind how computers are implemented, this material will serve as a useful intro- duction. If your curiosity is aroused but not sated by this appendix, the references at the end provide several additional sources of information.
  • Gate Logic Logic Optimization Overview

    Gate Logic Logic Optimization Overview

    Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim - Think about transistors as switches - Build collections of switches that do useful stuff - Don’t much care whether the collection of transistors is a gate, switch logic, or some combination. It is a collection of switches. But this is pretty complicated - Switches are bidirectional, charge-sharing, - Need to worry about series resistance… MAH, AEN EE271 Lecture 5 2 Logic Gates Constrain the problem to simplify it. • Constrain how one can connect transistors - Create a collection of transistors where the Output is always driven by a switch-network to a supply (not an input) And the inputs to this unit only connect the gate of the transistors • Model this collection of transistors by a simpler abstraction Units are unidirectional Function is modelled by boolean operations Capacitance only affects speed and not functionality Delay through network is sum of delays of elements This abstract model is one we have used already. • It is a logic gate MAH, AEN EE271 Lecture 5 3 Logic Gates Come in various forms and sizes In CMOS, all of the primitive gates1 have one inversion from each input to the output. There are many versions of primitive gates. Different libraries have different collections. In general, most libraries have all 3 input gates (NAND, NOR, AOI, and OAI gates) and some 4 input gates. Most libraries are much richer, and have a large number of gates.
  • Deep Learning for Logic Optimization Algorithms

    Deep Learning for Logic Optimization Algorithms

    Deep Learning for Logic Optimization Algorithms Winston Haaswijky∗, Edo Collinsz∗, Benoit Seguinx∗, Mathias Soekeny, Fred´ eric´ Kaplanx, Sabine Susstrunk¨ z, Giovanni De Micheliy yIntegrated Systems Laboratory, EPFL, Lausanne, VD, Switzerland zImage and Visual Representation Lab, EPFL, Lausanne, VD, Switzerland xDigital Humanities Laboratory, EPFL, Lausanne, VD, Switzerland ∗These authors contributed equally to this work Abstract—The slowing down of Moore’s law and the emergence to the state-of-the-art. Finally, our algorithm is a generic of new technologies puts an increasing pressure on the field optimization method. We show that it is capable of performing of EDA. There is a constant need to improve optimization depth optimization, obtaining 92.6% of potential improvement algorithms. However, finding and implementing such algorithms is a difficult task, especially with the novel logic primitives and in depth optimization of 3-input functions. Further, the MCNC potentially unconventional requirements of emerging technolo- case study shows that we unlock significant depth improvements gies. In this paper, we cast logic optimization as a deterministic over the academic state-of-the-art, ranging from 12.5% to Markov decision process (MDP). We then take advantage of 47.4%. recent advances in deep reinforcement learning to build a system that learns how to navigate this process. Our design has a II. BACKGROUND number of desirable properties. It is autonomous because it learns automatically and does not require human intervention. A. Deep Learning It generalizes to large functions after training on small examples. With ever growing data sets and increasing computational Additionally, it intrinsically supports both single- and multi- output functions, without the need to handle special cases.
  • Logic Gates, Truth Tables and Canonical Forms

    Logic Gates, Truth Tables and Canonical Forms

    Lecture 4 The “WHY” slide ◆ Logistics ◆ Logic Gates and Truth Tables ■ HW1 due Wednesday at start of class ■ Now you know 0’s and 1’s and the basic Boolean algebra, now you ■ Office Hours: are ready to go back and forth between truth table, Boolean µ Me: 12:20-1:00 CSE 668 plus one later this week expression, and logic gates. This ability to go back and forth is an µ TAs: Today at 3:30, tomorrow at 12:30 & 2:30 in CSE 220 extremely useful skill designing and optimizing computer hardware. ■ Lab2 going on this week ◆ Implementing Logic Functions ◆ Last lecture --- Boolean algebra ■ Now with these basic tools you learned, you can “implement” logic ■ Axioms functions. We use Boolean algebra to implement logic functions that ■ Useful laws and theorems are used in the computers. And these logic functions are used by ■ Simplifying Boolean expressions computer programs you write. ◆ Today’s lecture ◆ Canonical forms ■ Logic gates and truth tables in detail ■ There are many forms to expression one Boolean function. It is ■ Implementing logic functions good to have one standard way. A canonical form is the standard ■ Canonical forms form for Boolean expressions. It has a nice property that allows you to go back and forth between truth table/expressions/gates easily. CSE370, Lecture 4 1 CSE370, Lecture 4 2 Logic gates and truth tables Logic gates and truth tables (con’t) XYZ XYZ X 0 0 0 X 0 0 1 ◆ Z ◆ NAND • Z AND X•Y XY Y 0 1 0 X Y XY Y 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 XYZ XYZ ◆ + X 0 0 1 NOR X Y Z 0 1 0 ◆ OR X+Y X Z 0 0 0 Y Y 0 1 1 1 0 0 1 1 0 1 0 1
  • Sequential Optimization for Low Power Digital Design

    Sequential Optimization for Low Power Digital Design

    Sequential Optimization for Low Power Digital Design Aaron P. Hurst Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2008-75 http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-75.html May 30, 2008 Copyright © 2008, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement Advisor: Robert Brayton Sequential Optimization for Low Power Digital Design by Aaron Paul Hurst B.S. (Carnegie Mellon University) 2002 M.S. (Carnegie Mellon University) 2002 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science in the GRADUATE DIVISION of the UNIVERSITY OF CALIFORNIA, BERKELEY Committee in charge: Professor Robert K. Brayton, Chair Professor Andreas Kuehlmann Professor Margaret Taylor Spring 2008 The dissertation of Aaron Paul Hurst is approved. Chair Date Date Date University of California, Berkeley Spring 2008 Sequential Optimization for Low Power Digital Design Copyright c 2008 by Aaron Paul Hurst Abstract Sequential Optimization for Low Power Digital Design by Aaron Paul Hurst Doctor of Philosophy in Electrical Engineering and Computer Science University of California, Berkeley Professor Robert K. Brayton, Chair The power consumed by digital integrated circuits has grown with increasing tran- sistor density and system complexity.
  • Synthesis and Optimization of Synchronous Logic Circuits

    Synthesis and Optimization of Synchronous Logic Circuits

    SYNTHESIS AND OPTIMIZATION OF SYNCHRONOUS LOGIC CIRCUITS disserttion sumi ttedtothe deprtmentofeletrilengi neering ndtheommitteeongrdutestudies ofstnforduniversi ty in prtilfulfillmentoftherequirements forthedegreeof dotorofphilosophy By Maurizio Damiani May, 1994 I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Giovanni De Micheli (Principal Adviser) I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. David L. Dill I certify that I have read this thesis and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the degree of Doctor of Philosophy. Teresa Meng Approved for the University Committee on Graduate Stud- ies: Dean of Graduate Studies ii Abstract The design automation of complex digital circuits offers important benefits. It allows the designer to reduce design time and errors, to explore more thoroughly the design space, and to cope effectively with an ever-increasing project complexity. This dissertation presents new algorithms for the logic optimization of combinational and synchronous digital circuits. These algorithms rely on a common paradigm. Namely, global optimization is achieved by the iterative local optimization of small subcircuits. The dissertation first explores the combinational case. Chapter 2 presents algorithms for the optimization of subnetworks consisting of a single-output subcircuit. The design space for this subcircuit is described implicitly by a Boolean function, a so-called don’t care function. Efficient methods for extracting this function are presented.
  • Routing Architectures for Hierarchical Field Programmable Gate Arrays

    Routing Architectures for Hierarchical Field Programmable Gate Arrays

    Routing Architectures for Hierarchical Field Programmable Gate Arrays Aditya A. Aggarwal and David M. Lewis University of Toronto Department of Electrical and Computer Engineering Toronto, Ontario, Canada Abstract architecture to that of a symmetrical FPGA, and holding all other features constant, we hope to clarify the impact of This paper evaluates an architecture that implements a HFPGA architecture in isolation. hierarchical routing structure for FPGAs, called a hierarch- ical FPGA (HFPGA). A set of new tools has been used to The remainder of this paper studies the effect of rout- place and route several circuits on this architecture, with ing architectures in HFPGAs as an independent architec- the goal of comparing the cost of HFPGAs to conventional tural feature. It first defines an architecture for HFPGAs symmetrical FPGAs. The results show that HFF'GAs can with partially populated switch pattems. Experiments are implement circuits with fewer routing switches, and fewer then presented comparing the number of routing switches switches in total, compared to symmetrical FGPAs, required to the number required by a symmetrical FPGA. although they have the potential disadvantage that they Results for the total number of switches and tracks are also may require more logic blocks due to coarser granularity. given. 1. Introduction 2. Architecture and Area Models for HPFGAs Field programmable gate array architecture has been Figs. l(a) and I@) illustrate the components in a the subject of several studies that attempt to evaluate vari- HFPGA. An HFPGA consists of two types of primitive ous logic blocks and routing architectures, with the goals blocks, or level-0 blocks: logic blocks and U0 blocks.
  • Testing and Logic Optimization Techniques for Systems on Chip

    Testing and Logic Optimization Techniques for Systems on Chip

    Linköping Studies in Science and Technology Dissertations. No. 1490 Testing and Logic Optimization Techniques for Systems on Chip by Tomas Bengtsson Department of Computer and Information Science Linköpings universitet SE-581 83 Linköping, Sweden Linköping 2012 Copyright © 2012 Tomas Bengtsson ISBN 978917519-7425 ISSN 03457524 Printed by LiU-Tryck 2012 URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-84806 Abstract Today it is possible to integrate more than one billion transistors onto a single chip. This has enabled implementation of complex functionality in hand held gadgets, but handling such complexity is far from trivial. The challenges of handling this complexity are mostly related to the design and testing of the digital components of these chips. A number of well-researched disciplines must be employed in the efficient design of large and complex chips. These include utilization of several abstraction levels, design of appropriate architectures, several different classes of optimization methods, and development of testing techniques. This thesis contributes mainly to the areas of design optimization and testing methods. In the area of testing this thesis contributes methods for testing of on-chip links connecting different clock domains. This includes testing for defects that introduce unacceptable delay, lead to excessive crosstalk and cause glitches, which can produce errors. We show how pure digital components can be used to detect such defects and how the tests can be scheduled efficiently. To manage increasing test complexity, another contribution proposes to raise the abstraction level of fault models from logic level to system level. A set of system level fault models for a NoC-switch is proposed and evaluated to demonstrate their potential.
  • Lecture 1: Introduction to Digital Logic Design

    Lecture 1: Introduction to Digital Logic Design

    CSE 140, Lecture 2 Combinational Logic CK Cheng CSE Dept. UC San Diego 1 Combinational Logic Outlines 1. Introduction • Scope • Boolean Algebra (Review) • Switching Functions, Logic Diagram and Truth Table • Handy Tools: DeMorgan’s Theorem, Consensus Theorem and Shannon’s Expansion 2. Specification 3. Synthesis 2 1.1 Combinational Logic: Scope • Description – Language: e.g. C Programming, BSV, Verilog, VHDL – Boolean algebra – Truth table: Powerful engineering tool • Design – Schematic Diagram – Inputs, Gates, Nets, Outputs • Goal – Validity: correctness, turnaround time – Performance: power, timing, cost – Testability: yield, diagnosis, robustness 3 Scope: Boolean algebra, switching algebra, logic • Boolean Algebra: multiple-valued logic, i.e. each variable have multiple values. • Switching Algebra: binary logic, i.e. each variable can be either 1 or 0. • Boolean Algebra ≠ Switching Algebra Switching Algebra BB Two Level Logic Boolean Algebra <4> Scope: Switching Algebra (Binary Values) • Typically consider only two discrete values: – 1’s and 0’s – 1, TRUE, HIGH – 0, FALSE, LOW • 1 and 0 can be represented by specific voltage levels, rotating gears, fluid levels, etc. • Digital circuits usually depend on specific voltage levels to represent 1 and 0 • Bit: Binary digit Copyright © 2007 1-<5> 5 Elsevier Scope: Levels of Logic • Multiple Level Logic: Many layers of two level logic with some inverters, e.g. (((a+bc)’+ab’)+b’c+c’d)’bc+c’e (A network of two level logic) • Two Level Logic: Sum of products, or product of sums, e.g. ab + a’c + a’b’, (a’+c )(a+b’)(a+b+c’) Features of Digital Logic Design • Multiple Outputs Boolean Algebra • Don’t care sets Switching Algebra BB Two Level Logic <6> 1.2 George Boole, 1815 - 1864 • Born to working class parents: Son of a shoemaker • Taught himself mathematics and joined the faculty of Queen’s College in Ireland.