Embedded Development

#160 November 2003 www.circuitcellar.com CIRCUIT CELLAR®

THE MAGAZINE FOR COMPUTER APPLICATIONS EMBEDDED DEVELOPMENT

Mixed-Signal Simulator

All-Digital Amplifier

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EDITORIAL DIRECTOR/FOUNDER CHIEF FINANCIAL OFFICER Tools and Techniques of the Trade Steve Ciarcia Jeannette Ciarcia MANAGING EDITOR CUSTOMER SERVICE Jennifer Huber Elaine Johnston TECHNICAL EDITOR ach year, we use the Embedded Development issue to feature the C.J. Abate ACCOUNTANT E Jeff Yanco newest methods and tools used to design hardware and software. This WEST COAST EDITOR month, we have a variety of compelling articles about developing embed- Tom Cantrell ART DIRECTOR KC Prescott ded applications. CONTRIBUTING EDITORS Ingo Cyliax When you’re working with both analog and digital signals, simulation GRAPHIC DESIGNER Fred Eady Mary Turek can get complicated if you have to handle the signals separately. But, what George Martin if you could simultaneously simulate both parts? Engin Ipek and Bruce George Novacek STAFF ENGINEER Jeff Bachiochi Land explain how to build a mixed-signal simulator that you can use to John Gorsky gather analysis for display on a monitor (p. 14). The simulator was origi- NEW PRODUCTS EDITOR nally designed for use with small Atmel AT90S8515-based projects, but the John Gorsky QUIZ COORDINATOR David Tweed source code can be modified to work with multiple processors. PROJECT EDITORS Aubrey Kagan provides a solution to another problem (p. 44). In Steve Bedford Ken Davidson embedded systems, space is often critical. By carefully organizing hierar- David Tweed chal menus, Aubrey devised a way to reuse software for displaying and changing parameters in order to save ROM space. This is especially use- ADVERTISING ful when your client’s requirements change; with a flexible menu, you can PUBLISHER Dan Rodrigues E-mail: [email protected] simply alter the flow of the hierarchy to modify the program. ASSOCIATE PUBLISHER/DIRECTOR OF SALES This month, we’re also showcasing the winners of the Motorola Flash Sean Donnelly Fax: (860) 871-0411 Innovation 2003 Design Contest (p. 22). The contestants worked with the (860) 872-3064 E-mail: [email protected] Cell phone: (860) 930-4326 HC08 Q-Family to develop a number of unique and exciting projects. For those of you who are interested in reading more about the winning ADVERTISING COORDINATOR Valerie Luster Fax: (860) 871-0411 designs, we have posted dozens of abstracts and full entries on our web (860) 875-2199 E-mail: [email protected] site (www.circuitcellar.com/fi2003). ADVERTISING ASSISTANT While you’re on the web site, you should also take the opportunity to Deborah Lavoie Fax: (860) 871-0411 check out the revised Author’s Guide (www.circuitcellar.com/authors). With (860) 875-2199 E-mail: [email protected] the editorial calendar, you will find definitions of our monthly themes and Cover photograph Chris Rakoczy—Rakoczy Photography suggestions for article topics. The issues fill up quickly, so it’s a good idea PRINTED IN THE UNITED STATES to send in your proposals as early as possible. (Note that the deadlines are CONTACTING CIRCUIT CELLAR for final materials. Proposals should be submitted in advance.) SUBSCRIPTIONS: INFORMATION: www.circuitcellar.com or [email protected] To Subscribe: (800) 269-6301, www.circuitcellar.com/subscribe.htm, or 2004 Editorial Calendar [email protected] PROBLEMS: [email protected] GENERAL INFORMATION: Issue Theme Deadline TELEPHONE: (860) 875-2199 Fax: (860) 871-0411 INTERNET: [email protected], [email protected], or www.circuitcellar.com January Analog Techniques October 1 EDITORIAL OFFICES: Editor, Circuit Cellar, 4 Park St., Vernon, CT 06066 February Wireless Communication November 3 NEW PRODUCTS: New Products, Circuit Cellar, 4 Park St., Vernon, CT 06066 [email protected] March Embedded Applications December 1 AUTHOR CONTACT: April Robotics January 2 E-MAIL: Author addresses (when available) are included at the end of each article May Communications February 2 For information on authorized reprints of articles, contact Jeannette Ciarcia (860) 875-2199 or e-mail [email protected]. JuneWWW.GiURUMELE.Hi2.RO Measurement & Sensors March 1 CIRCUIT CELLAR®, THE MAGAZINE FOR COMPUTER APPLICATIONS (ISSN 1528-0608) and Circuit Cellar Online are pub- July Graphics & Video April 1 lished monthly by Circuit Cellar Incorporated, 4 Park Street, Suite 20, Vernon, CT 06066 (860) 875-2751. Periodical rates paid at August Embedded Programming May 3 Vernon, CT and additional offices. One-year (12 issues) subscription rate USA and possessions $21.95, Canada/Mexico $31.95, all other countries $49.95. Two-year (24 issues) subscription rate USA and possessions $39.95, Canada/Mexico September Signal Processing June 1 $55, all other countries $85. All subscription orders payable in U.S. funds only via VISA, MasterCard, international postal money order, or check drawn on U.S. bank. October Data Acquisition July 1 Direct subscription orders and subscription-related questions to Circuit Cellar Subscriptions, P.O. Box 5650, Hanover, NH November Internet & Connectivity August 2 03755-5650 or call (800) 269-6301. Postmaster: Send address changes to Circuit Cellar, Circulation Dept., P.O. Box 5650, Hanover, NH 03755-5650.

December Embedded Development September 1 Circuit Cellar® makes no warranties and assumes no responsibility or liability of any kind for errors in these programs or schematics or for the consequences of any such errors. Furthermore, because of possible variation in the quality and condition of materials and workmanship of reader-assembled projects, Circuit Cellar® disclaims any responsibility for the safe and proper function of reader-assembled projects based upon or from plans, descriptions, or information published by Circuit Cellar®. The information provided by Circuit Cellar® is for educational purposes. Circuit Cellar® makes no claims or warrants that readers have a right to build things based upon these ideas under patent or other relevant intellectual property law in their jurisdiction, or that readers have a right to construct or operate any of the devices described herein under the relevant patent or other intellectual property law of the reader’s jurisdiction. The reader assumes any risk of infringement liability for constructing or operating such devices. Entire contents copyright © 2001 by Circuit Cellar Incorporated. All rights reserved. Circuit Cellar and Circuit Cellar INK are registered trademarks [email protected] of Circuit Cellar Inc. Reproduction of this publication in whole or in part without written consent from Circuit Cellar Inc. is prohibited.

4 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO November 2003: Embedded Development FEATURES

14 Mixed-Signal AVR Simulator 34 Pure Digital Audio Engin Ipek & Bruce Land Build An All-Digital Amplifier Yoon Cho, Joe Huntley, Greg Nuttall, Bryan Olson, & 22 Flash Innovation 2003 Design Contest Winners Derek Richardson, edited by David Tweed Announcement 44 Hierarchical Menus in Embedded Systems 28 Timing (Analysis) is Everything Aubrey Kagan A How-To Guide for Timing Analysis Philip Nowe 56 High-Temperature Superconductor Overview Danny Graves

60 Programming the 386 in 32-Bit Protected Mode Jim Turley

COLUMNS

64 APPLIED PCs 76 SILICON UPDATE RF Made Simple Go Sell the Spartans Fred Eady Tom Cantrell

70 FROM THE BENCH OOPic Eases Programming Headaches Jeff Bachiochi

DEPARTMENTS

4 TASK MANAGER Tools and Techniques of the Trade Jennifer Huber

8 NEW PRODUCT NEWS editedWWW.GiURUMELE.Hi2.RO by John Gorsky 13 TEST YOUR EQ edited by David Tweed 94 INDEX OF ADVERTISERS December Preview

96 PRIORITY INTERRUPT Internet Infamy Steve Ciarcia

6 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com Our AVR microcontroller is probably 12 times faster than the one you’re using now. (It’s also smarter.)

Introducing the Atmel AVR®. An 8-bit MCU that And when you consider that it can help slash months off your can help you beat the pants off your competition. development schedule and save thousands of dollars in project AVR is a RISC CPU running single cycle instructions. cost, it could make you look pretty smart, too. With its rich, CISC-like instruction set and 32 working registers, AVR comes in a wide range of package and performance it has very high code density and searingly fast execution–up to options covering a huge number of consumer and industrial 16 MIPS. That’s 12 times faster than conventional 8-bit micros. applications. And it’s supported by some of the best development We like to think of it as 16-bit performance at an 8-bit price. tools in the business. With up to 128 Kbytes of programmable Flash and EEPROM, So get your project started right. Check out AVR today at AVR is not only up to 12 times faster than the MCU you’re using www.atmel.com/ad/fastavr. Then register to qualify for your free now. It’s probablyWWW.GiURUMELE.Hi2.RO 12 times smarter, too. evaluation kit and bumper sticker. And get ready to take on the world.

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© 2002 Atmel Corporation. Atmel and the Atmel logo are registered trademarks of Atmel Corporation. NEW PRODUCT NEWS Edited by John Gorsky LOW-COST SDK FOR BLUESTREAK ARM9-BASED SoC The LH7A400 Zoom SDK is a complete hardware and 10/100BaseT Ethernet controller. It also includes audio software solution, enabling developers to immediately codec, CompactFlash, and MCU-specific peripherals (e.g., begin developing applications and evaluating the function- an integrated LCD controller, USB client, I2C, ality of the Sharp LH7A400 SoC and Card Engine (embed- PCMCIA/CF, and RTC). ded-computing module). The SDK simplifies development The LH7A400 is a highly integrated general-purpose by providing production quality software (device drivers SoC that’s based on an industry-standard ARM9 core. It’s and bootloader) and binary board support packages for specifically designed to meet the performance, power con- Windows CE and Linux. It also provides optional display sumption, and cost requirements of engineers designing kits that can be immediately connected to the develop- multimedia and mobile handheld applications. The starter ment kit, as well as expansion headers that provide easy kit developed for the BlueStreak LH7A400 SoC is designed access to all of the Card Engine periph- to scale with the OEM’s product erals for application development, proto- roadmap. You can seamlessly plug typing, and debugging. Sharp’s next-generation BlueStreak The compact LH7A400 Card Engine is MCUs and SoCs into the same applica- a product-ready embedded-computing tion board. The Zoom Starter module that offers the essential features Development Kit for Sharp’s BlueStreak for handheld and embedded-networking LH7A400 costs $349. applications in the industrial, consumer, and medial markets. The Card Engine Logic Product Development comes standard with the following hard- (612) 672-9495 ware: an LH7A400 ARM922T SoC run- www.logicpd.com ning at 200 MHz, on-board flash memory (up to 32 MB), SDRAM (up to 64 MB), Sharp Microelectronics a touchscreen controller, and a www.sharpsma.com

MODULAR rfPIC DEVELOPMENT TOOL The rfPIC Development Kit 1 provides you with an easy 433-MHz frequencies. The receiver modules, featuring the way to evaluate low-power RF communication links for rfRXD0420 device, plug directly into the PICkit 1 develop- embedded-control applications based on the rfPIC12F675 ment board for demonstration and development. All of the microcontroller plus an UHF RF transmitter and the design files are available, offering you the ability to rfRXD0420 receiver device. migrate the module design into the application for lower- Designed to work in tandem with the popular PICkit 1 cost volume production. Flash Starter Kit, the rfPIC Development Kit 1 consists of Target applications for the rfPIC family of products transmitter and receiver modules supporting the 315- and include the following: remote control (e.g., home appliances, fan control, light control, and PC peripherals); command and control (e.g., air conditioning thermostats and water irrigation systems); wireless sensors (e.g., temperature, smoke detectors, and water level); home security (e.g., garage door openers and remote infrared sensors); and automotive (e.g., tire pressure sensors, remote control, and remote keyless entry). Available with 315/433-MHz amplitude shift keying, the rfPIC receiver module costs $25. The rfPIC transmitter module costs $30. For $135, you can purchase a kit that WWW.GiURUMELE.Hi2.ROincludes two receivers, two transmitters, and the PICkit 1 Flash Starter Kit.

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STATEMENT REQUIRED BY THE ACT OF AUGUST 12, 1970, TITLE 39, UNITED STATES CODE SHOWING THE OWNERSHIP, MANAGEMENT AND CIRCULATION OF CIRCUIT CELLAR, THE MAGAZINE FOR COMPUTER APPLICATIONS, published monthly at 4 Park Street, Vernon, CT 06066. Annual subscription price is $21.95. The names and addresses of the Publisher, Editorial Director, and Managing Editor are: Publisher, Daniel Rodrigues, 4 Park Street, Vernon, CT 06066; Editorial Director, Steven Ciarcia, 4 Park Street, Vernon, CT 06066; Managing Editor, Jennifer Huber, 4 Park Street, Vernon, CT 06066. The owner is Circuit Cellar, Inc., Vernon, CT 06066. The names and addresses of stockholders holding one percent or more of the total amount of stock are: Steven Ciarcia, 4 Park Street, Vernon, CT 06066. The average number of copies of each issue during the preceding twelve months is: A) Total number of copies printed (net press run) 24,890; B) Paid/Requested Circulation (1) Mail subscriptions: 13,908; (3) Sales through dealers and carriers, street vendors and counter sales: 5,871 C) Total paid circulation: 19,779; D) Free distribution by mail (samples, and other free issues): 208; E) Free distribution outside the mail (carrier, or other means): 763; F) Total free distribution: 971; G) Total Distribution: 20,750; H) Copies not distributed: (1) Office use leftover, estimated newsstand returns, spoiled after printing: 4,140; I) Total: 24,890. Percent paid and/or requested circulation: 95.32%. Actual number of copies of the single issue published nearest to filing date is October 2003, Issue #159; A) Total number of copies printed (net press run) 24,040; B) Paid/Requested Circulation (1) Mail subscriptions: 12,040; (3) Sales through dealers and carriers, street vendors and counter sales: 6,648; C) Total paid circulation: 18,688; D) Free distribution by mail (samples, and other free issues): 211; E) Free distribution outside the mail (carrier, or other means): 861; F) Total free distribution: 1,072; G) Total Distribution: 19,760; H) Copies not distributed: (1) Office use leftover, estimated newsstand returns, spoiled after printing: 4,280; I) Total: 24,040. Percent paid and/or requested circulation: 94.58%. I certify that the statements made by me above are correct and complete. Daniel Rodrigues, Publisher.

8 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO NEW PRODUCT NEWS NIOS DEVELOPMENT KIT The Nios Development Kit (Stratix Professional able user-defined I/O pins), a power supply, and a Edition) features the largest FPGA available in a Nios ByteBlaster II download cable. The Nios processor also development kit, greater on-chip memory, increased contains the enhanced on-chip instrumentation (OCI) debug features, and newly bundled debugging software. core and software provided by First Silicon Solutions The kit’s Stratix FPGA provides resources to support the (FS2) for real-time software debugging. development of complex, high-performance designs, and The development kit includes the Quartus II design the increased debug features and bundled software accel- software and a complete suite of software development erate the development of systems based on the soft Nios tools. Bundled tools include Red Hat’s GNUPro compil- embedded-processor core. er and GDB/insight debugging The development kit tool, as well as evaluation ver- includes the latest release sions of Accelerated of the Nios embedded Technology’s Nucleus RTOS and processor, V. 3.02, and the the code/lab Developer Suite, Stratix EP1S40 device. The which offers native support for development board features FS2’s BlackBox debug probe and 16 MB of SDRAM, 1 MB of support for Altera’s ByteBlaster II SRAM, 8 MB of flash mem- download cable for software ory, a 10/100 Ethernet port, debug. The Nios Development two serial ports, and a Kit (Stratix Professional Edition) Mictor connector for soft- costs $2495. ware trace debugging. Furthermore, it includes Altera Corp. two expansion headers (408) 544-7000 (with more than 80 avail- www.altera.com

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10 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com NEW PRODUCT NEWS PSoC EVALUATION KIT SERIAL R/C SERVO AND I/O CONTROLLER The PSoC Evaluation Kit is a flexible evaluation sys- The PicoServio (or Servio) is an intelligent serial R/C tem that allows easy interfacing with the included PSoC servo and I/O slave controller capable of controlling up to chip. The kit is easily integrated for use in embedded 20 R/C servos with 16-bit resolution and 256 speed set- systems. The 28-pin PSoC chip is socketed to allow for tings. It has eight A/D converter ports capable of 10-bit the insertion of the ICE pod foot from the Cypress PSoC resolution at 40 samples per second. The controller has Designer development kit for full in-circuit emulation. two PWM signal generators capable of up to 10-bit resolu- In-system serial programming connectors are provided tion with direction control for H-Bridge connections. Any for both the Cypress ISSP interface and the Arista unused A/D or servo ports can be configured as digital I/O. Systems RS-232 Serial PSoC Programmer. The Servio offers powerful features such as monitoring Included are a precision analog interface, an RS-232 and sweep commands that offload the burden of constant port, a precision oscillator, and in-system serial program- polling and control from the master CPU. An included ming. The kit also features an input voltage range of 7 to comprehensive user and technical manual explains all 30 VDC, a 9-VDC wall- aspects of operation and provides code examples. mount power supply, The Servio consumes less than 14 mA and weighs only headers for all of the 0.8 oz. (22 grams) in a 2.5″ × available I/O, and a large 2.5″ (63 mm × 63 mm) foot- prototyping area. The print, which makes it ideal PSoc Evaluation Kit for battery and mobile opera- costs $199. Custom ver- tions. PicoServio costs sions are available. $99.95.

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www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 11 NEW PRODUCT NEWS

LOW-COST, 900-MHZ TRANSCEIVER The 9XCite is a low-cost, FCC-approved, 900-MHz environments, and 1000′ (300 m) line-of-sight with dipole wireless OEM module. The module breaks the low-cost antennas. pricing barrier while providing long-range wireless to The 9XCite module accepts 2.85 to 5.50 VDC and is OEMs with no configuration required. optimized for low-power applications. Transmit and The 9XCite module has a 1-mW power output. It is pin- receive current is less than 50 mA; power-down current for-pin and software-compatible with MaxStream’s 100- can operate as low as 20 µA. Data throughput is user-selec- mW 9XStream 900-MHz transceiver. With OEMs, only table at 9600 or 38,400 bps, and it provides interface data one interface needs to be designed to integrate wireless rates from 1200 to 57,600 bps. Frequency hopping or sin- links of various power gle-channel modes are requirements into also user-selectable. applications. Support for RS-232 is This high-perform- available for peer-to-peer, ance transceiver boasts point-to-point, point-to- a –10-dBm receive sen- multipoint, and multidrop sitivity providing networking topologies. extended transmission. The 9XCite develop- The high-receiver sensi- ment kit costs $199. tivity allows the 9XCite 9XCite modules are avail- to compete with mod- able for $37 in quantities ules operating at 10 of 1000. times the power output. The 9XCite communi- MaxStream cates 300′ (90 m) (801) 765-9885 indoors and in urban www.maxstream.net

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12 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com T e s t Yo u r EQ CIRCUIT CELLAR— Edited by David Tweed

Problem 1—While browsing some C code, you Problem 2—What is the Curie point of a material? come across an aaa.h file, which contains the following lines: Problem 3—How can this be used to regulate tem- GLOBAL int aaa_function1(); perature of, say, a soldering iron? GLOBAL int aaa_function2();

The corresponding aaa.c file includes the following: Problem 4—A certain kind of spectroscopy requires that an AC voltage in the range of 1 to

#define GLOBAL extern 25 kHz at 2 kVRMS be applied to a capacitive load of #include "bbb.h" about 1 nF. How much power does the power supply #include "ccc.h" need to deliver? How much current? #undef GLOBAL

#define GLOBAL Contributed by David Tweed #include "aaa.h" What’s your EQ?—The answers are posted at What is the purpose of the GLOBAL symbol? www.circuitcellar.com/eq.htm You may contact the quizmasters at [email protected]

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www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 13 FEATURE ARTICLE by Engin Ipek & Bruce Land Mixed-Signal AVR Simulator

Engin and Bruce have designed a mixed-signal AVR simulator that you can use to analyze the analog, digital, and program behavior of small systems built around AT90S8515 microcontrollers. The simulator is a great tool to have in the classroom, but, as you’ll soon see, it’s also perfect for your workbench, particularly because you can modify the source code to handle multiple processors.

Today, one of the most efficient and describing external events (e.g., button view the contents of the memory and cost-effective methods of placing ran- pushes, received signals, noise, etc.), the register file at each time step. It is dom logic in electronic equipment is and a hex file describing the initial also possible to perform DC and tran- to use a microcontroller. Because of state of the instruction and data mem- sient analyses on the analog circuitry their high I/O capabilities, low cost, ories of the microcontroller. (These and timing analysis on the logic compo- low power, and off-the-shelf availabili- hex files can be easily generated from nents (e.g., CMOS, TTL, etc.). An RS- ty, microcontrollers are widely used in assembly files using Atmel’s AVR 232 terminal emulator is implemented embedded design projects, from engine Studio or a compiler.) After the files to model communication using the control systems to cellular phones, cal- have been provided, the simulator ’8515’s UART. You have the ability to culators, and digital clocks. In many of compiles the circuit, checks for poten- edit models for new devices or change these real-time applications, a micro- tial problems, and reports any errors. certain parameters on the existing controller is used to interface to the After a circuit has been compiled suc- devices. The results of the analog simu- external world in order to monitor, cessfully, you can run the hex files and lation are output in an Excel file, and generate, or sample analog and digital the digital and RTL-level simulation signals by interacting with other hard- results can be viewed using GTKwave. Netlist file Parser ware. In cases where the design con- Hex file address There are several devices that are pro- tains both analog and digital signals, it Logic element vided by the simulator as library mod- is usually insufficient to simulate the els: linear resistors and capacitors, ideal Hex file digital and analog parts separately. LogicLogic Compiler and controlled sources, ideal op-amps,

In an attempt to provide a solution Element A, z diodes, and MOSFETs (Spice level 1 to this problem, as well as to facilitate Hex model) and Bipolar Junction Transistors Logic Solver AT90S8515 the lab preparation process for the reader (BJTs). Noise sources, push-button Analog results Digital results microcontroller-based digital design switches, logic gates and flip-flops, class at Cornell University, we XLS VCD AT90S8515 microcontrollers (at RTL designed a mixed-signal simulator that level), and the RS-232 terminal emula- can be used to analyze the analog, dig- Excel file containing VDC file containing tor are also provided by simulator. results of analog results of digital ital (gate level), and program behavior simulation simulation of small systems built around Atmel HIGH-LEVEL DESIGN AT90S8515 microcontrollers.WWW.GiURUMELE.Hi2.RO The Figure 1—The parser class reads the netlist file. The The simulator was written in Java. compiler class generates linear models of every analog simulator allows you to set up mixed- circuit element for the next iteration. The logic class Refer to Figure 1 to see how we organ- signal systems by using a simple hard- instantiates a logic solver based on the information about ized the code. Each box represents a ware-description language whose syn- the logic gates. The hex reader reads the contents of the class, and the arrows denote the inter- tax is similar to Spice netlist format. hex file and loads the microcontroller model with the action of one class with another. The appropriate data and instructions. The solver class calcu- You can also specify the programs to lates the voltages at every node for the current iteration. outputs of one type of class that are run on the microcontrollers. The current voltage levels at each node are passed back passed to another class as inputs are In order to run the simulator, you to the compiler class, which generates linear models of shown on each arrow (e.g., the parser must provide a netlist file that lists all all circuit elements for the next iteration. The XLS class passes an array of logic elements to creates an Excel file containing the results of the analog of the electrical connections in the simulation, and the VCD class generates a VCD file the logic class). For simplicity, only system, an optional stimulus file containing the results of the digital simulation. the major classes and the main

14 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com inputs/outputs of those classes are analog elements with initial conditions specified simulation termination time shown. You may download the code on nodes at time t = 0, and then passes is reached. At that point, the solver from the Circuit Cellar ftp site. the array to the compiler class. The passes the values it has stored The simulation begins when the pars- compiler generates linear models of throughout the simulation to the XLS er reads the netlist file and determines every component for the next iteration and VCD classes, which generate an the location of the hex file containing an of the simulation, and it uses these lin- Excel file containing the analog image of the memory at time t, which ear models with the initial conditions results and a VCD file (to be viewed equals zero. This information is passed to generate a matrix equation: by GTKwave) containing the RTL- to the hex reader, which reads the hex level and digital results, respectively. Ax = z file and loads the appropriate data and The nonlinear equations are solved instructions into the RTL-level model where A is an n × n matrix (for n ana- using the Newton-Raphson algorithm, of the ’8515. The loaded model is then log components) and z is a vector of while the transient analysis is based on given to the solver class as an input. length n. the Backward-Euler integration formula. As the parser goes through the After the logic simulator, the RTL- At every iteration, the results for the netlist file, it also creates an array of level model of the microcontroller and shared nodes of all three simulations the logic elements (logic gates and flip- the matrix equation are passed to the (RTL, logic, and analog) are converted to flops) that you reference. Every logic solver. The solver determines the the appropriate signal domain and passed element object in this array includes dependencies between the submitted as an input to the appropriate model (e.g., the type of the element (e.g., D flip- nodes and solves the matrices and logic the microcontroller’s digital outputs that flop) and the connections to its fan-in equations for the next time step. It also are inputs to analog circuitry are convert- and fan-out. The array is passed to the advances the microcontroller’s simula- ed into analog and passed to the analog logic class, which instantiates a logic tion by one clock cycle. The results compiler class for the next iteration). solver based on the nodes, connections, from the current time step are returned Because of the use of the Backward- and initial inputs in the LogicElement[] to the compiler, which regenerates the Euler formula, only stable circuits can array. This logic solver is then given to linear models for the next iteration and be successfully simulated. Hence, the solver class as an input. passes A and z back to the solver. undamped sine wave oscillators Finally, the parser creates an array of This cycle continues until the user- should be implemented using the voltage sources. The Wien-bridge oscillator, for instance, will have an artificial damping constant associated with it. Thus, the simulation results will not reflect the physical reality.

NETLIST FILES Every netlist file begins with a statement in the form of MCU filename.hex. Note that filename.hex is the hex file that contains a memory image of the initial processor state. This statement is followed by a description of the connections in the circuit. In order to make these connections, you must assign a unique number from one to n to each node, where n is the number of nodes in the circuit (excluding GND). By default, node 0 always corresponds to ground, but aside from this WWW.GiURUMELE.Hi2.ROconvention, you are free to select any number to correspond to any node. Listing the element name, the input and output nodes, and the parameters related to the operation of the element specifies connections. For instance, R 1 2 1000 places a 1-kΩ resistor between nodes 1 and 2. You may Figure 2—Port C of the microcontroller is set up to generate a sine wave. The output is then converted to analog using an R-2R ladder DAC. The signal is amplified by an inverting op-amp circuit with a gain of –2. To illustrate download a full list of the parameters the use of logic gates, the two least significant bits of port C are input to an AND gate, and the result is ORed that must be specified for every ele- with bit 2 of port C. ment from the Circuit Cellar ftp site.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 15 a) Op-amp output vs. number of cycles b) Op-amp output vs. DAC output 6 2 4 0 2 -10123456 0 –2 –2 0 2000 4000 6000 8000 10000 12000 opAmpOut –4 –4 dacOut –6 –6

Voltage (V) y = –2x + 2E–11 –8 2 –8 (V) Op-amp output R = 1 –10 –10 –12 –12 Time (CPU clock cycles) DAC Output (V)

Figure 3a—The voltages at the output of the DAC and the op-amp are shown by dacOut and opAmpOut, respectively. The microcontroller spends the initial 3600 cycles running the boot code and no changes to port C take place. After the boot code is executed, the microcontroller generates a 4.95-kHz sine wave. The DAC converts the sine wave to analog and the op-amp amplifies the output of the DAC by a factor of –2. b—The x- and y-axes show the voltages at the outputs of the DAC and the op-amp, respectively. The op-amp’s gain is equal to –2, and the amplifier is perfectly linear because it is an ideal op-amp.

Connections to the microcontroller the node number that you specify. have stimulus files associated with are made by statements in the follow- DUMPLOGIC’s format is identical to them. At each simulation step, the val- ing form: DUMPANALOG’s format. ues for the buttons and random voltage Buttons and random voltage sources sources are read from these files. An PORT node_number IO_address bit_number Listing 1—The netlist file describes the hardware depicted in Figure 2. The first line specifies the name of the hex file containing the memory image at t = 0. Statements of the form R node1 node2 where node_number specifies the num- resistance (Ohms) define the DAC. Port C connections are made by statements in the following ber you assign, IO_address gives the form: PORT bit_number IO_address node_number. The op-amp is defined by declaring address of the port, and bit_number the following: OPAMP pos_terminal neg_terminal output_terminal pos_sup- shows which bit of the port to connect. ply_voltage(V). The AND gate is specified by AND input1 input2 output. The OR gate is similar to the AND gate in terms of its declaration. DUMP statements map memory locations and nodes To store the values of any nodes, reg- to user specified names so that the results are more readable. isters, or memory locations and view them after the simulation, use the MCU itestsinewave.hex DUMP, DUMPANALOG, and DUMPLOGIC R 1 9 20000 statements. The DUMP statement is for R 9 0 20000 R 2 10 20000 the microcontroller, and DUMPANALOG R 3 11 20000 is for analog signals. The DUMPLOGIC R 4 12 20000 statement is used for logic signals. R 5 13 20000 R 6 14 20000 The DUMP statement has the follow- R 7 15 20000 ing general form: R 8 16 20000 R 9 10 10000 R 10 11 10000 DUMP name1 memAddr1 name2 R 11 12 10000 memAddr2 … end R 12 13 10000 R 13 14 10000 R 14 15 10000 where name1…N is any string you choose, R 15 16 10000 and memAddr is the memory address of PORT 1 21 0 the specific register/memory location PORT 2 21 1 PORT 3 21 2 that you want to view. The VCD file PORT 4 21 3 uses name1… nameN when displaying the PORT 5 21 4 results. Because there is no memory PORT 6 21 5 WWW.GiURUMELE.Hi2.ROPORT 7 21 6 address for the PC, the memAddr field PORT 8 21 7 should be “PC” when storing the PC OPAMP 17 0 18 (e.g., DUMP mcuPC PC end). R 17 18 2000000 R 18 0 1000 The DUMPANALOG statement has the R 16 17 1000000 following general form: AND 1 2 20 OR 3 20 21 DUMPLOGIC logicOUT 21 ENDDUMP DUMPANALOG name1 node1 name2 DUMP portc 53 R0 0 R1 1 R2 2 R3 3 R4 5 R5 5 R6 6 R7 7 R8 8 R9 9 node2 … end ENDDUMP DUMPANALOG opAmpOut 18 dacOut 16 zeroOut 9 opAmpNegTerminal 17 ENDDUMP where name1…N is any string you end choose and node1…N corresponds to

16 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO WWW.GiURUMELE.Hi2.RO example stimulus file is provided below, troller was found to be cycle-accurate assuming that button b1 and random in all test cases. The circuit in Figure 2 voltage source v1 have been declared and and corresponding results in Figure 3 tied to this stimulus file in the netlist: are typical outcomes of the simulation. The circuit in Figure 2 generates a #0 4.95-kHz sine wave. Port C of the b1 0 microcontroller is set up to generate a v1 0 new value every one-sixteenth of a #5 cycle so that you can obtain a total of b1 1 16 samples per cycle of the sine wave. #10 The output is then converted to analog b1 0 using an R-2R ladder DAC, and the sig- v1 2.45 nal is amplified by an inverting op-amp end circuit of gain –2. To illustrate the use of logic gates, port C’s two least signifi- The button is off and the random voltage cant bits are input to an AND gate. source is outputting 0 V at cycle 0 (of the The result is ORed with bit 2 of port C. MCU). At cycle 5, b1 turns on. At cycle Listing 1 is the netlist file describing 10, b1 turns off and v1 outputs 2.45 V. the hardware in the schematic diagram. The first line provides the name of the RESULTS hex file to be loaded into the memory. The results of the simulation were The DAC is defined next, followed by found accurate to six decimal places the connections to port C and the when PSpice analog simulator was logic gates. The DUMP statements at taken as a reference. The microcon- the end specify the nodes whose values

Listing 2—As you study the C code for the sine wave generator, remember that the values for the sine function are stored in an array. A timer-based interrupt is used to output the next sine value each time it is triggered.

//Sine wave generator using C //4.95kHz frequency #include <90s8515.h> //Define constants #define prescale1 1 #define clear_on_match 8 //Sample number unsigned char sample ; //Table of sine values flash unsigned char sinetable[16]={0x80, 0xb1, 0xda, 0xf6, 0xff, 0x26, 0x0a,0x00, 0x0a, 0x26, 0x4f}; //*************************************************************** //timer 1 compare-match A ISR interrupt [TIM1_COMPA] void cmpA_overflow(void) { PORTC = sinetable[sample++] ; //PORTC = Next sine value if (sample == 16) sample=0 ; //Go back to beginning of //table if period complete } //***************************************************************

void main(void) { WWW.GiURUMELE.Hi2.RO sample = 0 ; //Initialize sample # to beginning of table TIMSK = 0x40 ; //Timer 1 CompareA DDRC = 0xff ; //Port C are outputs OCR1A = 100; //Set up OCR1A TCCR1B = prescale1 + clear_on_match ; //Setup clear on match TCNT1 = 0; //Turn on all interrupts #asm sei #endasm while(1){} //Do nothing, wait for ISR to be called }

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 19 are to be stored in Excel and could be extended to handle VCD files for viewing after the multiple processors by modify- simulation. These nodes are ing the source code. You could also named in the body of the implement frequency domain DUMP statements to facilitate the analysis. Furthermore, it viewing process. would be relatively easy to Listing 2 shows the C code that write additional library models runs on the microcontroller. To (e.g., an LCD). As a result, we run the simulator, we compiled believe that the simulator this file using the CodeVisionAVR could be used as a teaching tool C compiler with Intel hex select- in any lab setting. I ed as the output file format. Figure 3 depicts the results of Engin Ipek is currently studying the simulation. The plots are Photo 1—The top row shows the value of port C at each time step. The toward a Ph.D. in Electrical and second row corresponds to the output of the OR gate. R0 through R9 taken directly from the Excel Computer Engineering at Cornell show the values of registers zero through nine. As expected, port C output file generated by the simulator. corresponds to the sine value stored in memory, and the output of the OR University, where he earned his The node names agree with the gate corresponds to Port C.0 and Port C.1, or Port C.3. B.S. His technical interests definitions in the DUMP state- include computer architecture, ments. Figure 3a shows the output of of its time (30% for this example) gen- digital VLSI design, and embedded the DAC and the output of the op-amp erating the output files, so reducing systems. You may contact Engin at versus time. The microcontroller the number of output nodes for which [email protected]. spends the initial 3600 cycles running the simulator saves data significantly the boot code. Consequently, port C improves performance. Hence, for fast Bruce Land is a senior research asso- does not change during this time. simulations, only essential signals ciate in both Neurobiology and Figure 3b shows the op-amp’s gain. As should be stored. Behavior and Electrical and Computer expected, the gain is equal to –2, and Figure 4 depicts the performance of Engineering at Cornell University. He the amplifier is perfectly linear because the simulator for the sine wave gener- teaches two courses in Neurobiology it is an ideal op-amp. (R2 = 1 and y = –2x ator example. As indicated by the plot, and Behavior and one in Electrical on the plot.) the simulator is approximately 700 times and Computer Engineering. Bruce also The results of the digital simulation slower with respect to real time, which provides general research support in are shown in Photo 1. The top two is adequate for testing typical microelectronics design and computer tech- rows show the values of port C and the controller-based designs. For instance, niques. When time allows, he enjoys output of the OR gate, respectively. it takes roughly 1.5 min. to simulate neural modeling. You may reach him The performance of the simulator one million instructions of the sine at [email protected]. was evaluated based on the ratio of the wave generator, where 10,000 instruc- simulation time to real time. Although tions are enough to see four full cycles PROJECT FILES the nonlinear transient analysis algo- of the sine wave. To download the code and a list of rithm used in the simulator has O(n3) the supported circuit elements, go asymptotic complexity, linear circuits THINKING AHEAD to ftp.circuitcellar.com/pub/ such as the one shown here can be Test results showed that our pro- Circuit_Cellar/2003/160. simulated reasonably quickly. The gram could successfully simulate the program spends a significant amount mixed-signal behavior of small systems built around RESOURCES AT90S8515 micro- V. Litovski and M. Zwolinski, VLSI Simulation time vs. real time controllers in a rea- Circuit Simulation and sonable amount of Optimization, Chapman and Hall, time. The major dif- London, England, 1997. WWW.GiURUMELE.Hi2.ROference between our W. H. Press, et al., Numerical simulator and simi- Recipes in C: The Art of Scientific lar commercially Computing, Cambridge University

Real time (ms) available simulators Press, Cambridge, England, 1993. is that we provide an open-source implementation. Although SOURCES Simulation time (µs) only a single micro- AT90S8515 Microcontroller controller is support- Atmel Corp. Figure 4—The y–axis indicates the simulation time in microseconds, and the x–axis indicates the real time in milliseconds. For the sine wave example, the ed, the simulator (408) 441-0311 simulator is approximately 700 times slower with respect to real time. was designed so it www.atmel.com

20 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO Flash Innovation 2003 Design Contest Winners Announcement

The Motorola Flash Innovation 2003 Design Contest was a great success. Innovative designs are what we asked for, and innovative designs are what we got—tons of them. Last spring, engineers began entering projects featuring the HC08 Q-Family from Motorola, and when our judges sat down to study the submissions, they were presented with entries from such diverse locations as the United States, Italy, and Thailand. Richard Dreher took the Grand Prize for his Remote Observation Station, which is an 68HC908QY4-based design that allows you to monitor a track of land by sending video images to an off-location television. Dozens of other contestants earned First Prize and Distinctive Entry honors for their innovative, cost-effective designs. Congratulations to the winners! We would like to thank all of the entrants for helping to make this design contest one of our most competitive to date. You proved that with a little ingenuity and a straightforward design plan, the potential for HC08-based embedded applications is limitless.

Remote Observation Station Have you ever wondered what the birds, deer, or bears were doing in your backyard when you weren’t around? With the Remote Observation Station, you can watch wildlife on your TV in the com- Grand Prize fort of your living room. The station includes a camera and transmitter that sends a picture to a TV, which can be up to a mile or two away. The station gets its power from a PV solar panel and a rechargeable battery, which rely on the system’s control board for direction. The control board also produces battery state information, which it overlays on the picture sent to your TV. So, while you’re watching the wildlife, you can also monitor the status of your battery. The unit integrates six electronic devices, including a CCD video camera, PV solar panel, rechargeable battery, temperature sensor, RF video transmitter, and the system control board (PVCC). The control board is based on the Motorola 68HC908QY4 microcontroller. The board sits at the center of the system, providing a PV charge controller, two high-efficiency voltage regulators, a video sync separator, and an RS-232 serial interface for system configuration. The PVCC control board provides a simple on/off battery charger using the PV solar panel as a power source. The primary job of the charge controller is to prevent the battery from being overcharged. The control board also adds battery state information in the form of a text overlay (on-screen display, or OSD) to the video signal generated by the CCD camera before it reaches the video transmitter. Additionally, a PC can be connected to the control board via the DB9 connector. The system has three operating modes: Configuration mode allows you to control user settings with your PC; Charge Control mode with OSD sends the battery’s voltage and temperature to the video signal; and Charge Control mode without OSD is used when you don’t need the diagnostic display. The PVCC configuration utility communicates with the PVCC board while in Configuration mode. With this utility, you can set a variety of options, including the full-charge set point (the off set point) and the PV reconnect set point (the on WWW.GiURUMELE.Hi2.ROset point). You can also choose to enable the transmission of an Amateur Radio call sign if a ham frequency is being used. Richard Dreher U.S. For complete projects, visit www.circuitcellar.com/fi2003 First Prize North America and South America Region

NTSC Video Using the 68HC908QY4 Wireless, The Motorola 68HC908QY4 is used to produce an NTSC video signal that can be Solar-Powered, used in several applications. By using a 28.63636-MHz clock, the ‘908QY4 bus speed is 7.15909 MHz, which is twice the chroma frequency of 3.579545 MHz. Acoustic Wave The interrupt timer is used to generate an interrupt every 455 bus cycles, resulting Soil Moisture in an interrupt rate of 15.734 kHz, which is the frequency of NTSC sync. Because Detection interrupts that occur in the middle of a multicycle instruction are not recognized until the instruction is completed, the main line consists of a table of NOPs. All of System the sync functions are performed during the inter- The advantage of rupt, and the interrupt routine is returned to the using acoustic start of the NOP table. The ‘908QY4 can be used waves to measure to produce NTSC sync for applications such as an the moisture con- NTSC test-pattern generator that produces simple tent of soil is that test patterns in order to evaluate a TV’s geometric acoustic waves measure the moisture con- distortion, high-voltage regulation, and interlace tent in a volume of soil that radiates out- quality. ward from the acoustic source to the detec- Jed Margolin tor rather than measure the moisture con- tent at only one point. Each detector is solar-powered and uses wireless trans- Smart-E-Touch ceivers to send the measured data to a serv- The Smart-E-Touch is an intelligent, touch screen-based user interface design. A er. The heart of each source and detector Nitron 68HC908QY4 microcontroller controls and monitors a pair of Motorola e-field unit (SDU) is the 68HC908QT4. The SDU’s sensors. The e-field sensors, in turn, monitor an XY grid on the PCB for the capaci- acoustic source consists of a piezoelectric tive sensing of the touch screen. After the Nitron has translated a “touch” from the speaker excited by a 5-kHz square wave e-field sensor data, it then outputs an XY coordinate to its RS-232 serial port. A generated by the 68HC908QT4. The SDU’s main system controller—a PC or equivalent controller—then receives this XY coordi- detector unit consists of an electret micro- nate and can act upon it. The touch screen phone whose output is AC coupled to a is built into the circuit board that houses the high-gain, band-pass filter. The result is then controller circuitry. So, the touch screen is peak detected before being sampled by the part of the system controller board. The microcontroller’s ADC. The ’908QT4 is con- Smart-E-Touch is a natural replacement for nected to a Manchester CODEC and RF resistive touch screens and custom-made transceiver for communications with a desk- user interfaces. top computer. Bruce Pride Cheng-Yang Tan U.S. U.S. Distinctive Excellence North America and South America Region Servo Digitizer Canada The Servo Digitizer, which is based on the 68HC908QT4, channels control input from a model airplane radio Enviro-Alarm remote control to a flight simulator program running on a PC. It translates a PWM signal output from the Built with a 68HC908QT4, an optically isolated remote alarm interface, a low-dropout voltage regulator, a 9-V remote control into ASCII data and sends it to the PC via an RS-232 serial port. Sitti Amarittapark, U.S. battery, and a few sensors, the Enviro-Alarm monitors for leaks around a basement sump pump. The remote alarm interface connects to a Cat 5 cable that runs to a wiring closet for integration with a PC-based home Laser Spirograph automation system. Kenneth Lumia, U.S. The 68HC908QT4-based laser projects onto a primary offset mirror. The primary mirror spins a circular image onto the secondary mirror, which is also spinning. The secondary mirror then projects the first pattern Peak Power Controller onto a wall or screen. The difference in mirror speeds of the two motors creates spirograph-like images. The Peak Power Controller acts as an impedance transformer between the source and load. It monitors the Matthew Bieker, U.S. power output from the source and dynamically adjusts the effective load impedance to maintain operation at the peak power point. The 68HC908QT4-based controller operates as a boost converter, maximizing the Printed Circuit Board Drill input power. James McGuire, U.S. The low-cost, fully automatedWWW.GiURUMELE.Hi2.RO machine drills blank PCBs with minimum custom machining. Data is transferred to the PCB drill from an Excellon drill file generated by a PCB CAD program running on a PC. The con- Flow Rate Failure Detector troller is designed around the 68HC908QY4. Thomas Dvorak, U.S. The 68HC908QT4-based detector monitors conditions that may cause a rise in temperature, such as a significant drop of the air-flow rate and an escalation of the intake temperature. The detector also monitors equip- Intelligent Humidity-Compensated Thermostat ment for overheating. Colin O’Flynn, Canada Built with an intelligent sensor, 68HC908QY4, and a couple of relays and switches, the thermostat periodically reads both the temperature and relative humidity of the inside air. Using a preprogrammed table, it com- Nitro-Debugger pares these temperatures to user-defined preferences, and adjusts the heat or air conditioning accordingly. The 68HC908QY4-based Nitro-Debugger is a small, non-intrusive debugging device that connects to an exter- Charles Edmondson, U.S. nal circuit board’s microprocessor bus. It monitors, captures, and then converts a single bus cycle into useful data. The data is displayed by an ASCII terminal emulator via an RS-232 connection. Bruce Pride, U.S. Martial Arts Digital Simulator The interactive martial arts training system incorporates high-quality digitized audio and speech feedback to Boost Pump Control simulate sparring with an opponent. The 68HC908QT4 “listens” for impacts on the sensor through its built- The liquid pump monitor system protects a pump from running dry by monitoring the inlet and outlet pres- in ADC, monitors the spar time, and tracks the user’s performance during the workout. Themi Kotsiras, sures. The 68HC908QY2-based system is typically used to assist freon compressors that have long pipes For complete projects, visit www.circuitcellar.com/fi2003 Innovate with the HCO8 First Prize from Motorola Europe, the Middle East, and Africa Region

Low-Cost Intelligent Sensors Network Gas Alarm The low-cost intelligent sensors network is based on The Gas Alarm is ideal for use in the kitchen the 68HC908QY4. It is ideal for applications that or garage, near a gas boiler, or while camp- require low-speed, two-wire bidirectional data coming. The 68HC908QT2 microcontroller-based munication, including home or office automation, combustible gas detector is small, cost-effec- remote technological process monitoring, industry tive, and flexible. The electronic circuit evalu- control, security/fire alarm systems, and remote light ates change in the internal sensor resistance. control. A simple time-triggered protocol ensures a A few comparators are used to watch the ref- predictable data delivery time. The quasi-harmonic erence voltage, sensor resistance, and sensor constant frequency network signals are secure from proper operation. An oscillator isn’t needed electromagnetic compatibility problems. because the detector uses the Nitron micro- Victor Kremin controller’s oscillator. There are built-in delays Ukraine for after power-up and after gas is first detected in order to avoid false alarms. By Smart Tracker 2: An Innovative Wire Tracker changing the sensor type, the detector can be The Smart Tracker 2 is a low-cost, compact wire identification device. A 10-chan- used for various gases. You can also add an nel transmitter injects test signals into up to 10 wires. A small probe can be con- additional comparator to detect two different nected between any of the wires to identify both of them simultaneously, without a gas concentrations. ground connection. The probe also identifies any short circuits between the wires. Radek Vaclavik The transmitter has 10 outputs—each identified by a different color—with a small Czech Republic grabber on each end. The outputs, which are driven by a 68HC908QY4, are connected to one end of the wires to be identified, in any order. The receiver has two inputs (red and green) and 10 bicolor red/green LEDs, each of which is associated with one of the transmitter colors. The transmitter successively injects a binary word on each of the 10 outputs using a software-based bit- banging UART transmitter. The receiver can identify a wire by “listening” to the input. Robert Lacoste France Distinctive Excellence Europe, the Middle East, and Africa Region Magic Lamp Radio Security System With a 68HC908QT4, some transistors, resistors, and three LEDs (red, green, and blue), the Magic Lamp can The Radio Security System system uses a 68HC908QT1-based transmitter and a 68HC908QT2-based receiv- control LED light intensity. Jens Altenburg, Germany er to thwart car radio theft by hiding a radio receiver. The theft-deterrent system uses short-distance remote control with a low-frequency radio signal. Salvador Perdomo, Spain Rear Muffler Actuator Control The Rear Muffler Actuator Control adjusts the sound of an electromotive actuated muffler based on engine DVD-Thermometer speed. The 68HC908QT4 evaluates the speed, the position of an optional mode switch, and the actuator The 68HC908QT4-based multimedia DVD-Thermometer displays the temperature on a TV with full-color graph- current. It also controls the motor driver and provides the control algorithm and safety functions. ics. Animated pictures can be added along with CD-quality audio announcements. Alberto Ricci Bitti, Italy Andreas Bartelmus, Germany Wireless Mousetrap Monitoring System 414O Option Board The 68HC908QT4-based system consists of a monitoring station—a computer-controlled receiver with an The Nitron 68HC908QY1CP-based project makes a 4I4O board compatible with a former 4E4S board, and LCD and a relay output—and up to 20 mouse sensors. A sensor is placed inside each live-catch trap. When a enables the use of other 0- to 10-V and 4- to 20-mA opto-isolated boards. Damien Bataille, France mouse is captured, the sensor transmits the trap ID to a master unit, which logs the trap ID and displays it on the LCD. The receiver can also dispatch a call to an external service, triggering an ordinary automatic Artificial Vision System forWWW.GiURUMELE.Hi2.RO the Blind phone dialer connected to its relay out. Alberto Ricci Bitti, Italy The vision system measures the distance to an object and records the data on a unique hand-held slider, which is read similarly to Braille. The device estimates an object’s speed using the Doppler effect. Counter Victor Kremin, Ukraine The Counter is based on the MC68HC908QTx. Five seven-segment LEDs are used for display. Powered by a single 5-V power supply, the counter is ideal for industrial process control and monitoring applications. Low-Cost Evaluation Board/Programmer for ’908Qx Series Microcontrollers Tito Smailagich, Yugoslavia The evaluation board enhances the 68HC908Q demo board. This board enables you to build a prototype of a small device, program 68HC908Q chips, and monitor the connection board using a two-wire (one signal plus Tiny Altimeter ground) connection to the target system and RS-232C connection to a PC. A 10-position DIP switch is used The Tiny Altimeter measures altitude and can store data in internal memory every 200 ms. Based on the to configure the board. There are also three push-button switches and a socket for an oscillator. 68HC908QT4, the altimeter measures atmospheric pressure and recalculates pressure changes to the alti- Grzegorz Mazur, Poland tude values without an antenna. The system achieves 0.5-m (1.6′) resolution. Radek Vaclavik, Czech Republic For complete projects, visit www.circuitcellar.com/fi2003 First Prize Asia and the Pacific Rim Region*

Programmable DC Power Supply Acoustical Cellular Automata Instead of the classic transformer—with a regulator, lots of wires, and a 5-V Parallel Processor power supply—this power supply is more like a real tool. The power supply is The mathematical concept known as cellular based on the 68HC908QT4, and features 0.6- to 20-V output voltage with 8-mV automata (CA) is primarily modeled as a two- resolution, and 0- to 2.5-A output current with dimensional graphical presentation. Humans 10-mA resolution. Other features include short- have the ability to localize sound sources in circuit protection, adjustable current limit (5-ms two and even three dimensions due to the response time), 5-mVPP maximum output ripple, physical shape of the human head and ears. and a 2 × 16 LCD. The power supply can drive Thus, we have the ability to discern the posi- the LCD using only three I/O lines, two of which tion of the sounds around us. The Acoustical are shared with other peripherals. The resolution Cellular Automata Parallel Processor applies of the internal ADC can be increased from 8 to cellular automata to a two-dimensional array 14 bits. Integer arithmetic is used to save com- of sound emitters. The design uses multiple putational power and ROM. microcomputers connected in a two-dimen- Mihai Tudosie sional array to form a larger parallel array Japan processor. The array processor, built with the 68HC908QY4, is programmed to handle the Tilt Detector specific case of CA with multiple sound emit- The Tilt Detector is based on a 68HC908QT4 microcontroller. The small detector ters to display the cell states. The microcom- can measure 360° of tilt and display the result on its LCD, which is controlled by puter module actually controls four cells in only two pins. The tilt data is stored in the detector and can be displayed on the the array, and is connected to four sound screen. The detector can handle operations, or it can send stored data to a PC. In emitters (transducers). The module can be order to improve the measurement accuracy, the gadget can calibrate the sensor connected and save the calibration parameters for to other better performance. It can also measure modules to acceleration in the range of –2 to +2 g. form a large There are two versions of the circuit: one array that is a digital version, which is powered by could con- an input capture function with high accura- ceivably cy, and the other is a low-cost analog ver- cover a sion, which is powered by the inner ADC. wall. Hua Zhou Raymond China Weisling Distinctive Excellence Asia and the Pacific Rim Region* µTelemetry: The Micro Telemetry System for R/C Race Cars Blood Pressure Monitor The µTelemetry is an inexpensive, wireless telemetry system that monitors voltage, speed, and temperature The Blood Pressure Monitor measures the oscillations in pressure in the cuff. A sensor translates the pres- in real-time. It was designed for use in remote-controlled race cars, but also works well for a variety of data- sure to capacitance, which is then measured by a 68HC908QT4-based circuit. The circuit also detects the acquisition applications. The transmitter and receiver are designed with the 68HC908QT4. small variations in pressure during deflation to calculate the systolic and diastolic readings, which it displays Virachat Boondharigaputra, Thailand on a 1 × 16 LCD. Ganesh Raaja Maharajan, India Intelligent Fishbowl The Intelligent Fishbowl controls and displays the temperature in a fishbowl, and also automatically feeds Automobile Cruise Control the fish. Based on the 16-pin 68HC908QT2, the low-cost system also controls lighting for the fishbowl. The stand-alone Automobile Cruise Control is a microwave radar-guided, 68HC908QT4-based cruise control Zhang Chongguang, China system for all types of vehicles. Using the Doppler effect, the system detects stationary and moving objects 50 to 75 m ahead or behind the vehicle. Indranil Majumdar, India Mini Node The Mini Node is a creative solution to the horizontal switch plates now popular in Australia. To continue VGA Signal Probe using an HCS II and X10 system for home control, the 68HC908QT4-based Mini Node connects to the HCS This VGA Signal Probe uses a 68HC908QT4 to digitize an analog signal and generate a corresponding VGA II via the RS-485 network. It automates house lights that are controlled by more then one wall switch. video signal that represents the time sequence of the samples. This allows a simple audio-bandwidth CRO to WWW.GiURUMELE.Hi2.ROKamal Gendi, Australia be implemented using two eight-pin ICs. Lindsay Meek, Australia iButton-based Personal Identification System (iBPIS) Intellistick: The Eye of the Blind For use in offices, the iBPIS stores personnel information on the Maxim iButton; the data then can be dis- The 68HC908QT4-based Intellistick is a walking stick for blind people that uses ultrasonic ranging to detect played on a PC or hand-held device through an IR link. The system consists of three modules: the obstacles. Audible warning sounds (various beeps) indicate the distance of the obstacle. H.N. Naveen, India 68HC908QT4-based iButton user module (iBU), the iButton enquiry module (iBE), and iButton programming module (iBP). Sunil Jha, India RS-232-to-RS-485 Communications Multiplexer The multiplexer provides eight RS-485 communications ports using one RS-232-to-RS-485 conversion circuit. Low-Power Optical Smoke Detector A 68HC908QY1 controls eight analog switches and builds connections between a real RS-485 communica- The 68HC908QT4 is the core processor of the Low-Power Optical Smoke Detector. Using an infrared LED tions port and any one of the eight virtual ports. You can control the target channel manually, let the MCU do and receivers, the unit detects the presence of smoke particles in the air, thus triggering a signal to any com- it automatically, or use a specially designed program running on the PC. An LCD displays the statuses. mercial fire-monitoring panel so that an alarm can sound or other recovery actions can be taken. Hua Zhou, China Steven Wong Kai Juan, Singapore *Includes all other countries not included in other regions For complete projects, visit www.circuitcellar.com/fi2003 WWW.GiURUMELE.Hi2.RO WWW.GiURUMELE.Hi2.RO FEATURE ARTICLE by Philip Nowe Timing (Analysis) is Everything A How-To Guide for Timing Analysis

Philip’s main issue with young engineers is that many of them have been taught excellent circuit design techniques but haven’t been schooled in the importance of timing analysis. What is timing analysis? Why is timing analysis important? How do you perform timing analysis? Whatever your level of expertise, you’re sure to find Philip’s answers informative.

As a hardware designer and managing constraints imposed by compo- and hold timing. Red indicates that a er, I’ve noticed that many electrical nents or interfaces are met. Typically, condition has not been met. If the set- engineering students are often missing this means that you are trying to up time is read and has a margin of –1, something when they begin their first prove that all set-up, hold, and pulse- the set-up time has not been met and full-time jobs. They’ve been taught width times are being met. is off by 1 ns. The hold time indicates how to design great circuits, some of A minimum or maximum digital that there is 1-ns margin. them quite complex, but they haven’t simulation is not actually the worst- In Photo 1, the gray areas of the been taught the importance of timing. case analysis. That is what a number waveforms indicate the uncertainty of What does timing analysis mean? of entry-level engineers believe. The when the edge occurs. Notice that the Why is timing analysis important? worst-case analysis takes into account output of logic gate 2 has the largest How is it done? In this article, I minimum delays through some paths uncertainty, because the uncertainty answer these questions. In addition, I and maximum delays through other is cumulative as you go through a present you with a real design prob- paths. For instance, the worst-case delay chain. So, the delay at the out- lem that was solved with timing set-up timing with respect to flip-flop B put of logic gate 2 is equal to the delay analysis. So, here we go! in Figure 1 would be the minimum from CLK A to Q of flip-flop A as well delay to the clock input combined as the delays through logic gates 1 and WHY TIMING ANALYSIS? with the maximum delay to the data 2. Note that the waveform also uses There are a couple of reasons for input of flip-flop B. color highlighting to indicate that con- performing timing analysis. First and Let’s assume the timing values in straints are not being met. foremost, it can be used to verify that Table 1 are for the circuit elements in As you can see in Photo 1, there is a a circuit will meet all of its timing Figure 1. Do you think that there is a D input set-up time problem to flip- requirements. Timing analysis can problem with these values? Take a flop B. Sometimes, when discussing also help with component selection. look at this circuit in a waveform timing issues, I hear designers say that An example is when you are trying to view in Photo 1. Notice that the bot- timing doesn’t really matter because determine what memory device speed tom of the photo shows the parame- the processor has a memory controller you should use with a microprocessor. ters used in determining the set-up with variable timing. This may be true, Using a memory device that is but it usually means that the too slow may notWWW.GiURUMELE.Hi2.RO work in the processor allows for a pro- circuit (or would degrade per- grammable number of wait DQLogic Logic DQ formance by introducing wait gates gates states. If you add another wait 1 2 states), and using one that is D Flip-flop D Flip-flop state (i.e., one more clock too fast will likely cost more A B cycle before clocking in the than it needs to. CLK B data), then the problem in CLK CLK Photo 1 will go away. But CLK A A WORKING DEFINITION Clock what if you don’t want the per- delay Timing analysis is the formance hit of adding a wait methodical analysis of a digital Figure 1—The simplified digital circuit contains delays in the data and the state, or what if the processor circuit to determine if the tim- clock paths. The timing values are shown in Table 1 (see p. 29). doesn’t allow wait states? You

28 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com would have to solve the Timing parameter Minimum value Maximum value the signal timing, I put on timing problem. the diagram the minimum Another case involves Nominal CLK frequency 25 MHz 25 MHz and maximum timing for hold problems. Adding CLK to Q delay (both flip-flops) 2 ns 5 ns every signal edge. Each Clock delay 1 ns 3 ns wait states often cannot Propagation delay through logic gates 1 3 ns 15 ns time I changed the compo- solve this, because the Propagation delay through logic gates 2 5 ns 12 ns nents in a signal path, I timing chain for the D input setup time to CLK (both flip-flops) 10 ns updated the numbers on D input is tied to the D input hold time after CLK (both flip-flops) 6 ns the drawing. The next pos- current clock edge not to Table 1—Here are the timing values for the circuit illustrated in Figure 1. sible step in the evolution the delays from the pre- of timing analysis would vious clock edge. In such be to put the timing num- a case, you need to make some make a change to your circuit, rerun bers in a spreadsheet and let the changes to the design to make the the timing analysis to make sure that spreadsheet do the calculations. timing work. the problem is fixed and that another Table 2 shows the original simpli- Okay, so you agree that there is a one hasn’t been created. Hopefully, I fied circuit analyzed in a spreadsheet problem. So what? What will happen have convinced you that timing analy- format. For the set-up time calcula- if you don’t fix it? There are three sis is important. Now I’ll show you tion, use the maximum data delay and possibilities for set-up and hold times how to do it. the minimum clock delay (less set-up (see Figure 2). time) to determine if the set-up time As you can see in Figure 2a, the sig- HOW IS IT DONE? is met. For the hold time, use the nal of interest can meet the timing Timing analysis has been achieved minimum data hold delay and the with proper set-up and hold times. in many different ways over the years. maximum clock delay plus the hold The next possibility is that the signal You can use anything from a manual time to see if the hold time is met. may miss it completely and get approach (i.e., using spreadsheets and This is straightforward but time-con- caught on the next clock edge (see a drawing program or just pen and suming. What you need to do is to cal- Figure 2b). (Note that this can be a paper) to what I refer to as semimanu- culate each of the signal paths going problem if you don’t want the per- al CAD programs. You can also use to flip-flop B, for instance. The advan- formance penalty.) fully automatic static and dynamic tage of using a spreadsheet is that it The last possibility is that the input timing-analysis tools. saves you time when making changes signal changes inside of the set-up and I am visually oriented like most to the design. A combination of a hold window (see Figure 2c). What engineers, so I prefer to draw my timing spreadsheet and a drawing seems like happens in this case? The output of diagrams. For the first board I devel- the right way to go. the flip-flop can become metastable, oped, I used my schematic drawing I’m familiar with two popular semi- which means that the output can tool to draw the timing waveforms. For manual timing analysis products: oscillate from zero to one or from one to zero a few times (or many times) before it stabilizes to a zero or one. The resulting state is random. (For more information on metastability, refer to H. Johnson and M. Graham’s book, High-Speed Digital Design: A Handbook of Black Magic). Obviously, this is not a good situation, because the output of the flip- flop may be wrong, and it may take longer than the normal propagation delay to get to the wrong value. Knowing thatWWW.GiURUMELE.Hi2.RO you have a problem is the first step. So, how can you fix it? There are many ways to solve timing problems. In this simplified circuit, you are off by 1 ns. You can change either logic gates 1 or 2 so that they are faster parts. Another option is to select a flip- flop that has a smaller set-up and hold window. Timing analysis doesn’t fix the problem; it just tells you that there Photo 1—I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray is a problem. Remember, when you areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 29 SynaptiCAD’s Timing view in the diagram editor win- Diagrammer Pro and Forte a) dow and shows the areas of tim- Design’s Systems ing uncertainty. TimingDesigner. These two prod- Timing Diagrammer Pro ucts are roughly similar. The CLK allows you to use libraries of T T timing diagrams in this article SU H timing values for parts. Thus, use Timing Diagrammer Pro. you can reuse some of the work

The Timing Diagrammer Pro D that you’ve (or someone else) is a timing analysis tool done already. designed to assist the digital Q designer in modeling and ana- b) DESIGN SEQUENCE lyzing digital circuits. (Another D You now know how to use tool from SynaptiCAD is Timing Diagrammer Pro to per-

Waveformer Pro, which also Q form timing analysis, but how allows you to export waveforms c) can you use the tool in a real as VHDL or Verilog for simula- project? The following sequence tion purposes.) It has two main D has worked well for my team for Q State windows for analysis, the first unknown a number of design projects. of which is the diagram editor First, capture the interface window where you draw the specifications in Timing waveforms. There are special Figure 2a—Data arrives before the set-up time requirement. Data is Diagrammer Pro with all of the tools to help with clocks, and clocked into the flip-flop on the rising edge of CLK. b—Data arrives after timing constraints shown. An you can create waveforms from the hold time, which results in the data being clocked into the flip-flop on interface is any part of the design the next rising edge of CLK. c—Data arrives within the set-up and hold other waveforms. You can do window, which results in an indeterminate output from the flip-flop. that interacts with another part, so with a Boolean equation— such as a write cycle from a (SIG0 and SIG1 and SIG3) delay microprocessor to a memory and 20 ns—or it can be specified using the waveforms. Initially, there are no a connection to a PCI bus. These inter- VHDL or Verilog. The other impor- delays or constraints; you don’t have face specifications form the basis for tant window is the parameter win- to be accurate at first, because the subsequent design decisions; they may dow, which is like the aforemen- accuracy comes when you add the give the designers an early indication tioned spreadsheet; it holds the tim- delays and constraints. as to whether the design is feasible, ing parameters of the design. The Second, you need to add the delay impossible, or sheer lunacy. For power of Timing Diagrammer Pro is and constraint information to the instance, if the interface specifications that the parameter values and the waveforms; this will automatically dictate that you will have to use a timing waveforms are linked. add the delays and constraints to the 34-ps SRAM, you’ll probably try to get parameter spreadsheet. Then, enter on another design project! TIMING DIAGRAMMER PRO the exact minimum and maximum As the design progresses, put real tim- Performing a timing analysis using numbers for the delays and con- ing numbers into Timing Diagrammer Timing Diagrammer Pro is straight- straints in the parameter spreadsheet. Pro, which will immediately tell you forward. First, you need to draw in Doing so automatically updates the if the constraints are still met. At

Set-up time calculation Data delay Clock delay Timing parameter Minimum (ns) Maximum (ns) Timing parameter Minimum (ns) Maximum (ns) CLK A or CLK B to Q delay 2 5 CLK A or B period 40 40 Propagation Delay1 through logic gates 3 15 CLK A to B delay 1 3 Propagation Delay2 through logic gates 5 12 WWW.GiURUMELE.Hi2.RO Minus D input setup time to CLK1 10 10 Total data propagation delay 10 32 Time from CLK to CLK1 accounting for set-up time 31 33 Slack for set-up time –1 Hold time calculation Data hold Clock delay Timing parameter Minimum (ns) Maximum (ns) Timing parameter Minimum (ns) Maximum (ns) CLK A or CLK B to Q delay 2 5 CLK A to B delay 1 3 Propagation Delay1 through logic gates 3 15 D input hold time after CLK B 6 6 Propagation Delay2 through logic gates 5 12 Total data hold time beyond CLK B 10 32 Time from CLK to CLK1 accounting for set-up time 7 9 Slack for hold time 1 Table 2—For the simplified circuit, the set-up time slack is equal to the minimum clock delay minus the maximum data delay. The hold time slack is equal to the minimum data delay minus the maximum clock delay.

30 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com problem, we hooked up the logic analyzer to see what was going on. At first glance, the timing looked fine, and we scratched our heads. But just before we went home late that evening, one of the ASIC designers said that he found it funny that the first write cycle that had worked was the only one that worked. It would have been nicer if he had mentioned that earlier! When we returned to the lab the next day, we concentrated on looking at the second and subsequent write cycles. One of the control signals to the ASIC was rising at the same time as the clock. Our hypothesis was that Photo 2—Note the width of the Board Clkout signal. This is the result of it being an ordinary buffer that is heavily loaded on the board. Again, red indicates a timing violation. the timing wasn’t OK. We decided to try moving the clock signal in time by delaying the clock. some point, there may be more than instance, if the elements in the simpli- We initially did this by adding a long one option. Using this tool, you can fied circuit depicted in Figure 1 are in wire to the clock signal. As a result, model each of the possible solutions one FPGA, it is less likely that the the write cycle worked! Well, it most- to determine if they work. If they do data path will exhibit a maximum ly worked. Next, we used a footprint- not work, then redesign, whether that delay and the clock path will exhibit a compatible buffer, which was slower means simply changing to a faster minimum delay. This is because they and seemed to work well enough for component or a completely new cir- are in the same part, and delays on a the card to be used by the SW develop- cuit. An alternative might be to chip tend to track each other. The data ers and other testers to continue with change the original requirements, path may be at the maximum delay their work. However, it didn’t explain assuming that your customer allows but the clock delay will be too. For exactly what was wrong. Why was the you to do so. Don’t count on it! most other cases, however, it is best to control signal so close to the clock sig- When it comes time to review your use worst-case timing numbers. nal? Why hadn’t we seen this on the design prior to building your PCB, for previous version of the card? instance, if the Timing Diagrammer A PROBLEM SOLVED We went back to the timing analysis Pro files are up to date, you have proof At a former employer of mine, we for the previous version of the card, and that your design will meet the timing had a problem with a card we were it showed that there shouldn’t have been requirements. Note that if your circuit working on. We couldn’t write to some any problems. On closer inspection, has critical timing paths, you may of the address space in one of our however, we noticed that the analysis want to include PCB delays in the ASICs on a new spin of the card. So, was done to the wrong clock edge. When timing analysis as well. after playing with the software to make the timing analysis was changed to sure that it was not the cause of the the correct clock edge, it immediately AUTOMATIC CAD TOOLS ASIC designers have been using static timing analysis tools for a long time. Synopsys’s Primetime is an example. The tools go through the entire design and determine if there are any timing violations (with some constraints from the user to minimizeWWW.GiURUMELE.Hi2.RO false paths). There are static timing analysis tools for board-level design, as well (e.g., BLAST, which was developed by Innoveda). These tools generally cost significantly more than Timing Diagrammer Pro and Timing Designer. What if a tool shows that you are in error? Is this always true? You may say that timing analysis is too pessimistic Photo 3—I used a zero-delay clock driver. The area of uncertainty on this clock is significantly less than the Board and, at times, you may be right. For Clkout signal in Photo 2. Notice the lack of red this time. It works!

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 31 flagged that there was a problem. we had solved a few other problems RESOURCE Why wasn’t there a problem with with the ASIC, the board worked. the previous version of the card? After Photo 2 shows the timing analysis H. Johnson and M. Graham, High- talking to the software folks, we found for the circuit with the old clock Speed Digital Design: A Handbook out that the same write cycle on the buffer. Photo 3 depicts the timing of Black Magic, Prentice Hall, previous version of the card didn’t analysis with the zero-delay buffer. (I Upper Saddle River, NJ, 1993. work either! They had found a way used Forte Systems’s Timing Viewer, around it, so they didn’t complain too because the analysis was performed loudly. At that point, we knew that in Timing Designer.) SOURCES we had a problem that needed to be Timing Designer solved on both circuit cards. The prob- CONVINCED YET? Forte Design Systems lem with the timing in the circuit was I hope I’ve convinced you of the (800) 585-4120 that the clock was being delayed quite importance of timing analysis, which www.forteds.com a bit because of the load on the clock. you can now perform manually or with The new version of the card added two a semiautomatic CAD tool. Remember, BLAST more loads to the clock line, which, whether you have a design running at Mentor Graphics Corp. (Innoveda) in turn, caused the clock to rise more 1 MHz or 1.5 GHz, timing matters! I (800) 547-3000 slowly and arrive coincidently with www.innoveda.com the control signal. Philip Nowe earned a Bachelor’s in PrimeTime We looked at the buffer and found Engineering at Carleton University in Synopsys, Inc. another part that was a zero-delay Ottawa, Canada. He has been work- (800) 541-7737 buffer, which meant it had a PLL in it to ing in the hardware design industry www.synopsis.com synchronize the output clocks with the for the past 20 years. He has experi- input clock. We put the timing numbers ence in board design, PLD/FPGA Timing Diagrammer Pro and from the new part in the timing analy- design, and hardware management. Waveformer Pro sis, and it worked. We then dead-bugged Currently, Philip is a digital design SynaptiCAD, Inc. the part on the board, which was not an consultant. You may contact him at (800) 804-7073 easy feat with a number of BGAs. After [email protected]. www.synapticad.com

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Pure Digital Audio Build An All-Digital Amplifier CONTEST ENTRY What do you get when you lock a group of engineers, a PIC16F877, and various audio parts in the same electronics lab? Just what you’d expect—an intelligent design that will enhance any home entertainment system without breaking the bank. Follow this step-by-step article, and you’ll soon have a powerful, all-digital audio amplifier for your home entertainment system.

Over the past few years, a number channels); it performs optional mixing outputs of the DDX-4100 to power lev- of digital audio technologies have and bass redirection, and produces up els that can deliver up to 35 W per chan- matured to a point that makes it pos- to four two-channel I2S streams. nel, or the sections can be paralleled to sible to build a powerful, low-cost sur- The Apogee DDX-4100 digital audio create a single channel of up to 70 W round-sound processor and multichan- processor accepts one or two I2S (into 4 Ω). It includes built-in thermal nel power amplifier. These technolo- streams, and it can accept S/PDIF and overload and short-circuit protection, gies include single-chip implementa- AC97 streams directly. The DDX- and operates from a single supply of 9 to tions of several key functions. 4100 performs optional sample-rate 30 V. The DDA-2060 is so efficient (88% The Crystal/Cirrus CS8415A receiv- conversion followed by digital signal minimum) that the only heatsinking er handles multiple S/PDIF, TOSLINK, processing (bass redirection, equaliza- needed can be built into the PCB’s art- and AES/EBU inputs by performing tion, and surround-sound processing). work—about 5″ squared of 2-oz. copper. signal switching along with clock and Finally, it outputs the audio on its five And last, but certainly not least, the data recovery. The Philips SAA2505H DDX (three-state PWM) outputs or as Microchip PIC16F877 provides the DUET input processor decodes PCM three I2S streams. means to control the system through (two channels), MPEG (one to eight The DDX-2060 two-channel digital its I2C bus. It supports input from channels), or Dolby AC-3 (one to six power amplifier converts the PWM both an IR remote control and a front- panel keypad. System status is displayed on an alphanumeric vacuum- fluorescent display. 28 V DDX2060 Power supply Center For our senior design project at 5 V DDX4100 Digital IR 3.3 V power Camosun College, we decided to pull PIC16F877 On/off controls DDX Receiver amplifier Control Digital Effects these technologies together into a VF Display processor audio highly integrated, easy-to-use unit for 4 MHz processor Digital Push buttons DDX power home-theater applications. We also Subwoofer amplifier (bridged) decided to enter the project in the 2002 Mad Dash for Flash Cash DDX2060 EEPROMWWW.GiURUMELE.Hi2.RO 2 Microchip PIC design contest. I C DDX2060 TO SLINK The project required us to solve Digital Left #1 I2S DDX I2S power interface problems, overcome noise in TO SLINK Digital Digital Digital amplifier #2 I2S Right audio 40.5 audio audio the data lines, come up with a suitable S/PDIF #1 receiver decoder I2S processor DDX MHz Digital Left user interface, and design a power sup- S/PDIF #2 power surround Right ply capable of supporting it all. Figure 1 CS8415A SAA2505 DDX4100 amplifier surround DDX2060 shows the solution we came up with.

Figure 1—We combined the Microchip PIC16F877, Crystal/Cirrus CS8415A, Philips SAA2505H, and Apogee DDX4100 and DDX2060 to produce a powerful seven-channel, all-digital audio processor and amplifier. The unit DIGITAL AMPLIFICATION accepts linear PCM stereo signals, compressed multichannel MPEG, or AC-3 streams, and drives six full-range Applying digital technology to audio speakers at up to 35 W each and a seventh subwoofer channel at up to 70 W. entertainment equipment affects three

34 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com broad areas. First, digital signals are The DDX4100 processor produces a desired signal, the noise is amplified easy to multiplex, making it easier for three-state PWM signal that is passed to along with it and appears at the output. a single interconnect cable or optical the DDX2060 power amplifier, which, The digital approach avoids noise by con- fiber to carry stereo linear PCM sig- in turn, applies positive supply volts, 0 V, verting to analog at an extremely high nals, compressed MPEG, or AC-3 or negative supply volts to the output power level and then using only coils streams representing up to seven or filter. A bridge configuration of the out- and capacitors in the output filter. The eight channels. Metadata is easily put drivers ensures that the peak output only possible sources of noise are the combined with the audio data so that voltage is precisely symmetrical by con- power supply and output power transis- a piece of equipment can readily iden- necting the same power supply in two tors. There’s also a possibility that the tify the type of signal being presented. different ways to the output pins. filter coils pick up stray magnetic fields, Secondly, digital signals are easy to Analog circuits suffer from nonlinear- but this can be controlled. manipulate and modify, thanks to ities primarily because of the semicon- Analog audio power amplifiers typi- advances in digital signal processing. ductor devices used in the signal path, cally operate in a Class AB mode in Simple functions such as volume control, which are not inherently linear. This is order to strike a good balance between equalization, and bass redirection (for usually reduced, but not eliminated, by efficiency and distortion. However, the satellite/subwoofer setups) can be com- using large amounts of negative feed- maximum efficiency of a Class B bined with more advanced functions back. The digital circuit eliminates this amplifier is 50%, and the further a such as MPEG and AC-3 decompression by operating the power devices at just Class AB amplifier moves away from and surround-sound decoding. In many one value when on or off completely. Class B operation, the worse it gets. ways, it is easier to preserve the overall The only remaining nonlinearities arise The digital power amplifier operates its audio quality in a digital-processing chain from the finite slew rate of the output output devices in either a full-off or than in an analog chain. Some functions devices interacting with short pulses. full-on state, which means that either can’t be done in the analog domain at all. Analog circuits, especially those the current through the device is zero The remote control of signal manipu- dealing with low signal levels, can pick or the voltage across it is extremely lations is another consideration. With up noise from the environment or even low. Because the power dissipated by an analog signal-processing chain, from their own devices (e.g., resistors and the device is the product of the current motorized potentiometers or digitally transistors). After it’s combined with the through it and the voltage across it, the controlled variable resistors value is low in either case. An are required. The former are overall efficiency of nearly a) expensive, while the latter are 90% is readily achievable. I2S Control difficult to use without cou- DDX Five channel pling the control signals into S/PDIF SPECIFICATION the audio path. A digital chain Sample Digital The devices and audio I2S MUX rate signal avoids these issues and pro- converter processor input format mostly deter- AC97 vides the greatest flexibility in mine the audio performance user interface design. Six channel specifications. Follow the sig- Phase- 2 Ext. I S in three pairs locked Finally, it is easy to increase Ref. nal chain backward from the loop the power level of a digital sig- speaker terminals to see how nal to speaker levels with high these play together. efficiency without introducing b) Left ∑ Left The DDX2060 output audible distortion. This side- devices provide two channels steps many of the issues asso- Center Center that each can handle a power ciated with conventional D/A Right ∑ Right supply of 9 to 30 V and a max- converters and analog power imum output current of 5 A amplifiers. Left surround Left surround (short-circuit limit). The out- Optional matrixing Staying in the digital domain Right surround Right surround put power rating of 35 W for as long as possible avoids translates to 16.7 VRMS and WWW.GiURUMELE.Hi2.ROBass Ω many of the problems of con- redirection mix 2.1ARMS across an 8- load, or ventional analog circuits. Low-frequency 24 V and 3-A peak for a sine ∑ Subwoofer These problems include non- effects wave signal. The two chan- linearities, noise, and the wast- nels of a single device can be Figure 2a—The DDX4100’s basic signal flow is simple. Included are sample ing of power. DDX technology rate conversion to 48 kHz and digital-signal processing. Five of the output chan- operated in parallel in order to takes this to its ultimate con- nels are available in the proprietary DDX format. All six are available as conven- double the current capacity, clusion by performing even the tional I2S signals. b—The DSP functionality includes bass redirection, phantom which means that up to 70 W power amplification in the dig- center, tone controls, parametric equalization, and volume controls for six chan- can be delivered to a 4-Ω load. nels. The center and low-frequency-effects channels are only available when ital domain and using a passive There are not a lot of details using the AC97 input, so they are shown as dotted lines. Similarly, the center low-pass filter for the final output channel is only available via I2S. There is an optional matrixing function available about the DDX three- digital-to-analog conversion. between the surround channels that supports side-firing speakers. state PWM signal, but it

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 35 Figure 3—The PIC16F877 is the centerpiece of the design. We can control the entire system through the microcontroller’s I2C bus.

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36 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com appears to switch at a rate of 384 kHz Power-up six channels in AC97 format. If neces- nominally, which is eight times over- Text scrolls on sary, the digital audio processor sample WELCOME TO sampling for an audio signal sampled at DOLBY DIGITAL ! rate converts the audio to the 48-kHz 48 kHz. Presumably, a relatively high- output rate used in the DDX process. EEPROM Displays for 3 s if order noise shaper is used in the LOADED up arrow is pressed. You can use a configurable DSP to

DDX4100 processor to move the quan- VOLUME = 88 *****MUTE***** implement volume control, tone con- tization noise away from audio frequen- VOL– VOL+ > trols and parametric equalization, phan- SYSTEM SHUTDOWN cies. The overall specification given in BASS CONTROL: tom center channel processing, and bass GOODBYE ! the DDX2060 datasheet is 0.08% typi- redirection for an independent subwoofer cal THD+noise at an output power TREBLE CONTROL: channel. The chip can output up to five level of 1 W and 0.33% typical at 30 W. BALANCE CONTROL: channels of audio in the DDX format, The power efficiency is given as 88% which is suitable for directly driving DELAY: 54 msec SOUND CHECK… typical, which means that a device sup- DEL+ > DEL– > DDX amplifier chips, and up to six chan- plying a total of 70 W to one or two loads nels in I2S format for additional process- CHANNEL SELECT LEFT SPEAKER only dissipates about 10 W. Because most CHANNEL: CH.1 ing or conventional D/A conversion. program material has a low duty cycle The chip includes a PLL for clock CHOOSE INPUT: RIGHT SPEAKER with respect to full-power operation, STEREO: < DOLBY:> multiplication and distribution that can the minimal heatsinking of the output SUR. VOLUME: 75 be driven by internal or external refer- LEFT SURROUND devices is required, and it can be built VOL– < VOL+ > ences. All of the features of the chip 2 right into the PCB artwork. Apogee has LFE VOLUME: 62 can be configured via an I C interface. RIGHT SURROUND an entirely separate document devoted VOL– < VOL+ > The amplifier is intended to be able to this aspect of the design. [1] CTR VOLUME: 83 to handle multichannel audio formats CENTER SPEAKER As you can see in Figure 2, the VOL– < VOL+ > such as MPEG and AC-3. Because the RUN SOUND CHECK? DDX4100 digital audio processor incor- LFE SPEAKER DDX4100 cannot decode them, we also YES: < NO: > porates numerous functions: it accepts incorporated the Philips SAA2505H up to two channels of audio informa- Figure 4—It helps to create a diagram that shows all DUET audio processor, which includes tion in S/PDIF serial digital format, up of the possible displays on the VFD. Make sure they dual DSP cores running at 40 MHz that to four channels in I2S format, or up to proceed in a logical sequence. can decode both formats in addition to

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www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 37 handling conventional stereo PCM. Its ing left, right, up, and down. The seven front of the display in order to see the I/O capabilities include two I2S inputs buttons on the universal IR remote con- characters. Even a small variation in the (up to four channels of PCM audio, or trol are used to provide the same inputs. angle can result in the appearance of MPEG/AC-3) and four I2S outputs When the amplifier’s power is off, the faded characters (or they can disappear (eight PCM channels). Furthermore, it only possible input is to press the Power completely). A VFD is used in most has an auxiliary S/PDIF output and is switch on the front panel or on the VCRs, microwaves, and other home controlled by an I2C interface. remote, which powers up the amplifier appliances. The VFD’s brightness and The SAA2505H also provides audio and puts the controller in its main loop. clarity allow you to see the display clear- processing functions, some of which In the main loop, the Power, Menu, ly from across a room and at any angle. overlap with the capabilities of the Mute, and volume control functions We used a Noritake VFD. The 2 × 16 DDX4100: low frequency enhancement, (i.e., the left and right arrows) are display module is a drop-in replace- bass redirection, karaoke voice mixing, immediately accessible. To change ment for a typical LCD module (see dynamic range compression, adjustable any amplifier parameters other than Photo 1), which means that we didn’t time delay for center and surround volume, the Menu button activates a need to modify software (or our circuit channels, digital word length reduction, series of submenus for bass, treble, diagram) to use the VFD module in audio mute, and error concealment. balance, delay, input channel, input place of an LCD. Finally, to provide a flexible array of mode, surround volume, LFE volume, Most standard LCDs (as well as the input options for the amplifier, we center volume, and channel test. Each VFD from Noritake) conform to the included the CS8415A digital audio submenu displays an appropriate title HD44780 model of operation. The receiver chip, which can select AES/EBU, and the current value of the parame- HD44780 is an Hitachi LCD con- S/PDIF, or TOSLINK signals from up to ter, which you can modify using the troller/driver. Its specification outlines seven sources. In addition, the chip can arrow keys (see Figure 4). initialization procedures for an LCD perform clock recovery, separate the DDA users appreciate having a visual module as well as the necessary func- audio data from the auxiliary data chan- confirmation of the changes they make tions to transmit data for character dis- nels in the digital stream, and provide the to user functions. We chose a VFD play. This specification contained more audio on an I2S output and the auxiliary module to implement the user display information than we needed to initial- data via its I2C control interface. We because it offers several advantages over ize our display and send data to it. attached S/PDIF (RCA) connectors to an LCD module or backlit LCD. An Instead, we used the procedure for inter- two of the inputs and TOSLINK (optical LCD must be viewed up close, at eye- facing to Hitachi HD44780-based LCDs fiber) receivers to another two inputs. level, to see the characters. A backlit that Myke Predko outlines on his web LCD improves viewing, although you site (www.myke.com/engres/lcd.htm). USER INTERFACE still need to be more or less directly in We interfaced the PIC to the VFD To pull all of these func- via four data lines. The tions together and provide a VFD is also capable of unified user interface, we used Switching eight-line communication, a PIC16F877 microcontroller, regulator To microcontroller but that would require 5 V particularly because of its From microcontroller logic on/off eight of the PIC’s pins to be H-Bridge on/off large amount of program Switching dedicated to VFD commu- memory and abundance of I/O regulator nications. Using the 4-bit 13.5 V from 5 V pins (see Figure 3). Our code rectifier/filter To digital mode allowed us to reserve audio signal path uses approximately 6 KB of Switching four additional pins on the the 8 KB available in program regulator PICF16877 for future use. 3.3 V memory and all but five of the Because of the limitations

I/O pins. It talks to the audio Switching LDO of instruction encoding, the chips via I2C interfaces in regulator regulator program memory in the 29 V 27.5 V order to determine what kind PIC16F877 is divided into of signal is coming in and to four logical sections, each of WWW.GiURUMELE.Hi2.ROSwitching LDO configure the audio chain regulator regulator which is capable of storing 29 V 27.5 V appropriately. In addition, it 2048 words of data. After 34.5 V from To output drivers accepts user commands via rectifier/filter Switching LDO our program’s code became both a set of front panel push regulator regulator so large that it crossed one 29 V 27.5 V buttons and an IR receiver, of the boundaries, we had to and it displays settings and rearrange it so that it would Switching LDO status via a front panel vacu- regulator regulator still operate properly. The um fluorescent display (VFD). 29 V 27.5 V problem occurs because the The front panel has seven Figure 5—The power supply includes two-stage regulation to produce clean power PIC CALL and GOTO instruc- buttons: Power, Menu Select, for the audio output drivers. It also includes features such as software control and tions can only hold the low- Mute, and four arrows point- brownout detection. order 11 bits of the destina-

38 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com tion address, which gives 2048 (211) mem- run ground lines in parallel between formats and protocols such as PCM, ory locations that can be accessed direct- data and clock lines as a means of can- SPDIF, and I2S. ly. Whenever one of the instructions is celing out crosstalk. Wherever it is not We spent approximately three weeks executed, the upper two bits of the 13-bit possible to avoid crossing signal lines, on the design and implementation of the program counter are loaded from bits 4 be sure to do so at a 90° angle so that decoder test board containing the audio and 3 of the PCLATH register. [2] the two lines do not couple magnetical- receiver and decoder. Unfortunately, When our program grew to more than ly (they cancel out). Additionally, if no after testing the implementation, we 2048 words, it crossed over to the next ground plane is opposite this point in were unable to produce an audio output. page of program memory. In order to the circuit, use ferrite beads to span Various audio formats were attempted jump from one page to a location on a the crossing of the connection. with no results. After five weeks of test- different page, it is necessary to first load Read all of the available datasheets ing, an application note from a Phillips PCLATH with the page number in bits 4 thoroughly. Make sure that you famil- distributor finally arrived containing and 3. We used a macro called LMCALL iarize yourself with the different audio information on initializing the to take care of this detail automatically.

IMPLEMENTATION The majority of the tricky problems we encountered involved the audio receiver, decoder, and main CPU along with its EEPROM. The proper integration of the units is crucial for ensuring good performance. The most important of our recommen- dations relates to the high-frequency data and clock lines. In our first design, we noticed a lot of audio distortion at the output whenever the unit switched from simple PCM format into the full six channels of Dolby decoded information. The distortion was traced to crosstalk and interference among the high-frequency data lines. The first PCB design didn’t take this possibility into consideration. A lengthy redesign of the circuit layout and routing of specific electrical connections enabled us to generate a clean audio output that’s free of distortion. More specifically, we recommend that you consider several points as you design the PCB. Carefully lay out the components to reduce the number of crossovers of their interconnections and limit the length of signal lines. Do not cross signal lines over power traces. If you need to cross the lines, place a ferrite chip over the connection. Use large crosshatched (grid) ground planes wherever possibleWWW.GiURUMELE.Hi2.RO in an effort to provide a clean reference to all of the signals at all of the points in the design. Run all critical signals over a continu- ous ground plane. This will create a Faraday cage effect and limit the pick- up of external noise. The clock lines from the decoder are of the highest importance and should be kept as short as possible to avoid interference. In the board-to-board cables,

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 39 SAA2505H. Two lines that we had left the chips when they were powered unconnected were tied to the appro- down while the I2C lines were not; it priate VCC or GND levels, and the caused the chips’ input protection SAA2505H began outputting audio diodes to conduct, and thus powered within minutes. The audio output up the chip. Consequently, we now from the SAA2505H was now ready to leave the 3.3-V supply on all the time send data to the DDX-4100 processors and only switch off the LCD. and digital amplifiers. One final feature required in the logic Another problem that we encountered Photo 1—The Noritake VFD is a drop-in replacement power supply was a brownout detector was not being able to interface the PIC’s for standard LCDs. It offers many advantages in line- for the DSPs. If the external power sup- I2C lines (5 V) to the DDX4100 lines powered equipment, where extremely low-power opera- ply ever drops to the point where the 3.3- (3.3 V). We solved the problem by using tion is not required. V regulator is unable to maintain 97% of a MAX3373E bidirectional converter. its output, a reset signal is sent to the ary winding on a toroid transformer. DSPs to hold them in Reset mode until POWER SUPPLY After full wave rectification, approxi- the power reaches an acceptable level The power supply for the project mately 13.5 V is sent to three fixed- again. Without this feature, the DSP underwent many different conceptual value switching regulators. We chose chips can lock up if a brownout occurs. forms, but we ended up with the one switch-mode regulators for their wide The H-Bridge portion of the power sup- shown in Figure 5. The design requires voltage input range as well as their ply provided the largest challenge in the three regulated voltage levels: 3.3-, 5-, high efficiency. There are two 5-V reg- design. One of the drawbacks of digital and 28-V lines. The 3.3- and 5-V sup- ulators and one 3.3-V regulator. One of amplification is its low (essentially non- plies are used in the logic portions of the 5-V regulators remains on and con- existent) power supply rejection ratio. the circuit. The 28-V line is supplied tinuously powers the microcontroller. Any variations or noise on the power to four different points to power the Originally, the other 5-V regulator supply line directly modulate the output H-Bridges in the Apogee DDX-2060 and the 3.3-V regulator were switched signal. The voltage to the output drivers digital power driver amplifier ICs. on and off by the microcontroller to must be exceptionally clean and well reg- The logic portion of the power sup- manage the power to the audio cir- ulated. These four lines are required to ply feeds originates from a 9-V second- cuits. However, we had problems with source up to 12 A of peak current when

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40 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO WWW.GiURUMELE.Hi2.RO the audio drives all the channels to full The DDA is a highly flexible audio Table Read,” AN-556, DS00556E, output. Therefore, we based the design system, thanks to its modular design. Microchip Technology, Inc., on a peak current of 3 A through each It’s a powerhouse in digital audio and Chandler, AZ, 2000. of the H-Bridge’s four branches. makes an excellent addition to any The 28 V originates from a separate home entertainment system! I RESOURCES higher-voltage toroid with 24-VAC sec- Apogee Technology Inc., Direct ondary windings. After rectification, the David Tweed was a contributing edi- Digital Amplification (DDX): voltage is approximately 34.5 V. We chose tor for this article. Pure Digital Sound from Source switch-mode regulators because they Yoon Cho holds a diploma from to Speaker, 2000. can handle input voltages up to 40 V. Camosun College, BC and is current- However, given the H-Bridge switching H. Behrends, “Application of the ly a third-year Computer Engineering speed, which is on the order of the 400 SAA2505 Digital Multichannel student at the University of Victoria. kHz, there would be undesirable interac- Audio Decoder IC (IIC-Control),” You may contact her at tions with the 260-kHz switching speed AN990000, 1999. [email protected]. of the regulators. To fix this problem, we R. Fischer, “Using the PICmicro used a secondary linear low dropout volt- Joe Huntley holds a diploma in MSSP Module for Master I2C age (LDO) regulator in series with each Technology in Computer Engineering Communications,” AN735, switching regulator. We adjusted the out- from Camosun College. He works as DS00735A, Microchip put of these regulators to provide a target a technologist at ESI Environmental Technology, Inc., 2001. voltage of 27.5 V, which is extremely Sensors, Canada. You may contact close to the ideal 28-V value. This allows Joe at [email protected]. National Semiconductor Corp., the necessary input voltage headroom for Greg Nuttall received a diploma in Webench PowerSimulation the LDOs (their maximum input is only Electronics Engineering Technology at WebSIM, www.national.com/ 29 V) while maintaining high efficiency. Camosun College. He currently works appinfo/webench/scripts/my_web The microcontroller controls the as a hardware engineer at Coincard ench.cgi. H-Bridge power supplies by using the International, and is a fourth-year enable pins on the switching regulators. Noritake Electronics Company, Electrical Engineering student at the The software specifically enables the “Vacuum Fluorescent Display University of Victoria. You may reach logic voltages first and then the H-Bridge Module Specification,” him at [email protected]. voltage after a short delay. This ensures GGM131A, 2000. that all logic is stable before the micro- Bryan Olson received a diploma in processor enables the audio output. Electronics Engineering Technology SOURCES The reverse occurs for the power-down from Camosun College. Currently, he DDX-2060 All-digital power ampli- sequence, ensuring a quiet power off. is a marine electronics technician at fier and DDX-4100 digital audio V.I. Radar. You may reach him at processor DESIGN FLEXIBILITY [email protected]. Apogee Electronics Corp. The Dolby Digital Decoder/Power Derek Richardson earned a diploma in www.apogeedigital.com Amplifier is a highly efficient digital Computer Engineering Technology from system that allows for the purest digi- CS8415A Audio receiver Camosun College. He is a third-year tal audio signal possible. There are Cirrus Logic, Inc. Computer Engineering student at the several ways in which this basic www.cirrus.com University of Victoria. You may reach design can be expanded. him at [email protected]. CU16026ECPB-W6J Vacuum fluo- The CS8415A digital audio receiver rescent display allows up to seven inputs, so you can GMA Electronic/Electrical add additional input connectors to PROJECT FILES Components Manufacturer’s support extra digital audio sources. To download the code, additional Representative Furthermore, you can change the out- WWW.GiURUMELE.Hi2.ROschematics, and photos go to www.gmarep.com put drivers to DDX-2100 chips (with ftp.circuitcellar.com/pub/Circuit_ suitable changes to the power supply Cellar/2003/160. PIC16F877 Microcontroller and heatsinking), which can supply up Microchip Technology, Inc. www.microchip.com to 50 W per channel, 100 W bridged. REFERENCES You can add support for the unused fea- Vacuum fluorescent display module tures of the SAA2505H to the firmware, [1] K. Korzeniowski, “Power Stage Noritake Co., Inc. including the surround-sound virtualiz- Thermal Design for DDX www.noritake-elec.com er, bass management and program down Amplifiers,” 13000003-02, mixing, and the MPEG 7.1 audio for- Apogee Technology, Inc., SAA2505H DUET Audio IC mat, which would allow up to eight Norwood, MA. Philips channels of surround sound. [2] S. D’Souza, “Implementing a www.semiconductors.philips.com

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 43 FEATURE ARTICLE by Aubrey Kagan Hierarchical Menus in Embedded Systems

What is the most efficient method for implementing menu structures in embedded systems? Aubrey had been mulling over this question for several months until he recently worked out a way to implement a hierarchical menu system that allows you to reuse software for displaying and changing parameters to save ROM space and achieve maximum flexibility.

In a 2002 article titled “Menu however, I will show you how to can display a series of options when Structures,” Robert Ashby made an implement a menu system that will the number of lines required for the appeal for some thoughts on a method- allow you to reuse the software for options exceeds the number of lines ology for implementing menu struc- displaying and changing parameters to on the display. Under some circum- tures on embedded systems with limit- save ROM space. More importantly, stances some of the options are not ed resources. [1] Like Robert, I also the approach will allow you to easily available. (Think of the grayed out thought that there seems to be a dearth change the flow of the hierarchy as selections in Windows.) Some of the of articles on the subject, and, as I pre- the customer and user change their options are merely lines of text, and pared a response to his request, I found requirements. some present data that changes peri- the basis for this article. [2] Several odically (e.g., time). Other options recent projects have allowed me to dis- HIERARCHICAL MENUS present parameters that may be till various methods into one consis- Intuitively, you already know how a changed under user control. There are tent approach for all of my future hierarchical menu system works (see different units within those parame- needs. This is my fourth attempt! Figure 1). The hierarchy of menus ters (e.g., seconds, percent, degrees As society has evolved, the devices must be defined at the beginning of a Celsius, and so on). you use have become increasingly project, because it influences the You should also ask yourself if it is sophisticated because more features approach taken and the flexibility at a desirable to change a parameter at any have been added. A microwave oven later date. Failure to do so, especially level of the hierarchy. Is it possible to has a fairly simple user interface, but if your customer doesn’t know what is place the parameter anywhere on a a VCR has several parameters that can possible, will entail additional work line? How can you cater to multiple be changed. Cost has dictated that you when your client discovers what can languages? Finally, check to see if you use simple display interfaces. Human be done. I have found that this have a timeout on the selection. How logic has allowed you to work with approach allows for changes of that easy would it be to update the software the limitations by presenting a series magnitude with relatively little effort. when the menu structure is changed? of options. A single selection allows You must address several issues The solutions to these questions are further refinement to the selection before beginning a design. First, you interrelated. Often, you cannot dis- process until you are left with a single must think about how you can select cuss one to the exclusion of another. parameter to change. This selection of an option on the display. After you Each project is unique, so presenting options is intuitive, but the actual have made a selection, how can you a generic approach is extremely diffi- implementationWWW.GiURUMELE.Hi2.RO can be confusing. The back out? Do you go up one level, or cult, if not impossible. I decided, for flashing 12:00 on many VCRs is evi- do you go all the way back to level 1? two reasons, to try explaining this dence of this. You must also think about how you approach while using a real example. Unfortunately, I cannot First, it seems to me present a method to create that talking about revo- a good human interface. Level 1 Level 2 Level 3 Level 4 lutions per minute is OptionLevel1 1 Aside from being subjec- OptionLevel1 2 OptionLevel2 1 more meaningful than tive, it also depends on the OptionLevel1 3 OptionLevel2 2 “Option1Level2.” In OptionLevel1 4 OptionLevel2 3 OptionLevel3 1 equipment being controlled, OptionLevel2 4 OptionLevel3 2 OptionLevel4 addition to immediately customer requirements, and OptionLevel2 5 OptionLevel3 3 recognizing a concept user opinion. In this article, Figure 1—Hierarchical menu selection isn’t a difficult concept to grasp. linked to a name, you

44 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com also notice other implicit information, Selection 1 Figures 3 and 4 show a portion of Selection 2 such as the value’s logical maximum. Selection 3 the menu hierarchy that I implement- Second, when you get to the software Selection 4 ed. Obviously, a real project would Selection 5 implementation, the code has already Selection 6 have many more screens. My project been tested and verified, and it is not Selection 7 had approximately 70 screens. A sys- a theoretical exercise. Figure 2—I’ve displayed a window containing four lines tematic approach is vital for the cod- from a larger screen. When the window includes ing, documentation, and verification OPTION SELECTION Selection 1, the up arrow disappears. When the window of the project. This project has several interface includes the last line of the screen, the down arrow disap- I numbered each screen (i.e., a collec- pears. The window will roll one line down when the left requirements: a 4 × 20 LCD; four arrow is in the last line of the window, when the down key tion of lines) for identification. A real input keys, which are used to control is pressed, and, of course, when the left arrow is not point- sequence of screens is unnecessary, the interface; and screens consisting ing at the last line in the screen. Similarly, the window will because the technique that I used of several lines of information. (The roll up one line when the left arrow is in the first line of allows this to be changed, if need be, the window, when the up key is pressed, and when left number of lines may exceed the num- arrow is not pointing at the first line in the screen. which was one of my original require- ber of lines on the display.) ments. I recommend using textual The keyboard contains four keys: indicate the new selection. identifiers associated with the numbers Menu, Enter, an up arrow (↑), and a The up and down symbols appear in (e.g., using the C macro #define to down arrow (↓). The Menu function is the rightmost character position on a establish the different screen numbers). used to initiate keyboard entry and screen line, and the left arrow appears A number of parameters have units, move the hierarchy up one level. The in the penultimate position. This and the units differ: several are in Enter key will complete a data entry means the text is limited to 18 charac- floating point, but others are integers, or accept a menu selection, as well as ters on a 20-character display. and some have discrete values with allow you to move down a level in the unique text (e.g., enabled or disabled). hierarchy and arrive at a parameter. MENU IMPLEMENTATION Consistency in the approach to modi- The up and down arrow keys are Five sublayers of hierarchy in the fication of parameters and the menu contextual, because they can be used menu and parameters, which can be structure will obviously lead to small- to alter parameters, but when there is set in any one of the levels, were also er program size; however, the real a menu selection to be made, the required in addition to several differ- world will conspire to defeat consis- selection pointer will move in the ent parameters that had to be changed. tency (no doubt a corollary to selected direction. If the pointer is at This required different approaches. Murphy’s Law!). the screen limit, then the screen will Depending on configuration options, Unfortunately, in order to explain roll in that direction. certain lines and parameters do not the software mechanisms, I need to A display larger than 2 × 16 intro- necessarily appear because the subse- familiarize you with the figures. This duces a problem. With smaller dis- quent lines are moved up a level. Note should help you understand the flexi- plays, only one chunk of information that multiple languages and a timeout bility of the approach. I have provided is visible. More information can be on keyboard entries are also necessary. only the software for the described presented on a larger display, but not enough for everything on a single Hierarchy Versn 1.xx screen. In order to view all Model X100 Screen 0 Dynamic Reading xx% of the information, the dis- 06.19.02 16:54 play screen should have a four-line window and must Menu be able to scroll up and down. Figure 2 depicts this SYSTEM STATUS Menu Screen 1 USER LEVEL principle. In order to indi- FACTORY LEVEL Enter DIAGNOSTICS cate that there is informa- BURNER CONTROLS WWW.GiURUMELE.Hi2.ROMenu tion above or below the Screen 2 CONTROL INPUT TYPE LANGUAGE CONTROLS Enter screen view, up and down SERVICE REMINDER arrows are added to the dis- FULL TANK BLOWDOWN BLOWDOWN CONTROLS BURNER 1: ENABLED BURNER 2: ENABLED play when necessary. LOW/HIGH RH ALARMS Enter ← DATE/TIME Screen 4 BURNER 3: ENABLED A left arrow ( ) is used to BURNER 4: ENABLED BURNER 5: DISABLED make menu selections. The BURNER 2 BURNER 6: ENABLED left arrow can move up and ENABLED Screen 5 down. When the pointer moves above or below the window’s limit, the window Figure 3—You can use the screens to change a binary parameter. When the Enter button is pressed, the selection indicated by must scroll up or down to the left arrow is processed.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 45 combinations; offering much more would confuse you beyond the point Listing 1—The messages, which can be entered in any order, are the same length—20 characters. of no return. const unsigned char English[20][30]= The piece of equipment is produced { as one of two models using the same //There are 30 messages below of 20 characters in one language controller. One model has three gas "HIERARCHY Versn ",//0 "MODEL X100 ",//1 burners. The second model, which is "Dynamic Reading ",//2 larger, has six burners. You can enable "SYSTEM STATUS ",//3 or disable each burner. Figure 3 "USER LEVEL ",//4 depicts the sequence to do so. In Screen 0, line 2, the model number is reported based on a configura- SOFTWARE REALIZATION associated number: tion setting. Line 3 includes a display Before I go into detail about my that continuously displays a change- implementation, I will provide you #define BURNER1 12 able reading. Line 4 is the date and with an overview of the software #define BURNER2 13 time derived from an integrated real- approaches that I used. Although I #define BURNER3 14 time clock. The colon, which func- used C, it can be easily implemented tions as a microcomputer activity in any language, but I hesitate to sug- The parameters are stored as an array indicator, flashes every second. gest that assembler is a viable option so they can be accessed using stan- In Screen 1, the FACTORY LEVEL for a full-blown system. Many projects dard array techniques (e.g., parame- line is visible only when the unit is do not have the RAM or ROM to sup- ters[BURNER]). being configured in the factory (see port this approach in its entirety. It is Each parameter has a number of Photo 1). In Screen 2, the LOW/HIGH possible to use a reduced approach, constants associated with it that RH ALARMS line is visible only keeping in mind that you must tabu- determine how it can be changed (i.e., under certain conditions. late everything, because it allows for maximum value, minimum value, and Depending on the model type, there versatility in making changes. step value). A fourth parameter is the are either three or six burners displayed Whenever there is a parameter on default value, which is normally used on Screen 4. Depending on the configu- the screen, it is incremented or decre- when the unit is first initialized. The ration, they will display as enabled or mented subject to upper and lower constants are stored in four constant disabled for each of the three or six bounds. In addition, some parameters arrays. During parameter modifica- burners. Figure 4 describes a sequence have a fairly wide range; so modifying tion, while incrementing, the value of to change a parameter that can vary them by one for each key press is the parameter is not permitted to between limits. Note that the parameter impractical. Holding the key down exceed the maximum. Similarly, the changes at a different level in the hierar- will increase the value every 0.5 s by minimum defines the parameter’s chy than the disable/enable of burner 2 units, and then tens, hundreds, and lowest possible value. The step value on the extreme right of Figure 3. thousands. The transition from units is the amount the parameter changes, All of the displayed messages are to tens (and so forth) occurs every 5 s. because the granularity of some based on the setting of a language parameters is not one. parameter. Although not implemented PARAMETER DEFINITION in this article, the option is visible on I organized my parameters in a long MESSAGE LINES Screen 2 in Figure 3. list, and gave each one a name and an After I had defined and numbered all of the screens, I collected all of the possible lines of text. In C, it is possi- Hierarchy Versn 1.xx Model X100 ble to collect the text messages into a Screen 0 Dynamic Reading xx% list residing in a two-dimensional con- 06.19.02 16:54 stant array. For consistency and ease

Menu of processing, each message should be WWW.GiURUMELE.Hi2.ROof the same length. With multiple lan-

SYSTEM STATUS Menu guages I could have used a three- Screen 1 USER LEVEL FACTORY LEVEL Enter dimensional array or three two-dimen- DIAGNOSTICS sional arrays. (The implementation of FACTORY LOCATION Menu C that I used ended up with a hybrid Screen 3 BLOWER RPM FAULT BLOWER RESPONSE Enter approach.) RPM TRANSITIONS CLEAR FAULT HISTORY Each line in the message list has a RPM TOLERANCE sequential index number associated RPM+/-: 0150 Screen 6 with it. This will make it easy to create a screen by grouping the index Figure 4—A different branch in a parameter selection has a variable parameter. numbers together to form a screen.

46 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com parameters should be calculated and

inserted in the appropriate places. Screen image The next step involves an investiga- tion of the line’s presence. If the line isn’t required, it’s deleted by shifting Display buffer up the lines beneath it. At a later stage, the image can be transferred Alternate image to the display buffer. The up/down and selection arrows are added when Figure 5—The image to be displayed is prepared in Photo 1—The FACTORY LEVEL option was removed necessary. RAM and then transferred to the display buffer. This from Screen 1, so the DIAGNOSTICS line moved up. I preserved the image in RAM until allows the image to be preserved while another message (e.g., an alarm or password entry) is displayed on a new screen image was required. This the screen. Creating and modifying screens only feature allows other data to supersede requires changing the index number the current display. For instance, if an groupings. The message lines can be alarm is present, it periodically flashes (through the second display buffer in entered in the program in any order so on the screen via a second display RAM). When the password entry is that adding additional messages does buffer in RAM. Outputting the origi- completed, it’s easy to return to the not introduce a sequencing problem. nal screen image without regenerating current display. All you need to do is This technique allows you to use a the screen restores it. Figure 5 demon- copy the RAM image back to the dis- single line in multiple screens. Lines strates this principle of operation. play buffer. In the interest of simplici- that differ by only a parameter and For this project, my customer want- ty, I didn’t include these features in variable (e.g., BURNER x: in Screen 4 ed the parameters to be visible as he the listings. and Screen 5 in Figure 3) can be one keys through the hierarchy. Note that As in all projects, you must decide on line that’s massaged to give the chan- parameters can be changed only after a certain limits. I opted for a maximum nel number and add the ENABLED or password has been entered. This of 10 lines in any particular screen as DISABLED in Screen 4, or the left approach allows the current screen be defined in the MAX_SCREEN_SEL blank in Screen 5. maintained in RAM while the display macro definition. To reiterate, only The @ character is an indicator used is occupied with password entry four of the display lines can be viewed when a parameter must be inserted; it’s needed when you’re using multiple languages, because the location of the variable is unlikely to be in the same place on the line. In English, for instance, the word “humidity” is eight letters long, and it would be followed by four spaces for a three-digit humidity number together with the percentage symbol (%). In German, the word is dampfleistung, so the placement of the variable would be much farther to the right. The processing of the line identifies and removes the symbol and inserts the value of the desired parameter starting at the desired location. The message list is depicted in Listing 1.

SCREENS WWW.GiURUMELE.Hi2.RO One of the requirements of this project is to ensure that if an option on a screen is not enabled, the line or parameter associated with the option is not displayed. One way to approach this is to create an area in RAM to produce the full screen image (along with some additional information) regard- less of whether or not the option is visible. The associated variables and

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 47 at any one time. The memory struc- the difference. (One of the lines in the cProcNum[ ] parameter is used to ture is shown in Listing 2. message array is a row of spaces.) define the action performed on the Each displayed screen requires some Some lines may need manipulation line when the message is copied to or all of the parameters to be filled in. to modify the initial message derived the RAM image (ProcessLine). Understanding these parameters is the from the list. For instance, the version When negotiating through the key to following what I have done. number is added to the message menus, pressing the Enter button cNumberOfLines is the parameter “HIERARCHY Versn” to produce line 1 takes you to a parameter for change or for the number of lines that make up on Screen 0 in Figures 3 and 4. The display. The parameter name (or a particular screen; it can be between four and 10. If there are less than four, the display bulks up by using blank Listing 2—Every screen must define most of these details to convey which messages are used, whether or lines. not arrows are needed, what the next state will be, and which parameter to alter. cArrowsRequired has to do with struct ScreenType { the number of necessary arrows. If the unsigned char cNumberOfLines; screen needs arrows, they will be unsigned char cArrowsRequired; added. If there are less than five lines, //Need to display selection arrows there won’t be any up or down arrows, unsigned char cMsgNo[MAX_SCREEN_SEL]; //Message to be displayed only the selection arrow. In other unsigned char cProcNum[MAX_SCREEN_SEL]; words, if this is a zero, a parameter //Process to be done on message will need to be changed. If it’s nonze- unsigned char cParamNum[MAX_SCREEN_SEL]; ro, there will be another menu screen //Parameter associated with line unsigned char cNextAction[MAX_SCREEN_SEL]; as the next level in the hierarchy. //Where to go when enter is pressed cMsgNo[] is the method by which unsigned char cAssociatedDisplay[MAX_SCREEN_SEL]; lines are grouped together to form a par- //What to display when enter is pressed ticular screen. A line index number //This can carry a number associated with the line, so that the lines can be //packed and still correctly identified (it could be eeprom address when the forms each element of the array. If there //line is actually a parameter are less than four lines, the lines should }; be padded with blank lines to make up

WWW.GiURUMELE.Hi2.RO

48 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com Autotrax TM Electronic Design Automation autodesk® authorised developer Schematic Capture SPICE Simulation PCB Layout Auto-Layout/Router 3D PCB Visualization

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To find out more go to www.autotraxEDA.com Over 25,000 new users in the last 12 months WWW.GiURUMELE.Hi2.ROFull version FREE to full time-students and schools/colleges (no limits) Free version available for small scale projects. (pin limited) 2.0 Why wait? Download AutoTRAX EDA NOW! It just gets Better! www.autotraxEDA.com address) as defined in the parameter variable iInterPhase in a switch Screens[] instantiation of the above list is entered in cParamNum[ ]. construction). When the Enter button structure as shown in Listing 3. As There should be an entry for each line is pressed, the next action is defined you can see, there are eight lines in in the display. With a parameter value by the cNextAction[ ] parameter the screen. The screen will require of zero, no parameter is used and a (DisplayInterfaceManager). the use of arrows. value of 255 (0xff) is for any unused If this is not a parameter modifica- The messages are grouped, and if line. Notice that all the 255 values tion screen, pressing the Enter but- you check the message listings you should be contiguous to the end of ton will invoke a new screen. will see that message 7 is BURNER the array line because this is used to cAssociatedDisplay[] will be the CONTROLS, and message 8 is CON- determine the end of the screen. display number that is invoked. There TROL INPUT TYPE, and so on to The flow of the software through should be an entry for each line in make up the display as shown in the hierarchy is set up as a series of the display. Screen 2 in Figure 3. states. (The numbers are used as the Now let’s consider part of the As you know, the LOW/HIGH RH ALARMS line is only displayed under certain conditions. Process 3 (in ProcessLine) analyzes these circumstances. There are no associated parameters (although there could be when the project is complete), so the values are zero, and the line is termi- nated by 255 (0xff) for the unused lines. After the Enter button is pressed for the BURNER CONTROLS line, the associated manager (DisplayInterfaceManager) will execute subtask BURNER_SELECTION_ENTRY. After the application is developed further, there will be other values for the remaining lines of the display. Finally, BURNER_SCREEN will be displayed if the Enter button is pressed on the line. Again, when the application is further developed, there will be other values for the remaining lines of the display.

CONTROL THE PROCESS A separate task, DisplayInterfaceManager, provides the user interface and controls what appears on the screen and when. It has many states, which are determined by the iInterPhase variable. Producing something on the screen is done in two stages. First, the screen image is prepared in RAM (CreateDisplay). At a later stage, WWW.GiURUMELE.Hi2.ROthe image that has been created is transferred to the display buffer with the arrows added (TransferDisplay). The separation of the tasks is necessary to simplify a refresh of the display when something simple is changed like the movement of the selection arrow. The keyboard is also monitored within these states to direct the selected displays. Finally, if a display screen has a

50 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com dynamically changing variable, it can to a parameter change, the selected as the Screens structure. The actual be updated as one of the states (e.g., parameter value (carried from the text is copied to the cLine array with- case INITIATE_DISPLAY+1 of the cParamNum constant defined in the in the structure. function). Remember that it takes Screens[] structure) is loaded into a Additional processing is performed time to write to the display, and the temporary location so the modifica- on the TransferMsg line for parame- display should not be updated faster tion can be ignored by pressing the ter values or other interpretation. If it than the update time, or you will only Menu button, which will return with- is determined that the line should be get partial screens. out modifying the parameter, rather removed, the cParamNum of the asso- At the outset, the initial display than the Enter button, which will ciated line is changed to 255. When image is created. After that, the user return after modifying the value. all of the lines of the particular dis- interaction is roughly the same, The up and down keys also are con- play have been processed, the next although the key entry may differ for textual. In a menu selection, a func- stage of the function (ProcessLine) different menu selections or changing tion (e.g., PointerUp, PointerDown) compacts the lines upward (based on different parameters. Even though I is invoked to move the selection whether or not cParamNum is equal to have tried to standardize two different arrow and the screen display if neces- 255) and overwrites any of the deleted kinds of entries for simplicity, the sary. In a parameter change, the up displays. At that point, the screen advantage of this method is that it is and down arrows modify a temporary image is created in RAM. possible to write numerous tasks to parameter (e.g., IncreaseParameter, At a later stage, another routine, allow almost any key sequence as need- DecreaseParameter). The value is TransferDisplay, locates the four ed. The disadvantage is that each sub- transferred back to the parameter lines to be displayed and copies them task increases the size of the program, when the Enter button is pressed and from the image to the display buffer. It especially because all keyboard inputs discarded when the Menu button is also analyzes which arrows are required must be considered in each instance. pressed. and adds them in the correct locations. When the menu selection leads to another menu, the process preserves GENERATE AN IMAGE HARDWARE IMPLEMENTATION the relevant details on a dedicated When a screen image is generated, At this stage of the game, I will stack (PushStack). When returning, some of the parameters from the drop down a level and become more the device (PopStack) returns to the Screens structure are copied to project-specific. Although the hard- selfsame display with the selection another structure in RAM (i.e., ware was developed around Rabbit arrow at the same menu entry. DisplayBuffer), as shown in Listing 4. Semiconductor’s RCM2020 module, I In the case of a selection that leads Most of the elements are the same have tried to make this approach as universal as possible. The RCM2020 module includes the Listing 3—I’ve included the full details for one line of the display. You can add the others as the application Rabbit 2000 microcomputer (a Z80 grows. derivative), 256 KB of flash memory, //USER_LEVEL_SCREEN 2-> Screen[2] and 128 KB of RAM all on a PCB 8, //Equals eight lines measuring less than 2″ × 2.5″. It also 1, //Arrows required includes I/O lines, an oscillator, and 7,8,9,10,11,12,13,14,0,0, //Message number facilities for battery backing up the 0,0,0,0,0,0,3,0,0,0, //Processes 0,0,0,0,0,0,0,0,0xff,0xff, //Associated parameters—0xff used to RAM as well as a battery-backed-up //denote line is to be blanked clock/calendar. This is a lot of func- BURNER_SELECTION_ENTRY,0,0,0,0,0,0,0,0,0, // tionality in a small, reasonably priced BURNER_SCREEN,0,0,0,0,0,0,0,0,0, // package. Rabbit manufactures and tests the module, which allowed me Listing 4—DisplayBuffer is the current display in a RAM image. The second element, to design a custom, low-volume, cScreenCreatedToGetHere, preserves the screen that was executed to generate this screen so through-hole board with all the advan- it can be regenerated if necessary. The third element, cLine, contains the text of all the message lines. tages of a dense SMD design. The WWW.GiURUMELE.Hi2.RORCM2020 is mounted on my design struct DisplayBufferType { //This is the memory for the displays sized for the maximum number of rows as a mezzanine board. The display module interface uses unsigned char cArrowsRequired; //Need to display selection arrows the standard Hitachi HD44780 proto- unsigned char cScreenCreatedToGetHere; //in order to recreate later col. I have implemented it as a 4-bit unsigned char cLine[MAX_SCREEN_SEL][21]; unsigned char cParamNum[MAX_SCREEN_SEL]; //Parameter associated with line data bus along with the three control unsigned char cNextAction[MAX_SCREEN_SEL]; //where to go when enter is pressed signals on the I/O pins of the Rabbit. unsigned char cAssociatedDisplay[MAX_SCREEN_SEL]; //Display to invoke when The keyboard input is multiplexed on //enter is pressed some Rabbit I/O pins and consists of }DisplayBuffer; four possible switch closures (or, of course, a combination of keys).

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 51 External logic provides the enable for comparisons on the ’Net between program as one long module. these switches. The software drivers Rabbit’s implementation of C to ANSI C In the version of Dynamic C that I for these are provided for complete- (groups.yahoo.com/group/rabbit-semi/), used, there was a restriction that con- ness, but they are not actually within but I’m not going address that issue. I stant arrays be placed in the lower the scope of this article. The basic have tried to keep with standard C; (i.e., root) 64 KB of flash memory. hardware connections are shown in however, Dynamic C does not allow With a large number of messages, the Figure 6. for classical multiple module develop- space in the root memory runs out ment. Using libraries in a manner quickly. The Dynamic C xstring DEVELOPMENT ENVIRONMENT similar to multiple modules must be function allows the strings to be The Rabbit development environment used to break down large programs. placed in extended memory. The is implemented on a PC and includes Rather than having to explain the xmem2root function then allows Dynamic C and a convenient emulator library construction (although it is access to the data as a three-dimen- interface to the RCM2020. You can find easy), I resorted to developing this sional array. Access to this routine is in the first section of the TransferMsg function. In Dynamic C, it is possible to change RAM locations while the program is running. This is advanta- geous for this program, because I have tried to remove it from my actual hardware, allowing simulation of switch changes through changing RAM locations.

USER INTERFACE The parameters in this application are grouped into two sets, user and factory. In the former, you can drill down the hierarchy and view a particular setting. In the latter, the option, and subsequent options and parameters, are only visible if a jumper is installed on the board. In order to change a parameter, it must be possible to invoke a password entry sequence at any point where a parameter is viewed. In this way, you can see a particular parameter’s setting, but only authorized users can change it with a password. The password entry sequence is not shown, but it could be introduced as a step in the keyboard decode when two keys are simultaneously pressed. This would then invoke an overriding sequence that would allow the pass- WWW.GiURUMELE.Hi2.ROword to be entered. IMPLEMENTATION I chose to implement the multitasking aspects of the project by breaking the structure down into tasks called “phases.” To select a task, I used a switch statement based on the iPhase variable (see Listing 5). In each task, a number of instructions are executed until a suitable break occurs to yield control back to the

52 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com next phase. In many cases, the task status bits; when one or more are Rabbit RCM2000 LCD may be divided into subphases and active, the associated line in RAM is perhaps subdivided even further. PD6 E output to the display. PD5 RS The tasks that are executed in this PD4 R/*W The keyboard process maintains a application are the display driver, the PD3 D7 buffer of three scans of the keyboard PD2 D6 keyboard interface, the display inter- PD1 D5 input. As a precaution against contact face manager, and the overall process. PD0 D4 bounce, all three must be equal for an The display driver deals with the analysis of the input. For any new key- tedious process of sending bytes to the board input, a timer is initiated so that Buffer display module hardware. The key- the keyboard timeout is refreshed. In PA7 ENTER board interface monitors key presses PA6 DOWN addition, when a key is held down, it PA5 UP and reports about the inputs. PA4 will periodically flag a valid input EN MENU Obviously, the display manager is the (typematic). After a number of these focus of this article. The overall flags, a variable is incremented to process substitutes for most of the Figure 6—As you study the basic hardware connec- allow the increment steps to be accel- other functions the processor would be tions, note that the enable for the keyboard buffer is erated. In other words, holding the key executing in the normal course of generated from some I/O lines and external logic. In down for longer than 1 s results in an events, which include, in this case, reality, several other groups of inputs are multiplexed increase of one followed by an addi- onto PA4–7. updating the system time and date. tional increase every 200 ms. The display driver is application-spe- After 10 typematic flags, an output cific. Initially, the display module must Although it is possible to address multiplier is changed, which allows be set to a particular configuration, each character on the display individu- increments of 10, 100, 1000, and which includes the 4-bit format, cursor ally, the driver software interfaces via 10,000. This task is used to control style, and data entry. Custom charac- an array in RAM for each line (e.g., the different timers. Furthermore, it ters (e.g., an up arrow) are saved as bit cBufferLine1[20]) and a bit on a creates the updated time/date and a patterns in the RAM on the module. status byte that requests an update of flashing colon between the minutes This provides a simple method of bring- the line (e.g., the WRITE_LINE2 bit on and seconds on the bottom line of the ing up these characters when desired. iStatus). The software scans the four display when the feature is enabled.

WWW.GiURUMELE.Hi2.RO

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 53 UTILITIES strategically place the _ENTRY in the capabilities of modern microcomput- Some utilities simplify the display DisplayInterfaceManager( ). ers have gone a long way to allay my generation. To write a percent value Writing your application can get reservations. I that is right-justified against the tricky. Make sure you understand the right-hand side of the screen, use the subtleties of the program before fol- Aubrey Kagan (P.E.) has 25 years of PerCent function. To insert a value lowing the aforementioned steps. experience designing electronic (left- or right-justified) starting on a industrial interfaces and controls. He particular line, use either the NO MORE HEADACHES earned a B.S.E.E. from the Technion, PasteLeft or PasteRight function. Over the years, the modification of Israel Institute of Technology and an To see how to combine these by insert- menus has given me many headaches. M.B.A. from the University of the ing a value at the @ symbol, refer to I hope that the system that I have pre- Witwatersrand. His diverse design case 9 of the ProcessLine function. sented here will preserve what is left of experience ranges from projects that Adding a menu item requires sever- my sanity and will reduce your devel- operated miles underground in a al steps. First, add the macro for opment and (especially) maintenance mine to 600 miles above the earth on _ENTRY phase, and then insert this times. I apologize to the C purists for the International Space Station. He is name in the sixth line (next process) using of so many global variables. I currently a senior design engineer for in the location associated with the guess all the assembly programming I Weidmuller Canada. You may reach entry in the screen definition. Next, have done has corrupted my style! him at [email protected]. check if MAX_SCREENS has been This section of the complete appli- exceeded, update, and add a macro cation uses 20 KB of flash memory _SCREEN to describe the new screen. and the messages use another 15 KB PROJECT FILES Insert this name in the seventh line for the three languages. The RAM To download the code, go to (associated display) in the location required amounts to 3200 bytes. ftp.circuitcellar.com/pub/Circuit_ associated with the entry in the These will place significant demands Cellar/2003/160. Screen definition. on a small system’s resources, The next step is to add the new mes- because many more menu entries are REFERENCES sages as necessary and sequentially likely and the rest of the application [1] R. Ashby, “Menu Structures,” number them. Following this, create a software needs to be completed. Most Chip Center, January 2002, new _SCREEN entry in the screen. of my early experience involved hand- www.chipcenter.com/eexpert/ (Pay attention to the number of lines, coding small microcomputers, so I am rashby/rashby054.html. arrows needed, parameters, and so aware that this is much larger than a [2] ———, “Responses to ‘Menu on.) If the message has a process minimal system can handle. Structures’ Article,” February associated with it, add a process However, the convenience of a high- 2002, www.chipcenter.com/ number (sequential) and the “case” in level language and the versatility of eexpert/rashby/rashby056.html. ProcessLine(). Finally, write or the approach along with the expanded RESOURCES

Listing 5—With simple cooperative multitasking, it is easy to add additional tasks by adding additional Rabbit Semiconductor, “Dynamic C cases. Remember to increment iPhase in every task. Premier: For Rabbit Semiconductor Microprocessors,” 020218-P, while (1) www.rabbitsemiconductor.com/docs/ { switch (iPhase) dcseries_doc.shtml. { case 0: ———, “RabbitCore 2000,” 001004- UpdateDisplay(); C, www.rabbitsemiconductor.com/ break; case 1: docs/rcm20_devkit_doc.shtml. WWW.GiURUMELE.Hi2.ROKeyboard(); break; case 2: SOURCES OverallProcess(); HD44780 break; Hitachi case 3: DisplayInterfaceManager(); (650) 589-8300 break; www.hitachi.com default: iPhase=0; RCM2020 RabbitCore break; } Rabbit Semiconductor } (530) 757-8400 www.rabbitsemiconductor.com

54 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO FEATURE ARTICLE by Danny Graves

High-Temperature Superconductor Overview

The expensive cooling processes needed to achieve the superconducting state can make using superconductors impractical. High-temperature superconductors, on the other hand, don’t need to be cooled as low, and are therefore less expensive to use. Danny’s review cov- ers the basics to get you started experimenting with high-temperature superconductors.

High-temperature superconductors more material and increased weight. (i.e., absolute zero). Absolute zero is and their characteristics simply amaze On PCBs, the conductive traces equal to –273.15°C. In kelvins, me. I hope people who read this arti- handle current just like wires in larger absolute zero is equal to 0K. Really cle will be inspired to experiment systems. If you need to handle more low temperatures are commonly with them. Eventually, I think some- current, you need to make the traces measured using the Kelvin scale, one will end up developing a room- wider or the copper thicker. Using developed by William Thomson temperature superconductor that thicker copper on PCBs increases the Kelvin in the nineteenth century, changes the world as we know it. cost. And using wider traces takes up rather than Celsius. In the 1980s, it looked as though we valuable space. If you don’t change to To liquify a gas, you must make it were on the brink of a technological thicker copper or wider traces when very cold. A liquified gas stays at its revolution with superconductors. The the current increases beyond the rec- boiling temperature until it has all advances made with high-temperature ommended limits for the PCB design, converted back to gas form. Therefore, superconductors (HTS) in the ’80s you run the risk of burning the traces liquified gases are a convenient way to were so amazing that Nobel prizes like a fuse or at least having hot spots cool other objects to very low temper- were quickly awarded to several super- on the PCB. atures. For example, liquefied hydro- conductor players. The term “super- Resistance in conductive traces lim- gen, helium, and nitrogen are 20.37, conductor” became a household word, its the minimum size of integrated 4.22, and 77.34K, respectively. At but the excitement has since waned, circuits. When you tightly pack the absolute zero, all molecular motion at least as far as the general public traces in an integrated circuit, you get stops. Absolute zero is not achievable goes. However, there’s still great to a point where the traces cannot be in the laboratory, although attempts potential for more advanced supercon- situated any closer because of manu- have resulted in temperatures as low ductor applications. facturing limitations, electromagnetic as 0.00000003K. These sorts of tem- issues, and so on. The next option is peratures are not practical. They’re ELECTRICAL RESISTANCE to make the traces smaller. You then useful only for research into the basic Resistance is the opposition to elec- get to a point where you cannot make properties of matter. trical current flow in a conductor. the traces any smaller because of the Electrical resistance results in heat current-handling requirements. SUPERCONDUCTORS generation. To this date, every room- Although the heat resulting from A superconductor is a material that temperature conductor has some electrical resistance is a nuisance in has zero resistance to electrical current resistance. SomeWWW.GiURUMELE.Hi2.RO conductors, such as many cases, some applications require when it is cooled to a certain tempera- gold, have lower resistance than oth- it. For example, electric heaters, sol- ture. The term “superconductor” was ers, but the resistance is still there. In dering irons, hair dryers, hand dryers, coined by Heike Kamerlingh Onnes in a simple, round wire, the resistance is and clothes dryers depend on the 1911. What’s the big deal about super- proportional to the length of the wire resistance of their heater elements in conductors? Electrical resistance caus- and inversely proportional to the order to generate heat. es things to be heavier and less effi- cross-sectional area of the wire. If you cient. In other words, it costs money. want lower resistance wire, you must TEMPERATURE REVIEW So, if you get rid of electrical resist- make the wire have a bigger diameter. There is no limit to how hot some- ance, you save lots of money. Making wires have bigger diameters thing can get. However, there is a Superconductors also exhibit costs more money because it requires limit to how cold something can get strange properties such as excluding

56 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com all magnetic fields from their interiors much higher temperatures than that perature superconductors such as (i.e., the Meissner effect). So what? of liquid helium. In fact, inexpensive YBCO is that they are brittle. It is dif- You can make magnets levitate! and easily obtainable liquid nitrogen ficult to make a flexible wire out of

Seeing this effect in action will shock (LN2) will sufficiently cool an HTS. the current HTS ceramic materials. In some people the way seeing a UFO or Liquid nitrogen has a boiling point of addition, ceramics cannot handle the Bigfoot would. It is truly a strange –196°C. That’s still cold, but much mechanical stresses of winding elec- effect. It is magic except there is no easier to accomplish than –273°C. In tromagnets. The brittleness is a signif- trickery by a magician. There is no Uri addition, nitrogen makes up 80% of icant hindrance to practical usage. Gellar spoon-bending trickery here. the air we breathe. So, other than the If you have some basic chemistry You get conductors to become dangers from the extremely low tem- experience and equipment, you can superconductors by cooling them. perature, LN2 can be handled safely. make your own superconductor pellet Many materials will superconduct if One of the most popular HTS mate- from scratch. You can download the cooled enough. The temperature at rials is yttrium barium copper oxide instructions from the web site for the which a material becomes a supercon- (YBCO). The lesser-known constituent Oak Ridge National Laboratory, which ductor is called the critical tempera- element, yttrium, is an abundant ele- is managed by UT-Battelle for the U.S. ture. Unfortunately, the critical tem- ment. YBCO is a ceramic material Department of Energy. Essentially, perature for most materials is often that is an insulator at room tempera- you combine the basic ingredients, close to absolute zero. ture. Yes, that is correct. It is an elec- which are fairly inexpensive, grind It is interesting to note that many trical insulator at room temperature; them with a mortar and pestle, bake, good room-temperature conductors, however, when you cool it with LN2, and then repeat. The process is fairly such as copper, gold, and silver, will YBCO becomes a perfect conductor of simple and is performed in many high not become superconductors (at least electricity. Strange stuff! school chemistry labs. not so far). One theory to explain this YBCO was discovered at the If you don’t have the inclination to is the lack of a strong interaction University of Houston by a research create a superconductor pellet from between the electrons and the ion lat- team led by Paul C. W. Chu, who filed scratch, there are several vendors that tice within the material. This lack of a patent application on the same day will sell you inexpensive kits that interaction means that the electrons that they made the discovery. YBCO contain a superconductor pellet ready are freer to move at room tempera- looks nothing like a conductor. It is a to go. Futurescience carries an inex- ture, which results in a good conduc- black, powdery material, and if you pensive kit that contains a small disk tor of electricity. However, the Cooper check it with a common conductivity of YBCO, a rare earth magnet, tweez- pair superconductor theory maintains meter, you will see it is truly an insu- ers, Styrofoam cups to hold LN2, and that a strong interaction between the lator at room temperature. However, if more. You can experiment with the electrons and the ion lattice is neces- you pour LN2 over YBCO and check it unusual characteristics of supercon- sary for a superconductor. with a conductivity meter again, you ductors such as the Meissner effect Nearly 100 years ago, it was discov- will find that it now has become a and the zero-resistance effect. The ered that liquid helium could make conductor. YBCO disk is mounted via silicone on superconductors out of materials such One drawback to current high-tem- a copper pedestal. The silicone allows as mercury. Helium was first liquefied the disk to expand and contract within 1908 by Kamerlingh Onnes. Liquid out breaking it. The copper pedestal is helium has a temperature of 4.2K, or for increased heat conduction. With only 4.2K above the coldest tempera- better heat conduction, you can use ture possible. Liquid helium is not less of the LN2. The copper/silicone practical or cheap and requires an pedestal setup also holds the disk at a expensive refrigeration system. good viewing height. While the critical temperature of I bought another kit from a different mercury is 4.2K, the critical tempera- supplier that was much less well tures of lead, aluminum, tin, tungsten, thought out than the Futurescience kit. and titanium areWWW.GiURUMELE.Hi2.RO 7.2, 1.2, 3.7, 0.015, This kit came with the superconductor and 0.39K, respectively. All of these disk, a small rare earth magnet, and a materials, like mercury, require expen- pair of tweezers. Attempts to make the sive, impractical cooling processes to disk superconduct failed. Apparently, the achieve the superconducting state. YBCO disk was not prepared correctly.

Obviously, to be practical, higher tem- LN2 is not included with the kits perature superconductors are needed. you can buy off the shelf, but you can Photo 1—As the LN warms, it changes back into the 2 get it from your local industrial/med- gas state. The loose-fitting top prevents explosion. The HTS ical gas supplier (see Photo 1). LN2 LN2 lasts a surprisingly long time in this size container. High-temperature superconductors usually costs about $2 per gallon in I got this 10-liter LN2 container from Airgas in exhibit superconductor properties at Clarksville, Tennessee. small quantities. You may have to try

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 57 several suppliers before you find one a) b) that has a proper experimental/educational LN2 container that they will let you borrow. You can even get a small quantity of LN2 in a stainless steel thermos, although it will not last long. You cannot seal the thermos to prevent loss of LN2. As the LN2 changes to the gas state, the pressure created will burst the thermos; there- ″ Photo 2a—The neodymium-iron-boron magnet is floating about 0.25 above a LN2 cooled yttrium-barium-copper- fore, you must leave the thermos vent- oxide superconductor. When I poured about a quarter of a cup of LN2into the Styrofoam cup, the levitation effect ed. LN can be handled safely if proper 2 amazingly lasted for almost 15 min. before it needed a boost from another shot of LN2. b—Here, you can see precautions are taken, but you must be another view of a neodymium-iron-boron magnet floating above a LN2 cooled yttrium-barium-copper-oxide super- careful with it to prevent injury. If you conductor. search on the Internet for “superconductors” or “liquid nitrogen,” you will one is fixed). When the superconduc- them more suitable for practical find several sites that give tips on the tor disk is cooled with LN2, the mag- magnetic applications. A notable proper handling of LN2. net actually levitates to a position Type II superconductor is an alloy

Although LN2 itself is fairly cheap, above the disk from a resting position consisting of niobium and germanium. you will find that many dealers want on top of the superconductor disk. Unfortunately, most Type II supercon- to charge you $10 to $20 for a few The Meissner effect results from the ductor materials have critical temper- pints. They lose a bunch of LN2 when superconductor material setting up atures between 10 and 25K. they try to fill a small thermos, so surface currents that oppose the exter- they have to charge for the lost mate- nal magnetic field. Because there is no SUPERCONDUCTOR rial too. In addition, the labor of filling electrical resistance in the supercon- APPLICATIONS the container with LN2 may cost more ductor, the surface currents can flow There are numerous applications for than the LN2 itself. without loss. Therefore, the surface superconductors, such as power-line

Make sure to pour the LN2 over the currents can flow for as long as need- conductors, super-fast computers, superconductor disk slowly. If you just ed to oppose the magnetic field. electromagnetic spacecraft launching dump a bunch of LN2 over the super- If a magnet is placed on the super- devices, noncontact bearings, and conductor, you risk cracking the disk. conductor disk after the disk is small, inexpensive medical imaging Make sure you wear eye protection cooled, the zero-resistance effect is equipment. Another application is when using LN2, because things have demonstrated as opposed to the Superconducting Quantum a tendency to violently crack when Meissner effect. This will result in the Interference Devices (SQUIDs), which they are cooled so drastically. If you magnet floating above the supercon- are used to detect extremely low-level don’t wear the glasses, you could end ductor disk. The physical height at electromagnetic fields. up with a chunk of YBCO in your eye. which a magnet floats above the The really exciting thing is that the superconductor disk because of zero best applications have not even been MEISSNER AND ZERO RESISTANCE resistance is higher than the levitation thought of yet. When transistors were A substance that exhibits diamag- height that is achieved with the invented, did the pioneers imagine netism opposes a magnet similarly to Meissner effect. Photos 2a and 2b that they would eventually be shrunk the way two magnet faces of the same show the zero-resistance effect in down to microscopic size and used in polarity oppose each other. A super- action floating a neodymium-iron- cell phones, GPS receivers, video conductor exhibits perfect diamagnet- boron magnet. games, and PDAs? I doubt it! ism because it excludes magnetic So, why would someone want fields from its interiors. Any fields MAGNETIC FIELD PROBLEMS to learn about superconductors, that were present prior to the super- Placing a superconductor in a mag- experiment with the materials, or conducting stateWWW.GiURUMELE.Hi2.RO are eliminated. When netic field decreases the critical tem- develop practical applications for the a superconductor repels a magnet that perature. In fact, if the magnetic field materials? It is fun and interesting is placed on it prior to cooling, it is is strong enough (i.e., critical magnet- for one thing. Another reason is that called the Meissner effect. ic field), superconductivity becomes there’s a goldmine to be found in The Meissner effect was named for impossible. Obviously, this fact limits superconductor application, just like one of its discoverers, Walther Meissner. the practical uses for superconductors the goldmine there was for the tran- Meissner and Robert Ochsenfeld dis- because many applications involve sistor back in its early days. It will covered the effect in 1933. The magnetics. probably be some hobbyist in his Meissner effect results in a magnet A group of superconductors known garage who makes a big break- being levitated above a superconduc- as Type II superconductors have large through in new superconducting tor (or vice versa depending on which critical magnetic fields that make materials or applications for existing

58 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com materials. The government even conductors (or even materials that encourages superconductor research. will superconduct via freon or dry-ice cooling) to be the next great techno- PATENT INSPIRATION logical leap awaiting mankind. Even

When you submit a patent applica- LN2-cooled superconductors that can tion, you can request that the applica- be easily formed into flexible wires tion be “made special” so that the would be a great leap. Higher tem- patent prosecution is accelerated. perature superconductors or more This is called a Petition to Make practical applications for current Special (PTMS). As slow as the U.S. HTSs could find use in commercial, Patent and Trademark Office’s military, medical, and spacecraft processes are, this is a good thing. applications. I Certain things such as advanced age of the applicant, environmental appli- Danny Graves, P.E., holds an M.S.E.E. cations, energy applications, illness of and is a technical consultant. He cur- the applicant, and, yes, superconduc- rently performs technical analysis for tivity result in a free PTMS. The fol- patent infringement cases. He also lowing is an excerpt from the USPTO enjoys technical writing and is in the Manual of Patent Examining process of becoming a registered U.S. Procedures (MPEP), chapter 708.2, patent agent. You may reach Danny regarding superconductivity: at [email protected]. In accordance with the President’s mandate…the U.S. Patent and Trademark Office will, on request, REFERENCE accord ‘special’ status to all patent [1] U.S. Patent and Trademark applications for inventions involving Office, Manual of Patent superconductivity materials. Examples Examining Procedures, ed. 8, of such inventions would include GPO, Washington, D.C., rev. those directed to superconductive February 2003, chapter 708.2. materials themselves as well as to their manufacture and applica- RESOURCES tion…No fee is required. [1] Liquid nitrogen container Interestingly, the patent process Airgas may have hindered the development www.airgas.com of HTSs. Some companies have tried to patent the entire class of HTSs. Superconductor kit The legal confrontations resulting Futurescience, Inc. from such legal maneuvers have www.futurescience.com stalled some research and the publica- Instructions to build a supercon- tion of research results. The commer- ductor pellet cial potential of high-temperature Oak Ridge National Laboratory superconductors is enormous. When www.ornl.gov/reports/m/ornlm3 you have such big commercial poten- 063r1/pt7.html tial, cooperation among individuals and corporations is naturally hin- Futurescience, Inc., dered. Secrecy is also prevalent and Superconductivity Magnetic communication is strategic. Levitation Demonstration Kit My recent searchWWW.GiURUMELE.Hi2.RO for “superconduc- Model 150, 1994, www.future- tor” in the patent database on the science.com/manual/sc150.pdf. USPTO web site (www.uspto.gov) J. Langone, Superconductivity: resulted in 4750 hits. A search for The New Alchemy, “YBCO,” under claims, resulted in Contemporary Books, Inc., New 199 patent hits. Obviously, there’s York, NY, 1989. been a lot of superconductor patent activity during the last 25 years. A. Stwertka, Superconductors: The Irresistible Future, (Venture FUTURE OF HTSs Books) Franklin Watts, Inc., New I consider room-temperature super- York, NY, 1991.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 59 FEATURE ARTICLE by Jim Turley

Programming the 386 in 32-Bit Protected Mode

Remember when the 386 was the hottest chip on the market? Today, there are dozens of other 32-bit CPUs, and the 386 is no longer the superlative processor. But wait, there’s a lot you might not know about the 386. In this article, Jim explains how entering Protected mode will open your eyes to the 386’s applicability.

Believe it or not, there was a time AMD, Transmeta, VIA/Centaur, operating modes: Real mode, Virtual 86 when Intel’s 386 was the hottest PC VAutomation, and other vendors. But mode, and Protected mode. Real mode chip around. At 66 MHz, it was blazing- the 386 is also a big step up from its is the default: it’s how the chip powers ly fast. And, best of all, it was a 32-bit predecessor, the 286. If you’re an accom- up, and it’s compatible with the 286 processor. Nervous PC users described plished 8086 or 286 programmer, you’ve and earlier processors. It’s also called, its performance in hushed tones. What got some real treats in store. This with some justification, Brain Dead would they do with all that power? month, I’ll take a look at some of what mode. Virtual 86 mode is hardly ever Would it be used for good or evil? makes the 386 so different from all the used, and I’ll ignore it for now. These days, 32-bit processors are, other x86 chips that came before it. To really enjoy all the 32-bit good- almost literally, a dime a dozen. Just The first difference to wrap your head ness of the 386, you have to enter counting embedded processors, there are around is something called Protected Protected mode. Protected mode opens more than 100 different varieties of mode. When Intel upgraded from the up an entirely new programming world. 32-bit CPUs, each and every one with 16-bit 286 to the 32-bit 386, the compa- The 386 changes its memory manage- hundreds of happy programmers and ny had a tough time adding 32-bit good- ment, segmentation is different, new customers. Some cost less than $5. ness while still allowing all the old 16- instructions are available, and hardware Others have prices that soar above $500. bit (and 8-bit) code to run. To remedy privilege protection is enabled. In short, Through it all, the x86 family (i.e., 8086, this, the 386 now has three different when the 386 is in Protected mode, it 186, 286, 386, 486, and several flavors behaves like a real 32-bit processor, of Pentium and Athlon) has remained not just a faster 8086. among the most popular. Now that the 31 15 7 0 The first thing you’ll notice about 386 is too old for PCs, it has found a EAX AH AL Protected Mode is how roomy it is. new life in embedded systems. EBX BH BL Everything gets bigger. Bigger registers, And why not? Intel still makes the ECX CH CL bigger memory segments, and a bigger

386, and it even produces the special EDX DH DL instruction set. Most registers double in embedded-only 386EX processor. (AMD size to 32 bits (see Figure 1). AX becomes ESI SI wound down its 386 chips several EAX (extended AX), BX becomes EBX, months ago.) The 386 may not be the EDI DI and so on. You can still access the low cheapest, fastest, or most power-efficient EBP BP 16 bits as AX, and even the low 8 bits processor around,WWW.GiURUMELE.Hi2.RO but it’s familiar to a lot ESP SP as AL, just like before. Likewise, the of programmers, and it’s well supported. CS four address pointers SI, DI, BP, and SP

Software, talent, and tools for 386-based DS now have 32-bit extended versions. projects are plentiful and often free. = New 386 registers ES That’s easy enough, and it’s a welcome change from the cramped regis- FS SAME OLD BOSS ters of the 8086 and 286. But wait, it GS Part of the 386’s charm, if I can call it gets better. The 386’s memory seg- SS that, is that it’s part of the x86 family, mentation also changes completely in which is the best-known chip architec- Protected mode. Segmentation is per- ture around. That means the 386 is Figure 1—Registers in the 386’s Protected mode haps the most hated feature of all x86 expand to 32 bits with new mnemonics. The older 8-bit upward- and downward-compatible and 16-bit registers are still accessible. Two new seg- processors. Their habit of breaking with older and newer chips from Intel, ment registers, FS and GS, have been added. memory into 64-KB chunks finally has

60 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com been broken, but it’s a seriously able, and it can be anything from strange transformation for the FFFFF 1 byte to 4 GB. Intel never does experienced x86 programmer. anything the easy way, so natu-

Let’s review the old style of x86 DS 1 2 3 4 SI rally the descriptor doesn’t sim- memory segmentation. To touch ply use 32 bits to define the SI + 1 2 3 4 Offset address a byte or word in memory, you length of the segment. Instead, 1 3 5 7 4 have to load its address into you get 20 bits plus a granularity both a segment register and an bit that controls how the other offset register. Then, the proces- 20 bits are interpreted by the sor shifts the segment register to DS 00000 processor. The remaining 12 bits the left by four bits (multiplies by Segment base address in the descriptor set how the 16) and adds the result to the off- segment is used, whether it’s set register, as shown in Figure 2. Figure 2—Old-style memory segmentation relies on a 16-bit segment write-protected, how privileged The result is your final memory register and a separate 16-bit offset register. The actual memory it is, and even whether or not address is the sum of the offset plus the segment shifted left by 4 bits. address. Simple enough, but it the segment is actually present. means you have to increment or And you, dear programmer, get reload the segment register every 64 KB. the real base address of the segment. to set all of these parameters for every This granularity usually keeps data Before, if you loaded 0x400 into DS, segment (see Figure 4). structures, stacks, and code confined you knew the segment started at Although you will rejoice at the to 64-KB chunks. Getting around this address 0x4000 (i.e., 0x400 shifted left demise of the 64-KB segment limit, limitation has been a never-ending 4 bits). That’s no longer true; DS is there are some extremely odd side game for most x86 programmers. merely a pointer into a table. (To effects to the 386’s new type of seg- make matters worse, the location of mentation. First of all, you must cre- WHAT YOU KNOW IS WRONG the table itself is determined by ate segment descriptors for every area All of the old weirdness of memory another register, GDTR.) It’s the con- of memory you’re going to access, segmentation is gone, and it has been tents of the descriptor DS is pointing ever. The 386 absolutely will not read replaced by new weirdness. Figure 3 to, not the value of DS itself, which or write any address that isn’t part of illustrates how it works in Protected determines where the segment begins. some descriptor. Second, you cannot mode. Are you ready? Take a breath. Let’s take a closer look at this myste- simply look at a segment register and First, a new 40-bit register, called rious descriptor that seems to define all know the segment’s location. Segment the global descriptor table register memory on the 386. There must be registers are now just pointers into the (GDTR), points to the base of a table exactly one descriptor in the descriptor descriptor table; they’re not significant somewhere in memory. Each entry in table for every segment in memory. bits of any address. Unless you exam- this table, called a descriptor, is Segments don’t exist without descrip- ine the descriptor itself and tease the 8 bytes long. Your familiar segment tors. The 386 won’t allow you to access data out of it, there’s no way to know registers (e.g., DS, CS, ES, and so on) arbitrary addresses in memory unless where your segment registers are actu- are now index pointers into this table. you have already defined a descriptor ally pointing. If DS equals zero, it points to the first for that segment. At a minimum, you Likewise, there’s no way to know (0th) descriptor; if DS equals eight, it should define three segment descrip- how long a segment is (or where it points to the second descriptor (at off- tors—one each for code, data, and stack. ends) without reverse-engineering the set 8), and so on. Every descriptor is a The descriptor, in turn, holds all of 64-bit (8-byte) entry in a FFFF FFFF the information about a memory seg- table of similar entries. ment. The segment’s base address, Thirty-two bits, or one- 5 length, type (i.e., code, data, or stack), half, of the descriptor set ESI SI 4 protection level, and many other the base address for that details are all encoded in the descrip- segment. As you can see, tor. Thirty-twoWWW.GiURUMELE.Hi2.RO bits in the descriptor you can start a segment point to where the segment referenced at any arbitrary address in DS actually begins. anywhere in the 386’s 3 Descriptor Finally, your familiar offset register enormous 4-GB address Descriptor (extended SI in Figure 3) determines space—even an odd 2 Descriptor DS Descriptor the offset into this memory segment. address. No longer do 0000 0000 1 So, although you still use the register memory segments have GDTR pair DS:SI as a pointer to memory, the to start on 16-byte way it works is utterly different. boundaries. Figure 3—New-style memory segmentation uses several levels of indirection to ultimately determine the beginning and end of each memory seg- For starters, the value you load into The length of a segment. Segments can now start (and end) at any arbitrary address in the DS has absolutely nothing to do with ment is also user-defin- 386’s entire 4-GB address space.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 61 descriptor that defines it. You have the 386 switch between 63 56 47 39 16 0 might run off the edge of the them on a regular basis. The segment after 64 KB like before, processor handles all the load- but probably not. A particular ing and storing of variables, data segment might be only freezing state information, and 100 bytes long, or it might be a Base address (32 bits) so on. It’s hugely complex to Length (effectively 32 bits) megabyte. There’s no easy way Type (code, data, stack, etc.) set up but wonderfully useful to know. (By the way, the 386 Privilege level (0–3) when you do. You can even Present/not present no longer wraps around the end 16/32-bit segment define your interrupt service of a segment. If you try to read Limit granularity routines as separate tasks and beyond the last byte of a seg- Figure 4—Each 386 segment is defined by a 64-bit segment descriptor in have the 386 perform an auto- ment, wherever that may be, the global descriptor table. Descriptors define the beginning, end, and matic task switch when an the 386 aborts your code.) characteristics of the segment. Different segment descriptors define the interrupt occurs. The hardware processor’s code, data, and stack space. Areas of memory not defined by Increasing the value in DS or a descriptor cannot be accessed under any circumstances. automatically saves all the ES doesn’t automatically bump variables and stack informa- you up to the next 64-KB seg- tion for you on every interrupt ment of memory, either. Incrementing THE END OF THE WORLD without writing a single line of code! a segment register just points to the Have you wrapped your head around There’s a whole lot more to the 386: next descriptor, which might define a Protected mode memory segmenta- new instructions, new task manage- code segment, a data segment, or no tion? Good, because I haven’t even ment, new four-level privilege man- segment at all. In other words, most begun to plumb the depths of the agement, and new hardware features. values that you can put into a segment 386’s more interesting features. There’s enough to fill a fat book, register are invalid. There’s no way to Briefly, interrupts and exceptions which is exactly what I did a few simply table-walk through memory by (faults and failures) get even more con- years ago when I developed 386 hard- bumping DS or ES every 64 KB. voluted. In addition to the large table ware and software. You may down- Segment descriptors can also define of memory descriptors, the 386 also load my book, Advanced 80386 (in fact, they must define) whether it’s maintains (courtesy of you, the pro- Programming Techniques, in search- OK to write into a segment or whether grammer) a table of interrupt gates. able Adobe Acrobat format. Visit my it’s write-protected. Trying to store data Interrupt gates are a bit like an inter- web site, www.jimturley.com, for in a write-protected memory segment, rupt vector table, with a separate instructions. either accidentally or on purpose, traps interrupt vector for each interrupt. In For more information on the topic, the offending instruction and aborts this case, the vector table is stuffed you can also review Ed Nisley’s Firm- your code. This is a great way to pro- with descriptors that add yet another ware Furnace series “Journey to the tect sensitive data tables from acciden- level of indirection to your interrupt Protected Land” (Circuit Cellar 48–65). I tal overwriting. Finally, code segments service routines. are always write-protected, so say good- Whenever there’s an interrupt or Jim Turley is an independent analyst, bye to self-modifying code. fault, the 386 either fetches or gener- columnist, and speaker specializing in Actually, there is a workaround for ates a vector, from zero to 255. It uses microprocessors and semiconductor self-modifying code, and one that high- that vector as an index into the inter- intellectual property. He is the former lights still more differences between rupt descriptor table (IDT), the loca- editor of Microprocessor Report and the 386 and earlier x86 processors. tion of which is determined by the host of the annual Microprocessor You’re more than welcome to create interrupt descriptor table register, or Forum and Embedded Processor two different segment descriptors that IDTR. Sound familiar? Each interrupt Forum conferences. You may write to point to the same place in memory. descriptor points to a memory seg- him at [email protected] or visit his This is known as aliasing, and it’s ment descriptor that, in turn, points web site at www.jimturley.com. extremely useful. For instance, you can to the code for the interrupt service create one descriptor that defines the routine. You did define memory seg- RESOURCE memory betweenWWW.GiURUMELE.Hi2.RO 0x1000 and 0x1FFF ments for all your interrupt service J. Turley, Advanced 80386 as code, and another descriptor that routines, right? Programming Techniques, McGraw- says the same addresses are data. Load Hold on, there’s more. The 386 can Hill/Osborne Media, Emeryville, a pointer to the first descriptor into CS do its own hardware task manage- CA, 1988. and a pointer to the second descriptor ment. If you’re using a multitasking into DS or ES, and you can write all operating system, or just want to keep over your own code space. Or, if you different tasks away from one another, SOURCE just want to examine your code but the 386 can probably handle it in hard- 386 and 386EX Microcontrollers not modify it, create a second descrip- ware. You can create elaborate task Intel Corp. tor that defines 0x1000 through state segments (TSSs) that hold all the (800) 538-3373 0x1FFF as write-protected data. dynamic data for each task, and then www.intel.com

62 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO APPLIED PCs by Fred Eady

RF Made Simple Think of Fred as your own personal litmus test for all of the new embedded technology thrown your way. This month, he brings the LPRS easy-Radio to the Florida room and puts it to the test. Read on to find out if his results impress you enough to try your hand at building an easy-Radio/CH2124 modem station.

RF is magical and mysterious, and ic fields around my food isn’t bad Using frequency hopping in low- so are RF engineers. I truly believe enough, RF engineering has gone so power radios like the easy-Radio has that RF engineers are really disguised far as to leave its mark on the musical its advantages. By hopping at predeter- holdovers from the time of Merlin and arts. Ask yourself this: When was the mined intervals between preset fre- Camelot. Look at what the RF engi- last time you saw a celebrity using a quencies in a band of unlicensed fre- neering wizards have done to us. Do microphone? Was it wireless? You bet! quencies, the chances of interference you own and operate a cell phone? Is Not to be left out of the enchant- from other radio transmissions your pager a constant companion? I’m ment, this month I’ve got my eye on decreases. Because the data is dis- from Tennessee, where blackberries some new data radios and a new persed over a number of channels, bet- grow on thorny vines along fencerows. embedded modem. Both the data ter data security is achieved as well. I’ll bet you get e-mail with your radios and the modem are purportedly Over time, the use of frequency hop- Blackberrys. What about that cordless “easy” to put into operation. You ping reduces the average power level phone in your kitchen? These days, know me, when someone claims that is transmitted at a single frequen- you don’t even need to have wire to something is “easy,” I try it out and cy, which allows higher peak power get on an Ethernet LAN. The RF guys tell you how it went. levels than those allowed for single- are even messing around with our band transmitters. food. I went out to eat recently, and EASY-RADIO Interfacing to the easy-Radio mod- the waitress took my order with a Low Power Radio Solutions (LPRS) ule is easy, because it provides two wireless Palm PC. If cranking magnet- has claimed that its easy-Radio allows handshake lines and a serial interface you to ignore the radio link and running at 19,200 bps. The easy-Radio treat it as if it were a wire. A handshake lines control the flow of simple TTL or RS-232 data data to and from the easy-Radio trans- source is all that’s required to move data from point A to point B, and vice versa, using a pair of easy-Radio transceivers. All of the messy encoding, decoding, and checksum calcu- WWW.GiURUMELE.Hi2.ROlations are achieved by the easy-Radio’s internal processor. The easy-Radio uses frequency hopping and a maximum of 20 mW of output power to achieve a range of 500-m line-of-sight. Photo 1—I used an unused in-line socket to mount the My 900-MHz easy-Radios hop at PIC12F675 data rate converter module. I took this photo before I 25 times per second over 25 chan- beefed up the voltage regulator on both of the easy-Radio Photo 2—The iModem evaluation board is a great nels, which, under the control of boards. I used the RS-232 port and the services of RS-232 cir- tool; it saved me lots of time during the development cuitry on an unrelated microcontroller-based project board to the internal microcontroller, is phase of this project. Everything you need to make the feed the remote easy-Radio during development and debugging. transparent to the data radio user. modem go is on the iModem board.

64 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com the easy-Radio’s receive buffer that can be transferred to the host processor, it will flow on the serial link that exists between the module and the host processor. After all of the data Photo 3—The text you see in the original e-mail shot is has been transferred out easily changed using the @TM1 command. Each of the easy-Radio’s remote easy-Radio can send a custom message by receive buffer, the easy- using this command followed by the microcontroller- Radio deactivates the Photo 4—The remote non-modem-equipped easy-Radio generated the entire generated text message. line beginning with @TM1. The end of a message is signaled by a carriage Busy output line. return dot carriage return. The @TDM1 was also generated by the easy-Radio The host processor on the non-modem side of the RF link. The rest of the messages, which were ceiver. If the easy-Radio is busy inter- can use the easy-Radio’s ignored, are from the CH2124. You can see them because I have Serialtest nally, the Busy line is asserted. The Host Ready line as a Async tracing both the CH2124 and the easy-Radio serial connections. easy-Radio’s Busy line alter ego is the flow-control line. To Host Ready input line that informs stop the flow of data on the serial link orate circuit boards or write any fancy the module that the host processor is between the host processor and the microcontroller firmware to make the ready to transfer data out of the easy-Radio module, the receiving host easy-Radios work. receive buffer for further processing. processor raises the Host Ready line. I grabbed a couple of the easy-Radio To send data using an easy-Radio, Lowering the easy-Radio’s Host Ready hoppers and plugged them into the the host processor checks to see if the line resumes the data transfer. The evaluation kit radio boards. The evalu- module is busy. If it isn’t, the host host processor has approximately 2 s ation radio boards are simple and con- processor feeds a maximum of 80 bytes to transfer everything out of the easy- sist of an RS-232 converter IC, a low- of data to the easy-Radio via the Radio’s receive buffer before the mod- power 5-V regulator, configuration 19,200-bps serial link that exists ule takes control and flushes the jumpers, a couple of blocking diodes, a between the host and the module. If less receive buffer. 9-V battery clip, an in-line socket for than 80 bytes of data are to be transmit- the easy-Radio module, a wall-wart ted when the host processor has finished DEAD-EASY WIRELESS jack, an antenna connector, and some its transfer, two byte times later, the Enough theory already. If I’ve missed LEDs. The easy-Radio hoppers are easy-Radio starts processing the data it something, I’ll cover it as I explain nine-pin, in-line devices that are received from the host processor and how to assemble easy-Radio hardware. keyed for foolproof insertion into the activates the Busy output line. I have an easy-Radio evaluation kit in-line socket on the evaluation board. The 2-byte time between the end of and four easy-Radio 900-MHz hoppers. Using my laptop as point A and a a message that’s less than 80 bytes in The radio boards that came with the PC as point B, I connected the easy- length and the beginning of transmis- evaluation kit are shown in Photo 1. Radios to the PCs with a standard sion processing is called the end-of- This is supposed to be easy, so I’m not nine-pin, male-to-female cable. I data gap. At 19,200-bps, the end-of- going to design and fabricate any elab- invoked HyperTerminal on the PCs, data gap is 1.04 ms. If the strapped a couple of 9-V bat- message from the host proces- teries on the radio evaluation sor exceeds the 80-byte easy- boards, and fired them up. Radio limit, all of the bytes Everything worked as I had beyond the module’s 80-byte planned. I was able to trans- buffer maximum are discard- mit and receive on both PCs ed, and the remaining con- using the easy-Radio modules. tents of the easy-Radio transmit buffer are WWW.GiURUMELE.Hi2.ROprocessed for DEAD-EASY E-MAIL transmission. You guessed it, the easy- Any easy-Radio module Radios are going to join an within range picks up the initi- easy-Radio frequency-hopping ated transmission, drives its network and send whatever BUSY signal active, and starts data they share as an e-mail. to decode the incoming mes- Again, there will be no intri- sage. The receiving host Photo 5—The nine-pin gender changer connects the easy-Radio’s MAX202 to cate custom PCBs or tricky processor should then take the the iModem evaluation board’s MAX237. After all of the development and software involved in the e- debugging is done, the easy-Radio, PIC12F675, and CH2124 are the only easy-Radio Host Ready line components needed (in addition to power and a phone line) to generate an e- mail process. I have a proper low. As soon as there is data in mail using the embedded RF link. English friend, Trevor, who

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 65 uses the term “dead easy” quite often access, which prompted me to discon- local phone number and an easy-to- in our electronic conversations. tinue my dial-up service. When I had use embedded modem to boot. Because LPRS is a United Kingdom- finalized the idea for this column, I What you see in Photo 2 is the new based company, I’m really surprised went dial-up ISP shopping. I really and improved Cermetek CH2124 that LPRS didn’t call this “Dead-Easy don’t need 199 mailboxes, spam relief, mounted on an iModem evaluation Radio” (grin). or high-speed access and a web page. I board. This version of the CH2124 My web site ISP recently sold all of simply want to dial up, hook up, and sends and receives e-mail using the its dial-up accounts. Because my e- transfer a few bytes of data between standard PPP or CHAP authentication mail package is rolled into my web Internet widgets. The cheapest local protocols. The circuitry and algo- site contract, I used the dial-up dial-up ISP wanted $12 per month pre- rithms within the new CH2124 have account for Internet gadget testing paid for one year. That’s pretty good, been updated to provide faster and purposes. The new dial-up provider but I know where I can get the data more reliable dial-up connections. doubled the price of my dial-up service I want for $2 per month with a You don’t need to be intimate with TCP/IP, SMTP, POP3, or any of those nerdy protocols to use a CH2124; it is a set-and-forget, stand-alone kind of communications device. There are provisions for interfacing to an external microcontroller, but you don’t need to add one, because the CH2124 can store a canned e-mail message and send it with the drop of a logic level. On the other hand, you can get as nerdy as you wish. For instance, you can acquire full control of the CH2124 modem and send/receive process using your hardware, code, and favorite processor or microcontroller. Shortly after my regular FedEx representative, Chris, delivered my new CH2124, I plugged it into my iModem evaluation board, attached a phone line, supplied some power via a 9-VDC wall wart, and hit the Send button (see Photo 2). I spend an inordinate amount of time in front of my all-in- one e-mail PC (it sits next to my production and design monitors), and I like to answer e-mail messages as quickly as I get them. So, I set the e- mail PC to ask for e-mail messages every 60 s. I heard the iModem evaluation board/CH2124 combination connect, and, less than 1 min. later, I had an e-mail from the CH2124. You’re probably saying, “No way, Fred!” My initial e-mail from the out- WWW.GiURUMELE.Hi2.ROof-the-box CH2124 is shown in Photo 3. I told you this would be dead easy, did- n’t I? All Cermetek CH2124 iModems are customized and tested before delivery. To put the CH2124 online in Stand- Alone mode and deliver the message of my choice, all I have to do is connect the iModem evaluation board to a PC running a terminal emulator program, and then issue a simple @T iModem command to change the canned message.

66 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com Everything else needed for sending an e- using the CH2124. The concept is CH2124 won’t be retrieving e-mails in mail using the Cermetek $2 ISP and the simple; however, the implementation this application, all that’s needed is CH2124 was already loaded. is a click above dead easy. In the to convert the easy-Radio’s 19,200 bps CH2124 and the easy-Radio, we have to 2400 bps, and then feed the low- DEAD-EASY APPLICATION two intelligent devices. The easy- ered data rate data to the CH2124’s Well, almost. This is an embedded Radio and the CH2124 have serial 2400-bps serial interface. project, and you all know the first rule ports, which presents Problem 1. The production easy-Radio/CH2124 of embedded programming (repeat Although both of the smart devices units didn’t need the RS-232 conver- after me): nothing is free. have serial interfaces, the easy-Radio sion circuitry present on both the I wanted various microcontroller- serial interface’s speed seems to be CH2124 and easy-Radio evaluation supported easy-Radios to report to a fixed at 19,200 bps. The CH2124 platforms. But remember that this was central module that reports to me wants to see a 2400-bps serial datas- supposed to be easy, so I verified the with an e-mail message. The idea was tream at its serial interface, which data rate converter hardware and to have the CH2124-equipped easy- stands to reason, because it’s an intel- firmware using the known-good easy- Radio station poll the remote easy- ligent 2400-bps modem module. Radio and known-good CH2124 evalu- Radio stations for their data. Every Checking the CH2124 datasheet, ation hardware already on hand. After I easy-Radio station within an earshot the CH2124 cannot be commanded to had a working data rate converter cir- picks up a transmission, so I’m also do 19,200 bps at its serial interface. My cuit, I was able to eliminate the RS-232 considering having each radio listen goal was to not have a microcontroller conversion ICs and stick the itty-bitty for a transmission, wait for a predeter- in the CH2124-equipped easy-Radio microcontroller between the easy- mined amount of time, and then station. There’s more than enough Radio and CH2124 serial interfaces. transmit its data. Whether to poll or intelligence between the easy-Radio use a timed sequence for transmission and the CH2124 to make this RF-to-e- REMODELING THE BOARD depends on the application. mail thing happen. Now “dead easy” The blue power indicator LED on In any case, the central CH2124- has turned into “dead in the water.” the easy-Radio evaluation boards equipped easy-Radio station simply OK, if I have to add a microcon- stayed. Right now, I don’t know about assembles the incoming data from the troller to solve Problem 1, it’s going to the rest of the easy-Radio’s evaluation radios in the network into an e-mail I be an itty-bitty one, and the code is board’s power train. There it is, the can read and shoots it down the line going to be itty-bitty, too. Because the potential Problem 2. Easy-Radio engineers warned me that I didn’t have the latest spin of the easy-Radio evalua- Listing 1—Most of the work is done by the Custom Computer Services C compiler. The Custom Computer Services C Compiler Project Wizard generated 99% of the set-up code. I used two serial streams and tion boards. They also said that the wrote only three itty-bitty lines of C source code to turn the itty-bitty PIC into a data rate converter. voltage regulator currently on the evaluation boards wasn’t up to snuff #include <12F675.h> for the new 900-MHz hoppers. #include #use delay(clock=4000000) I’m not planning on adding much #fuses INTRC_IO,NOWDT,NOMCLR,NOPROTECT,NOCPD,NOBROWNOUT more of a load to the easy-Radio evaluation board’s power supply, but I #use fast_io(A) don’t want to add enough load to #use rs232(baud=19200,parity=N,xmit=PIN_A5,rcv=PIN_A4,bits=8,stream=radio) cause a shutdown of the evaluation #use board’s on-board 78L05 SMT voltage rs232(baud=2400,parity=N,xmit=PIN_A0,rcv=PIN_A1,bits=8,stream=modem) regulator. There’s ample ground plane area on the bottom of the evaluation void main() board to clear some heatsink space for { a small-package 78M05 voltage regulator that can handle up to 500 mA, setup_adc_ports(0); which is more than enough to handle setup_adc(ADC_OFF);WWW.GiURUMELE.Hi2.RO setup_counters(RTCC_INTERNAL,RTCC_DIV_2); the easy-Radio hopper module and setup_timer_1(T1_DISABLED); what little else I’ll add. setup_comparator(NC_NC_NC_NC); You can power an easy-Radio evalu- setup_vref(FALSE); ation board with either a 9-VDC wall SET_TRIS_A(0b00010010); wart or 9-V battery. The evaluation board’s on-board, 5-V SMT regulator while(1) pre-regulates the incoming 9 VDC pro- { vided by the wall wart. Pre-regulation fputc(fgetc(radio),modem); is a good thing, because as the average } } unregulated 9-VDC wall wart actually supplies about 12 VDC under light

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 67 load conditions. The easy- shown in Photo 5. Adding the Radio has an internal 3.6-V data rate converter took a bit regulator and a 5 V-tolerant of the “easy” out of the I/O interface. It’s a safer bet design, but, as you can see in than applying 5 VDC, because Listing 1 and Figure 1, not it won’t tax the easy-Radio’s much of the simplicity was internal regulator. destroyed, because the code The easy-Radio and the Figure 1—I simply inserted the PIC12F675 between the easy-Radio’s 19,200-bps and circuitry of the data rate CH2124 are both configured serial data-out line and the MAX202 RS-232 converter IC’s TTL-side transmit converter is minimal. pin. The PIC12F675 does no buffering and dumps out the data rate-converted as DCE, which allows a data as soon as it gets it. Character pacing is handled by the remote sending As I worked on this project, straight-through cable to con- easy-Radio, because it’s going from a faster to a slower data rate. I purposely tried to avoid nect either of them to a stan- designing additional support dard DTE PC serial port. Because I The simplicity of the PIC12F675- hardware, because the products I used wanted to stick with the CH2124 and based data rate converter allows you were supposed to make an RF-chal- easy-Radio evaluation boards, one of to mount the PIC12F675 in an in-line lenged (or communications-chal- them had to be converted to a DTE fashion using one of the unused in-line lenged) product design engineer’s life configuration. I’m already chopping radio receptacles on the easy-Radio easier. I think the point has been on the easy-Radio evaluation board, evaluation board. The evaluation proven, because both products were and, in the traditional sense, the board is a simple double-sided board, literally ripped out of their boxes and CH2124 evaluation board should be which allows you to cut and reroute thrown into service without perform- the DCE device because it holds the existing traces to accommodate the ing any kind of configuration or setup. modem, which is considered a DCE data rate converter’s power and I/O. It cannot get any less complicated and device. So, one of the Easy-Radio eval- All of the data rate conversion is per- more embedded than that. I uation board’s serial receive and trans- formed on the TTL side of the serial mit lines will be swapped to trans- link. The CH2124 and the easy-Radio Fred Eady has more than 20 years of form the board into a DTE device. are both designed to use TTL levels on experience as a systems engineer. He If I poll for data, I will need a micro- the serial link and eliminate the need has worked with computers and com- controller on the CH2124 end of the RF for RS-232 voltage levels to communi- munication systems large and small, link to initiate the polling sequence. If I cate serially with a host processor. simple and complex. His forte is allow the easy-Radios to police them- Normally, the addition of a micro- embedded-systems design and com- selves, I still would require a microcon- controller would allow for the buffer- munications. Fred may be reached at troller on the CH2124 side of the RF ing of the data between the easy-Radio [email protected]. link because I need data rate conver- and the CH2124. In this case, the lit- sion between the CH2124 and the easy- tle PIC has no USART or USART Radio module. So, it looks like my no- interrupt structure, and I’ve tied up SOURCES microcontroller-at-the-modem-station the PIC12F675’s time to such an CH2124 Modem and iModem idea is a bogus concept. With that, I’ve extent that there may not be enough evaluation board got a couple of ideas about which cycles to perform a buffering opera- Cermetek Microelectronics, Inc. microcontroller I should use. tion without missing an incoming bit. (800) 882-6271 My first inclination was to use an The solution is to not attempt to www.cermetek.com eight-pin PIC12F675 for the data rate buffer the data with the PIC and allow C Compiler converter. If I go with the little eight- the data rate-converted data to flow Custom Computer Services, Inc. pin PIC, I’ll have to allow the easy- freely from the easy-Radio to the (262) 797-0455 Radios to operate on a timed basis, CH2124 modem. www.ccsinfo.com because I’ll most likely consume all of The CH2124 can be instructed to the PIC12F675’s processing time con- store a message and transmit the mes- easy-Radio verting data rates and transferring sage using @T iModem commands. LPRS data. To allowWWW.GiURUMELE.Hi2.RO the CH2124-equipped Because the channel is always open +44 1993 709418 easy-Radio station to poll, I’ll need a between the easy-Radio and the www.lprs.co.uk microcontroller with a USART and CH2124, the @T commands can be North American Radio Solutions USART interrupt capability. That embedded in the incoming datastream (distributor) takes the “easy” out of it, so I’ll go that originates at a remote easy-Radio (207) 286-1600 with the itty-bitty PIC. station. A typical message from a www.easyradiousa.com The PIC12F675 doesn’t need an remote easy-Radio is shown in Photo 4. external crystal because it contains an PIC12F675 Microcontroller internal 4-MHz oscillator. All I need RESULTS Microchip Technology, Inc. externally to support the PIC12F675 The final prototype of the easy- (480) 792-7200 is a 0.1-µF bypass capacitor. Radio/CH2124 modem station is www.microchip.com

68 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO FROM THE BENCH by Jeff Bachiochi

OOPic Eases Programming Headaches

Does programming give you a headache? If so, Jeff recommends OOPic, which allows you to combine predefined objects (e.g., keypads and LCDs) in a virtual circuit, and then compile and download the code in a special processor. It’s that simple.

My wife Beverly leaves our home tend to confuse the average consumer. The OOPic library of predefined each morning at approximately 6:30 a.m. So, manufacturers now include specif- objects makes your design job easier. She is a registered nurse at a local ic buttons such as Popcorn and Baked You need not worry about a microcon- nursing home. Being somewhat of a Potato. You don’t need to think. troller’s registers and how they must coffee connoisseur, she makes a pot of Simply push one button and the be coaxed into submission to produce java each morning using her secret microwave will determine the ulti- a function like keypad input. OOPic recipe. She drinks it straight. I happen mate program to produce a gourmet has predefined objects. As a designer, to do the opposite. I can’t tell good cof- meal, so to speak. you can select the functions you need fee from bad coffee, caffeinated from You probably don’t think too much and connect them in a logical way decaffeinated, so I need to cover up about your microwave’s small parts that’s dictated by your circuit to pro- the taste with milk and heaps of working together behind the scenes. duce an OOPic circuit. Objects sugar. Beverly savors her coffee during These parts may be similar to those include digital I/O, analog I/O, the time it takes it to cool to room used in other appliances, but, in a PWMs/timers/counters, serial com- temperature. I hate cold coffee; truth microwave, they are dedicated to a sin- munication, keypads, LCDs, and be told, I don’t really like it hot either, gle function—reheating this morning’s many others. but it is the lesser of the two evils. stale coffee. Good engineering design Unlike sequential programming Needless to say, I nuke my morning makes these small parts invisible. languages, OOPic is event-driven, coffee to get it back up to temperature which means that independent from after adding milk from the fridge. LANGUAGE TOOLS the background code that may be One morning, as my mug was riding If you’re like me, then you are executing, certain events will trigger on the microwave’s carousel, I gazed interested in mechanical things and the immediate execution of special through the protective window as if don’t like to spend more time than code. The OOPic development sys- staring at an evening’s starry sky. As necessary on the programming aspect tem runs on all Windows operating the cup of joe passed by the third of a project. Software companies are systems. The development system time, I turned my attention to the continuously developing new ways to allows you to combine objects into a microwave’s control panel. The array help you reduce programming time virtual circuit and then compile and of flat-panel buttons suggested how far and ease the learning curve needed to download the resultant code into an the microwave has come as an appli- pick up a new language. Most pro- OOPic processor. Yes, the compiled ance. This was only the second grammers have their favorites and code requires the use of a special microwave weWWW.GiURUMELE.Hi2.RO had purchased. The will die defending them. microprocessor with the OOPic oper- first one had one knob that served as The trick for nonprogrammers, or ating system inside it (starting at both the on/off switch and timer. those of us hackers, is to find a lan- $39). The processor is a flash memo- Gone is the mechanical timer. Today, guage that protects against the raw ry PIC that’s manufactured by timing is done digitally. In fact, using bits. Savage Innovations provides a Microchip and preprogrammed by an embedded microcontroller lends unique programming environment via Savage Innovations. itself to many other features. its object-oriented programming inte- Most microwaves can throttle back grated circuit (OOPic). OOPic treats OBJECTS their output power and, thanks to the the individual parts (e.g., the carousel, Besides the system object—which carousel, prevent uneven cooking. moisture sensor, and user panel of a defines the basic properties of the However, too many bells and whistles microwave) as objects. OOPic operating system—and the

70 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com sion, and event-manag- commands. The right side of the ing). Refer to Photo 3 screen shows every instance of the for a list of processing objects you’ve included in the appli- objects. cation. I’m using the OOPicII+ mod- Hardware objects are ule, which is a 24-pin, DIP-style not limited to hardware pinout that’s compatible with the functions built into the Parallax Basic Stamp. The OOPic car- microprocessor like, rier PCB provides access to all of the say, an A/D converter; I/O. In addition, it has a serial RS-232 they also cover items DB9 (for connection to your PC), and that are externally con- can run on a 9-V battery. nected, such as a key- Objects have properties associated pad. New hardware with them. Let’s take a look at the objects are constantly digital I/O bit (oDIO1) object, which Photo 1—User-definable objects allow you to create your own objects. added to the OOPic’s has six properties: Address, Direction, Advanced programmers will find this a useful way of adding items neces- list of supported IOLine, Nonzero, String, and Value. sary for specialized applications. System objects are mandatory for each devices. The presently An object becomes part of an appli- application. They set up the groundwork for the operating system based on the available microprocessor hardware. supported objects are cation when you tell the OOPic com- listed in Photo 4. piler to use it by dimensioning the user-defined object, there are three object. I named the 0DIO1 object types of OOPic objects: hardware, OOPic PROCESSOR green, and dimensioned it with the processing, and variable (see Photo 1). The OOPic language is Variable objects include instances preprogrammed into a for the temporary storage of bit, PIC microprocessor nibble, byte, and word data. (OOPicII+ equals ’16F877 Additional variable objects include in either a 40-pin DIP or a buffer for string/data storage, 44-pin QFP). The internal access to RAM, and nonvolatile processor RAM has suffi- EEPROM data storage. Photo 2 is a cient room in RAM bank 1 list of the variable objects. for 96 bytes of object Processing objects perform data space. (Note that each manipulation functions. The process- instance of an object ing objects operate on the values of requires a few bytes of variable and hardware objects. object space, generally Although the math-processing object 3 bytes or less.) The RAM Photo 2—Variable objects store values of various sizes (all versions). might be the most familiar, other object directly addresses functions also fall into this category the banked RAM. dim green as new oDIO1 command. (e.g., logic, counting, time, conver- The flash memory microprocessor As you can see in Photo 5, an object has 256 bytes of inter- appears on the right with the name nal EEPROM for non- green1. When you click on the new volatile storage. Your object, a Properties box pops up. The compiled application Properties box is a direct SCP inter- goes into the external face to and from the application, I2C serial E2PROM, which was compiled and run on the which means you can OOPicII+ using the Make and change programs by Download selection from the File pull- replacing the E2PROM. down menu. (I’ll say more about SCP WWW.GiURUMELE.Hi2.ROYour application size later.) As you can see, the Properties (independent of the box has been assigned an object object storage) is based address (by the compiler), but no other on E2PROM size. properties have been established. To get started with After the object has been estab- OOPic, download the lished, the properties can be changed free compiler and open at any time within the application. it on your PC. The left All applications begin with a subrou- side of the screen is a tine called main. I placed three lines Photo 3—The processing objects are used to manipulate the values of other box in which you can of code there to initialize the proper- objects by providing input or receiving output from them. enter and edit OOPic ties of the oDIO1 objects, IOLine,

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 71 Direction, and Value. The falling edge of the 1-Hz clock commands appear in the fol- will not cause the event; how- lowing format: ever, by creating a virtual object, by linking the 1-Hz object name.property = data clock to the event with an oFanOut object, both the ris- where green.ioline = 5, ing and falling edges can trig- green.direction = 0, and ger an event object. This is green.value = 1. accomplished by using the As soon as the code is com- invert property of one of the piled and loaded, it automati- oFanOut object outputs. cally begins execution. Photo 6 When the oFanOut object is shows how these properties created, it is defined as having have been initialized, and it two outputs. By enabling the indicates that I/O line 5 is now .InvertOut2 property of the an output with a value of 1. second output, it goes through This OOPic has three status an additional (virtual) inverter. SMT LEDs on the module. The oFanOut object property I/O 5 just happens to be the output 1 links to a rising edge green LED, which is glowing. event, and (inverted) output 2 You can click on either the links to a falling edge event. Value or Nonzero check boxes The sub procedure code for an in the Properties box to change Photo 4—Many specialized hardware devices are supported in the expand- event is named with the event ed set of OOPic objects (version B). their value. The properties box name plus the text _code. In is a live conduit to and from Photo 8, one procedure simply OOPic, and your property change will the emulation of a physical circuit by turns on output bit 5 and the other turn the LED off. This demonstrates the OOPic operating system. It can procedure turns it off. Are you begin- how you have access to the objects comprise many objects, but at least ning to see the power here? even while the application is running. one is a processing object. The OOPic object has both 1- and Let’s go back to the 1-Hz example. TOPIC NETWORKING 60-Hz clocks available to applications. By creating a virtual object (i.e., link- Based on the Philips’s I2C interface, The 1-Hz property can be used by any ing the 1-Hz clock and the output bit OOPic takes advantage of the inter- application. In this example, it’s used with an oGate), you can create a situ- face’s ability to communicate with to blink the green LED by adding a ation in which the output bit gets it other devices over an open-collector loop and redefining the green.value value directly from the 1-Hz value. In pair of conductors. The OOPic can in the following way: this case, the application is not respon- play master or slave device, which sible for updating the green.value, essentially means any OOPic can ini- do and so the green.value does not rely tiate communication with another green.value = OOPic.Hz1 on the loop execution speed. Photo 7 device or respond to communications loop shows how the link is accomplished from another OOPic. The oDDELink in a situation in which the loop code object has the ability to be either the where the value of the green output might be slow. master or slave by defining the bit 5 is continuously updated with the The sub procedure is a block of code object’s .direction property. When value of the 1-Hz clock during the eval- executed on demand from another the .input property is linked to a uation. The application uses a standard part of the application. An event is a loop process. What happens to the triggering of a sub procedure because green.value if the other code within of some action in an object. The event the loop requiresWWW.GiURUMELE.Hi2.RO long execution times? object is the only object that can cause This means that green.value may a sub procedure to break normal pro- not be updated quickly enough to ade- gram execution, so it is one of the quately reflect the 1-Hz rate. Hmm, most powerful objects. Let’s go back hold that thought! to the green LED example and use the I used two of the five components 1-Hz clock to produce an event—well, that can make up an application—an actually two events. object and the main procedure. The event object is triggered by a Additionally, your application might rising edge; therefore, the sub proce- Photo 5—A dimensioned object has properties that contain a sub procedure, an event, and dure code associated with the event must be defined as shown by the oDIO1:green a virtual circuit. A virtual circuit is will occur once every second. The properties box.

72 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com local object, the object’s value can be passed to another OOPic, when as master, it initiates communication with another OOPic or as a slave receives a request for the data from another OOPic. When the .output property is linked to a local object, the object’s value is updated from another OOPic; as master, it initiates a request for data with another OOPic or as slave is given data by another OOPic. An oDDELink object is required for the transfer of one value (bit/byte/ word) between any OOPic. By carefully adjusting the oDDELink object’s properties on the fly, your application can give or take values from any other OOPic located on the same I2C interface.

OOPic LIVE One of the most useful advances in today’s microcontroller technology is the ability to monitor what’s going on inside an application while it’s running on the actual hardware. An application monitor that can be appended to an application usually handles this. OOPic uses the primary serial port as a shared conduit that’s capable of controlling program execution and accessing RAM and EEPROM memory. The hardware port, which defaults as a serial object, is available to your application. It does, however, monitor the data passing through it for a two-character escape sequence. Serial control mode is enabled when a \0 escape sequence has been received. (Note that the second character—zero in this case—indicates that the escape sequence is recognized by all OOPic nodes as a general call, as opposed to a value of one through 127, which would be recognized only by that OOPic node.) The command redirects communications through the serial control protocolWWW.GiURUMELE.Hi2.RO (SCP) module until it is disabled (i.e., when a \A escape sequence is received). All SCP communications are in a readable ASC format with single letter commands, single values passed in decimal format, and multiple values passed in hexadecimal format. SCP commands can affect the execution of your application, the application itself, or application’s data. You may download the SCP command list

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 73 because RAM address 0 is available in multiple banks, each of which contains an address 0. The sub address also manipulates data so as to mask and shift individual bits. If accessing external EEPROM, the sub address is used as the I2C device’s address value. By presetting these memory descriptors, the Read and Store Memory commands can access all aspects of the OOPic memory. Photo 7—By linking the Hz1 property of the OOPic Most of the additional commands object to value property of the green object, the green will affect the application’s program output bit will automatically reflect the state of the 1-Hz Photo 6—In theory, every property can be defined by OOPic clock without having to evaluate it in a loop. other objects operating on them; however, it is a good execution. Using SCP commands, you idea to initialize the properties. In this case, bit 5 will be can start, stop, single-step, branch, used as an output and initialized with a value of one. and reset your application. Although After looking through the prede- the concepts used to debug an applica- fined objects in OOPic’s library, you from the Circuit Cellar ftp site. To read tion are a far cry from the simplicity may come to the realization that or write from OOPic memory, descrip- of choosing objects and linking them many have direct robotic applications. tive registers must be initialized. together to form their application, For those of you who are mechanical- Memory Type refers to the kind of serious programmers will want this ly inclined but not necessarily com- memory that will be accessed, any of level of sophistication. puter literate, OOPic offers you an your application’s object default proper- opportunity to get your robot moving ties (in RAM), other internal RAM, ODDS AND ENDS and shaking without having to take internal EEPROM, or external EEP- The order in which objects are classes in microcontroller program- ROM (i.e., your compiled application added to your application may have ming. OOPic user groups are flourish- code via I2C). The Memory Type regis- some impact on the way evaluations ing, which means stability in the ter also indicates whether or not multi- are made. If you are defining virtual product market. And don’t think that ple locations will be read, and if the objects, where multiple inputs define OOPic can’t meet your needs just Memory Address will be automatically an output, be sure to place them in because your project has nothing to do incremented. The Memory Address is a such a way that the objects providing with robotics. If you’re looking for an 16-bit value of the address of interest. an input are evaluated prior to the easy way to get the job done, OOPic A sub address register is needed object using the inputs. This is offers simplicity with the added when addressing internal RAM, accomplished by the order in which advantage of a short learning curve. they are created in OOPic. Oh-la-la. I your application. The objects are evaluated Jeff Bachiochi (pronounced BAH-key- in the order they AH-key) has been writing for Circuit appear in your appli- Cellar since 1988. His background cation. This object includes product design and manu- list defines the evalu- facturing. He may be reached at ation order of the exe- [email protected]. cution loop for your application. PROJECT FILES Your application will be limited to the num- To download the command list, go ber of objects that can to ftp.circuitcellar.com/pub/ WWW.GiURUMELE.Hi2.ROfit in the 86 bytes of Circuit_Cellar/2003/160. remaining object RAM. The requisite RESOURCE OOPic object requires OOPic freeware, 10 of the available www.oopic.com/dload.htm. 96 bytes. Generally, Photo 8—Events are triggers for a background task that can interrupt normal pro- this isn’t a problem. gram flow. The oFanOut object allows a single output to be shared by multiple The example I used SOURCE objects. One of the oFanOut properties allows any or all of the outputs to be only required an addi- OOPic inverted. Inverting the 1-Hz clock allows a falling edge to look like a rising edge and trigger an event. The risingedge_code and fallingedge_code tional 11 bytes of Savage Innovations events happen on alternate edges of the 1-Hz clock. object space. www.oopic.com

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ALSO: SCALABLE LED DISPLAY PANELS, TEMP-HUMIDITY Saelig Co. brings to USA unique, easy-to-use control and MONITORS, THERMOCOUPLE P.C. ADAPTERS, ENVIRONMENT instrumentation products from overseas. Customers inc: MONITORING SYSTEMS, EDUCATIONAL SCIENCE PROJECTS, Saelig Co. Inc. Intel, Philips, NEC, Kodak, Nokia, US Military, Microsoft, GRAPHICS SOFTARE, AutoCAD PROGRAMMING COURSE, USB-PIC Dell, Xerox, Universities, T.I., Harris, Sony, J&J, BOARDS, FLASH PROGRAMMERS - IF YOU DON’T SEE WHAT YOU 585-425-3753 • fax: -3835 Thomson, Sandisk, General Dynamics, H-P/Compaq, etc. NEED MAYBE WE CAN FIND IT FOR YOU? - JUST ASK FOR ALAN! www.saelig.com • [email protected] SILICON UPDATE by Tom Cantrell

Go Sell the Spartans

What does the future hold for the modern FPGA? The answer isn’t cut and dry. FPGAs are massively successful, but as time presses on, they are becoming increasingly complex and remaining pricey. This month, Tom looks at the direction of the FPGA industry.

I’ve definitely got mixed feelings, at which an ASIC makes more sense BIGGER IS BETTER? bordering on a full-on love/hate rela- than an FPGA as fixed cost (NRE) grows As I wrote back in 1998 (“VolksArray,” tionship, when it comes to FPGAs. On and variable cost (gates) shrinks. Back Circuit Cellar 93), the name for Xilinx’s the positive side, I consider FPGAs in the ’80s, an ASIC might have been then new Spartan lineup of FPGAs was (more correctly, “programmable logic,” viable for as few as 50,000 units. Today, chosen no doubt in light of its mod- going all the way back to the seminal you’re probably looking at 500,000 units ern interpretation as a “byword for PAL days) one of the most profound as a reasonable minimum. As the trend endurance and rugged simplicity.” Since chip concepts, right up there with continues, the FPGA suppliers can sim- then, we’ve seen the Spartan-II, Spartan- heavyweights such as the microproces- ply wait with open arms to welcome IIE, and now the Spartan-3. The good sor and memory. And there’s no doubt ever-increasing legions of ASIC refugees news is that the latest parts have all in my mind that the fantastic progress fleeing the NRE juggernaut. the bells and whistles. demonstrated by leading FPGA compa- Who’ll be left using ASICs? Ironically, Naturally, during the five years nies like Xilinx and Altera will contin- it’s the suppliers of standard chips that since the original Spartan, density has ue apace. In particular, with Moore’s will have the volume to justify appli- shot up. Indeed, the smallest Spartan-3 Law on their side, FPGAs are poised to cation-specific IC techniques. And it’s in the eight-chip lineup (see Table 1), put a world of hurt on ASICs. not just the fabless chip companies the XC3S50, delivers more gates than Yes, the march of silicon benefits driving the trend. Today, there’s the largest of the originals (50,000 ver- both FPGA and ASIC suppliers in terms already a good chance the standard sus 40,000). At the other extreme, the of gate cost and performance. But it’s microcontroller you buy from a com- XC3S5000 packs a whopping five the so-called nonrecurring engineering pany like Motorola or Philips is in fact million gates! (NRE), specifically the mask cost, that’s an ASIC that was made in a foundry. As an aside, I will not be elaborating the showstopper for ASICs. Mask costs Yes, the future is bright for FPGAs on the controversy over gate counts, are shooting up to a million bucks and at the high end, but it’s also the high- which I’ve referred to in the past as beyond with each schuss down the end orientation that is the source of standing for “gratuitous attempt to slope of Moore’s curve past ever-finer most of my frustration. Let’s take a enhance sales.” It’s a lot like MIPS, as geometries on ever-bigger wafers. closer look at a modern FPGA and the in “meaningless indicator of processor What this all boils down to is an inex- tools that go with it, and I think speed.” The point is, the number of orable increaseWWW.GiURUMELE.Hi2.RO in the trade-off volume you’ll see what I mean. gates is a highly subjective number System Max distributed Number of Block RAM Number of dedicated Number of Max differential Max single- gates RAM (bits) block RAMs (bits) multipliers clock mgrs. I/O ended I/O

XC3S50 50K 12K 4 72K 4 2 56 124 XC3S200 200K 30K 12 216K 12 4 76 173 XC3S400 400K 56K 16 288K 16 4 116 264 XC3S1000 1000K 120K 24 432K 24 4 175 391 XC3S1500 1500K 208K 32 576K 32 4 221 487 XC3S2000 2000K 320K 40 720K 40 4 270 565 XC3S4000 4000K 432K 96 1728K 96 4 312 712 XC3S5000 5000K 520K 104 1872K 104 4 344 784

Table 1—So many gates, so little time to market. With up to five million gates on tap, the new Spartan-3 lineup puts the ball squarely in the toolchain’s court.

76 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com depending on, for instance, how much I can understand that the Spartan using the same tools as a chip design logic is used as RAM. But because we’re marketing concept as kind of a loss- guru at Intel or Motorola. And that comparing apples to apples (i.e., Xilinx leader version of Virtex-II, much as a includes making the big post-schematic to Xilinx), the company’s own interpre- Chevy looks a lot like a Cadillac era move to logic synthesis using hard- tation of “gates” is an acceptable metric. under the hood, but dare I say that the ware description languages (HDLs) like Beyond lots of gates, the new rugged simplicity theme is a bit of a Verilog or VHDL. Spartan-3 comes with plenty of other stretch? All the more ironic to note, It gets even more complicated with goodies. Probably the most useful is Spartan-3 is actually manufactured the emergence of on-chip CPU cores, block RAM, because it eliminates the using a state-of-the-art, 90-nm process such as the hard PowerPC core (make need to jury-rig general-purpose logic versus 150 nm for Virtex-II. that cores, up to four of them) on the (i.e., configurable logic blocks, a.k.a. Virtex-II Pro and the 32-bit MicroBlaze CLBs) for use as RAM, which is an TOOL TIMEOUT soft core. You can imagine the chal- extremely inefficient practice that con- Configuring the original programma- lenges associated with designing, simu- sumes way too many gates per bit. And ble logic PAL chips was easy. Type in a lating, and debugging a lash-up of CPUs I’m not talking about a few bits of few sum-of-products logic equations and OSs buried in millions of gates and block RAM either. The XC3S50 starts and let a simple PALASM program bits hidden behind hundreds of pins. the ball rolling with 72 Kb growing to crunch ’em a bit and spit out a few bits The original inspiration for this arti- a whopping 1.8 Mb in the aforemen- of fuse map. And, of course, the origi- cle was sparked by my encounter with tioned top-of-the-line XC3S5000. A few nal FPGA schematic capture methods the new Xilinx embedded development million gates here, a few million bits using MSI TTL-like macros (e.g., regis- kit (EDK) at the Spring ESC show in of RAM there, and pretty soon you’re ters, decoders, multiplexers, etc.) were San Francisco. The purpose of the EDK talking about real silicon. familiar to any board-level designer. is to fill the hardware-software code- Other high-end Spartan-3 features Later, core generator enhancements sign gap with a tool that helps config- include up to 104 (!) dedicated multi- based on higher-level parameterizable ure and integrate the major hardware pliers, frequency-synthesizing and functions such as arbitrary width and software functional blocks that phase-shifting 300-plus-MHz digital timer/counters and multiplier/accumu- comprise an FPGA-based System-on-a- clock managers (DCMs), and digitally lators made life easier. Chip. Originally, I had planned to actu- controlled impedance I/O that can But between the ASIC-killer aspira- ally hook up a board and play around handle a full selection of 23 single- tions and incredible density boost, now with this latest-and-greatest FPGA ended and differential standards. you have a situation where FPGA tools setup, but, discretion being the better If some of this seems familiar, that’s are as complicated as the ASIC tools of part of valor, it wasn’t long before I because these “new” features actually yore. Indeed, with big-ticket ASIC tool retreated from that worthy goal. first appeared on the company’s pre- suppliers like Cadence, Synopsys, and In retrospect, the fact that the pack- mium platform Virtex-II FPGAs. Mentor Graphics branching into FPGAs, age arrived with five CDs was perhaps Indeed, the Spartan-3 is much closer an FPGA designer may literally be the first hint that I was in trouble. in architecture and capabilities to the high-end Virtex-II than to the original Spartan chips whose name it shares. 16 Registers 8 bits Although the original Spartan ran on a Port PORT_ID[7:0] sF s7 single 3.3-V supply and was able to address READ_STROBE sE s6 pp control tolerate standard 5-V TTL connec- sD s5 WRITE_STROBE sC s4 tions, note that Spartan-3 cannot han- IN_PORT[7:0] sB s3 OUT_PORT[7:0] sA s2 dle 5-V TTL and requires up to three s9 s1 ALU s8 s0 Arithmetic separate supplies: 1.2 V for the core logical logic; 1.2 to 3.3 V for the I/O; and 2.5 V shift kk rotate for special functions. Scratch pad memory PARITY Similarly, the original Spartan start- 64 bytes 18-bit Instruction word ed at 84 pins andWWW.GiURUMELE.Hi2.RO maxed out at 256 for ss 8-bit Data path ZERO and Interrupt CARRY the package. Spartan-3 offers a 100-pin 8-bit Port address shadow flags INTERRUPT flags option, but only for the entry-level 10-bit Program address Interrupt INTERRUPT_ACK control parts. Beyond that, the smallest pack- Constants age for the mid-range one million gate Program Program ADDRESS[9:0] INSTRUCTION[17:0] flow counter Program chip is 256 pins, and things escalate Operational aaa control ROM/RAM control quickly from there. For instance, if and RESET you want the top-of-the-line, four or 1024 words instruction CLK decoding aaa/pp/ss/kk Program counter stack five million gate Spartan-3s, you’re getting a part with at least 900 pins Figure 1—Here’s the PicoBlaze—in this case, the KCPSM3 version—at a glance. And that’s all it takes. The whether you need them or not. KCPSM and KCPSM2 versions are even smaller.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 77 The “Getting Started” guide dutifully PicoBlaze line consists of various incar- outlined the somewhat intimidating nations of what’s now referred to as installation and registration rituals, KCPSM—the “KC” ostensibly standing made a bit less daunting by virtue of for constant (K) coded (see Figure 1). the fact I’d been through them before When it comes to defining computer with an earlier generation of Xilinx architecture, a top-down approach tools. But soon I was reading how I’d starts with a clean sheet of paper with have to get my simulation libraries up little concern for implementation con- to snuff, referring to a bunch of syn- straints. By contrast, a bottom-up thesis stuff I know little about like approach accepts the premise of a given SIMPRIM, UNISIM, MODELSIM, hardware platform and crafts a design SWIFT, VCM, VCS, and so on. that makes the most of it. PicoBlaze is Opening the EDK “Embedded definitely the latter. Systems Tools Guide” to find it clocked For instance, the address space and in at 322 pages gave me pause. The real- instruction set for the various versions ity check was further reinforced by a of PicoBlaze are directly aligned with a glance through the table of contents, particular FPGA’s block RAM organiza- which is littered with acronyms like tion. Thus, the base KCPSM that tar- XPS, PSF, MHS, MPD, PAO, BBD, MVS, gets Spartan-II and Virtex devices has MSS, MLD, MDD, and XMK. Oh yeah, a maximum program size of 256 16-bit don’t forget getting up to speed with the instructions reflecting the devices’ entire GNU C toolchain (nontrivial if 256 × 16 block RAMs. Meanwhile, you haven’t done it before), and, what KCPSM2 and KCPSM3, which target the heck, you may as well throw in Virtex-II and Spartan-3, support more the WindRiver RTOS too. (1024) and fancier instructions thanks It was almost with a sense of relief to those devices’ 1024 × 18 block RAMs. that I discovered my few-year-old PC The size of the register file (16 or wasn’t up to the task. (EDK requires 32 bytes) and CALL/RETURN stack Windows 2000; I’m running Me.) It (15 or 31 levels) are similarly con- coughed up the first CD and wouldn’t strained to optimize silicon utilization. even install the software, giving me a For the original KCPSM and face-saving way of bailing out. KCPSM2, the registers are the only data memory option. KCPSM3 PICO THE LITTER includes a 64-byte scratchpad RAM When I was poking around the accessed with FETCH and STORE Xilinx web site, I stumbled across instructions. Of course, using the PicoBlaze. As the name implies, INPUT and OUTPUT instructions, it’s PicoBlaze is a soft-core CPU along the possible to access additional on- or off- lines of MicroBlaze, only, dare I say, FPGA data via software. much more rugged and simple. Indeed, this little 8-bit puppy Dual-port block RAM makes a PIC or 8051 16 × 256 we look like a Cray by data_in address comparison (see Target

target_clk data_outreset_target connection Figure 1). UART Interface logic Actually, PicoBlaze FIFO Rx KCPSM WWW.GiURUMELE.Hi2.ROisn’t new news. 16 bytes serial_rx

Indeed, its roots go Monitor Terminal Terminal

FIFO connections Target

connections Tx program back more than 16 bytes

10 years to what its serial_tx Data rate generator creator, Xilinx Staff 8 bits, 1 stop Engineer Ken bit, no parity

Chapman, originally reset_monitor described as a pro- monitor_clk grammable state Figure 2—For test, configuration, or calibration tasks, a PicoBlaze core with a machine, or PSM. [1] UART and small monitor provides an easy way for a PC (or other serial device) These days, the to access the FPGA on-chip block RAM.

78 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com Otherwise, the instruction connect it. Similarly, set is blessedly simple and PicoBlaze could provide the literally can be understood basis for an externally at a glance (see Table 2). accessible field-test capa- Actually, even that figure bility. For instance, by overstates the matter, adding a soft UART, it’s because the arithmetic and possible to craft a scheme logic group instructions are by which a connected PC shown twice for variants could download and exe- that only differ in using a cute various chip-, board-, register or constant for one and box-level diagnostic proof the operands. Similarly, grams. Because a PicoBlaze the conditional JUMP, core only consumes a small CALL, and RETURN fraction of the FPGA instructions are shown for resources (e.g., less than 5% each condition. By my of an XC3S200), it’s even fea- count, it’s really only a cou- sible to consider using multiple dozen instructions to ple cores for tackling larger remember. Notice that Photo 1—The friendly assembler/simulator from Mediatronix is a quick and easy tasks or to implement a vari- branch addresses are way to get a feel for PicoBlaze programming. ety of useful coprocessors. absolute (i.e., constants), so leave your computed GOTOs at home. What is PicoBlaze good for? Well, as YEAH, BUT… There is provision for a single inter- the original programmable state On the software side, there’s a full rupt input; it just stacks the program machine moniker indicates, it would C/C++ compiler, Java virtual machine, counter and flags, and then vectors to be useful for complex state machines and RTOS including TCP/IP stack. a fixed (the last) location in memory (e.g., recursion) that aren’t easily han- Rumor has it a port of Linux is in the where you put a branch instruction to dled by raw gates. At only two clocks works. Ha, just checking to see who’s the interrupt service routine. Yes, it’s per instruction (every instruction in still awake out there. If you didn’t simple minded, but it’s also fast—just all cases, thank you), you’re looking at immediately choke on the aforemen- a few clock cycles from interrupt perhaps 40 to 60 MIPS and beyond, tioned statement, you’re probably request to servicing. If you need mul- depending on the particular FPGA. reading the wrong magazine. tiple inputs, programmable priority By virtue of being on-chip, the core The fact is, what you can download schemes, and so forth, remember that is uniquely able to access the FPGA from the Xilinx web site is a simple- this is an FPGA, so you can have it internal logic and I/O pins, making it minded assembler with bare-bones your way by adding logic external to a natural for adding self-test features, features running in a DOS window no the processor. Just make sure to keep possibly eliminating the need for an less. There’s also a more modern track of your stack, though—there’s extra processor along with the FPGA graphical assembler/simulator from an no overflow detection. resources (gates, pins) required to outfit called Mediatronix (see Photo 1),

Program control group Arithmetic group Logical group Shift and rotate group Interrupt group Storage group Input/output group

JUMP aaa ADD sX, kk LOAD sX, kk SR0 sX RETURNI ENABLE STORE sX, ss INPUT sX, pp JUMP Z, aaa ADDCY sX, kk AND sX, kk SR1 sX RETURNI DISABLE STORE sX, (sY) INPUT sX, (sY) JUMP NZ, aaa SUB sX, kk OR sX, kk SRX sX JUMP C, aaa SUBCY sX, kk XOR sX, kk SRA sX ENABLE INTERRUPT FETCH sX, ss OUTPUT sX, pp JUMP NC, aaa COMPARE sX, kk TEST sX, kk RR sX DISABLE INTERRUT FETCH sX, (sY) OUTPUT sX, (sY) CALL aaaWWW.GiURUMELE.Hi2.RO ADD sX, sY LOAD sX, sY SL0 sX CALL Z, aaa ADDCY sX, sY AND sX, sY SL1 sX CALL NZ, aaa SUB sX, sY OR sX, sY SLX sX CALL C, aaa SUBCY sX, sY XOR sX, sY SLA sX CALL NC, aaa COMPARE sX, sY TEST sX, sY RL sX X and Y—register numbers in the 0–Fh range RETURN kk—constant value in the 00–FFh range RETURN Z aaa—address in the 000–3FFh range RETURN NZ pp—port address in the 00–FFh range RETURN C ss—internal storage address in the 00–3Fh range RETURN NC

Table 2—PicoBlaze’s blessedly simple instruction set is a welcome relief from the creeping complexity of bloatware architectures. Note that CALL and RETURN support up to a stack depth of 31.

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 79 although in terms of credentials (i.e., boards to choose from (see Photo 2). QA, compatibility, and documentation), But if you’re an FPGA newbie, plan there’s no guarantee you’ll get more than on spending plenty of time getting up what you pay for with this freeware. to speed. As I described earlier, Simple tools for a simple processor, FPGAs have a bit of their own NRE what’s wrong with that? Nothing at crisis, as in the nonrecurring educa- all. But even though the architecture tion crisis needed to get beyond the and software tools are blessedly sim- “Getting Started” guide. ple, just remember PicoBlaze ulti- Even with all the chips, tools, and mately inherits the complexity of the know-how in hand, things are a little entire FPGA toolchain in all its glory. cumbersome. For instance, the small Sure, with little more than the (256 × 16 or 1024 × 18) ROM your PicoBlaze application note (40 pages) PicoBlaze program resides in is actual- and assembler (84 KB), you’re ready to ly a block RAM, the initialized con- write your first Hello World program. tents described somewhere in the mil- No problem on the hardware side lions of configuration bits that are either because there are plenty of cute bootstrapped into the FPGA at power- and thrifty Spartan and Virtex EV up. Thus, even the tiniest PicoBlaze

Listing 1—By overtly specifying structure (e.g., specific LUTs and flip-flops), the VHDL code for PicoBlaze favors speed and gate count over readability.

-- Architecture low_level_definition of shift_rotate_process is -- -- Attribute to define LUT contents during implementation -- The information is repeated in the generic map for functional simulation attribute INIT : string; attribute INIT of high_mux_lut : label is "E4"; attribute INIT of low_mux_lut : label is "E4"; attribute INIT of carry_out_mux_lut : label is "E4"; -- -- Internal signals -- signal upper_selection : std_logic; signal lower_selection : std_logic; signal mux_output : std_logic_vector(7 downto 0); signal shift_in_bit : std_logic; signal carry_bit : std_logic; -- begin -- -- 4 to 1 mux selection of the bit to be shifted in -- high_mux_lut: LUT3 --translate_off generic map (INIT => X"E4") --translate_on port map( I0 => code0, I1 => operand(0), I2 => inject_bit, O => upper_selection ); WWW.GiURUMELE.Hi2.ROlow_mux_lut: LUT3 --translate_off generic map (INIT => X"E4") --translate_on port map( I0 => code0, I1 => carry_in, I2 => operand(7), O => lower_selection ); final_mux: MUXF5 port map( I1 => upper_selection, I0 => lower_selection, S => code1, O => shift_in_bit );

80 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com cheap, especially when compared to the triple- and even quadruple-digit prices FPGA suppliers are able to command for their highest-end parts. For an accomplished ASIC designer or folks who already have a lot of FPGA experience, the complexity of the parts and tools is less of a barrier. They have been there, done that. But I’m thinking there will come a time Photo 2—When it comes to evaluating Spartan-3 when the ASIC suppliers are driven FPGAs, hardware is the least of your worries thanks to back into the highest-volume niches this low-cost ($150) evaluation board from Insight Memec. and the FPGA suppliers will also recognize there’s a huge potential program change calls for rebuilding demand for simple parts and simpler the entire design and downloading a tools. Or maybe they’ll notice the new configuration bitstream. efforts of companies like Triscend and An easier way out is to simply Cypress Micro who are bringing pro- devote another PicoBlaze core to act grammable logic capability to design- as a monitor. As shown in Figure 2, ers who aren’t, and shouldn’t have to the extra core talks to a PC (or what- be, chip design experts. ever) via UART and implements a few So, if I seem overly harsh when I commands to read/write an attached grouse about the high-end, ASIC-replace- dual-ported block RAM, which can ment orientation of FPGAs, just consider then be used as downloadable ROM it an example of that old saying, “You for the second PicoBlaze under test. only hurt the ones you love.” I Let’s raise a glass to our dear and departed schematics, because it looks Tom Cantrell has been working on like HDL and synthesis are taking over. chip, board, and systems design and Just out of curiosity, I glanced through marketing for several years. You may the VHDL for the PicoBlaze core. Given reach him by e-mail at the touted high-level attributes of syn- [email protected]. thesis and the simplicity of the core, you might expect the code to be rather REFERENCES short and sweet. Instead, you’ll find it’s [1] K. Chapman, “Dynamic nearly 50 pages of rather cryptic stuff Microcontroller Using XC4000 like the snippets shown in Listing 1. FPGAs,” Xilinx, 1994. It’s not the designer’s fault but rather a case of the tool wagging the RESOURCE chip. A VHDL version is a must in order for PicoBlaze to make the most Xilinx, Inc., “Embedded System of the toolchain (e.g., simulation). But, Tools Guide,” V.3.2.2, May 2003. at the same time, the gate bloat and performance hit (clock rate reduction) SOURCES associated with a more behavioral Spartan-3 LC 50J FPGA Evaluation (i.e., readable) description isn’t desir- kit able. Thus, the PicoBlaze VHDL codi- Insight Memec fies an extremelyWWW.GiURUMELE.Hi2.RO structural definition www.insight-electronics.com that tells the synthesizer explicitly PicoBlaze Assembler/simulator which gates go where. Kind of like Mediatronix feeding a C compiler a bunch of in- +31 235625449 line assembly language, I guess. www.mediatronix.com

DON’T BE CRUEL Spartan-3 FPGA, PicoBlaze 8-bit Make no mistake: outfits like Xilinx Soft-core CPU and Altera know what they’re doing. If Xilinx, Inc. I were in their shoes, I’d probably fol- (408) 559-7778 low much the same strategy. Talk is www.xilinx.com

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www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 91 WWW.GiURUMELE.Hi2.RO

92 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO

www.circuitcellar.com CIRCUIT CELLAR® Issue 160 November 2003 93 INDEX OF ADVERTISERS The Index of Advertisers with links to their web sites is located at www.circuitcellar.com under the current issue. Page Page Page Page 84 Abacom Technologies 73 DesignCon 2004 50 MaxStream 75 Saelig Company 86 Acacetus 59 DLP Design 90 MCC (Micro Computer Control) 3 Scott Edwards Electronics Inc. 91 ActiveWire, Inc. 11 Dynon Instruments, Inc. 53 Microchip 90 Scidyne 10 Adcon Telemetry 91 Easy Radio USA 92 microEngineering Labs, Inc. 88 Sealevel Systems 19 AeroComm, Inc. 12 Earth Computer Technologies 82 Micromint 86 Senix Corp. 78 All Electronics Corp. 87 EE Tools (Electronic Engineering Tools) 90 MJS Consulting 95 Sierra Proto Express 91 Amaranthine LLC 36 EMAC, Inc. 86 Mosaic Industries, Inc. 83 Signum Systems 93 Amazon Electronics 93 Embedded Micro Software 88 Mouser Electronics 85 Softools 85 Animated Lighting, L.C. 88 eProtos 42 MVS 84 TAL Technologies 84 AP Circuits 69 ESEC Tokyo 86 Mylydia Inc. C3 Tech Tools 9 Arcom 10 ExpressPCB C2 NetBurner 89 Techniprise 7 Atmel 83 FDI-Future Designs, Inc. 88 OKW Electronics, Inc. 26, 27 Technologic Systems 49 AutoTRAX 92 Front Panel Express 53 On Time 90 Technological Arts 85 Avocet Systems, Inc. 92 Futurlec 92 Ontrak Control Systems 89 Tern Inc. 84 Bagotronix, Inc. 85 Hagstrom Electronics 40 PCB123 89 Texas Embedded Solutions 90 Basic Micro 55 HI-TECH Software, LLC 73 PCBexpress 86 TLData Corp. 91 Bellin Dynamic Systems, Inc. 13 ICOP Technology Inc. 87 PCB Fab Express 85 Trace Systems, Inc. 84 BMT Microelectronics Center 89 IMAGEcraft C4 Parallax, Inc. 91 Triangle Research Int’l, Inc. 66 CadSoft Computer, Inc. 84 Intec Automation, Inc 83 Phytec America LLC 37 Trilogy Design 88 Capitol Automation 84 Intrepid Control Systems 87 Phyton, Inc. 93 Weeder Technologies 87 Carl’s Electronics 91 Intronics, Inc. 84 Picofab Inc. 93 Xeltek 59 CCS-Custom Computer Services 33 Jameco 93 Pioneer Hill Software 87 Z-World 92 Conitec 32, 86 JK microsystems, Inc. 86 PrintCapture 86 Zagros Robotics 37 Connecticut microComputer, Inc. 85 JPA Consulting 93 Pulsar, Inc. 91 Zanthic Technologies Inc. 83 Cyberpak Co. 80 JR Kerr Automation & Engineering 48 R2 Controls 86 Zexus 39 Cygnal Integrated Products 80 LabJack Corp. 18 R4 Systems Inc. 41 Zilog, Inc 1 Cypress MicroSystems 80 Lakeview Research 21 Rabbit Semiconductor 89 CWAV 47 Lemos International 40 Remote Processing 91 DataRescue 2 Link Instruments 5,63 Renesas Technology Corp. 83 Decade Engineering 52 Linx Technologies 17 Renesas Contest 89 Delcom Engineering 88 Machine Bus Corp. 90 RLC Enterprises, Inc.

Preview of December Issue 161 ATTENTION ADVERTISERS i Theme: Graphics & Video January Issue 162 Generate Video Using Software Thread Integration Deadlines The PICAVRP: A Unique Programming Solution Space Close: Nov. 10 Low-Cost Serial LCD: Convert a Discount LCD into a Serial ASCII Display WWW.GiURUMELE.Hi2.ROMaterial Due Date: Nov. 18 Computer Graphics 101 Theme: TV Oscilloscope Analog Techniques I Above the Ground Plane: Multiplying, Dividing, and Filtering

I Applied PCs: Easing into eZ80Acclaim! Applications Call Sean Donnelly to reserve your space! I From the Bench: Tabletop DMX Control 860.872.3064 I Silicon Update: Spin Control e-mail: [email protected]

94 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com Their boards come with a packing slip. Ours come with a Microsection Analysis Report

In today’s competitive climate, offering the best product at a competitive price is a must 14 Layer Board to satisfy your customers. Sierra Proto Microsection Express offers the fastest, most reliable, turns Learn more about our unique Evidence of Quality report that comes with every PCB at the highest quality. And we’ll prove it in at www.protoexpress.com every shipment with our unique Evidence of Quality reports, so you know your board is right the first time. One proof of quality is our Microsection Analysis Report, as featured here, so you can see the quality inside your board. And that is just part of our comprehensive quality tests. It’s in our process, not in our price. In fact, it is our commitment to total quality that enables us to run our operation cost effectively. And that comes back to you in our competitive price. Talk to a Sierra Proto Express Account

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by Steve Ciarcia, Founder and Editorial Director Internet Infamy

I recently read an interesting observation. It said that all the spam attacks lately are good for the Internet because it spurs business growth in anti-spam technology and keeps everyone on a system upgrade path that is ultimately good for both hardware and software manufacturers. When I read warped logic like this, I cannot help but think of the same lame trickle-down argument from Indian gambling lobbyists who think that because casinos employ lots of people they shouldnt have to pay taxes. But dont get me started on that. Spam and virus attacks are an outrageous nuisance that without remedial intervention could ultimately deep-six one of the few remaining free-enterprise zones on the planet. The growth of the Internet has been driven by commerce and communication. These days, could you really live without e-mail or the ability to get your hands on vast quantities of information on virtually any subject with the click of a key? The future vitality of the Internet depends on the unfettered interaction of legitimate users and sources, both commercial and private. How anxious are you to continue ordering products online when you have to worry that your credit card number might be hacked by someone sitting in the same Wi-Fi-enabled coffee shop or, worse yet, that you actually entered all of your credit information in a fraudulent phisher site that exactly mimics a legitimate e-commerce site? Antivirus utilities and spam filters attack only part of the problem these days. Statistics suggest that 30% of the e-mail on the Internet is spam, up from 10% a couple of years ago. I cannot speak for you, but fully 95% of my e-mail is spam. That is, unless it is the result of some virus attack and it goes even higher. I remember a recent two-day span when all we saw around our place were piles of incoming e-mail with 100K attachments clogging the system. The combination of spam, viruses, and outright fraud are making the Internet a very inhospitable placea situation that will surely stunt its continued growth. One argument is to blame it on Microsoft, but it is naive and unfair to simply blame the situation on the failings of Microsoft products, especially Outlook. The predominance of Windows and Outlook is a de facto state of affairs brought on by the rapid evolution of the Internet. Outlook gets hacked because it is there. If we all switched to Linux and another e-mail program, it would merely become the new target. At least Microsoft has enough resources to plug the holes when they arise. Many other companies would not. The latest hall of Internet infamy is something called browser spam, which pops up random advertisements as you are surfing the Net. Slipped into your computer with spyware or freeware programs, the program silently watches where you surf. When you land on a site containing keywords, it pops up ads intended to divert you to the spammers site. It sounded fearfully familiar to me when I heard about it, and I remember experiencing something even worse. I remember accidentally clicking on something once that replaced my browser home page designation, stuffed a dozen very offensive web sites into my Favorites list, and disabled my ability to erase cookies. I had to reload the entire computer to clear out all the crud. Were at a critical point where we have to decide who will control the Internet. I dont want the alternatives to be the government or none. To regain control of the Internet, every legitimate constituency that uses it will have to bear some responsibility for maintaining its integrity. Corporations from the size of IBM down to little guys like Circuit Cellar will have to recognize that there is a certain expense involved in maintaining Net security with the proper firewall software. Having a computer system that can be easily hacked so that it becomes a focal point of virus proliferation should not be allowed. The government will have to make the Net safe for businesses by truly cracking down on spammers and con men. If sending a porn spam message to someone under 14 in the U.S. is a felony, then put them in jail. Finally, Internet users have to become savvier. Phisher sites wouldnt proliferate if people were smart enough not to respond to stupid e- mails askingWWW.GiURUMELE.Hi2.RO them to enter their complete financial details on a phony web site for no other reason than being asked. Net users need to be educated that there are some really nasty things that they have to be aware of when they go online and then actually have it sink in. Only by all of us maintaining an adequate level of system defense at every stage along with a workable strategy for validating interactive communication can we ever hope to counteract the con men, spammers, and hackers. It shouldnt be left to the government alone.

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96 Issue 160 November 2003 CIRCUIT CELLAR® www.circuitcellar.com WWW.GiURUMELE.Hi2.RO WWW.GiURUMELE.Hi2.RO