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DAC Reconstruction Filter EE247 Lecture 17 DAC Converters (continued) – Reconstruction filter • DAC self calibration techniques – Current copiers – Dynamic element matching ADC Converters • Sampling – Sampling switch induced distortion – Sampling switch charge injection • Complementary switch • Use of dummy device • Bottom-plate switching EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 1 DAC Reconstruction Filter B fs/2 • Need for and 1 requirements depend 0.5 DAC Input on application 0 0 0.5 1 1.5 2 2.5 3 1 6 x 10 0.5 • Tasks: sinc 0 0 0.5 1 1.5 2 2.5 3 – Correct for sinc distortion 1 6 x 10 – Remove “aliases” 0.5 (stair-case DAC Output 0 0 0.5 1 1.5 2 2.5 3 approximation) Frequency 6 x 10 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 2 Reconstruction Filter Options Digital SC CT DAC ZOH Filter Filter Filter • Digital and SC filter possible only in combination with oversampling (signal bandwidth B << fs/2) • Digital filter – Band limits the input signal à prevent aliasing – Could also provide high-frequency pre-emphasis to compensate in-band sinc amplitude droop associated with the inherent DAC ZOH function EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 3 DAC Implementation Examples • Untrimmed segmented – T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983 – A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315 • Current copiers: – D. W. J. Groeneveld et al, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517 • Dynamic element matching: – R. J. van de Plassche, “Dynamic Element Matching for High- Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 4 2m tech., 5Vsupply 8x8 array Segmented (6+2) EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 5 Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 6 Current-Switched DACs in CMOS VV- 2 Ik1 = ( GSM1 th) V=V-4RI,V=-V7RI I GSM2GSM1GSM3GSM1 out V=V-9RI,V=-V10RI GSM4GSM1GSM5GSM1 2 æö4RI VV- 2 1- VDD I21==kI( GSM2 th) ç÷ VV- èøGSM1 th 2I1 g = M1 I M2 M3 M4 M5 mM1 1 I I I I VV- 2 3 4 5 GSM1 th 2 æö4Rg mM1 ®I2=»II11ç÷1- (1-4Rgm ) èø2 M1 2 æö7Rg Rx4I Rx3I Rx2I RxI mM1 ®I3=»II11ç÷1- (1-7Rgm ) èø2 M1 2 æö9Rg mM1 Example: 5 unit element current sources ® I4=»II11ç÷1- (1-9Rgm ) èø2 M1 2 æö10Rg mM1 ®I5=»II11ç÷1- (1-10Rgm ) èø2 M1 •Assumption: RI is small compared to transistor gate overdrive à Desirable to have gm small EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 7 Current-Switched DACs in CMOS Example: INL of 7 unit element DAC 0.3 Sequential current source switching Symmetrical current source switching 0.2 0.1 INL [LSB] 0 -0.1 0 1 2 3 4 5 6 7 Input Example: 7 unit element current source DAC- assume gmxR=1/100 •If switching of current sources sequential (1-2-3-4-5-6-7) à INL= +0.25LSB •If switching of current sources symmetrical (4-3-5-2-6-7 ) à INL = +0.09, -0.058LSB EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 8 Current-Switched DACs in CMOS Example: DNL of 7 unit element DAC 0.2 0.1 0 DNL [LSB] -0.1 Sequential current source switching Symmetrical current source switching -0.2 1 2 3 4 5 6 7 Input Example: 7 unit element current source DAC- assume gmxR=1/100 •If switching of current sources sequential (1-2-3-4-5-6-7) à DNLmax= + 0.15LSB •If switching of current sources symmetrical (4-3-5-2-6-7 ) à DNL = + 0.15LSB EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 9 (5+5) More recent published DAC using symmetrical switching built in 0.35m/3V analog/1.9V digital, area x10 smaller compared to previous example EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 10 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 11 16bit DAC (6+10)- MSB DAC uses calibrated current sources I/2 I/2 Current Divider I EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 12 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 13 Current Divider Accuracy I/2 I/2 I/2+dId /2 I/2-dId /2 IId1+ d2 Id = M1 M2 M1 M2 2 dIII- d= d1d2 I I IIdd W Ideal Current dI2d éùæöd L Real Current =´+dVth Divider êúç÷W Divider IVV- èøL dGSth ëû M1& M2 mismatched àProblem: Device mismatch could severely limit DAC accuracy EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 14 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 15 Dynamic Element Matching During F1 During F2 (1) (2) 1 I=1 I1( +D ) I=I1o1( -D ) 1 2 o1 1 2 Io/2 Io/2 (1) (2) 1 I=1 I1-D I=I1o1( +D ) I 2 2 o1( ) 2 2 1 I2 fclk II(1)+ (2) 22 / 2 error D1 I2 = 2 I (11-D) +( +D ) Io = o 11 22 Io »Dfor1 small 2 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 16 EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 17 Dynamic Element Matching During F Io/2 During F1 2 Io/4 Io/4 I (1) 1 (2) 1 3 I4 I2 I1 = 2 Io (1+ D1 ) I1 = 2 Io (1- D1 ) (1) 1 (2) 1 fclk I2 = 2 Io (1- D1 ) I2 = 2 Io (1+ D1 ) (1) 1 (1) (2) 1 (2) I3 = 2 I1 (1+ D2 ) I3 = 2 I1 (1- D2 ) / 2 error D2 1 1 = 4 Io (1+ D1 )(1+ D2 ) = 4 Io (1- D1 )(1- D2 ) I1 I (1) + I (2) I = 3 3 3 2 f I (1+ D )(1+ D )+ (1- D )(1- D ) clk = o 1 2 1 2 4 2 Io = (1+ D1D2 ) 4 / 2 error D1 I 2 o E.g. D1 = D2 = 1% à matching error is (1%) = 0.01% EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 18 Summary D/A Converter • D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL – Segmented- unit element MSB(B1)+ binary weighted LSB(B2)à complexity B1 proportional (2 -1) + B2 – DNL compromise between the two • Static performance – Component matching • Dynamic performance – Glitches • DAC improvement techniques – Symmetrical DAC element switching rather than sequential switching – Current source self calibration – Dynamic element matching EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 19 MOS Sampling Circuits EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 20 Re-Cap Analog Input Analog Anti-Aliasing Preprocessing Filter A/D Sampling • How can we Conversion +Quantization 000 build circuits DSP ...001... 110 that "sample" D/A "Bits to Conversion Staircase" Analog Reconstruction Post processing Filter Analog Output EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 21 Ideal Sampling f1 • In an ideal world, vIN vOUT zero resistance S1 sampling switches C would close for the briefest instant to sample a continuous f1 voltage vIN onto the capacitor C T=1/fS • Not realizable! EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 22 Ideal T/H Sampling f1 vIN vOUT S1 C f1 T=1/fS • Vout tracks input when switch is closed • Grab exact value of Vin when switch opens • "Track and Hold" (T/H) (often called Sample & Hold!) EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 23 Ideal T/H Sampling Continuous time Time T/H signal (SD Signal) Clock DT Signal EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 24 Practical Sampling f1 vIN vOUT M1 C • Switch induced noise power à kT/C • Finite Rsw à limited bandwidth • Rsw = f(Vin) à distortion • Switch charge injection • Clock jitter EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 25 kT/C Noise k T D2 B £ C 12 2 æ 2B -1ö ç ÷ C ³ 12kBT ç ÷ è VFS ø In high resolution ADCs kT/C noise usually dominates overall error (power dissipation considerations). B Cmin (VFS = 1V) 8 0.003 pF 12 0.8 pF 14 13 pF 16 206 pF 20 52,800 pF EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 26 Acquisition Bandwidth • The resistance R of f switch S1 turns the 1 sampling network into a v lowpass filter with IN vOUT R S1 risetime = RC = t C • Assuming Vin is constant during the sampling period and C v (t) = v (1- e-t /t ) is initially discharged out in EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 27 Switch On-Resistance æö1 Vin-Vtout ç÷=<<D èø2 fs f1 -1 2 f t Ve s <<D in vIN vOUT S1 Worst Case: VVin= FS R T 1 C t <<- 2 ln(21B - ) 11 R <<- 2 fC B s ln(21- ) f1 Example: T=1/fS B = 14, C = 13pF, fs = 100MHz T/t >> 19.4, R << 40W EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 28 Switch On-Resistance WVæöDS 1 dID()triode ID()triode=mCoxç÷VGS-VVTH-@DS , Lèø2 RONdVDS VDS ®0 11 R == ON WW mmC(V-V) C(V--VV) oxLLGSthoxDDthin 1 for R = o W mC(VV- ) oxL DDth R R = o ON V 1- in VVDD- th EECS 247 Lecture 17: Data Converters © 2005 H.K.
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