IXAN0010 MOSFET/IGBT DRIVERS THEORY AND APPLICATIONS By Abhijit D. Pathak 1. Introduction 1.1. MOSFET and IGBT Technology. 1.2. MOSFET Models and critical parameters 1.3. Turn-on and Turn-off phenomenon and their explanations 1.4. Power losses in Drivers 2. Types of Drivers 2.1. IC Gate Drivers 2.2. Techniques available to boost current outputs 2.3. Techniques available to generate negative bias during turn-off 2.4. Need for under-voltage protections 2.5. Overload and Short Circuit Protection 3. Isolation Techniques 3.1. Employing Charge-pump and Bootstrap Techniques 3.2. Examples of use of Opto-couplers in practical Driver Circuits 3.3. Examples using transformers in practical Driver Circuits 4. IXYS Line of MOSFET/IGBT Drivers 4.1. Technical details of all IXYS Drivers 4.2. Features and Advantages of IXYS Drivers 4.3. Applying IXYS Drivers in various topologies 5. Practical Considerations 6. Conclusion © 2001 IXYS Corporation 1 IXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr. 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-503627 IXAN0010 1. INTRODUCTION 1.2 MOSFET MODELS AND CRITICAL PARAMETERS Modern Power Electronics makes generous use of MOS- Fig. (1A) shows the internal cell structure of a DMOS FETs and IGBTs in most applications and, if the present trend is any indication, the future will see more and more SOURCE GATE applications making use of MOSFETs and IGBTs. C Although sufficient literature is available on characteris- GS N+ N+ DRAIN BODY tics of MOSFETs and IGBTs, practical aspects of driving PARASITIC BJT P C GD P DEPLETION LAYER them in specific circuit configurations at different power CDS levels and at different frequencies require that design en- N- INTERNAL BODY DIODE gineers pay attention to a number of aspects. N+ An attempt is made here to review this subject with some DRAIN illustrative examples with a view to assist both experienced Fig. (1B) Cross sectional view of N-Channel MOSFET design engineers and those who are just initiated into this showing various inter-junction capacitances discipline . MOSFET. As can be seen, the Gate to Source Capaci- 1.1 MOSFET AND IGBT TECHNOLOGY tance consists of three components, namely, Cp, the com- ponent created by the Gate Electrode over the P-base Due to the absence of minority carrier transport, MOS- region; CN+, due to the overlap of the Gate Electrode above FETs can be switched at much higher frequencies. The the N+ source region and, CO, arising due to the proximity limit on this is imposed by two factors: transit time of elec- of the Gate Electrode to the source metallization. In fact, trons across the drift region and the time required to charge all these are added to yield CGS, which we call Gate-to- and discharge the input Gate and ‘Miller’ capacitances. Source Capacitance. It is this total value of capacitance that needs to be first charged to a critical threshold volt- IGBT derives its advantages from MOSFET and BJT. It age level VGS(th), before Drain Current can begin to flow. operates as a MOSFET with an injecting region on its The Gate-to-Drain capacitance, CGD, is the overlap ca- Drain side to provide for conductivity modulation of the pacitance between the Gate electrode and the N-drift Drain Drain drift region so that on-state losses are reduced, region. CGD is sometimes referred to as the ‘Miller’ ca- especially when compared to an equally rated high volt- pacitance and contributes most to the switching speed age MOSFET. limitation of the MOSFET. The junction capacitance be- tween the drain to the P-Base region is CDS. The P-Base As far as driving IGBT is concerned, it resembles a MOS- region of the MOSFET is shorted to the N+ source. Fig. FET and hence all turn-on and turn-off phenomena com- (2) shows curve of ID (Drain Current) versus VGS (Gate Source ments, diagrams and Driver circuits designed for driving MOSFET apply equally well to an IGBT. Therefore, what follows deals only with MOSFET models. I SOURCE D METALIZATION Co GATE Electrode ID I CN+ Cp CGD gm = D VGS N+ RB P-BASE VGS DRAIN CURRENT DRAIN Actual Linearized N-DRIFT CDB O Depletion boundaries VGS(th) VGS Fig. (1A) MOSFET cell internal structure Fig. (2) Transfer characteristics of a power MOSFET 2 IXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr. 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-503627 IXAN0010 1.3 Turn-on and Turn-off Phenomena Voltage). The graph has a slope ( ID/ VGS) equal to gm, which is called transconductance. Please note that the 1.3.1 Turn-on Phenomenon actual relationship between VGS and ID is shown by dotted line and it can be observed that in the vicinity of VGS(th), the To understand Turn-on and Turn-off phenomena of the Power relationship between VGS and ID is parabolic in nature: MOSFET, we will assume clamped inductive switching as 2 it is the most widely used mode of operation. This is shown ID= K [VGS-VGS(th)] Eq.1.1 in Fig. (4A) and Fig. (4B). A model of MOSFET is shown However, for Power MOSFETs, it is appropriate to con- with all relevant components, which play a role in turn-on and turn-off events. As stated above, MOSFET’s Gate to sider the relationship to be linear for values of VGS above V The manufacturer’s data sheet value of V is speci- Source Capacitance CGS needs to be charged to a critical GS(th). o GS(th) fied at 25 C. voltage level to initiate conduction from Drain to Source. A few words of explanation will help understand Fig. (4A) and Fig. (4B). The clamped inductive load is being shown Fig. (3A) shows a symbol of N-Channel MOSFET and an equivalent model of the same with three inter-junction para- by a current source with a diode D connected antiparallel across the inductor. The MOSFET has its intrinsic internal sitic capacitances, namely: CGS, CGD and CDS. I have shown all these as variable as they indeed are. For example the Gate resistance, called RGint. As described above, the in- ter-junction parametric capacitances (C , C and C ) CGD, decreases rapidly as the Drain to Source voltage rises, GS GD DS are shown and connected at their proper points. V repre- as shown in Fig. (3B). In Fig. (3B), the high value of CGD is DD sents the DC Bus voltage to the Drain of the MOSFET called CGDh, while the low value of CGD is termed CGDl. Fig. (1B) shows another cross-sectional view of a MOSFET through the clamped inductive load. The Driver is supplied with all these capacitances. In addition, It also shows the by Vcc of value Vp and its ground is connected to the internal body diode and the parasitic BJT. common ground of VDD and is returned to the Source of the MOSFET. The output from the Driver is connected to D the Gate of the MOSFET through a resistor R . D Gext +VDD CGD D RGint RDS(on) G G CDS V CC D CGS IGD C t GD S o/p RGext. RGint. Symbol of S O G i/p Rdr N-Channel MOSFET IG IGs C DS DRIVER C Fig. (3A) Symbol and equivalent circuit of a MOSFET GS S CGD CGDh Fig (4A) A MOSFET being turned on by a driver in a clamped inductive load. Now when a positive going pulse appears at the input ter- minal of the Driver, an amplified pulse appears at the out- put terminal of the Driver with an amplitude Vp. This is fed to the Gate of the MOSFET through RGext. As one can see the rate of rise of voltage, V , over Gate and Source termi- CGDl GS nals of the MOSFET is governed by value of the total resis- tance in series (R +R +R ) and total effective value of V DS = VGS V DS dr Gext Gint capacitance (CGS+CGD). Rdr stands for the output source impedance of the Driver. R is the resistance one gener- Fig. (3B) C GD variation with respect to VDS gext ally puts in series with the Gate of a MOSFET to control the turn-on and turn-off speed of the MOSFET. 3 IXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr. 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-503627 IXAN0010 +V DD Vp VDR D (a) VCC D O /P OF DRIVER -t/T1 V GS (t)=Vp(1-e ) TIME = t CGD O t R R -t/T2 Gext. Gint. VGS VGS (t)=Vp(1-e ) G i/p Rdr CDS VGS(th) (b) CGS GATE-SOURCE VOLTAGE GATE-SOURCE A1 TIME = t S A2 IG (c) I G (t) GATE CURRENT GATE TIME = t VDS (t) Fig. (4B) A MOSFET being turned off by a driver VDS (d) in a clamped inductive load. V (on) The waveforms drawn in Fig. (5) show variation of different DS DRAIN SOURCE VOLTAGE parameters with respect to time, so as to clearly explain TIME = t the entire turn-on sequence. In Fig. (4A) and Fig. (4B), the I D (t) (e) Free Wheeling Diode D is assumed to be ideal with zero ID reverse recovery current.