PDF 1.12 M ADRF6516: 31 Mhz, Dual Programmable Filters and Variable Gain Amplifiers Data Sheet

31 MHz, Dual Programmable Filters

and Variable Gain Amplifiers Data Sheet ADRF6516

FEATURES FUNCTIONAL BLOCK DIAGRAM Matched pair of programmable filters and VGAs ENBL INP1 INM1 VPS COM VICM OFS1 VPS Continuous gain control range: 50 dB Digital gain control: 15 dB 6-pole Butterworth filter: 1 MHz to 31 MHz VPSD OPP1 in 1 MHz steps, 1 dB corner frequency COMD OPM1

Preamplifier and postamplifier gain steps LE COM IMD3: >65 dBc for 1.5 V p-p composite output CLK GAIN HD2, HD3: >65 dBc for 1.5 V p-p output SPI Differential input and output DATA VOCM Flexible output and input common-mode ranges SDO COM

Optional dc offset compensation loop COM OPM2 SPI programmable filter corners and gain steps VPS ADRF6516 OPP2 Power-down feature Single 3.3 V supply operation

COM INP2 INM2 VPS COM OFDS OFS2 VPS APPLICATIONS 09422-001 Figure 1. Baseband IQ receivers Diversity receivers ADC drivers Point-to-point and point-to-multipoint radio Instrumentation Medical

GENERAL DESCRIPTION The ADRF6516 is a matched pair of fully differential, low noise The variable gain amplifiers that follow the filters provide 50 dB and low distortion programmable filters and variable gain of continuous gain control with a slope of 15.5 mV/dB. Their amplifiers (VGAs). Each channel is capable of rejecting large maximum gains can be programmed to various values through out-of-band interferers while reliably boosting the desired signal, the SPI. The output buffers provide a differential output impedance thus reducing the bandwidth and resolution requirements on the of 30 Ω and are capable of driving 2 V p-p into 1 kΩ loads. The analog-to-digital converters (ADCs). The excellent matching output common-mode voltage defaults to VPS/2, but it can be between channels and their high spurious-free dynamic range adjusted down to 700 mV by driving the high impedance over all gain and bandwidth settings make the ADRF6516 ideal VOCM pin. Independent, built-in dc offset compensation loops for quadrature-based (IQ) communication systems with dense can be disabled if fully dc-coupled operation is desired. The constellations, multiple carriers, and nearby interferers. high-pass corner frequency is defined by external capacitors on The filters provide a six-pole Butterworth response with 1 dB the OFS1 and OFS2 pins and the VGA gain. corner frequencies programmable through the SPI port from The ADRF6516 operates from a 3.15 V to 3.45 V supply 1 MHz to 31 MHz in 1 MHz steps. The preamplifier that precedes and consumes a maximum supply current of 360 mA when the filters offers a SPI-programmable option of either 3 dB or 6 dB programmed to the highest bandwidth setting. When disabled, of gain. The preamplifier sets a differential input impedance of it consumes <9 mA. The ADRF6516 is fabricated in an advanced 1600 Ω and has a common-mode voltage that defaults to VPS/2 silicon-germanium BiCMOS process and is available in a 32-lead, but can be driven from 1.1 V to 1.8 V. exposed paddle LFCSP. Performance is specified over the −40°C to +85°C temperature range.

Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADRF6516 Data Sheet

TABLE OF CONTENTS Features ...... 1 Maximizing the Dynamic Range...... 19 Applications ...... 1 Key Parameters for Quadrature-Based Receivers ...... 20 Functional Block Diagram ...... 1 Applications Information ...... 21 General Description ...... 1 Basic Connections ...... 21 Revision History ...... 2 Supply Decoupling ...... 21 Specifications ...... 3 Input Signal Path ...... 21 Timing Diagrams ...... 5 Output Signal Path ...... 21 Absolute Maximum Ratings ...... 6 DC Offset Compensation Loop Enabled ...... 21 ESD Caution ...... 6 Common-Mode Bypassing ...... 21 Pin Configuration and Function Descriptions ...... 7 Serial Port Connections ...... 22 Typical Performance Characteristics ...... 8 Enable/Disable Function ...... 22 Register Map and Codes ...... 15 Error Vector Magnitude (EVM) Performance ...... 22 Theory of Operation ...... 16 EVM Test Setup ...... 22 Input Buffers ...... 16 Effect of Filter Bandwidth on EVM ...... 22 Programmable Filters ...... 16 Effect of Output Voltage Levels on EVM ...... 23

Variable Gain Amplifiers (VGAs) ...... 17 Effect of COFS Value on EVM ...... 23 Output Buffers/ADC Drivers ...... 17 Evaluation Board ...... 24 DC Offset Compensation Loop ...... 17 Evaluation Board Control Software ...... 24 Programming the Filters and Gains ...... 18 Schematics and Artwork ...... 25 Noise Characteristics ...... 18 Outline Dimensions ...... 29 Distortion Characteristics ...... 19 Ordering Guide ...... 29

REVISION HISTORY 8/2017—Rev. B to Rev. C Change to Figure 4 ...... 7 Updated Outline Dimensions ...... 29 Changes to Ordering Guide Section ...... 29

2/2012—Rev. A to Rev. B Changes to Figure 57 ...... 24 Changes to Figure 58 ...... 25 Added Figure 59 ...... 26 Changes to Figure 60 and Figure 61 ...... 27 Changes to Table 6 ...... 27

9/2011—Revision A: Initial Version

Rev. C | Page 2 of 29 Data Sheet ADRF6516

SPECIFICATIONS

VPS = 3.3 V, T A = 25°C, ZLOAD = 1 kΩ, digital gain code = 111, unless otherwise noted.

Table 1. Parameter Test Conditions/Comments Min Typ Max Unit FREQUENCY RESPONSE

Low-Pass Corner Frequency, fC 6-pole Butterworth filter, 0.5 dB bandwidth 1 31 MHz Step Size 1 MHz

Corner Frequency Absolute Over operating temperature range ±15 % fC Accuracy

Corner Frequency Matching Channel A and Channel B at same gain and ±0.5 % fC bandwidth settings Pass-Band Ripple 0.5 dB p-p Gain Matching Channel A and Channel B at same gain and ±0.1 dB bandwidth settings Group Delay Variation From midband to peak Corner Frequency = 1 MHz 135 ns Corner Frequency = 31 MHz 11 ns Group Delay Matching Channel A and Channel B at same gain Corner Frequency = 1 MHz 5 ns Corner Frequency = 31 MHz 0.2 ns Stop-Band Rejection

Relative to Pass Band 2 × fC 30 dB

5 × fC 75 dB INPUT STAGE INP1, INM1, INP2, INM2, VICM pins

Maximum Input Swing At minimum gain, VGAIN = 0 V 1 V p-p Differential Input Impedance 1600 Ω Input Common-Mode Range 0.4 V p-p input voltage, HD3 > 65 dBc 1.1 1.65 1.8 V Input pins left floating VPS/2 V VICM Output Impedance 7 kΩ GAIN CONTROL GAIN pin

Voltage Gain Range VGAIN from 0 V to 1 V −5 +45 dB Gain Slope 15.5 mV/dB

Gain Error VGAIN from 300 mV to 800 mV 0.2 dB OUTPUT STAGE OPP1, OPM1, OPP2, OPM2, VOCM pins

Maximum Output Swing At maximum gain, RLOAD = 1 kΩ 2 V p-p HD2 > 65 dBc, HD3 > 65 dBc 1.5 V p-p Differential Output Impedance 30 Ω Output DC Offset Inputs shorted, offset loop disabled 35 mV Output Common-Mode Range 0.7 1.65 2.8 V VOCM pin left floating VPS/2 V VOCM Input Impedance 23 kΩ NOISE/DISTORTION Corner Frequency = 1 MHz

Output Noise Density Gain = 0 dB at fC/2 −141 dBV/√Hz

Gain = 20 dB at fC/2 −131 dBV/√Hz

Gain = 40 dB at fC/2 −112 dBV/√Hz Second Harmonic, HD2 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 82 dBc Gain = 40 dB 68 dBc Third Harmonic, HD3 250 kHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 71 dBc Gain = 40 dB 56 dBc

Rev. C | Page 3 of 29 ADRF6516 Data Sheet

Parameter Test Conditions/Comments Min Typ Max Unit IMD3 f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite output voltage Gain = 5 dB 61 dBc Gain = 35 dB 42.5 dBc IMD3 with Input CW Blocker f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite 40 dBc output, gain = 5 dB; blocker at 5 MHz, 10 dBc relative to two-tone composite output voltage Corner Frequency = 31 MHz Output Noise Density Midband, gain = 0 dB −143.5 dBV/√Hz Midband, gain = 20 dB −139 dBV/√Hz Midband, gain = 40 dB −125 dBV/√Hz Second Harmonic, HD2 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 68 dBc Gain = 40 dB 70 dBc Third Harmonic, HD3 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 55 dBc Gain = 40 dB 75 dBc IMD3 f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite output voltage Gain = 5 dB 55 dBc Gain = 35 dB 77.5 dBc IMD3 with Input CW Blocker f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite 55 dBc output, gain = 5 dB; blocker at 150 MHz, 10 dBc relative to two-tone composite output voltage DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS pins

Input High Voltage, VINH >2 V

Input Low Voltage, VINL <0.8 V

Input Current, IINH/IINL <1 µA

Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO pins (see Figure 2 and Figure 3)

fSCLK 1/tSCLK 20 MHz

tDH DATA hold time 5 ns

tDS DATA setup time 5 ns

tLH LE hold time 5 ns

tLS LE setup time 5 ns

tPW CLK high pulse width 5 ns

tD CLK to SDO delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL pins Supply Voltage Range 3.15 3.3 3.45 V Total Supply Current ENBL = 3.3 V Corner frequency = 31 MHz 360 mA Corner frequency = 1 MHz 330 mA Disable Current ENBL = 0 V 9 mA Disable Threshold 1.6 V Enable Response Time Delay following ENBL low-to-high transition 20 µs Disable Response Time Delay following ENBL high-to-low transition 300 ns

Rev. C | Page 4 of 29 Data Sheet ADRF6516

TIMING DIAGRAMS

tCLK tPW

CLK tLH tLS

LE tDS tDH

DATA WRITE BIT LSB B2 B3 B4 B5 B6 B7 MSBMSB - 2

NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN WRITTEN TO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK. 09422-003 Figure 2. Write Mode Timing Diagram

tCLK tPW tD CLK tLH tLS

tDS tDH

DATA READ BIT DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’TDON'T CARE CAREDON’T CARE

SDO LSB B2 B3 B4 B5 B6 B7 MSB

NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN REGISTERED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK. 09422-004 Figure 3. Read Mode Timing Diagram

Rev. C | Page 5 of 29 ADRF6516 Data Sheet

ABSOLUTE MAXIMUM RATINGS Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Supply Voltages, VPS, VPSD 3.45 V stress rating only; functional operation of the product at these ENBL, OFDS, LE, CLK, DATA, SDO VPSD + 0.5 V or any other conditions above those indicated in the operational INP1, INM1, INP2, INM2 VPS + 0.5 V section of this specification is not implied. Operation beyond OPP1, OPM1, OPP2, OPM2 VPS + 0.5 V the maximum operating conditions for extended periods may OFS1, OFS2 VPS + 0.5 V affect product reliability. GAIN VPS + 0.5 V ESD CAUTION Internal Power Dissipation 1.25 W

θJA (Exposed Pad Soldered to Board) 37.4°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C

Rev. C | Page 6 of 29 Data Sheet ADRF6516

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VICM

COM

VPS

OFS1

VPS

INM1

ENBL INP1 32 31 30 29 28 27 26 25

VPSD 1 24 OPP1 COMD 2 23 OPM1 LE 3 22 COM CLK 4 ADRF6516 21 GAIN DATA 5 TOP VIEW 20 VOCM SDO 6 (Not to Scale) 19 COM COM 7 18 OPM2 VPS 8 17 OPP2 9

10 11 12 13 14 15 16

VPS

INP2

COM

INM2

OFS2 OFDS NOTES 1. CONNECT THE EXPOSED PADDLE TO A LOW IMPEDANCE GROUND PAD. 09422-002 Figure 4. Pin Configuration

Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance.

3 LE Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.

4 CLK SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.

5 DATA SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V.

6 SDO SPI Data Output. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common using the lowest possible impedance. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 10, 11, 30, 31 INP2, INM2, Differential Inputs. 1600 Ω input impedance. INM1, INP1 14 OFDS Offset Compensation Loop Disable. Pull high to disable the offset compensation loop. 15, 26 OFS2, OFS1 Offset Compensation Loop Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. 30 Ω output impedance. Common-mode range is 0.7 V to 2.8 V; default is VPS/2. OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left floating. 21 GAIN Analog Gain Control. 0 V to 1 V, 15.5 mV/dB gain scaling. 27 VICM Input Common-Mode Voltage. VPS/2 V reference. Use to reference the optimal common-mode drive to the differential inputs. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad.

Rev. C | Page 7 of 29 ADRF6516 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VPS = 3.3 V, T A = 25°C, ZLOAD = 1 kΩ, digital gain code = 111, unless otherwise noted.

50 5.0 BANDWIDTH = 31MHz 4.5 BANDWIDTH = 31MHz 45 4.0 3.5 40 +25°C VPS = 3.15V, 3.3V, 3.45V 3.0 35 2.5 +85°C 2.0 VPS = 3.15V, 3.3V, 3.45V 30 1.5 –40°C 25 1.0 VPS = 3.15V, 3.3V, 3.45V 0.5 20 0 +85°C –0.5 GAIN (dB) 15 VPS = 3.15V, 3.3V, 3.45V –1.0 –1.5 10 GAIN ERROR (dB) –2.0 +25°C VPS = 3.15V, 3.3V, 3.45V 5 –2.5 –40°C –3.0 VPS = 3.15V, 3.3V, 3.45V 0 –3.5 –4.0 –5 –4.5 –10 –5.0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 V (mV) V (mV) 09422-005 GAIN GAIN 09422-008 Figure 5. In-Band Gain vs. VGAIN over Supply and Temperature Figure 8. Gain Conformance vs. VGAIN over Supply and Temperature (Bandwidth Setting = 31 MHz) (Bandwidth Setting = 31 MHz)

50 –5 8 45 BANDWIDTH = 31MHz BANDWIDTH = 31MHz 40 –6 7 35 30 –7 6 25 20 –8 DIGITAL GAIN = 111 5 15 10 –9 4 (dB)

5 P 0 –10 3 –5 GAIN (dB) –10 –11 2 GAIN STE GAIN –15 AMPLITUDE (dB) –20 –12 DIGITAL GAIN = 011 1 –25 –30 –13 0 –35 –40 –14 –1 –45 –50 –15 –2 1 10 100 0 5 10 15 20 25 30 35 09422-009 FREQUENCY (MHz) 09422-006 FREQUENCY (MHz) Figure 6. Gain vs. Frequency over VGAIN (Bandwidth Setting = 31 MHz) Figure 9. Gain Step and Gain Error vs. Frequency (Bandwidth Setting = 31 MHz, VGAIN = 0 V)

0.25 0 14 BANDWIDTH = 31MHz BANDWIDTH = 31MHz 0.20 –5 13 0.15

0.10 –10 DIGITAL GAIN = 011 12 0.05 (dB) TCH (dB) P A 0 –15 11

–0.05 GAIN STE GAIN AMPLITUDE (dB) –20 10 GAIN MISM GAIN –0.10 DIGITAL GAIN = 000

–0.15 –25 9 –0.20

–0.25 –30 8 0 100 200 300 400 500 600 700 800 900 1000 0 5 10 15 20 25 30 35 V (mV) GAIN 09422-007 FREQUENCY (MHz) 09422-010 Figure 7. Gain Matching vs. VGAIN (Bandwidth Setting = 31 MHz) Figure 10. Gain Step and Gain Error vs. Frequency (Bandwidth Setting = 31 MHz, VGAIN = 0 V)

Rev. C | Page 8 of 29 Data Sheet ADRF6516

20 40 BANDWIDTH = 31MHz BANDWIDTH = 31MHz 38 15 36 10 34 –40°C, VPS = 3.15V, 3.3V, 3.45V 5 DIGITAL GAIN = 111 32

0 30 GAIN (dB)

OP1dB (dBV) 28 –5 +25°C, DIGITAL GAIN = 000 26 VPS = 3.15V, 3.3V, 3.45V –10 +85°C, 24 VPS = 3.15V, 3.3V, 3.45V –15 22 1

–20 1 20 0 5 10 15 20 25 30 35 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GAIN (dB) 09422-0 V (mV) GAIN 09422-014 Figure 11. Output P1dB vs. Gain at 15 MHz (Bandwidth Setting = 31 MHz) Figure 14. Frequency Response over Supply and Temperature (Bandwidth Setting = 31 MHz, Gain = 30 dB)

40 1000 GAIN = 20dB 35 900

30 800 BW = 1MHz

25 700 (ns)

20 Y 600 A

15 500 DEL P

GAIN (dB) 10 400 GROU 5 300 BW = 10MHz BW = 31MHz

0 200 BW = 5MHz BW = 20MHz

–5 100

–10 0 1 10 100 0.3 3 30 50

FREQUENCY (MHz) 09422-012 FREQUENCY (MHz) 09422-015 Figure 12. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 15. Group Delay vs. Frequency (Gain = 20 dB) Log Scale

40 2.0 BANDWIDTH = 31MHz 35 1.5 30 1.0 25 TCH (ns)

A 0.5 20

15 MISM 0 Y

A GAIN = 20dB GAIN (dB) 10 –0.5 DEL P 5 –1.0 GAIN = 40dB

0 GROU –1.5 –5

–10 –2.0 0 10 20 30 40 50 60 70 80 90 100 0.3 3 30 09422-013 FREQUENCY (MHz) FREQUENCY (MHz) 09422-016 Figure 13. Frequency Response vs. Bandwidth Setting (Gain = 30 dB), Figure 16. Group Delay Matching vs. Frequency Linear Scale (Bandwidth Setting = 31 MHz)

Rev. C | Page 9 of 29 ADRF6516 Data Sheet

5 90 BANDWIDTH = 1MHz VOCM = 0.9V 4 VOCM = 1.2V VOCM = 1.4V GAIN = 0dB 80 VOCM = 1.65V 3

TCH (ns) 70 A 1

MISM 0 60 Y A T 16MHz (dBc)

–1 A DEL

P GAIN = 20dB 50 –2 HD2

GROU –3 40 –4

–5 30 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 5 10 15 20 25 30 35 40 45 09422-017 FREQUENCY (MHz) GAIN (dB) 09422-020 Figure 17. IQ Group Delay Matching vs. Frequency Figure 20. HD2 vs. Gain over Output Common-Mode Voltage (Bandwidth Setting = 1 MHz) (Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)

FREQUENCY (MHz) 90 0 0.5 1.0 1.5 2.0 2.5 3.0 0.50 80

60 0.25

50 TCH (dB)

A BANDWIDTH = 1MHz BANDWIDTH = 30MHz

T 24MHz (dBc) 40 0 A +25°C, VPS = 3.3V 30 +25°C, VPS = 3.15V HD3 +25°C, VPS = 3.45V +85°C, VPS = 3.3V 20 +85°C, VPS = 3.15V +85°C, VPS = 3.45V –0.25

AMPLITUDE MISM –40°C, VPS = 3.3V 10 –40°C, VPS = 3.15V –40°C, VPS = 3.45V 0 0 5 10 15 20 25 30 35 40 45 –0.50 GAIN (dB) 09422-022 0 5 10 15 20 25 30

FREQUENCY (MHz) 09422-018 Figure 18. IQ Amplitude Matching vs. Frequency Figure 21. HD3 vs. Gain over Supply and Temperature (Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)

90 90 VOCM = 0.9V VOCM = 1.2V 80 VOCM = 1.4V 80 VOCM = 1.65V 70

60 70

50 60 T 24MHz (dBc) T 16MHz (dBc) 40 A A +25°C, VPS = 3.3V 30 +25°C, VPS = 3.15V 50 HD3 HD2 +25°C, VPS = 3.45V +85°C, VPS = 3.3V 20 +85°C, VPS = 3.15V +85°C, VPS = 3.45V 40 10 –40°C, VPS = 3.3V –40°C, VPS = 3.15V –40°C, VPS = 3.45V 0 30 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 09422-023 GAIN (dB) 09422-019 GAIN (dB) Figure 19. HD2 vs. Gain over Supply and Temperature Figure 22. HD3 vs. Gain over Output Common-Mode Voltage (Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output) (Bandwidth Setting = 31 MHz, 1.5 V p-p, 8 MHz CW Fundamental Output)

Rev. C | Page 10 of 29 Data Sheet ADRF6516

80 110 GAIN = 0dB, HD2 GAIN = 0dB, HD3 100 GAIN = 10dB, HD2 75 GAIN = 10dB, HD3 90

80 70 70 ORTION (dBc) ORTION T 65 60

IMD3 (dBc) 50 GAIN = 30dB GAIN = 20dB 60 40 GAIN = 10dB GAIN = 0dB

HARMONIC DIS 30 55 20

50 10 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMPOSITE OUTPUT VOLTAGE (V p-p) 09422-027 VICM (V) 09422-024 Figure 23. HD2 and HD3 vs. Input Common-Mode Voltage Figure 26. In-Band Third-Order Intermodulation Distortion (Bandwidth Setting = 31 MHz, 0.4 V p-p Input Level) (Bandwidth Setting = 31 MHz, Digital Gain = 000)

45 100 BANDWIDTH = 31MHz f1 = 14MHz, f2 = 15MHz DIGITAL GAIN = 000 40 90

80 35 DIGITAL GAIN = 111 70 30 60 25 50 20 IMD3 (dBc) OIP3 (dBV) 40 15 GAIN = 40dB 30 GAIN = 30dB GAIN = 20dB 10 20 GAIN = 10dB GAIN = 0dB 5 10

0 0 0 5 10 15 20 25 30 35 40 45 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMPOSITE OUTPUT VOLTAGE (V p-p) 09422-028 GAIN (dB) 09422-025 Figure 24. In-Band OIP3 vs. Gain (Bandwidth Setting = 31 MHz) Figure 27. In-Band Third-Order Intermodulation Distortion (Bandwidth Setting = 31 MHz, Digital Gain = 111)

45 70 BANDWIDTH = 31MHz 60 –40°C f1 = 14MHz, f2 = 15MHz 50 BANDWIDTH = 31MHz 40 DIGITAL GAIN = 111 40 30 35 20 10 0 30 +85°C +25°C –10 –20 –30 2:1 SLOPE 25 –40 –50 –60 20 T 15MHz (dBV) A OIP3 (dBV) –70 –80 15 –90 IMD2 –100 –110 10 –120 –130 OUT-OF-BAND IIP2 5 –140 –150 PREAMP GAIN = 6dB –160 PREAMP GAIN = 3dB 0 –170 0 5 10 15 20 25 30 35 40 45 50 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 09422-026 GAIN (dB) INPUT LEVEL AT 115MHz AND 130MHz (dBV/TONE) 09422-029 Figure 25. In-Band OIP3 vs. Gain over Temperature Figure 28. Out-of-Band IIP2, IMD2 Tone at Midband (Bandwidth Setting = 31 MHz) (Bandwidth Setting = 31 MHz)

Rev. C | Page 11 of 29 ADRF6516 Data Sheet

10 –110 0 BANDWIDTH = 31MHz –115 –10 –20 Hz) –120 –30 √ DIGITAL GAIN = 000 –40 –125 DIGITAL GAIN = 100 (dBV/

–50 3:1 SLOPE Y DIGITAL GAIN = 110 –60 –130 DIGITAL GAIN = 111 –70 –135 –80 T 15MHz (dBV) A –90 –140 –100

IMD3 –110 –145 –120 OUT-OF-BAND IIP3 –150 –130 OUTPUT NOISE DENSIT NOISE OUTPUT –140 PREAMP GAIN = 6dB –155 –150 PREAMP GAIN = 3dB –160 –160 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 –20 –10 0 10 20 30 40 50

GAIN (dB) 09422-033 INPUT LEVEL AT 115MHz AND 215MHz (dBV/TONE) 09422-030 Figure 29. Out-of-Band IIP3, IMD3 Tone at Midband Figure 32. Output Noise Density vs. Analog Gain over Digital Gain (Bandwidth Setting = 31 MHz) (Bandwidth Setting = 31 MHz, Measured at 1/2 Bandwidth)

60 –100

55 –105 DIGITAL GAIN = 000 50 DIGITAL GAIN = 100 –110 DIGITAL GAIN = 110 1MHz 45 DIGITAL GAIN = 111 –115 (dBV/√Hz) 2MHz Y 4MHz 40 –120 8MHz 16MHz 35 –125 31MHz NF (dB) 30 –130

25 –135

20 –140 OUTPUT NOISE DENSIT NOISE OUTPUT 15 –145

10 –150 –20 –10 0 10 20 30 40 50 –5 0 5 10 15 20 25 30 35 40 45 50 GAIN (dB) GAIN (dB) 09422-034 09422-031 Figure 30. Noise Figure vs. Analog Gain over Digital Gain Figure 33. Output Noise Density vs. Gain over Bandwidth Setting (Bandwidth Setting = 31 MHz, Noise Figure at 1/2 Bandwidth) (Digital Gain = 111, Measured at 1/2 Bandwidth)

50 –100 1MHz GAIN = 40dB BANDWIDTH = 1MHz 2MHz –105 DIGITAL GAIN = 111 45 4MHz 8MHz –110 16MHz 31MHz –115

40 (dBV/√Hz) Y –120 GAIN = 20dB 35 –125 NF (dB) –130 30 –135

–140 GAIN = 0dB

25 DENSIT NOISE OUTPUT –145

20 –150 –5 5 15 25 35 45 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2

GAIN (dB) FREQUENCY (MHz) 09422-052 09422-032 Figure 31. Noise Figure vs. Gain over Bandwidth Setting Figure 34. Output Noise Density vs. Frequency (Digital Gain = 111, Noise Figure at 1/2 Bandwidth) (Bandwidth Setting = 1 MHz, Digital Gain = 111)

Rev. C | Page 12 of 29 Data Sheet ADRF6516

–110 50 35 BANDWIDTH = 31MHz BANDWIDTH = 31MHz –115 DIGITAL GAIN = 111 GAIN = 40dB 40 30 –120

–125 (Ω)

30 25 (nH)

–130

SERIES OUT 20 20 GAIN = 20dB SERIES OUT

–135 R L

–140 GAIN = 0dB 10 15 OUTPUT NOISE DENSITY (dBV/√Hz) DENSITY NOISE OUTPUT –145

–150 0 10 5 15 25 35 45 55 65 75 85 95 5 10 15 20 25 30

FREQUENCY (MHz) FREQUENCY (MHz) 09422-039 09422-051 Figure 35. Output Noise Density vs. Frequency Figure 38. Output Impedance vs. Frequency (Bandwidth Setting = 31 MHz, Digital Gain = 111) (Bandwidth Setting = 31 MHz)

–90 120 BANDWIDTH = 31MHz –95 DIGITAL GAIN = 111 –100 100 GAIN = 40dB –105 80 GAIN = 20dB –110 T 15MHz (dBV/√Hz) A

Y –115 GAIN = 0dB GAIN = 40dB 60 TION (dB) TION

–120 A

–125 ISOL 40 –130 GAIN = 20dB –135 20 GAIN = 0dB –140 BANDWIDTH = 31MHz OUTPUT NOISE DENSIT NOISE OUTPUT –145 0 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30

BLOCKER LEVEL AT 150MHz (dBV rms) FREQUENCY (MHz) 09422-040 09422-037 Figure 36. Output Noise Density vs. Input CW Blocker Level Figure 39. Channel Isolation, Output to Output, vs. Frequency (Bandwidth Setting = 31 MHz, Blocker at 150 MHz) (Bandwidth Setting = 31 MHz)

2500 40 365 BANDWIDTH = 31MHz 360

2000 20 355

350 (mA) Ω) Y ( (pF) 1500 0 L 345 IN IN R C SUPP I 340

1000 –20 335

DIGITAL GAIN = 000 330 DIGITAL GAIN = 111

500 –40 325 0 5 10 15 20 25 30 0 5 10 15 20 25 30 35

09422-038 BANDWIDTH (MHz) FREQUENCY (MHz) 09422-041 Figure 37. Input Impedance vs. Frequency Figure 40. Current Consumption at Minimum and Maximum Digital Gain (Bandwidth Setting = 31 MHz) vs. Bandwidth (Bandwidth Setting = 31 MHz, Gain = 30 dB)

Rev. C | Page 13 of 29 ADRF6516 Data Sheet

370 70 BANDWIDTH = 31MHz BANDWIDTH = 31MHz 368 60 GAIN = 40dB 366 50 GAIN = 20dB 364

362 40 (mA) Y L 360 30 CMRR (dB) SUPP I 358 20 356 10 354 DIGITAL GAIN = 000 DIGITAL GAIN = 111

352 0 –40 –20 0 20 40 60 80 100 0 5 10 15 20 25 30 09422-144 TEMPERATURE (°C) 09422-042 FREQUENCY (MHz) Figure 41. Current Consumption at Minimum and Maximum Digital Gain Figure 43. Common-Mode Rejection Ratio (CMRR) vs. Frequency vs. Temperature (Bandwidth Setting = 31 MHz, Gain = 30 dB) (Bandwidth Setting = 31 MHz)

BANDWIDTH = 31MHz

20dB GAIN STEP VGAIN = 750mV TO 450mV

28MHz SIGNAL = 60mV p-p TO 600mV p-p

200ns/DIV

09422-143 Figure 42. Gain Step Response

Rev. C | Page 14 of 29 Data Sheet ADRF6516

REGISTER MAP AND CODES The filter frequency, preamplifier gain, postamplifier gain, and VGA maximum gain can be programmed using the SPI interface. Table 4 provides the bit map for the internal 8-bit register of the ADRF6516. The preamplifier, postamplifier, and VGA maximum gain code bits (Bits[B3:B1]) are referred to elsewhere in this data sheet as Digital Gain Code 000 through Digital Gain Code 111.

Table 4. Register Map MSB LSB B8 B7 B6 B5 B4 B3 B2 B1 Filter frequency code Preamplifier gain Postamplifier gain VGA max gain code code code See Table 5 0 = 3 dB 0 = 6 dB 0 = 22 dB 1 = 6 dB 1 = 12 dB 1 = 28 dB

Table 5. Frequency Code vs. Corner Frequency Lookup Table 5-Bit Binary Frequency Code1 Corner Frequency (MHz) 5-Bit Binary Frequency Code1 Corner Frequency (MHz) 00000 No signal 10000 16 00001 1 10001 17 00010 2 10010 18 00011 3 10011 19 00100 4 10100 20 00101 5 10101 21 00110 6 10110 22 00111 7 10111 23 01000 8 11000 24 01001 9 11001 25 01010 10 11010 26 01011 11 11011 27 01100 12 11100 28 01101 13 11101 29 01110 14 11110 30 01111 15 11111 31

1 MSB first.

Rev. C | Page 15 of 29 ADRF6516 Data Sheet

THEORY OF OPERATION The ADRF6516 consists of a matched pair of buffered, program- The input buffers in both channels can be configured simul- mable filters followed by a cascade of two variable gain amplifiers taneously for a gain of 3 dB or 6 dB through the SPI (see the and output ADC drivers. The block diagram of a single channel Register Map and Codes section). When configured for a 3 dB is shown in Figure 44. gain, the buffers support a 400 mV p-p differential input level The programmability of the bandwidth and of the pre- and post- with ~70 dBc harmonic distortion. For a 6 dB gain setting, the filtering gain through the SPI interface offers great flexibility buffers support 280 mV p-p inputs. when coping with signals of varying levels in the presence of PROGRAMMABLE FILTERS noise and large, undesired signals nearby. The entire differential The integrated programmable filter is the key signal processing signal chain is dc-coupled with flexible interfaces at the input function in the ADRF6516. The filters follow a six-pole Butter- and output. The bandwidth and gain setting controls for the two worth prototype response that provides a compromise between channels are shared, ensuring close matching of their magnitude band rejection, ripple, and group delay. The 0.5 dB bandwidth is and phase responses. The ADRF6516 can be fully disabled programmed from 1 MHz to 31 MHz in 1 MHz steps via the serial through the ENBL pin. programming interface (SPI), as described in the Programming 1MHz TO 31MHz 6dB/12dB 3dB/6dB PROG. 25dB 25dB ADC the Filters and Gains section. PREAMP FILTERS VGA VGA DRIVER The filters are designed so that the Butterworth prototype filter BASEBAND BASEBAND INPUTS OUTPUTS shape and group delay responses vs. frequency are retained for any bandwidth setting. Figure 45 and Figure 46 illustrate the ideal six-pole Butterworth magnitude and group delay responses, respectively. The group delay, τg, is defined as 3dB/6dB 6dB/12dB 11dB/14dB τg = −∂φ/∂ω SPI INTERFACE where: φ is the phase in radians. GAIN AND FILTER PROGRAMMING ANALOG OUTPUT ω = 2πf (the frequency in radians/sec). SPI BUS GAIN CONTROL COMMON-MODE 15mV/dB CONTROL 09422-046 Note that for a frequency scaled filter prototype, the absolute Figure 44. Signal Path Block Diagram for a Single Channel of the ADRF6516 magnitude of the group delay scales inversely with the band- Filtering and amplification are fundamental operations in any width; however, the shape is retained. For example, the peak signal processing system. Filtering is necessary to select the group delay for a 28 MHz bandwidth setting is 14× less than intended signal while rejecting out-of-band noise and inter- for a 2 MHz setting (see Figure 46). ferers. Amplification increases the level of the desired signal 0 to overcome noise added by the system. When used together, –20 filtering and amplification can extract a low level signal of –40 interest in the presence of noise and out-of-band interferers. Such analog signal processing alleviates the requirements on –60 the analog, mixed signal, and digital components that follow. –80

INPUT BUFFERS –100

The input buffers provide a convenient interface to the sensitive –120

filter sections that follow. They set a differential input impedance RELATIVE MAGNITUDE (Hz) –140 of 1600 Ω and float to a common-mode voltage near VPS/2. The inputs can be dc-coupled or ac-coupled. If using direct dc coupling, –160 the common-mode voltage presented to the inputs must be –180 1M 10M 100M 1G approximately VPS/2 to maximize the input swing capacity. FREQUENCY (Hz) 09422-043 For a 3.3 V supply, the common-mode voltage can range Figure 45. Sixth-Order Butterworth Magnitude Response for 0.5 dB from 1.1 V to 1.8 V while maintaining a >65 dBc HD3 for a Bandwidths Programmed from 2 MHz to 29 MHz in 1 MHz Steps 400 mV p-p input signal. The VICM pin provides the optimal midsupply common-mode voltage and can be used as a reference for the driving circuit. The VICM voltage is not buffered and must be sensed at a high impedance point to prevent it from being loaded down.

Rev. C | Page 16 of 29 Data Sheet ADRF6516

500 50 0.3

15mV/dB 400 40 0.2 BW = 2MHz BW = 28MHz

300 30 0.1

200 20 0 14× GAIN (dB)

100 GAIN ERROR (dB) GROUP DELAY (ns) 10 –0.1

0 0 –0.2

–100 –10 –0.3 100k 1M 10M 100M 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 FREQUENCY (Hz) 09422-044

V (V) 09422-049 GAIN Figure 46. Sixth-Order Butterworth Group Delay Response for Figure 47. Linear-in-dB Gain Control Response of the X-AMP VGA Cascade 0.5 dB Bandwidths Programmed to 2 MHz and 28 MHz Showing Consistent Slope and Low Error The corner frequency of the filters is defined by RC products, OUTPUT BUFFERS/ADC DRIVERS which can vary by ±30% in a typical process. Therefore, all the parts are factory calibrated for corner frequency, resulting in The low impedance (30 Ω) output buffers of the ADRF6516 a residual ±15% corner frequency variation over the −40°C to are designed to drive either ADC inputs or subsequent amplifier +85°C temperature range. Although absolute accuracy requires stages. They are capable of delivering up to 1.5 V p-p composite calibration, the matching of RC products between the pair of two-tone signals into 1 kΩ differential loads with >65 dBc channels is better than 1% by observing careful design and IMD3. The output common-mode voltage defaults to VPS/2, layout practices. Calibration and excellent matching ensure but it can be adjusted from 700 mV to 2.8 V without loss of that the magnitude and group delay responses of both channels drive capability by presenting the VOCM pin with the desired track together, a critical requirement for digital IQ-based common-mode voltage. The high input impedance of VOCM communication systems. allows the ADC reference output to be connected directly. Even though the output common-mode voltage is adjustable and the VARIABLE GAIN AMPLIFIERS (VGAs) offset compensation loop can null the accumulated dc offsets The cascaded VGAs are based on the Analog Devices, Inc., (see the DC Offset Compensation Loop section), it may still be patented X-AMP® architecture, consisting of tapped 25 dB desirable to ac couple the outputs by selecting the coupling cap- attenuators followed by programmable gain amplifiers. The acitors according to the load impedance and desired bandwidth. X-AMP architecture generates a continuous linear-in-dB DC OFFSET COMPENSATION LOOP monotonic gain response with low ripple. The analog gains of both cascaded VGA sections are controlled through the high In many signal processing applications, no information is impedance GAIN pin with an accurate slope of 15 mV/dB. carried in the dc level. In fact, dc voltages and other low frequency disturbances can often dominate the intended signal The gain response shown in Figure 47 shows the GAIN pin and consume precious dynamic range in the analog path and voltage range and the absence of gain foldback at high VGAIN. bits in the data converters. These dc voltages can be present By changing the gains of both VGAs simultaneously, a more with the desired input signal or can be generated inside the gradual variation in noise and distortion is achieved. The fixed signal path by inherent dc offsets or other unintended signal- gain following each of the variable gain sections can also be pro- dependent processes such as self-mixing or rectification. grammed to two different values to maximize dynamic range. Because the ADRF6516 is fully dc-coupled, it may be necessary to remove these offsets to realize the maximum signal-to-noise ratio (SNR). This can be achieved with ac coupling capacitors at the input and output pins; however, large value capacitors with low impedance values are required because the high-pass corners must be <10 Hz. To address the issue of dc offsets, the ADRF6516 provides an offset compensation loop that nulls the output differential dc level, as shown in Figure 48. If the compensation loop is not required, it can be disabled by pulling the OFDS pin high.

Rev. C | Page 17 of 29 ADRF6516 Data Sheet

NOISE CHARACTERISTICS COFS OFDS OFSx The output noise behavior of the ADRF6516 depends on the gain and bandwidth settings. Figure 49 and Figure 50 show the total output noise spectral density vs. frequency for different bandwidth settings and VGA gains. FROM BASEBAND FILTERS OUTPUTS –110 BANDWIDTH = 31MHz 50dB OUTPUT ADC –115 DIGITAL GAIN = 111 VGA DRIVER GAIN = 40dB

GAIN 09422-050 –120 Figure 48. Offset Compensation Loop Operates Around the VGA and Output Buffer –125

–130 The offset compensation loop creates a high-pass corner, fHP, that is superimposed on the normal Butterworth filter response. –135 GAIN = 20dB Typically, fHP is many orders of magnitude lower than the lowest –140 programmed filter bandwidth so that there is no interaction GAIN = 0dB OUTPUT NOISE DENSITY (dBV/√Hz) DENSITY NOISE OUTPUT between them. Setting fHP is accomplished with capacitors, –145 COFS, from the OFS1 and OFS2 pins to ground. Because the –150 compensation loop works around the VGA sections, fHP is also 5 15 25 35 45 55 65 75 85 95 FREQUENCY (MHz) dependent on the total gain of the cascaded VGAs. In general, 09422-051 the expression for fHP is given by Figure 49. Total Output Noise Density with a 31 MHz Corner Frequency for Three Different Gain Settings fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF)) –100 where Post Filter Linear Gain is expressed in linear terms, not GAIN = 40dB BANDWIDTH = 1MHz –105 DIGITAL GAIN = 111 in decibels (dB), and is the gain following the filters, which excludes the preamplifier gain of 1.4 (3 dB) or 2 (6 dB). –110 –115 (dBV/√Hz)

Note that fHP increases in proportion to the gain. For this reason, Y –120 COFS must be chosen at the highest operating gain to guarantee GAIN = 20dB –125 that fHP is always below the maximum limit required by the system. PROGRAMMING THE FILTERS AND GAINS –130 –135 The 0.5 dB corner frequencies for both filters and the gains of –140 GAIN = 0dB the preamplifiers and postamplifiers are programmed simulta- DENSIT NOISE OUTPUT neously through the SPI port. An 8-bit register stores the 5-bit –145 code for corner frequencies of 1 MHz through 31 MHz, as well –150 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 as the 1-bit codes for the preamplifier gain, the VGA maximum FREQUENCY (MHz) 09422-052 gain, and the postamplifier gain (see Table 4). The SPI protocol Figure 50. Total Output Noise Density with a 1 MHz Corner Frequency not only allows frequency and gain codes to be written to the for Three Different Gain Settings DATA pin, but it also allows the stored code to be read back via Both the filter sections and the VGAs contribute to the total noise the SDO pin. at the output. The filter contributes a noise spectral density profile The latch enable (LE) pin must first go to a Logic 0 for a read or that is flat at low frequencies, peaks near the corner frequency, and write cycle to begin. On the next rising edge of the clock (CLK), then rolls off as the filter poles roll off the gain and noise. The a Logic 1 on the DATA pin initiates a write cycle, whereas a magnitude of the noise spectral density contributed by the filter, Logic 0 on the DATA pin initiates a read cycle. In a write cycle, expressed in nV/√Hz, varies inversely with the square root of the the next eight CLK rising edges latch the desired 8-bit code, LSB bandwidth setting, resulting in a total integrated noise in nV that is first. When LE goes high, the write cycle is completed and the nearly constant with bandwidth setting. At higher frequencies, frequency and gain codes are presented to the filter and ampli- after the filter noise rolls off, the noise floor is set by the VGAs. fiers. In a read cycle, the next eight CLK falling edges present Each of the X-AMP VGA sections used in the ADRF6516 con- the stored 8-bit code, LSB first. When LE goes high, the read tributes a fixed and flat noise spectral density to its respective cycle is completed. Detailed timing diagrams are shown in output, independent of the gain setting. Because the VGAs are Figure 2 and Figure 3. cascaded in the ADRF6516, the total noise contributed by the VGAs at the output increases gradually with higher gain. This is apparent in the noise floor variation at high frequencies at different VGA gain settings.

Rev. C | Page 18 of 29 Data Sheet ADRF6516

The exact relationship depends on the programmed fixed gain of As noted in the Input Buffers section, the input section can the amplifiers. At minimum gain, only the last VGA contributes handle a total signal level of 400 mV p-p for a 3 dB preamplifier to the −144 dBV/√Hz minimum noise floor, which is equivalent gain and 280 mV p-p for a 6 dB preamplifier gain with >70 dBc to 63 nV/√Hz. At lower frequencies within the filter bandwidth harmonic distortion. This includes both in-band and out-of-band setting, the VGAs translate the filter noise directly to the output signals. by a factor equal to the gain following the filter. To distinguish and quantify the distortion performance of the At low values of VGA gain, the noise at the output is the flat input section, two different IP3 specifications are presented. The spectral density contributed by the last VGA. As the gain first is called in-band IP3 and refers to a two-tone test where the increases, more noise from the filter and first VGA appears at signals are inside the filter bandwidth. This is exactly the same the output. Because the intrinsic filter noise density increases figure of merit familiar to communications engineers in which at lower bandwidth settings, it is more pronounced than it is the third-order intermodulation level, IMD3, is measured. at higher bandwidth settings. In either case, the noise density To quantify the effect of out-of-band signals, a new out-of-band asymptotically approaches the limit set by the VGAs at the (OOB) IIP3 figure of merit is introduced. This test also involves highest frequencies. For other values of VGA gain and bandwidth a two-tone stimulus; however, the two tones are placed out-of- setting, the detailed shape of the noise spectral density changes band so that the lower IMD3 product lands in the middle of the according to the relative contributions of the filters and VGAs. filter pass band. At the output, only the IMD3 product is visible Because the noise spectral density outside the filter bandwidth because the original two tones are filtered out. To calculate the is limited by the VGA output noise, it may be necessary to use OOB IIP3 at the input, the IMD3 level is referred to the input an external, fixed-frequency, passive filter prior to analog-to- by the overall gain. The OOB IIP3 allows the user to predict the digital conversion to prevent noise aliasing from degrading the impact of out-of-band blockers or interferers at an arbitrary signal-to-noise ratio. A higher sampling rate relative to the maxi- signal level on the in-band performance. The ratio of the desired mum required ADRF6516 corner frequency setting reduces the input signal level to the input-referred IMD3 at a given blocker order and complexity of this external filter. level represents a signal-to-distortion limit imposed by the out- DISTORTION CHARACTERISTICS of-band signals. The distortion performance of the ADRF6516 is similar to its MAXIMIZING THE DYNAMIC RANGE noise performance. The filters and the VGAs contribute to the The role of the ADRF6516 is to increase the level of a variable overall distortion and signal handling capabilities. Furthermore, in-band signal while minimizing out-of-band signals. Ideally, the front end must also cope with out-of-band signals that can be this is achieved without degrading the SNR of the incoming larger than the in-band signals. These out-of-band signals are signal or introducing distortion to the incoming signal. filtered before reaching the VGA. It is important to understand The first goal is to maximize the output signal swing, which can the signals presented to the ADRF6516 and to match these be defined by the ADC input range or the input signal capacity signals with the input and output characteristics of the part. of the next analog stage. For the complex waveforms often encoun- When the gain is low, the distortion is typically limited by the tered in communication systems, the peak-to-average ratio, or input section because the output is not driven to its maximum crest factor, must be considered when selecting the peak-to-peak capacity. When the gain is high, the distortion is likely limited output. From the selected output signal and the maximum gain by the output section because the input is not driven to its of the ADRF6516, the minimum input level can be defined. maximum capacity. An exception to this is when the input is Lower signal levels do not yield the maximum output and suffer driven with a small desired signal in combination with a large a greater degradation in SNR. out-of-band signal. In this case, the out-of-band signal may As the input signal level increases, the VGA gain is reduced from drive the input to distort. As long as the input is not overdriven, its maximum gain point to maintain the desired fixed output the out-of-band signal is removed by the filter. A high VGA level. The output noise, initially dominated by the filter, follows gain is still needed to raise the small desired signal to a higher the gain reduction, yielding a progressively better SNR. At some level at the output. The overall distortion introduced by the part point, the VGA gain drops sufficiently that the VGA noise depends on the input drive level, including the out-of-band becomes dominant, resulting in a slower reduction in SNR from signals, and the desired output signal level. that point. From the perspective of SNR alone, the maximum input level is reached when the VGA reaches its minimum gain.

Rev. C | Page 19 of 29 ADRF6516 Data Sheet

Distortion must also be considered when maximizing the dynamic KEY PARAMETERS FOR QUADRATURE-BASED range. At low and moderate signal levels, the output distortion RECEIVERS is constant and assumed to be adequate for the selected output The majority of digital communication receivers makes use of level. At some point, the input signal becomes large enough that quadrature signaling, in which bits of information are encoded distortion at the input limits the system. The maximum tolerable onto pairs of baseband signals that then modulate in-phase (I) input signal depends on whether the input distortion becomes and quadrature (Q) sinusoidal carriers. Both the baseband and unacceptably large or the minimum gain is reached. modulated signals appear quite complex in the time domain with The most challenging scenario in terms of dynamic range is the dramatic peaks and valleys. In a typical receiver, the goal is to presence of a large out-of-band blocker accompanying a weaker recover the pair of quadrature baseband signals in the presence in-band desired signal. In this case, the maximum input level is of noise and interfering signals after quadrature demodulation. dictated by the blocker and its inclination to cause distortion. In the process of filtering out-of-band noise and undesired inter- After filtering, the weak desired signal must be amplified to the ferers and restoring the levels of the desired I and Q baseband desired output level, possibly requiring maximum gain. Both signals, it is critical to retain their gain and phase integrity over the distortion limits associated with the blocker at the input and the bandwidth. the SNR limits created by the weaker signal and higher gains are The ADRF6516 delivers flat in-band gain and group delay, present simultaneously. Furthermore, not only does the blocker consistent with a six-pole Butterworth prototype filter, as scenario degrade the dynamic range, it also reduces the range described in the Programmable Filters section. Furthermore, of input signals that can be handled because a larger part of the careful design ensures excellent matching of these parameters gain range is used to simply extract the weak desired signal between the I and Q channels. Although absolute gain flatness from the stronger blocker. and group delay can be corrected with digital equalization, mismatch introduces quadrature errors and intersymbol interference that degrade bit error rates in digital communication systems.

Rev. C | Page 20 of 29 Data Sheet ADRF6516

APPLICATIONS INFORMATION BASIC CONNECTIONS For example, the high impedance VOCM input pin of the Figure 51 shows the basic connections for a typical ADRF6516 ADRF6806 quadrature demodulator can be directly connected application. to the VICM pin of the ADRF6516. This gives the ADRF6806 the optimal common-mode voltage reference to drive the SUPPLY DECOUPLING ADRF6516. A nominal supply voltage of 3.3 V must be applied to the supply OUTPUT SIGNAL PATH pins. The supply voltage must not exceed 3.45 V or drop below 3.15 V. Each supply pin must be decoupled to ground with at The low impedance (30 Ω) output buffers are designed to drive least one low inductance, surface-mount ceramic capacitor of a high impedance load, such as an ADC input or another amplifier 0.1 µF placed as close as possible to the ADRF6516 device. stage. The output pins—OPP1, OPM1, OPP2, and OPM2—sit at a nominal output common-mode voltage of VPS/2, but can The ADRF6516 has two separate supplies: an analog supply and be driven to a voltage of 0.7 V to 2.8 V by applying the desired a digital supply. Take care to separate the analog and digital common-mode voltage to the high impedance VOCM pin. supplies with a large surface-mount inductor of 33 µH. Decouple each supply separately to its respective ground through a 10 μF DC OFFSET COMPENSATION LOOP ENABLED capacitor. When the dc offset compensation loop is enabled via the OFDS INPUT SIGNAL PATH pin, the ADRF6516 can null the output differential dc level. The loop is enabled by pulling the OFDS pin low to ground. The Each signal path has input buffers, accessed through the offset compensation loop creates a high-pass corner frequency, INP1, INM1, INP2, and INM2 pins, that set a differential input which is proportional to the value of the capacitors that are impedance of 1600 Ω. These inputs sit at a nominal common- connected from the OFS1 and OFS2 pins to ground. For more mode voltage around midsupply. information about setting the high-pass corner frequency, see The inputs can be dc-coupled or ac-coupled. If using direct the DC Offset Compensation Loop section. dc coupling, the common-mode voltage, VCM, can range from COMMON-MODE BYPASSING 1.1 V to 1.8 V. The VICM pin can be used as a reference common- mode voltage for driving a high impedance sensing node of the The ADRF6516 common-mode pins, VICM and VOCM, must preceding cascaded part (VICM has a 7 kΩ impedance). be decoupled to ground. Use at least one low inductance, surface-mount ceramic capacitor with a value of 0.1 μF to decouple the common-mode pins.

INPUT1 (–) 0.1µF

VPS 0.1µF

INPUT1 (+) VPS VPS OUTPUT1 (+) 0.1µF

ENBL INM1 COM OFS1 INP1 VPS VICM VPS VPSD VPSD OPP1

0.1µF COMD OPM1 LE COM OUTPUT1 (–) SERIAL CLK GAIN CONTROL ADRF6516 DATA VOCM INTERFACE 0.1µF SDO COM 0.1µF

COM OPM2 0.1µF OUTPUT2 (–) VPS OPP2 INP2 VPS OFDS VPS VPS COM INM2 COM OFS2 VPS INPUT2 (+) 0.1µF

OUTPUT2 (+)

VPS INPUT2 (–) VPS 0.1µF

09422-053 Figure 51. Basic Connections

Rev. C | Page 21 of 29 ADRF6516 Data Sheet

SERIAL PORT CONNECTIONS EFFECT OF FILTER BANDWIDTH ON EVM The ADRF6516 has a SPI port to control the gain and filter band- Take care when when selecting the filter bandwidth. In a digital width settings. Data can be written to the internal 8-bit register transceiver, the modulated signal is filtered by a pulse shaping and read from the register. It is recommended that low-pass RC filter (such as a root-raised cosine filter) at both the transmit filtering be placed on the SPI lines to filter out any high frequency and receive ends to guard against intersymbol interference (ISI). glitches. See Figure 58, the evaluation board schematic, for an If additional filtering of the modulated signal is done, the signal example of a low-pass RC filter. must be within the pass band of the filter. When the corner ENABLE/DISABLE FUNCTION frequency of the ADRF6516 filter begins to encroach on the modulated signal, ISI is introduced and degrades EVM, which To enable the ADRF6516, the ENBL pin must be pulled high. can lead to loss of signal lock. Driving the ENBL pin low disables the device, reducing current consumption to approximately 9 mA at room temperature. Figure 52 shows that a digitally modulated QAM baseband signal with a bandwidth at 9.45 MHz has excellent EVM even ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE at a filter corner frequency of 8 MHz. Further reduction in the Error vector magnitude (EVM) is a measure used to quantify corner frequency leads to complete loss of lock. As RF input the performance of a digital radio transmitter or receiver by power was swept, the ADRF6516 attained an EVM of less than measuring the fidelity of the digital signal transmitted or −45 dB over an input power range of approximately 20 dB. received. Various imperfections in the link, such as magnitude 0 0.8 and phase imbalance, noise, and distortion, cause the –5 30MHz 0.7 constellation points to deviate from their ideal locations. –10 15MHz 10MHz 9MHz 0.6 In general, a receiver exhibits three distinct EVM limitations –15 8MHz GAIN VOLTAGE 0.5 vs. received input signal power. As signal power increases, the –20 distortion components increase. AGE (V) –25 0.4 LT

• EVM (dB) At large enough signal levels, where the distortion compo- –30 0.3

nents due to the harmonic nonlinearities in the device are GAIN VO –35 falling in-band, EVM degrades as signal levels increase. 0.2 –40 • At medium signal levels, where the signal chain behaves 0.1 in a linear manner and the signal is well above any notable –45 –50 0 noise contributions, EVM has a tendency to reach an opti- –25 –20 –15 –10 –5 0 5

mal level determined dominantly by either the quadrature RF INPUT POWER (dBm) 09422-054 accuracy and IQ gain match of the signal chain or the Figure 52. EVM vs. RF Input Power at Several Filter Corner Settings precision of the test equipment. (256-QAM, 14 MSPS Signal with α = 0.35; Output Differential Signal Level Held to 700 mV p-p; OFDS Pulled High) • As signal levels decrease, such that noise is a major con- tributor, EVM performance vs. the signal level exhibits Figure 53 shows the degradation that a fixed filter corner has a decibel-for-decibel degradation with decreasing signal on EVM as the signal bandwidth corner is increased in fine level. At these lower signal levels, where noise is the increments until loss of signal lock occurs. dominant limitation, decibel EVM is directly proportional 0

to the SNR. –5 EVM TEST SETUP –10 FILTER BANDWIDTH CORNER The basic setup to test EVM for the ADRF6516 consisted of an –15 Agilent E4438C used as a signal source and a Hewlett-Packard –20 89410A vector signal analyzer (VSA) used to sample and calculate –25 the EVM of the signal. The E4438C IQ baseband differential EVM (dB) –30 outputs drove the ADRF6516 inputs. The I and Q outputs of the –35 ADRF6516 were loaded with 1 kΩ differential impedances and –40 connected differentially to two AD8130 differential amplifiers to convert the signals into single-ended signals. The single-ended –45 –50 signals were connected to the input channels of the VSA. 3 4 5 6 7 8 9 10

SIGNAL BANDWIDTH CORNER (MHz) 09422-055 Figure 53. EVM vs. Signal Bandwidth Corner at a Filter Corner of 5 MHz and a 16-QAM Signal with α = 0.35

Rev. C | Page 22 of 29 Data Sheet ADRF6516

EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM Figure 55 shows degradation of the EVM vs. RF input power as Output voltage level can affect EVM greatly when the signal is the COFS capacitor value becomes smaller, which increases the compressed. When changing the output voltage levels of the high-pass corner for the dc offset compensation loop. ADRF6516, take care that the output signal is not in compres- 0 sion, which causes EVM degradation. –5 Figure 54 show EVM performance vs. RF input power for –10 several maximum differential I and Q output voltage levels –15 of 350 mV p-p up to 2.4 V p-p. For the lower maximum differ- –20 ential output voltage levels, the EVM is less than −45 dB over –25

approximately 20 dB of input power range. EVM (dB) –30 COFS = 1µF 0 COFS = 220nF –35 COFS = 1nF –5 –40 –10 –45 –15 –50 –20 –35 –30 –25 –20 –15 –10 –5 0 5

RF INPUT POWER (dBm) 09422-057 –25 350mV p-p MAX 700mV p-p MAX Figure 55. EVM vs. RF Input Power at Several COFS Values (Filter Corner = 10 MHz, EVM (dB) –30 1500mV p-p MAX 2400mV p-p MAX 256-QAM, 14 MSPS Signal with α = 0.35; Output Differential Signal Level Held to 700 mV p-p; OFDS Pulled Low) –35

–40 Figure 56 shows the effect that COFS has on several modulated

–45 signal bandwidths. The modulated bandwidth was swept while using 1000 pF and 1 µF values for COFS. Total gain was set to –50 –25 –20 –15 –10 –5 0 5 15 dB, so the high-pass filter corner of the 1000 pF capacitor is RF INPUT POWER (dBm) 09422-056 26.67 kHz, and the high-pass filter corner of the 1 µF capacitor Figure 54. EVM vs. RF Input Power at Several Output Maximum Differential is 26.67 Hz. It is recommended that at moderate signal band- Voltage Levels (Filter Corner = 10 MHz, OFDS Pulled High) widths, a 1 µF capacitor for COFS be used to obtain the best EVM For the largest tested maximum differential output voltage level when using the dc offset compensation loop. of 2.4 V p-p, the ADRF6516 begins to compress the signal. This 0 compression causes EVM to degrade, but it still remains below –5 −40 dB, albeit over a truncated input power range. At the high –10 end of the input power range, the signal is in full compression and EVM is large. Given that the gain is near its minimum, the –15 input signal level must be lowered to bring the output signal out –20 of full compression and into the proper linear operating region. –25 EVM (dB) EFFECT OF COFS VALUE ON EVM –30 COFS = 1000pF When enabled, the dc offset compensation loop effectively –35 nulls any information below the high-pass corner set by the –40

COFS capacitor. However, loss of the low frequency information –45 COFS = 1µF of the modulated signal can degrade the EVM in some cases. –50 0 1 2 3 4 5 6 7 8 9 10 As the signal bandwidth becomes larger, the percentage of SIGNAL BANDWIDTH CORNER (MHz) 09422-058 information that is corrupted by the high-pass corner becomes Figure 56. EVM vs. Signal Bandwidth Corner with COFS = 1 µF smaller. In such cases, it is important to select a COFS capacitor and COFS = 1000 pF (Filter Corner = 10 MHz) that is large enough to minimize the high-pass corner frequency, which prevents loss of information and degraded EVM.

Rev. C | Page 23 of 29 ADRF6516 Data Sheet

EVALUATION BOARD An evaluation board is available for testing the ADRF6516. When the user clicks the Write Bits button, a write operation is The evaluation board schematic is shown in Figure 58. Table 6 executed, immediately followed by a read operation. The updated provides the component values and suggestions for modifying information is displayed in the Current Pre-Amp Gain, Current the component values for the various modes of operation. Frequency, Current VGA Max Gain, and Current Post-Amp EVALUATION BOARD CONTROL SOFTWARE Gain fields. The ADRF6516 evaluation board is controlled through the When the parallel port is updated with a read/write operation, parallel port on a PC. The parallel port is programmed via the the current cumulative maximum gain of all the amplifiers is ADRF6516 evaluation software. This software controls the filter displayed in the Maximum Gain field. (The analog VGA gain corner frequency, as well as the minimum and maximum gains is not included in this value.) for each amplifier in the ADRF6516. For information about the Because the speed of the parallel port varies from PC to PC, register map, see Table 4 and Table 5. For information about SPI the Clock Stretch function can be used to change the effective port timing and control, see Figure 2 and Figure 3. frequency of the CLK line. The CLK line has a scalar range from After the evaluation software is downloaded and installed, start 1 to 10; 10 is the fastest speed, and 1 is the slowest. the basic user interface to program the filter corner and gain values (see Figure 57). To program the filter corner, do one of the following:  Click the arrow in the Frequency Select section of the window, select the desired corner frequency from the menu, and click Write Bits.  Click Freq +1 MHz or Freq −1 MHz to increment or decrement the corner frequency in 1 MHz steps from the current corner frequency. To program the preamplifier gain, the VGA maximum gain, and the postamplifier gain, move the slider switch in the appropriate section of the window to the desired gain.  The preamplifier gain can be set to 3 dB or 6 dB.  The VGA maximum gain can be set to 22 dB or 28 dB.

 The postamplifier gain can be set to 6 dB or 12 dB. 09422-060 Figure 57. ADRF6516 Evaluation Software

Rev. C | Page 24 of 29 Data Sheet ADRF6516

SCHEMATICS AND ARTWORK VPOSD VPOS INM1_SE_P R45 L2 OPEN 33µH VPS DIG_VPOS VPOS R31 R47 R55 VICM 0Ω 0Ω OPEN C9 C1 C2 1 R57 10µF 10µF 6 100nF 0Ω C27 COMD COM 2 0.1µF T1 R56 L1 C6 OPEN 33µH 4 3 C12 0.1µF R58 C10 0Ω 0.1µF INP1 R48 100nF C14 0Ω R37 OPP1 1000pF OPEN R43 VPS VPS OPEN C16 R12 R19 R41 P2 0.1µF R7 OPEN 0Ω 0Ω R29 0Ω 100Ω ENBL INM1 COM OFS1 C19 LE INP1 VPS VICM VPS 100nF T3 VPSD VPSD OPP1 R11 C29 VGAIN R8 C23 C4 OPM1 OPEN 330pF COMD 0Ω 0.1µF 0.1µF R20 R30 C30 LE COM C17 C20 R5 OPM1_SE_P 100Ω 330pF 0.1µF 100nF 0Ω VGAIN 0Ω CLK CLK GAIN R33 ADRF6516 R39 DATA DATA VOCM R6 VOCM OPEN 0Ω SDO COM C18 C21 0.1µF 100nF 0Ω R34 C5 COM OPM2 VOCM R14 R35 R38 R42 OPM2_SE_P SDO 0.1µF OPEN 0Ω OPEN 0Ω VPS OPP2 R9 0Ω R1 INP2 VPS OFDS VPS VPS COM INM2 COM OFS2 0Ω 10kΩ C22 100nF T4 R46 R13 C24 OPEN VPS R10 OPEN 0.1µF INP2 R51 C13 C15 0Ω R36 OPP2 R32 R49 C11 1000pF 0.1µF 0Ω 0Ω OPEN R53 C7 0.1µF 0Ω 1 100nF 6 0Ω R40 2 T2 OPEN R52 R3 VPS C3 10kΩ 4 3 OPEN R54 C8 0.1µF 0Ω R50 100nF P4 0Ω INM2_SE_P R44 VPS OPEN 09422-061 Figure 58. Evaluation Board Schematic

Rev. C | Page 25 of 29 ADRF6516 Data Sheet

Y1 24MHz 3V3_USB

3 1 C54 C51 22pF 22pF 4 2 3V3_USB R62 100kΩ R64 0Ω C45 0.1µF

C37 56 55 54 53 52 51 50 49 48 47 46 45 44 43 0.1µF VCC VCC GND GND CLKOUT PD1_FD9 PD0_FD8 WAKEUP PD7_FD15 PD3_FD11 PD5_FD13 PD2_FD10 PD6_FD14 PD4_FD12 1 RDY0_SLRD RESET_N 42

C48 2 RDY1_SLWR GND 41 10pF 3 AVCC PA7_FLAGD_SCLS_N 40

5V_USB 4 XTALOUT PA6_PKTEND 39

5 XTALIN PA5_FIFOARD1 38 P5 C49 1 0.1µF 6 AGND PA4_FIFOARD0 37 3V3_USB 2 7 AVCC PA3_WU2 3 CY7C68013A-56LTXC 36 LE 4 U4 8 DPLUS PA2_SLOE 35 CLK 5 G1 9 DMINUS PA1_INT1_N 34 DATA G2 G3 10 AGND PA0_INT0_N 33 SDO 3V3_USB G4 11 VCC VCC 32 3V3_USB 12 GND CTL2_FLAGC 31 13 IFCLK CTL1_FLAGB 30 14 RESERVED R61 CTL0_FLAGA 29 2kΩ PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 GND VCC GND PB0_FD0 PB2_FD2 VCC PB1_FD1 SCL SDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CR2

3V3_USB

3V3_USB R59 C38 24LC64-I_SN 2kΩ C39 10pF U2 0.1µF 5V_USB ADP3334 1 A0 SDA 5 R60 U3 3V3_USB 2kΩ 1 IN2 8 2 A1 SCL 6 3V3_USB OUT1 C52 R70 C50 2 OUT2 IN1 7 C47 1.0µF 140kΩ 1000pF 1.0µF 3 A2 WC_N 7 R65 3 FB SD 6 2kΩ 4 GND VCC 8 3V3_USB R69 4 NC GND 5 78.7kΩ CR1

DGND

3V3_USB

C40 C41 C42 C35 C36 C44 C46 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF

09422-159 Figure 59. USB Evaluation Board Schematic

Rev. C | Page 26 of 29 Data Sheet ADRF6516

09422-063

09422-062

Figure 60. Top Layer Silkscreen Figure 61. Component Side Layout

Table 6. Evaluation Board Configuration Options Components Function Default Conditions C1, C2, C4, C5, C11, C12, C15, Power supply and ground decoupling. Nominal supply decoupling C1, C2 = 10 µF (Size 1210) C16, L1, L2, R2 consists of a 0.1 µF capacitor to ground. C4, C5, C11, C12, C15, C16 = 0.1 µF (Size 0402) L1, L2 = 33 µH (Size 1812) R2 = 1 kΩ (Size 0402) T1, T2, C3, C6, C7 to C10, R31, Input interface. Input SMAs INP1, INM1_SE_P, INP2_SE_P, and INM2 T1, T2 = ADT8-1T+ (Mini-Circuits) R32, R43 to R58 are used to drive the part differentially by bypassing the baluns. C3, C6 = 0.1 µF (Size 0402) Using only INM1_SE_P and INP2_SE_P in conjunction with the baluns C7 to C10 = 100 nF (Size 0602) enables single-ended operation. The default configuration of the R31, R32, R47 to R50, R53, R54, evaluation board is for single-ended operation. R57, R58 = 0 Ω (Size 0402) T1 and T2 are 8:1 impedance ratio baluns that transform a single- R43 to R46, R51, R52, R55, R56 = ended signal in a 50 Ω system into a balanced differential signal in a open (Size 0402) 400 Ω system. R31, R32, R47, R48, R49, and R50 are populated for appropriate balun interface. R51 to R58 are provided for generic placement of matching components. To bypass the T1 and T2 baluns for differential interfacing, remove the balun interfacing resistors R31, R32, R47, R48, R49, and R50, and populate R43, R44, R45, and R46 with 0 Ω resistors. T3, T4, C19 to C24, Output interface. Output SMAs OPP1_SE_P, OPM1, OPP2, and T3, T4 = ADT8-1T+ (Mini-Circuits) R7 to R14, R19, R20, OPM2_SE_P are used to obtain differential signals from the part C19 to C22 = 100 nF (Size 0402) R35 to R42 when the output baluns are bypassed. Using OPP1_SE_P, C23, C24 = 0.1 µF (Size 0402) OPM2_SE_P, and the baluns, the user can obtain single-ended output R7 to R10, R19, R20, R35, R36, signals. The default configuration of the evaluation board is for R41, R42 = 0 Ω (Size 0402) single-ended operation. R11 to R14, R37 to R40 = open T3 and T4 are 8:1 impedance ratio baluns that transform a differential (Size 0402) signal in a 400 Ω system into a single-ended signal in a 50 Ω system. R7, R8, R9, R10, R19, R20, R35, R36, R41, and R42 are populated for appropriate balun interface. R7 to R14 are provided for generic placement of matching components. To bypass the T3 and T4 baluns for differential interfacing, remove the balun interfacing resistors R19, R20, R35, R36, R41, and R42, and populate R37, R38, R39, and R40 with 0 Ω resistors.

Rev. C | Page 27 of 29 ADRF6516 Data Sheet

Components Function Default Conditions P2 Enable interface. The ADRF6516 is powered up by applying a logic P2 = installed for enable high voltage to the ENBL pin (Jumper P2 is connected to VPS). P1, C28, C29, R1, R29, R30, R33, Serial control interface. The digital interface sets the corner P1 = installed R34 frequency, the preamplifier gain, the postamplifier gain, and the VGA R1 = 10 kΩ (Size 0402) maximum gain of the device using the serial interface via the LE, CLK, C28, C29 = 330 pF (Size 0402) DATA, and SDO pins. RC filter networks are provided on the CLK and R29, R30 = 100 Ω (Size 0402) LE lines to filter the PC signals. CLK, DATA, and LE signals can be R33, R34 = 0 Ω (Size 0402) observed via SMB connectors for debug purposes. P4, C13, C14, R3 DC offset compensation loop. The dc offset compensation loop is P4 = installed enabled (low) with Jumper P4. When enabled, the C13 and C14 C13, C14 = 1000 pF (Size 0402) capacitors are connected to circuit common. The high-pass corner R3 = 10 kΩ (Size 0402) frequency is expressed as follows: fHP (Hz) = 6.7 × (Post Filter Linear Gain/COFS (µF)) C27 Input common-mode setpoint. The input common-mode voltage C27 = 0.1 µF (Size 0402) can be set externally when applied to the VICM pin. If the VICM pin is left open, the input common-mode voltage defaults to VPS/2. C18, R6 Output common-mode setpoint. The output common-mode voltage C18 = 0.1 µF (Size 0402) can be set externally when applied to the VOCM pin. If the VOCM pin R6 = 0 Ω (Size 0402) is left open, the output common-mode voltage defaults to VPS/2. C17, R5 Analog gain control. The range of the GAIN pin is from 0 V to 1 V, C17 = 0.1 µF (Size 0402) creating a gain scaling of 15 mV/dB. R5 = 0 Ω (Size 0402) U2, U3, U4, P5 Cypress Microcontroller, EEPROM, and LDO U2 = Microchip MICRO24LC64 U3 = Analog Devices ADP3334ACPZ U4 = Cypress Semiconductor CY7C68013A-56LTXC P5 = Mini USB connector C35, C36, C40, C41, C42, C44, 3.3 V supply decoupling. Several capacitors are used for decoupling C35, C36, C40, C41, C42, C44, C46 C46 on the 3.3 V supply. = 0.1 µF (0402) C48, C49, C45, C56, C57, C58, Cypress and EEPROM components. C57, C48 = 10 pF (0402) R59, R60, R61, R62, R64, CR2 C56, C58, C45, C49 = 0.1 µF (0402) R59, R60, R61 = 2 kΩ (0402) R62, R64 = 100 kΩ (0402) CR2 = ROHM SML-21OMTT86 C47, C50, C52, R65, R69, R70, LDO components C47, C52 = 1 µF (0402) CR1 C50 = 1000 pF (0402) R65 = 2 kΩ (0402) R69 = 78.7 kΩ (0402) R70 = 140 kΩ (0402) CR1 = ROHM SML-21OMTT86 Y1, C51, C54 Crystal oscillator and components. 24 MHz crystal oscillator. Y1 = NDK NX3225SA-24MHz C51, C54 = 22 pF (0402)

Rev. C | Page 28 of 29 Data Sheet ADRF6516

OUTLINE DIMENSIONS

DETAIL A (JEDEC 95) 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR 25 32 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 1 0.50 BSC 3.25 EXPOSED PAD 3.10 SQ 2.95

17 8

0.50 16 9 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW THE EXPOSED PAD, REFER TO 0.05 MAX 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF 02-22-2017-A PKG-003898 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD Figure 62. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6516ACPZ-R7 −40°C to +85°C 32-Lead LFCSP, 7” Tape and Reel CP-32-7 ADRF6516-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

Rev. C | Page 29 of 29