RF MEMS Switch Integrated on Printed Circuit Board with Metallic Membrane First Sequence and Transferring Q

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552 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006 RF MEMS Switch Integrated on Printed Circuit Board With Metallic Membrane First Sequence and Transferring Q. X. Zhang, A. B. Yu, L. H. Guo, R. Kumar, K. W. Teoh, A. Q. Liu, G. Q. Lo, and D.-L. Kwong

Abstract—This letter reports, for the first time, on RF MEMS ing planarization with sacrificial photoresist or polyimide and switches integrated on flexible printed circuit boards (i.e., FR-4) low-temperature (100 ◦C) chemical-vapor-deposited (CVD) using transfer technology. The devices were first processed on SiN process [7], [8], a simple transfer of MEMS onto RF- Si-substrate using a modified MEMS sequence and subsequently transferred onto an FR-4 substrate by thermal compressive bond- compatible substrate should have been considered. ing, mechanical grinding, and wet removal of silicon. The switches Previously, transfer concept has been demonstrated by were demonstrated with flat metal membrane (top electrode), pre- Milanovic et al. [5] and Singh et al. [9], in which the MEMS cisely controlled gap between the membrane and bottom electrode, devices were fabricated on “donor” wafers and the microwave ≤ low insertion loss ( 0.15 dB at 20 GHz), and high isolation structures were fabricated on “target” wafers separately. In this (∼ 21 dB at 20 GHz). This technology shows the potential to monolithically integrate RF MEMS components with other RF approach, besides concern on wafers’ alignment, issue with devices on organic substrate for RF system implementation. controlling the gap distance should be addressed, especially so if it is for wafer-level manufacturing. Index Terms—FR-4, MEMS, plastic substrate, RF switch, transfer technology. This letter reports a new wafer transfer scheme to realize RF MEMS switches on PCB substrate, by forming the MEMS devices on rigid low-resistive substrate in a reversed integration I. INTRODUCTION sequence, and then transfer of such onto PCB through thermal F MEMS switches are major RF device components fab- bonding and silicon removal. Inasmuch as the metal bridge and R ricated by MEMS technology. They are attractive in the the bottom electrode are processed on Si wafer by the best implementation of the next-generation of telecommunication processes available in today’s IC fabrication lines, their surface systems for reasons of low insertion loss, high isolation, near- is well controlled. The metal bridge achieved is flat as the result zero power consumption, and good linearity in comparison of the integration sequence employed. In addition, the air gap with the currently used solid-state counterparts, i.e., field-effect between the movable membrane and the bottom electrode can transistor or p-i-n diodes. Among the substrate material choices, be precisely controlled as well. such as high-resistive silicon, silicon-on-insulator (SOI), GaAs, or quartz [1]–[5], direct-on printed circuit board (PCB) [6]–[8] offers unique advantages. Besides PCB being low cost, with II. RF MEMS SWITCH FABRICATION AND TRANSFER wide range of dielectric constants thickness, and low tangent The switch was first formed on an 8-in p-type low-resistive loss, direct-on PCB can minimize the impendence mismatch Si. Contrary to the normal RF MEMS switch fabrication, and signal loss (e.g., between RF devices and package, package a reversed process sequence was designed as illustrated in and board) because it eliminates the need for wire bond to be Fig. 1(a). After a stack of thermal oxide (1 kÅ) growth, de- used as packaging when constructing an RF system [8]. position of low-pressure CVD (LPCVD) nitride (1 kÅ), and However, as discussed by Ghodsian et al. [7] and Chang et al. plasma-enhanced CVD (PECVD) oxide (5 kÅ), 400-Å Ti/1-µm [8], MEMS fabrication directly on PCB faces several key Au was sputtered and patterned as a bridge layer in the capaci- technology obstacles, e.g., planarization of high aspect ratio tive switch structure. This metal layer is flat due to the flat sub- coplanar waveguide (CPW) Cu layers, its etch profile and strate underneath. PECVD oxide (2 µm) serving as a sacrificial surface roughness, and low-temperature (220 ◦C) compati- layer was deposited and then patterned. After the formation of bility requirement. Along with good progress that has been a patterned SiN dielectric layer of 1.5 kÅ, the CPW layer of made specifically tackling issues such as compressive mold- 400-Å Ti/1-µm Au was sputtered and patterned by wet etching. Finally, a SIN layer of 5 kÅ was deposited, serving as stress buffer layer between FR-4 and MEMS structure and also as Manuscript received March 9, 2006; revised April 26, 2006. The review of a protective layer for FR-4 material in subsequent HF release this letter was arranged by Editor C. P. Chang. Q. X. Zhang, L. H. Guo, R. Kumar, K. W. Teoh, G. Q. Lo, and D.-L. etch process. Kwong are with the Institute of Microelectronics, Singapore 117685 (e-mail: In the transfer process as shown in Fig. 1(b), the Si wafer [email protected]). was placed with front side facing down onto an FR-4 substrate A. B. Yu and A. Q. Liu are with the School of Electrical and Electronic ε = tan δ = h = Engineering, Nanyang Technological University, Singapore 639798. ( r 4.2, 0.022, and thickness 0.1 mm) with an Digital Object Identifier 10.1109/LED.2006.877282 epoxy-based glue film (thickness ∼ 40 µm) in between; no

Fig. 2. RF MEMS structures on an 8-in ﬂexible FR-4 substrate; the structures are within a 4-in area only due to existing 5-in mask set used.

Fig. 1. Process ﬂow for RF MEMS switch transfer. (a) RF switch is fabricated on Si wafer in reversed process sequence. (b) Si to FR-4 substrate thermal bonding. (c) Grinding and KOH etching to remove silicon. (d) RF switch release etch by HF.

critical alignment was required in this step. The bonding was conducted in a wafer bonder under a specially designed process condition to avoid wafer warpage. The temperature was ramped up to the bonding temperature (160 ◦C) in two steps, i.e., Fig. 3. Cross-sectional view of the flat metal bridge on top of CPW structure. 1) with a rate of ∼ 2 ◦C/min before 100 ◦C and 2) ∼ 0.5 ◦C/min Inset shows the enlarged view (left) and the whole switch structure on FR-4 substrate (right). after that. The pressure was kept at 400 lbf/in2 for 30 min during bonding. Then, the temperature was ramped down with III. RESULTS AND DISCUSSION gradually increased rate, e.g., ∼ 0.1 ◦C/min for 160–150 ◦C and ∼ 2 ◦C/min below 50 ◦C. The bonded structure was mechani- The RF switch on FR-4 is characterized using an HP8510C cally ground from Si side and stopped with 100 µm remaining. vector network analyzer and an RF probe station with 150-µm The remaining Si was then completely removed in KOH solu- probes. A full thru-reflect-line (TRL) routine is used to calibrate tion as shown in Fig. 1(c). After SiN layer removal by reactive with the NIST software MULTICAL. The switch has an initial ion etching (RIE), the oxide sacrificial layer was stripped in HF air gap of 2 µm and capacitance area of 200 × 55 µm2 between solution and cleaned in deionized (DI) water as illustrated in the metal bridge and the dielectric layer. The calculated pull- Fig. 1(d); thus, the Ti/Au bridge layer was released. down voltage is 25 V, whereas a higher dc voltage of 35 V is The perspective view of the MEMS devices on 8-in FR-4 applied to improve the contact between the metal bridge and the substrate is shown in Fig. 2. The devices are located within 4-in dielectric layer. area due to existing 5-in mask set used, although the process Fig. 4 shows measurement results of the switch. At upstate, is well extendable for 8-in size. Warpage effect will not be the insertion loss is less than 0.15 dB at 20 GHz, including the serious for 8-in to 8-in transfer, as with the same technology, insertion loss of 0.1 dB on the transmission line, and the return transferring of active transistors, RF passive components, and loss is less than −20 dB; at downstate, the isolation is about high-density interconnect have been successfully demonstrated 21 dB at 20 GHz. An equivalent circuit model is employed from 8-in Si to FR-4 substrate without any issues [10]. With to fit the measured S-parameters, as in the inset of Fig. 4. the use of the reversed integration sequence, the metal bridge The switch model has two short sections of CPW lines with layer of 800 µm long and 1 µm thick on top of the CPW line is characteristic impedance of Z0 and a lumped RLC model of flat with 0.4-µm flatness variation after transferring onto FR-4 the bridge with capacitance Cu or Cd at upstate or downstate. substrate (Fig. 3). The roughness on the contact metal surfaces The curve fitting was performed with commercial software of 35 nm is better than the reported 50–75 nm in direct fabrica- Agilent ADS software (Agilent Technology Inc.), according to tion on PCB [6]–[8]. Further improvement is possible through the measurement results of the switch. The fitted parameters modification of the release step as the original roughness on for the switch at downstate are Cd = 2.13 pF, L = 15 pH, and metal and dielectric layer can be as good as 1 nm by normal R = 1.2 Ω, whereas at upstate, Cu = 77 fF, including fringing silicon-based processes. capacitance of 27 fF. The downstate/upstate capacitance ratio 554 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006

mechanical polishing (CMP), and low-temperature deposition processes are common back-end processes. One way to reduce the cost in transfer approach is by starting with low-grade rigid substrate because it is sacriﬁcial. Major advantage can only be realized if more complex IC or components are to be built and then transferred.

IV. CONCLUSION Other than the cost advantage of PCB, the key advantages are that the switches were fabricated using standard MEMS processes with best roughness control and thus a ﬂat metal membrane, and the scheme to transfer the integrated structure precisely controlled the air gap. Therefore, it has promising potential to realize monolithic integration of RF MEMS with other RF components on the same PCB for implementation of a compact RF system.

ACKNOWLEDGMENT The authors would like to thank the staff of Semiconductor Process Technology Laboratory, Institute of Microelectronics, Singapore, for their help in wafer processing.

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