Design of 32-Bit Differential Paired Efuse OTP Memory in a Form of Two-Dimensional Array

J. Cent. South Univ. (2012) 19: 3484–3491 DOI: 10.1007/s11771-012-1433-3

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

KIM Yoon-kyu, JANG Ji-hye, YOON Geon-soo, LEE Dong-hoon, HA Man-yeong, HA Pan-bong, KIM Young-hee

Department of Electronic Engineering, Changwon National University, 9 Sarim-Dong, Changwon 641-773, Korea

Abstract: A differential paired eFuse OTP (one-time programmable) memory cell which can be configured into a 2D (two-dimensional) eFuse cell array was proposed. The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage. With this 2D array of differential paired eFuse OTP memory cells, we design a 32-bit eFuse OTP memory IP. We use a sense amplifier based D F/F circuit as the BL (bit-line) SA (sense amplifier) and design a sensing margin test circuit with a variable pull-up load. It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

Key words: eFuse; one-time programmable memory; 2-dimensional array 

NMOS transistor with big channel width that can flow a 1 Introduction big programming current, and a read NMOS transistor with small channel width that can reduce a read current In general, small-density program memories used in the read mode [2]. In addition, the differential paired for the analog trimming of PMICs (power management eFuse cell has a form that dual-port eFuse cells are ICs) are OTP (one-time programmable) memories of connected in pair, and can make the peripheral circuit eFuse type rather than EEPROMs or flash memories simpler without any reference voltage generator and the since they can be designed based on a logic process sensing resistance of the programmed eFuse link a half which does not require any additional processes [12]. smaller. The OTP memory of eFuse type is programmed by There is, however, a problem that the previously flowing an over-current through poly-silicon fuses, or proposed differential paired eFuse cells can have just eFuses [3]. The pre-program resistance of the eFuse cell one-dimensional cell array since they have BL[7:0] and is about 50–200 Ω and the post-program resistance is BLb[7:0], PD[7:0] and PDb[7:0] in the column direction. more than several kilos ohms. Thus, the eFuse is Memory failures can also occur since there is a programmed into either a conductive state or highly possibility that the eFuse link can be shortened to the resistive state [3]. VSS-biased p-substrate by the thermally ruptured eFuse. An eFuse OTP cell is classified into a single-port In addition, an additional layout area is required since an eFuse cell [34], a dual-port eFuse cell [5], and a external pad is required to supply a program voltage in differential paired eFuse cell [6]. The single-port eFuse the program mode. cell shares its read and write port, has the program In this work, we propose a differential paired eFuse resistance of several kilo ohms, and adopts an analog OTP (one-time programmable) memory cell which can sensing scheme. In contrast, the dual-port eFuse cell has be configured into a 2D (two-dimensional) eFuse cell its separate read and write port and has the program array. The sensible resistance of a programmed eFuse resistance of several tens kilos ohms since it uses a link is a half smaller than that of the single-ended NMOS transistor with big channel width to flow a big counterpart and BL datum can be sensed without a programming current. The peripheral circuit is simple reference voltage. Also, we remove an external pad to since a digital sensing scheme can be adopted. A supply a program voltage since we use VIO (I/O voltage) dual-port eFuse cell consists of an eFuse link, a program for programming in the PMIC chip.

Foundation item: Project supported by the Second Stage of Brain Korea 21 Projects Received date: 2012–02–09; Accepted date: 2012–04–20 Corresponding author: KIM Young-hee, Professor, PhD; Tel: +82−55−285−1023; E-mail: [email protected] J. Cent. South Univ. (2012) 19: 3484–3491 3485 Furthermore, we use a sense amplifier based D F/F is ‘0’ and the eFuse1 connected to BL is blown in case circuit as the BL (bit-line) SA (sense amplifier) and that DIN is ‘1’. The anodes of eFuse1 and eFuse2 are design a sensing margin test circuit with a variable connected to FSOURCE commonly and they are selected pull-up load in consideration of the variation of the column decoded PD[7:0] and PDb[7:0] in the differential programmed eFuse resistance. Also, we solve a problem paire eFuse cell of Fig. 1. Thus, the differential paired of an electrical shortage between an eFuse link and the eFuse cell do not have the row decoding function and VSS-biased p-substrate by placing a floated n-well under can be used only in a one-dimensional eFuse cell array. the eFuse link. We design the 32-bit eFuse OTP IP with Also, it requires an additional layout area since an MagnaChip’s 0.18 µm CMOS process. external pad is required to supply the programming voltage in the program mode. 2 Circuit design As shown in Fig. 2, differential paired eFuse OTP memory cells require the row decoded and column As shown in the simplified circuit of the eFuse OTP decoded signal to be configured in the two-dimensional memory using differential paired eFuse cells which can array. The proposed differential paired eFuse OTP be configured in one-dimensional array, it consists of memory cell consists of two program transistors (MN1 differential paired eFuse memory cell circuit, a and MN3), two read transistors (MN2 and MN4), and high-impedance pull-up loads, and differential amplifier two eFuses (eFuse1 and eFuse2). The used devices in Fig. [6]. The proposed differential paired eFuse cell is made 2 and the functions of RWL and BL/BLb are the same as by connecting conventional dual-port eFuse cells in pair. those in Fig. 1 while WWL and PD/PDb are used instead The left circuit (eFuse1, MN1 and MN2) of the proposed of FSOURCE. eFuse cell stores its program datum and the right one (eFuse2, MN3 and MN4) stores its complementary program datum. MN1 and MN3 are program transistors. MN2 and MN4 are read transistors. FSOURCE receives an external supply voltage directly and flows an over-current in the program mode. In the program mode, program voltage of FSOURCE should be applied with 5.5 V instead of 4.2 V in designing with MV transistors of 5 V rather than 3.3 V. Table 1 shows bias voltage conditions for various operation modes of each conventional one-dimensional configurable differential paired OTP memory cell node. The read NMOS transistors turn off since RWL keeps at 0 V in the program mode. Also, PD (program data) and PDb (program data bar) of the non-selected cell by

A[2:0] keep at 0 V while PD (program data) and PDb

(program data bar) of the selected cell keep at 0 V and

5.5 V in the case of DIN= ‘0’; 5.5 V and 0 V in the case of DIN= ‘1’. In the program mode, the eFuse2 connected Fig. 1 Simplified circuit of conventional differential paired to BLb of the selected cell is blown in the case that DIN eFuse OTP memory cell

Table 1 Bias voltage conditions for various operation modes of each conventional differential paired OTP cell node Program mode Cell Read mode Unselected Cell Selected Cell DIN 0 1 0 1 X X RWL 0 0 0 0 VDD VDD PD 0 V 0 V 0 V 5.5 V 0 V 0 V PDb 0 V 0 V 5.5 V 0 0 V 0 V FSOURSE 5.5 V 5.5 V 5.5 V 5.5 V Floating Floating BL Floating Floating Floating Floating 0 V VDD BLb Floating Floating Floating Floating VDD 0 V eFuse1 Unblown Unblown Unblown Blowing Unblown Blown eFuse2 Unblown Unblown Blowing Unblown Blown Unblown

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be 4.2 V in the program mode. On the other hand, the program transistor turns off since PD and PDb keep at 0 V. Figure 3 shows the layout image of the proposed differential paired eFuse OTP memory cell. The proposed eFuse cell size is 34.46 µm×6.94 µm (=239.15 µm 2). We use a p+ doped poly-silicon fuse as an eFuse, and the width and length of the eFuse link are 0.35 µm and 2.1 µm, respectively. There is, however, a possibility that the eFuse link can be shortened to the VSS-biased p-substrate by a thermal rupture and memory failures can occur. Thus, we solve a problem of an electrical shortage Fig. 2 Newly proposed differential paired eFuse OTP memory cell configured in a form of two-dimensional array between an eFuse link and the VSS-biased p-substrate by placing a floated n-well under the eFuse link, as shown Table 2 gives bias voltage conditions for various in Fig. 3 [7]. operation modes of each proposed two-dimensional Table 3 gives the major specifications of the 32-bit configurable differential paired OTP memory cell node. eFuse OTP memory IP using designed differential paired

Since RWL keeps at 0 V in the program mode, a read eFuse cells. The 32-bit OTP memory has a cell array of 4 NMOS transistor turns off. While selected WWL is rows × 8 columns and has a logic supply voltage of VDD activated to VIO (= 5.5 V), non-selected WWLs keeps at (= 1.8V) and an I/O voltage of VIO. VIO is 5.5 V in the 0 V. The eFuse link is not blown since a program current program mode and 5 V in the read mode. We can remove does not flow through the eFuse link. PD and PDb of the an external pad since we use VIO as the program voltage non-selected cell by A[2:0] keep at 0 V. On the other in programming PMIC chips, as shown in Table 3. There hand, PD and PDb of the selected cell drive 0 V and VIO are program and read mode as operation modes. Since (= 5.5 V) in the case that DIN is ‘0’, and VIO and 0 V in the programming current per bit for the eFuse OTP the case that DIN is ‘1’. In the program mode, the eFuse2 memory IP is about 29.8 mA, it is impossible to program connected to BLb of the selected cell is blown in the case byte by byte. Thus, programming is done bitwise, as that DIN is ‘0’ and the eFuse1 connected to BL is blown shown in Table 3. Reading is done byte by byte. The in the case that DIN is ‘1’. FSOURCE voltage is forced to programming time is 20 µs.

Table 2 Bias voltage conditions for various operation modes of each conventional differential paired OTP cell node Program mode Cell Read mode Selected column Uncelected column Selected 0 V 0 V 0 V 0 V VDD VDD RWL Uncelected 0 V 0 V 0 V 0 V 0V 0 V Selected VIO VIO VIO VIO 0 V 0 V WWL Uncelected 0 V 0 V 0 V 0 V 0 V 0 V DIN 0 1 0 1 X X PD 0 V 0 V 0 V 5.5 V 0 V 0 V PDb 0 V 0 V 5.5 V 0 0 V 0 V BL Floating Floating Floating Floating 0 V VDD BLb Floating Floating Floating Floating VDD 0 V eFuse1 Unblown Unblown Unblown Blowing Unblown Blown eFuse2 Unblown Unblown Blowing Unblown Blown Unblown

Fig. 3 Layout image of proposed differential paired eFuse OTP memory

J. Cent. South Univ. (2012) 19: 3484–3491 3487 Table 3 Major specifications of 32-bit eFuse OTP memory IP using differential paired eFuse cells

Supply voltage/V Temperature range/ ºC OTP cell Operating Program Program Process Fuse type Cell size array size mode bit /Read bit Time/μs VDD Program Read Program Read 34.46 µm× Magnachip 4 rows× Poly-Fuse 1.8± 40− Program / 5.5 5 0−125 1/8 20 6.94 µm 0.18 µm 8 columns (Co silicide) 10% 125 Read (=239.15µm2)

The block diagram of the designed 32-bit differential paired eFuse OTP memory of two-dimensional array type is shown in Fig. 4. It consists of an eFuse OTP cell array of 4 rows × 8 columns, a WL driver selecting one of four WLs by decoding the row address A[4:3], a PD (program data) driver circuit driving the selected program data to the OTP cells, a BL S/A (bit-line sense amplifier) sensing and outputting the BL datum to the DOUT port, and a control logic that supplies internal control signals which are suitable for both the program Fig. 5 Relation of column address A[2:0] and DOUT[7:0] and read mode with the control signals (RD and PGM). The PD driver circuit consists of eight PD drivers. PD column decoding A[2:0] in the program mode, the output and PDb selected by decoding the row address A[2:0] are signals of a PD driver in Fig. 8, PD and PDb, keep at 0 V. applied with bias voltages shown in Table 2 according to On the other hand, PD and PDb drive 0 V and VIO in DIN. Figure 5 shows the relation of a programmed bit by case that DIN is ‘0’ and they drive VIO and 0 V in the the column address A[2:0] and DOUT[7:0] outputted in case that DIN is ‘1’ since COL_SEL is VDD for selected the read mode. D0 bit is the LSB (least significant bit) of cells. Since the PD driver circuit requires one PD driver A[2:0]. The functional test read mode and the normal per bit, eight PD drivers are required for the 8-bit read mode are classified by TM_EN (Test mode enable) column. signal. In general, sensing failures can occur when the

resistance of an eFuse link decreases during the data retention time for an eFuse OTP memory cell. Thus, we propose a sensing margin test circuit with variable pull-up loads in the consideration of a resistance variation of a programmed eFuse. The variable pull-up load can vary the impedance of the pull-up load in the BL precharging circuit used in the functional test read and normal read mode [7]. Among pull-up transistors in Fig. 9(a), MP3 and MP4 are used only for a functional test of the chip, and MP1 and MP2 are in the off state. In the test read mode, the differential input voltage of the differential amplifier decreases and a sensible eFuse Fig. 4 Block diagram of designed 32-bit eFuse OTP memory resistance is bigger than that in the normal read mode. Thus, the sensible eFuse resistance difference between Figure 6 shows a cell array circuit of 4 rows × 8 the resistance in the functional test read mode and that in columns. RWL[3:0] and WWL[3:0] are routed in the row the normal read mode is a marginal resistance during the direction; PD[7:0]/PDb[7:0] and BL[7:0]/BLb[7:0] are data retention time. Figure 9(b) shows a BL S/A circuit routed in the column direction. using a S/A based D flip-flop which senses and latches Figure 7 shows a WL (Word-line) driver circuit. In the differential input voltage. The BL S/A is a negative entering the program mode, WLEN_PGM and edge-triggered D flip-flop. WLENb_PGM become a logic ‘1’ and logic ‘0’. This Figure 10 shows the layout image of the 32-bit OTP makes the selected WWL signal by ROWDEC decoded memory IP. The layout area of the designed eFuse OTP by the row address A[4:3] of VIO and the rest of 0 V. memory IP is 307.86 µm×150.46 µm (= 0.0463 mm2) Since COL_SEL is 0 V for non-selected cells by based on MagnaChip’s 0.18 µm CMOS process.

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Fig. 6 Cell array of differential paired eFuse OTP memory IP cells in form of 2D array

Fig. 7 WL driver circuit

Fig. 8 PD driver circuit

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Fig. 9 Sensing margin test circuit: (a) BL pull-up load; (b) BL S/A circuit using a S/A based D flip-flop circuit

from the control logic of Fig. 4. BL and BLb precharge to VSS by the PRECHARGE signal when a read command enters, as shown in Fig. 11. If RWL is activated to VDD and the read transistor of the eFuse OTP memory cell turns on, then a cell datum is transferred to BL and BLb after BL_LOADb is activated. The digital data of BL and BLb are sensed by the BL S/A and outputted to the node DOUT by the signal SAENb generated if signal voltages are developed sufficiently on BL and BLb. Figure 11(a) shows a simulation result for a ‘0’-programmed cell and Fig. 11(b) refers to the results from a ‘1’-programmed cell. Figure 12 shows simulation results of BL sensing voltages with respect to post-program eFuse resistances according to read modes. Under a typical simulation

condition (VDD=1.8 V, VIO=5 V, typical model Fig. 10 Layout image of designed 32-bit eFuse OTP memory IP parameters, and temperature is 25 °C), the sensing

3 Simulation and measurement results voltage of the BL S/A is about 100 mV and the sensing resistance is 4 kΩ in the test mode and 1 kΩ in the Figure 11 shows functional simulation results in the normal mode. Thus, we secure a margin over the read mode, the timing diagram for the control signal RD resistance variation of programmed eFuse for the data from the eFuse OTP memory IP in the read mode, and retention time. The peripheral circuit is simplified since the signals PRECHARGE, BL_LOADb, and SAENb the BL S/A does not require any reference voltage

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Fig. 11 Simulation results in read mode: (a) For a cell programmed with ‘0’; (b) For a cell programmed with ‘1’

Fig. 12 Simulation results of BL sensing voltage with respect to post-program eFuse resistance according to read modes

Figure 13 shows DOUT measurement waveforms for test dies of the differential paired eFuse OTP memory IP according to function modes. We can see that the programmed cells are read out normally. Also, it is Fig. 13 DOUT measurement waveforms for test dies of confirmed by the function test that the designed 32-bit differential paired eFuse OTP memory IP according to function OTP memory IP functions normally on 30 sample dies. modes: (a) In case of DIN = ‘0’; (b) In case of DIN =‘1’

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4 Conclusions References

1) A two-dimensional configurable differential [1] KIM J H, KIM D H, JIN L Y, HA P B, KIM Y H. Design of 1 kb paired eFuse OTP memory cell is proposed and a 32-bit eFuse OTP memory ip with reliability considered [J]. Journal of eFuse OTP memory IP is accordingly designed. The Semiconductor Technology and Science, 2011, 11(2): 88–94 sensible resistance of a programmed eFuse link is a half [2] KIM D H, JANG J H, JIN L Y, LEE J H, HA P B, KIM Y H. Design smaller than that of the single-ended counterpart and BL and measurement of a 1-kbit efuse one-time programmable memory datum can be sensed without a reference voltage. ip based on a BCD process [J]. IEICE transaction on Electronics, 2) Also, we reduce the layout area by removing an 2010, E93. C(8): 1365−1370. external pad to supply the program voltage since [3] ROBSON N, SAFRAN J, KOTHANDARAMAN C, CESTERO A, programming is done with VIO (I/O voltage) in the PMIC chips. XIANG C, RAJEEVAKUMAR R, LESLIE A, MOY D, KINHATA T, 3) In addition, we design a sensing margin test IYER S. Electrically programmable fuse (efuse): from memory circuit with variable pull-up loads. Furthermore, we redundancy to autonomic chips [C]// Proceeding of Custom solve a problem of an electrical shortage between an integrated circuits conference. San Jose: IEEE Press, 2007: 799−804. eFuse link and the VSS-biased p-substrate by placing a [4] KULKAMI S, CHEN Z, HE J, JIANG L, PEDERSEN B, ZHANG K. floated n-well under the eFuse link. High-density 3-D metal-fuse prom featuring 1.37 µm2 1T1R bit cell 4) The 32-bit eFuse OTP memory IP is designed in 32 nm high-k metal-gate CMOS technology [C]// 2009 with MagnaChip’s 0.18 µm CMOS process. The layout Symposium on VLSI circuits. Hillsboro: IEEE Press, 2009: 28−29. size is 307.86 µm×150.46 µm. It is confirmed by the [5] KIM J H, JANG J H, JIN L Y, HA P B, KIM Y H. Design of function test that the designed 32-bit OTP memory IP low-power OTP memory IP and its measurement [J]. Korean Institute functions normally on 30 sample dies at the program of Maritime Information and Communication Sciences, 2010, 14(11): voltage of 5.5 V. 2541−2547.

Acknowledgement [6] JANG J H, JIN L Y, JEON H G, KIM K I, HA P B, KIM Y H. Design of an 8-bit differential paired eFuse OTP memory IP reducing

This work is supported by Industrial Strategic sensing resistance by half [J]. Journal of Central South University: Technology Development Program funded by the 2012, 19(1): 168–173. Ministry of Knowledge Economy (MKE, Korea) [7] KIM M S, YOON K S, JANG J H, JIN L Y, HA P B, KIM Y H. (10039239, “Development of Power Management Design of a 32-bit eFuse OTP memory for PMICs [J]. Korean System SoC Supporting Multi-Battery-Cells and Multi- Institute of Maritime Information and Communication Sciences, Energy-Sources for Smart Phones and Smart Devices”). 2011, 15(10): 2209–2216. (Edited by HE Yun-bin)