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(12) United States Patent (10) Patent No.: US 6,928,011 B2 Krishnan Et Al

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(12) United States Patent (10) Patent No.: US 6,928,011 B2 Krishnan Et Al USOO6928O11B2 (12) United States Patent (10) Patent No.: US 6,928,011 B2 Krishnan et al. (45) Date of Patent: Aug. 9, 2005 (54) ELECTRICAL FUSE CONTROL OF (56) References Cited MEMORY SLOWDOWN U.S. PATENT DOCUMENTS (75) Inventors: Manjeri Krishnan, Richardson, TX 5,912,852 A * 6/1999 Lawrence et al. .......... 365/201 (US); Bryan Sheffield, Rowlett, TX 5,995,424. A * 11/1999 Lawrence et al. .......... 365/201 (US); Joel J. Graber, Richardson, TX 6,373,747 B1 * 4/2002 Harari et al. .......... 365/185.09 (US); Duy-Loan Le, Missouri City, TX (US); Sanjive Agarwala, Richardson, * cited by examiner TX (US) Primary Examiner Van Thu Nguyen (73) Assignee: Texas Instruments Incorporated, Assistant Examiner Tuan T. Nguyen Dallas, TX (US) (74) Attorney, Agent, or Firm-Robert D. Marshall, Jr.; W. James Brady, III; Frederick J. Telecky, Jr. (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 (57) ABSTRACT U.S.C. 154(b) by 5 days. Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse tech (21) Appl. No.: 10/630,963 niques by not requiring an additional processing Step and (22) Filed: Jul. 30, 2003 expensive equipment. Standard electrical fuse (eFuse) hard ware chains provide a soft test feature wherein the effect of (65) Prior Publication Data memory slow-down can be tested prior to actually program US 2005/0024960 A1 Feb. 3, 2005 ming the fuses. Electrical fuses thus provide very efficient non-volatile method to match the logic-memory interface (51) Int. Cl. ................................................ G11C 29/00 through memory trimming, drastically cutting costs and (52) U.S. Cl. ........................................ 365/201; 365/200 cycle times involved. (58) Field of Search .............................. 365/201, 225.7, 365/200 18 Claims, 6 Drawing Sheets MEMORYTESTAT OPERAINSSPEED FROMFG.3 APPLYST TEST PROGRAMDATA To 30 SELECHIGHESTSPEED MEMORYTERATION TERATION FOR BOTH "READ"AND"WRITE"OPERATIONS 500 Es 302- STTERATION FOR Both TOFOWCHART OFFIGURE3) REAANWRITE FUNCTONAL 501 READESRE) 303 FIG 4 PROGRAMMATIONDATA MEMORY FIG 3 402 FULLY FUNCTIONAL A00 PROCESSR 405 52 APPY SOFTTESTPROGRAM ELEMENT LOGICFUNCINS ATATOEACH e-SEIN CAN DSPORCPuy N 403 35 APPY SOFT TEST TERATION:2 DIED 406 503- WALUATEINWUAE FOR (NEXTSPEEDEVEL MEMDRYTRIM (DFT) PROGRAMFUSES NoN-MEMORY RELAYEL 504 306 TEST TERATIONE2FR3TH efSE CACHE MEMORY SELECTFTPRSRAM OFTION "REAANIRFUNCONALTY coTROLLER RELJNANCYREPAIR USES RENERATESIRE 40 FROGRAMMATIONAATO MMORY 505 INCLUE MEMORYDFT ejSES FULY FUNCTIONAL OPTIMAL PROGRAMMNS 307 NO APPLY PROGRAPUSLE 56 TEACH FUSENCHAN 509 APPLYSOFTESTERATIONZ 309 (LOWESTSPEEDLEVEL READ ANDERNE RESULT 507 MeFUSESNCHAN TEST TERATNaz. Forsch 31 "REAANRTEFUNCONALY AL DESIRED CHAN EEMENSSUCCESSFULLY NEMORY PROGRAMMED YES 34 FULLY FUNCTIONAL 508 510 PROGRAMMINGOMPLETE 33 511 U.S. Patent Aug. 9, 2005 Sheet 1 of 6 US 6,928,011 B2 FIG. I. 111 (PRIOR ART) is INTZ 112 PDATA IN D Cl R O PDATA OUT O 103 113 PDATA O 115 aw CLR 0. CELL, DATAN DAACLOCK-HH n 106 in FUSE OUTPUT MARGIN 114 ENABLE CLOCK 108 109 VPP PROGRAM 110 FIG. 4 402 405 PROCESSOR 400 ELEMENT LOGIC FUNCTIONS (DSP OR CPU) DEID MEMORYTRIM (DFT) PROGRAMFUSES eFUSE CACHE MEMORY CONTROLLER REDUNDANCY REPAIR FUSES 401 U.S. Patent Aug. 9, 2005 Sheet 3 of 6 US 6,928,011 B2 MEMORYTESTAT OPERATING SPEED APPLY SOFT TEST PROGRAM DATA TO 301 SELECT HIGHEST SPEED MEMORY ITERATION TERATION # 1 FOR BOTH "READ" AND "WRITE" OPERATIONS 302 TEST TERATION # 1 FOR BOTH "READ" AND "WRITE FUNCITONALTY 303 MEMORY FIG. 3 YES FULLY FUNCTIONAL 305 APPLY SOFT TEST TERATION A2 (NEXTSPEED LEVEL) 306 TEST TERATION #2 FOR BOTH "READ" AND "WRITE FUNCITONALITY MEMORY FULLY FUNCTIONAL ? 307 NO APPLY SOFT TEST TERATION #Z 309 (LOWEST SPEED LEVEL) TEST TERATION #Z FOR BOTH 310 "READ" AND "WRITE" FUNCITONALITY MEMORY FULLY FUNCTIONAL YES 314 2 STORE eFUSE TERATION FOR 311 NO LATER MEMORY PROGRAMMATION COMPLETE 313 REECT MEMORY TESTN-315 TO FIG. 5 U.S. Patent Aug. 9, 2005 Sheet 4 of 6 US 6,928,011 B2 FROM FIG. 3 FIG. 5 \ COMPLETE MEMORY TEST 500 (ASCONDUCTED ACCORDING TO FLOW CHART OF FIGURE 3) 501 READ DESIRED PROGRAMMATION DATA 502 APPLY SOFT TEST PROGRAM DATA TO EACH eFUSE IN CHAIN 503 EVALUATE INDIVIDUAL DEFOR NON-MEMORY RELATEDYELD 504 SELECT DFT PROGRAM OPTION REGENERATE DESIRED PROGRAMMATION DATA TO 505 INCLUDE MEMORY DFT eFUSES OPTIMAL PROGRAMMING APPLY PROGRAM PUSLE 506 TO EACH eFUSE IN CHAIN 509 READ AND DETERMINE RESULT 507 ON eFUSES IN CHAIN ALL DESIRED CHAIN ELEMENTS SUCCESSFULLY PROGRAMMED 508 YES 510 511 PROGRAMMING COMPLETE U.S. Patent Aug. 9, 2005 Sheet 5 of 6 US 6,928,011 B2 FIG. 6 62O 620 690 20 || || || || 58 III Sa |||| || || || || 604 || || || || || || || || || || || III s ROWADDRESS ADDRESS LATCH BT LINE DRIVERS MEMORY 611 TIMING 602 WZ (ACTIVE AND LOW WRITE") ) CONTROL 612 609 | COLUMN SYSTEM ADDRESS CLOCK COLUMNDECODERMULTIPLEXER 617 605 Gas 607 608 INPUT/OUTPUT WRITE READ ------------------------. V-sa-7 619-1-------------- 610 eFUSE INPUTS US 6,928,011 B2 1 2 ELECTRICAL FUSE CONTROL OF amount of power to the fuse body to melt and Separate the MEMORY SLOWDOWN fuse body material. This changes the eFuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: TECHNICAL FIELD OF THE INVENTION unblown or blown. The technical field of this invention is control of memory Efuse Implementation Speed of operation on an integrated circuit including both a The eFuse for a conventional programmable device appli microprocessor and memory. cation is normally configured as a chain or two-dimensional BACKGROUND OF THE INVENTION array Sometimes containing hundreds of eFuses and Sup 1O porting logic. Several definitions will be helpful in clarifying Microprocessor chips fabricated with current CMOS the descriptions of eFuse implementation to follow. technology are designed with great care to comprehend the 1. The eFuse is a circuit element having a natural circuit performance variations that occur as the proceSS un-programmed State, but may be permanently programmed shifts from one tolerance extreme to the other. Designers to the opposite State. have become accustomed to speak of MOS transistors 15 2. An eFuse element is an eFuse along with its program having maximum drive capability as Strong transistors and ming and Sensing circuits. MOS transistors with minimum drive capability as weak 3. An eFuse cell is an eFuse element plus the local logic transistors. At both of these extremes, the transistors are required to integrate it into an eFuse chain. within Specified process tolerance limits. It is desirable to 4. An eFuse chain is a collection of one or more eFuse maximize the uSeable yield of all functional devices even cells connected in Series or arrayS. though different Speed performance devices will be pro 5. An eFuse controller is the control logic designed to duced. Normally the whole performance distribution is access the eFuse chains or arrayS. Salable. 6. An un-programmed eFuse has a pre-defined maximum In practice, designs are analyzed according to (a) transis low resistance value. tor strength, (b) power Supply voltage tolerances, (c) inter 25 7. A programmed eFuse has a pre-defined minimum high connect resistance and capacitance, and (d) operating resistance value. temperature, among other possible parameters. Logic por The eFuse chain is programmed by loading the desired tions of the circuit must match as closely as possible the fused State and non-fused State locations into a programming memory portions of the circuit and the interface should be database containing a record for the individual elements of optimized on every die as much as practical. the entire chain. Then those values are programmed into Experience has shown that to optimize overall yield, both each eFuse Sequentially. memory designs and logic designs should carried out for FIG. 1 illustrates the conventional eFuse cell circuit highest possible Speed performance considering all the configuration, which includes an eFuse element 101 plus the design parameters. The most effective matching between local logic required to integrate it into an eFuse chain. CData elements of the logic and elements of memory has been 35 flip-flop 103 is clocked by the Enable Clock 108 and stores shown to be achievable by adjusting memory performance cell data in the chain. PData flip-flop 102 is clocked by the downward incrementally as necessary to improve to usabil Data Clock 106 and latches program data being passed into ity of the full performance Spread of the logic circuit the eFuse cell. portions. Hence, memory designers have conventionally In the program mode, incoming PData In 107 is latched designed-in memory trimming circuitry to incrementally 40 into PData flip-flop 102. This data is programmed into the lower the speed of the memory function. These memory eFuse element on the occurrence of one or more program trimming circuits are generally used to adjust the propaga pulses at Program input 110. PData Out 116 passes to the tion delays in the read and write control circuits and have in eFuse cell via path 116. In the program mode, PData Out Some cases also been applied to adjustment of memory Sense passes through multiplexers 104 and 105 and is latched into amplifier reference elements. 45 the CData flip-flop 102. VPP 109 is the programming power Pervious Techniques for Memory Trimming Source input. Program data is passed Serially to the next cell Originally, memory trimming was achieved by utilizing in the chain at PData Out line 116. Spare gates by way of a revision of the chip interconnect In the test mode, the CData flip-flop 103 latches the data pattern. This incurs Significant costs and cycle times to from the present cell and passes it to Cell Data Out 115.
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