IP Addresses with Majid Tahir
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Virtual Memory
Chapter 4 Virtual Memory Linux processes execute in a virtual environment that makes it appear as if each process had the entire address space of the CPU available to itself. This virtual address space extends from address 0 all the way to the maximum address. On a 32-bit platform, such as IA-32, the maximum address is 232 − 1or0xffffffff. On a 64-bit platform, such as IA-64, this is 264 − 1or0xffffffffffffffff. While it is obviously convenient for a process to be able to access such a huge ad- dress space, there are really three distinct, but equally important, reasons for using virtual memory. 1. Resource virtualization. On a system with virtual memory, a process does not have to concern itself with the details of how much physical memory is available or which physical memory locations are already in use by some other process. In other words, virtual memory takes a limited physical resource (physical memory) and turns it into an infinite, or at least an abundant, resource (virtual memory). 2. Information isolation. Because each process runs in its own address space, it is not possible for one process to read data that belongs to another process. This improves security because it reduces the risk of one process being able to spy on another pro- cess and, e.g., steal a password. 3. Fault isolation. Processes with their own virtual address spaces cannot overwrite each other’s memory. This greatly reduces the risk of a failure in one process trig- gering a failure in another process. That is, when a process crashes, the problem is generally limited to that process alone and does not cause the entire machine to go down. -
Networking: Network Layer
CS 4410 Operating Systems Networking: Network Layer Summer 2013 Cornell University 1 Today ● How packages are exchanged in a WAN? ● Network Layer ● IP ● Naming ● Subnetwork ● Forwarding ● Routing Algorithms 2 Protocol Stack Computer A Computer B Message M Application Application Segment Ht M Transport Transport Datagram Hn Ht M Network Network Frame Hl Hn Ht M Link Link Physical Physical 3 WAN ● Usually, thousands of computers need to be interconnected. ● The capabilities that LANs offer cannot support larger networks. ● We need more services than the Link Layer offers. ● Why? ● Clever Naming ● Efficient forwarding/routing of messages. 4 Network Layer ● Mission: Transfer messages from the source-computer to the destination- computer. ● Attention: this is different from the mission of the Link Layer. ● Services: ● Forwarding / Routing ● Guaranteed delivery, bandwidth, etc ● Security ● Not all the protocols support these services. ● The Network Layer protocol depends on the kind of network we want to built: ● Virtual-circuit networks ● Datagram networks ● Necessary network device: ● Router: It knows where to forward the message. 5 Network Layer ● Virtual-circuit networks ● 3 phases ● Establish a virtual circuit. – The Network Layer finds the path from the source to the destination. – Reserve resources for the virtual circuit. ● Transfer data – Packets pass through the virtual circuit. ● Destroy virtual circuit. – Release resources. ● Disadvantages? ● Datagram networks ● Every packet has the destination address and it is routed independently in the network. ● The router uses the destination address to forward the packet towards 6 the destination-computer. IP ● Network Layer Protocol for the Internet: ● Internet Protocol ● For Datagram networks. ● IPv4, IPv6 ● Datagram structure: Version Header Type of Length Length service Identification Flags Fragment Offset Time to live Protocol Header Checksum Source IP Address (32-bit) Destination IP Address Options Data 7 Naming ● All the computers in the Internet have one or more IP addresses. -
Internet Routing Over Large Public Data Networks Using Shortcuts
Internet Routing over Large Public Data Networks using Shortcuts Paul F, Tsuchiya, Bellcore, [email protected] When a system (a router or host) needs to send an internet packet, it must determine the destination subnetwork Abstract address to send the packet to. (IP systems traditionally do this as a two-step process. First the 1P address of the With the emergence of large switched public data networks receiving system is determined. Then the subnetwork that are well-suited to connectionless internets, for instance address associated with the 1P address is derived.) On SMDS, it is possible that larger and larger numbers of broadcast LANs this has proven to be relatively simple. internet users will get their connectivity from large public This is because 1) broadcast LANs have a small number of data networks whose native protocols are not the same as attached systems (hundreds), and 2) broadcast LANs have the user’s internet protocol. This results in a routing an inexpensive multicast, thus making “searching” for problem that has not yet been addressed. That is, large systems on a LAN inexpensive and easy. numbers of routers (potentially tens of thousands) must be able to find direct routes to each other in a robust and On very large general topology subnetworks (called here efficient way. This paper describes a solution to the public data networks, or PDNs2), however, determining problem, called shortcut routing, that incorporates 1) a “next hop” subnetwork (or PDN) addresses is not sparse graph of logical connectivity between routers, 2) necessarily simple. There may be (eventually) tens of hierarchical addressing among the public data network thousands of systems attached to a PDN, making it subscribers, and 3) the use of “entry router” information in inefficient to distribute up-to-date information about all packets to allow routers to find one hop “shortcuts” across systems to all systems. -
2-Atn-Bgp-Pdf
A Simple BGP-Based Routing Service for the Aeronautical Telecommunications Network (with AERO and OMNI) IETF 111 rtgwg session (July 28, 2021) Fred L. Templin (The Boeing Company) [email protected] [email protected] 1 Document Status • “A Simple BGP-based Mobile Routing System for the Aeronautical Telecommunications Network” • BGP-based “spanning tree” configured over one or more Internetworking “segments” based on Non-Broadcast, Multiple Access (NBMA) interface model and IPv6 Unique Local Address (ULA) prefixes • ASBRs of each segment in a “hub-and-spokes” arrangement, with peering between adjacent segment hubs • IETF rtgwg working group item since August 30, 2018 - coordinated with International Civil Aviation Organization (ICAO) Aeronautical Telecommunications Network (ATN) • https://datatracker.ietf.org/doc/draft-ietf-rtgwg-atn-bgp/ • Work ready for IETF rtgwg WGLC • “Automatic Extended Route Optimization (AERO)” • Route optimization extensions that establish “shortcuts” to avoid strict spanning tree paths • Mobility/multilink/multinet/multihop support based on agile “hub-and-spokes” ClientProxy/Server model • https://datatracker.ietf.org/doc/draft-templin-6man-aero/ • Work ready for IETF adoption • “Transmission of IP Packets over Overlay Multilink Network (OMNI) Interfaces” • Single NBMA network interface exposed to the IP layer with fixed 9KB MTU, but configured as an overlay over multiple underlying (physical or virtual) interfaces with heterogeneous MTUs • OMNI Adaptation Layer (OAL) – minimal mid-layer encapsulation that -
Virtual Memory - Paging
Virtual memory - Paging Johan Montelius KTH 2020 1 / 32 The process code heap (.text) data stack kernel 0x00000000 0xC0000000 0xffffffff Memory layout for a 32-bit Linux process 2 / 32 Segments - a could be solution Processes in virtual space Address translation by MMU (base and bounds) Physical memory 3 / 32 one problem Physical memory External fragmentation: free areas of free space that is hard to utilize. Solution: allocate larger segments ... internal fragmentation. 4 / 32 another problem virtual space used code We’re reserving physical memory that is not used. physical memory not used? 5 / 32 Let’s try again It’s easier to handle fixed size memory blocks. Can we map a process virtual space to a set of equal size blocks? An address is interpreted as a virtual page number (VPN) and an offset. 6 / 32 Remember the segmented MMU MMU exception no virtual addr. offset yes // < within bounds index + physical address segment table 7 / 32 The paging MMU MMU exception virtual addr. offset // VPN available ? + physical address page table 8 / 32 the MMU exception exception virtual address within bounds page available Segmentation Paging linear address physical address 9 / 32 a note on the x86 architecture The x86-32 architecture supports both segmentation and paging. A virtual address is translated to a linear address using a segmentation table. The linear address is then translated to a physical address by paging. Linux and Windows do not use use segmentation to separate code, data nor stack. The x86-64 (the 64-bit version of the x86 architecture) has dropped many features for segmentation. -
Ipv6 Addresses
56982_CH04II 12/12/97 3:34 PM Page 57 CHAPTER 44 IPv6 Addresses As we already saw in Chapter 1 (Section 1.2.1), the main innovation of IPv6 addresses lies in their size: 128 bits! With 128 bits, 2128 addresses are available, which is ap- proximately 1038 addresses or, more exactly, 340.282.366.920.938.463.463.374.607.431.768.211.456 addresses1. If we estimate that the earth’s surface is 511.263.971.197.990 square meters, the result is that 655.570.793.348.866.943.898.599 IPv6 addresses will be available for each square meter of earth’s surface—a number that would be sufficient considering future colo- nization of other celestial bodies! On this subject, we suggest that people seeking good hu- mor read RFC 1607, “A View From The 21st Century,” 2 which presents a “retrospective” analysis written between 2020 and 2023 on choices made by the IPv6 protocol de- signers. 56982_CH04II 12/12/97 3:34 PM Page 58 58 Chapter Four 4.1 The Addressing Space IPv6 designers decided to subdivide the IPv6 addressing space on the ba- sis of the value assumed by leading bits in the address; the variable-length field comprising these leading bits is called the Format Prefix (FP)3. The allocation scheme adopted is shown in Table 4-1. Table 4-1 Allocation Prefix (binary) Fraction of Address Space Allocation of the Reserved 0000 0000 1/256 IPv6 addressing space Unassigned 0000 0001 1/256 Reserved for NSAP 0000 001 1/128 addresses Reserved for IPX 0000 010 1/128 addresses Unassigned 0000 011 1/128 Unassigned 0000 1 1/32 Unassigned 0001 1/16 Aggregatable global 001 -
Advanced X86
Advanced x86: BIOS and System Management Mode Internals Input/Output Xeno Kovah && Corey Kallenberg LegbaCore, LLC All materials are licensed under a Creative Commons “Share Alike” license. http://creativecommons.org/licenses/by-sa/3.0/ ABribuEon condiEon: You must indicate that derivave work "Is derived from John BuBerworth & Xeno Kovah’s ’Advanced Intel x86: BIOS and SMM’ class posted at hBp://opensecuritytraining.info/IntroBIOS.html” 2 Input/Output (I/O) I/O, I/O, it’s off to work we go… 2 Types of I/O 1. Memory-Mapped I/O (MMIO) 2. Port I/O (PIO) – Also called Isolated I/O or port-mapped IO (PMIO) • X86 systems employ both-types of I/O • Both methods map peripheral devices • Address space of each is accessed using instructions – typically requires Ring 0 privileges – Real-Addressing mode has no implementation of rings, so no privilege escalation needed • I/O ports can be mapped so that they appear in the I/O address space or the physical-memory address space (memory mapped I/O) or both – Example: PCI configuration space in a PCIe system – both memory-mapped and accessible via port I/O. We’ll learn about that in the next section • The I/O Controller Hub contains the registers that are located in both the I/O Address Space and the Memory-Mapped address space 4 Memory-Mapped I/O • Devices can also be mapped to the physical address space instead of (or in addition to) the I/O address space • Even though it is a hardware device on the other end of that access request, you can operate on it like it's memory: – Any of the processor’s instructions -
Chapter5(Ipv4 Address)
Chapter 5 IPv4 Address Kyung Hee University 1 5.1 Introduction Identifier of each device connected to the Internet : IP Address IPv4 Address : 32 bits The address space of IPv4 is 232 or 4,294,967,296 The IPv4 addresses are unique and universal Two devices on the Internet can never have the same address at same time Number in base 2, 16, and 256 Refer to Appendix B Kyung Hee University 2 Binary Notation and Dotted-Decimal Notation Binary notation 01110101 10010101 00011101 11101010 32 bit address, or a 4 octet address or a 4-byte address Decimal point notation Kyung Hee University 3 Notation (cont’d) Hexadecimal Notation 0111 0101 1001 0101 0001 1101 1110 1010 75 95 1D EA 0x75951DEA - 8 hexadecimal digits - Used in network programming Kyung Hee University 4 Example 5.1 Change the following IPv4 addresses from binary notation to dotted-decimal notation a. 10000001 00001011 00001011 11101111 b. 11000001 10000011 00011011 11111111 c. 11100111 11011011 10001011 01101111 d. 11111001 10011011 11111011 00001111 Solution We replace each group of 8 bits with its equivalent decimal number (see Appendix B) and add dots for separation. a. 129.11.11.239 b. 193.131.27.255 c. 231.219.139.111 d. 249.155.251.15 Kyung Hee University 5 Example 5.4 Change the following IPv4 address in hexadecimal notation. a. 10000001 00001011 00001011 11101111 b. 11000001 10000011 00011011 11111111 Solution We replace each group of 4 bits with its hexadecimal equivalent. Note that hexadecimal notation normally has no added spaces or dots; however, 0x is added at the beginning of the subscript 16 at the end a. -
Virtual Memory in X86
Fall 2017 :: CSE 306 Virtual Memory in x86 Nima Honarmand Fall 2017 :: CSE 306 x86 Processor Modes • Real mode – walks and talks like a really old x86 chip • State at boot • 20-bit address space, direct physical memory access • 1 MB of usable memory • No paging • No user mode; processor has only one protection level • Protected mode – Standard 32-bit x86 mode • Combination of segmentation and paging • Privilege levels (separate user and kernel) • 32-bit virtual address • 32-bit physical address • 36-bit if Physical Address Extension (PAE) feature enabled Fall 2017 :: CSE 306 x86 Processor Modes • Long mode – 64-bit mode (aka amd64, x86_64, etc.) • Very similar to 32-bit mode (protected mode), but bigger address space • 48-bit virtual address space • 52-bit physical address space • Restricted segmentation use • Even more obscure modes we won’t discuss today xv6 uses protected mode w/o PAE (i.e., 32-bit virtual and physical addresses) Fall 2017 :: CSE 306 Virt. & Phys. Addr. Spaces in x86 Processor • Both RAM hand hardware devices (disk, Core NIC, etc.) connected to system bus • Mapped to different parts of the physical Virtual Addr address space by the BIOS MMU Data • You can talk to a device by performing Physical Addr read/write operations on its physical addresses Cache • Devices are free to interpret reads/writes in any way they want (driver knows) System Interconnect (Bus) : all addrs virtual DRAM Network … Disk (Memory) Card : all addrs physical Fall 2017 :: CSE 306 Virt-to-Phys Translation in x86 0xdeadbeef Segmentation 0x0eadbeef Paging 0x6eadbeef Virtual Address Linear Address Physical Address Protected/Long mode only • Segmentation cannot be disabled! • But can be made a no-op (a.k.a. -
Introduction to IP Multicast Routing
Introduction to IP Multicast Routing by Chuck Semeria and Tom Maufer Abstract The first part of this paper describes the benefits of multicasting, the Multicast Backbone (MBONE), Class D addressing, and the operation of the Internet Group Management Protocol (IGMP). The second section explores a number of different algorithms that may potentially be employed by multicast routing protocols: - Flooding - Spanning Trees - Reverse Path Broadcasting (RPB) - Truncated Reverse Path Broadcasting (TRPB) - Reverse Path Multicasting (RPM) - Core-Based Trees The third part contains the main body of the paper. It describes how the previous algorithms are implemented in multicast routing protocols available today. - Distance Vector Multicast Routing Protocol (DVMRP) - Multicast OSPF (MOSPF) - Protocol-Independent Multicast (PIM) Introduction There are three fundamental types of IPv4 addresses: unicast, broadcast, and multicast. A unicast address is designed to transmit a packet to a single destination. A broadcast address is used to send a datagram to an entire subnetwork. A multicast address is designed to enable the delivery of datagrams to a set of hosts that have been configured as members of a multicast group in various scattered subnetworks. Multicasting is not connection oriented. A multicast datagram is delivered to destination group members with the same “best-effort” reliability as a standard unicast IP datagram. This means that a multicast datagram is not guaranteed to reach all members of the group, or arrive in the same order relative to the transmission of other packets. The only difference between a multicast IP packet and a unicast IP packet is the presence of a “group address” in the Destination Address field of the IP header. -
Virtual Memory
CSE 410: Systems Programming Virtual Memory Ethan Blanton Department of Computer Science and Engineering University at Buffalo Introduction Address Spaces Paging Summary References Virtual Memory Virtual memory is a mechanism by which a system divorces the address space in programs from the physical layout of memory. Virtual addresses are locations in program address space. Physical addresses are locations in actual hardware RAM. With virtual memory, the two need not be equal. © 2018 Ethan Blanton / CSE 410: Systems Programming Introduction Address Spaces Paging Summary References Process Layout As previously discussed: Every process has unmapped memory near NULL Processes may have access to the entire address space Each process is denied access to the memory used by other processes Some of these statements seem contradictory. Virtual memory is the mechanism by which this is accomplished. Every address in a process’s address space is a virtual address. © 2018 Ethan Blanton / CSE 410: Systems Programming Introduction Address Spaces Paging Summary References Physical Layout The physical layout of hardware RAM may vary significantly from machine to machine or platform to platform. Sometimes certain locations are restricted Devices may appear in the memory address space Different amounts of RAM may be present Historically, programs were aware of these restrictions. Today, virtual memory hides these details. The kernel must still be aware of physical layout. © 2018 Ethan Blanton / CSE 410: Systems Programming Introduction Address Spaces Paging Summary References The Memory Management Unit The Memory Management Unit (MMU) translates addresses. It uses a per-process mapping structure to transform virtual addresses into physical addresses. The MMU is physical hardware between the CPU and the memory bus. -
Networking Basics
Networking Basics Pre-class work…read/watch all the material at least once before class…I will clarify in class. Binary Training(Google search for “binary tutorial”): http://www.math.grin.edu/~rebelsky/Courses/152/97F/Readings/student-binary http://www.codeconquest.com/tutorials/binary/ https://www.youtube.com/watch?v=0qjEkh3P9RE https://www.youtube.com/watch?v=VBDoT8o4q00 Subnet Addressing and Masks(Google search for “subnet mask tutorial”: http://www.techopedia.com/6/28587/internet/8-steps-to-understanding-ip-subnetting http://www.subnetting.net/Tutorial.aspx https://www.youtube.com/watch?v=aA-8owNNy_c 2/10/2017 1 Table of Contents (3)What is the OSI Model? (6)What is a Hub, Switch, & Router/Access Server? (10)Mac Addresses and IP Addresses (15)The “3 GOLDEN PARAMETERS” (16)Day in the Life of a Packet (17)Duplex Issues (18)PC Configuration Guidance (21)Basic Discovery & Connectivity Tools (23)IPv4 Layers and Port Numbers 2/10/2017 2 What is the OSI Model? OSI – open systems interconnection Main functions Network dependent functions Application-oriented functions Seven layer model Each layer performs a well- defined set of functions 2/10/2017 3 Data Encapsulation Application User data Presentation converted for Data (PDU) transmission Session Add transport Segments Transport type header Add network Packets Network header (datagram) Add datalink Frames Datalink header Convert 11001010…100 Bits Physical to bits 2/10/2017 4 ISO’s OSI Reference Model Application Application Presentation Presentation Session Session Transport Transport