Architecture Reference Guide

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Architecture Reference Guide V2500 Server First Edition A5074-96004 V2500 Server Customer Order Number: A5074-90004 June, 1999 Printed in: USA Revision History Edition: First Document Number: A3725-96004 Remarks: Initial release June, 1999. Notice Copyright Hewlett-Packard Company 1999. All Rights Reserved. Reproduction, adaptation, or translation without prior written permission is prohibited, except as allowed under the copyright laws. The information contained in this document is subject to change without notice. Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance or use of this material. Contents Preface . xv Notational conventions . xvi 1 Introduction . 1 The PA-8500 processor . .2 The node . .3 Control and status registers (CSRs) . .5 Description of functional blocks. .5 Processor agent controller. .5 Routing attachment controller—Hyperplane crossbar . .6 Memory access controller . .7 CUB and core logic bus . .8 Shared memory . .9 Multiple nodes . .11 Coherent toroidal interconnect . .12 Globally shared memory (GSM) . .14 GSM subsystem . .14 Memory interleave . .14 GSM and memory latency . .15 GSM and cache coherence . .17 2 Physical address space . 19 Physical addresses. .20 Node addressing . .22 Node Identifiers . .23 Coherent memory space . .24 Coherent memory layout . .25 Addressing a byte of memory. .25 Memory interleaving . .27 Memory interleave generation. .29 Force node ID function . .30 Memory board, bus and bank index selection . .32 Memory board interleave pattern . .33 Memory bus interleave pattern . .35 Memory bank interleave pattern . .36 Memory board, bus bank interleave pattern . .37 CTI cache layout . .39 Nonexistent memory . .42 Table of Contents iii Core logic space . 43 Local I/O space . 44 Non-I/O CSR space. 45 Accelerated CSR access . 47 CSR access . 48 Runway-local access . 48 PAC-local access . 49 Node-local accesses . 50 Remote access . 50 Access to nonexistent CSRs . 51 System Configuration register . 52 PAC Configuration register . 56 PAC Processor Configuration register . 57 PAC Memory Board Configuration register . 58 MAC Configuration register. 60 MAC Memory Region register . 61 Unprotected Memory register . 61 Normal CTI Cache Memory Region register . 62 Unprotected CTI Cache Memory Region register . 62 Memory region access checking summary . 62 Memory Region Access Checking Summary . 64 TAC Configuration register . 66 3 Cache Management . 67 Cache concepts . 68 PA-8500 caches . 68 CTI cache. 68 Cacheability. 69 Address aliasing . 70 Cache operations . 71 PA-8500 cache operations . 71 CTI cache operations . 72 CTI cache global flush . 72 CTI cache flush entry . 72 CTI cache prefetch for read . 72 CTI cache prefetch for write . 72 Cache operation summary . 73 Cache operation interfaces . 75 PA-8500 cache interfaces . 75 CTI cache interfaces . 75 CTI cache AIL routines. 75 Instruction method of issuing cache management operations . 76 CTI cache flush global instruction . 77 iv Table of Contents CTI cache prefetch read . .79 CTI cache prefetch write. .81 CSR method of issuing cache management operations . .83 Operation CSRs. .83 Instruction sequence . .83 Cache management CSRs . .85 Cache management operations . .85 PAC Operation Context register. .85 Context State Save/Restore . .88 PAC Operation Address registers. .89 Cache Management Operation addresses . ..

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Contents [Edit] History
HP 9000 is the name for a line of workstation and server computer systems produced by the Hewlett-Packard Company (HP). The HP 9000 brand was introduced in 1984 to encompass several existing technical workstations models previously launched in the early 1980s. Contents [hide] • 1 History • 2 Workstation models o 2.1 Series 200 o 2.2 Series 300/400 o 2.3 Series 500 o 2.4 Series 700 . 2.4.1 VME Industrial Workstations o 2.5 B, C, J class • 3 Server models o 3.1 D-class o 3.2 R-class o 3.3 N-class o 3.4 L-class o 3.5 A-class o 3.6 S/X-class o 3.7 V-class • 4 Operating systems • 5 See also • 6 Notes • 7 References • 8 External links [edit] History The first HP 9000 models comprised the HP 9000 Series 200 and Series 500 ranges. These were rebadged existing models, the Series 200 including various Motorola 68000- based workstations such as the HP 9826 and HP 9836, and the Series 500 using HP's FOCUS microprocessor architecture introduced in the HP 9020 workstation. These were followed by the HP 9000 Series 300 and Series 400 workstations which also used 68k- series microprocessors. From the mid-1980s onwards, HP started to switch over to its own microprocessors based on its proprietary PA-RISC ISA, for the Series 600, 700, 800, and later lines. More recent models use either the PA-RISC or its successor, the HP/Intel IA-64 ISA. All of the HP 9000 line run various versions of the HP-UX operating system, except earlier Series 200 models, which ran standalone applications.
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PC Hardware Contents
PC Hardware Contents 1 Computer hardware 1 1.1 Von Neumann architecture ...................................... 1 1.2 Sales .................................................. 1 1.3 Diﬀerent systems ........................................... 2 1.3.1 Personal computer ...................................... 2 1.3.2 Mainframe computer ..................................... 3 1.3.3 Departmental computing ................................... 4 1.3.4 Supercomputer ........................................ 4 1.4 See also ................................................ 4 1.5 References ............................................... 4 1.6 External links ............................................. 4 2 Central processing unit 5 2.1 History ................................................. 5 2.1.1 Transistor and integrated circuit CPUs ............................ 6 2.1.2 Microprocessors ....................................... 7 2.2 Operation ............................................... 8 2.2.1 Fetch ............................................. 8 2.2.2 Decode ............................................ 8 2.2.3 Execute ............................................ 9 2.3 Design and implementation ...................................... 9 2.3.1 Control unit .......................................... 9 2.3.2 Arithmetic logic unit ..................................... 9 2.3.3 Integer range ......................................... 10 2.3.4 Clock rate ........................................... 10 2.3.5 Parallelism .........................................
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Integrating DMA Into the Generic Device Model
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Internals Training Guide HP E3000 MPE/Ix Computer Systems
Internals Training Guide HP e3000 MPE/iX Computer Systems Edition 1 Manufacturing Part Number: 30216-90316 E0101 U.S.A. January 2001 Notice The information contained in this document is subject to change without notice. Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability or ﬁtness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for direct, indirect, special, incidental or consequential damages in connection with the furnishing or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. This document contains proprietary information which is protected by copyright. All rights reserved. Reproduction, adaptation, or translation without prior written permission is prohibited, except as allowed under the copyright laws. Restricted Rights Legend Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. Rights for non-DOD U.S. Government Departments and Agencies are as set forth in FAR 52.227-19 (c) (1,2). Acknowledgments UNIX is a registered trademark of The Open Group. Hewlett-Packard Company 3000 Hanover Street Palo Alto, CA 94304 U.S.A. © Copyright 2001 by Hewlett-Packard Company 2 Contents 1. Hardware Overview Monitor and I/O Services 2. PCISCSI Device Adapter Manager (DAM) Internals Training . 38 Additional References . 40 Introduction. 40 PCI Based SCSI Interface Cards .
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The Hp Pa-8000 Risc Cpu
. THE HP PA-8000 RISC CPU Ashok Kumar he PA-8000 RISC CPU is the first of a bits (40 bits on the PA-8000). A new mode new generation of Hewlett-Packard bit governs address formation, creating Hewlett-Packard Tmicroprocessors. Designed for high- increased flexibility. In 32-bit addressing end systems, it is among the world’s most mode, the processor can take advantage of powerful and fastest microprocessors. It fea- 64-bit computing instructions for faster tures an aggressive, four-way, superscalar throughput. In 64-bit addressing mode, 32- implementation, combining speculative exe- bit instructions and conditions are available cution with on-the-fly instruction reordering. for backward compatibility. The heart of the machine, the instruction In addition, the following extensions help reorder buffer, provides out-of-order execu- optimize performance for virtual memory tion capability. and cache management, branching, and Our primary design objective for the PA- floating-point operations: 8000 was to attain industry-leading perfor- mance in a broad range of applications. In • fast TLB (translation look-aside buffer) addition, we wanted to provide full support insertion instructions, for 64-bit applications. To make the PA-8000 • load and store instructions with 16-bit truly useful, we needed to ensure that the displacement, processor would not only achieve high bench- • memory prefetch instructions, mark performance but would sustain such • support for variable-size pages, performance in large, real-world applications. • halfword instructions for multimedia To achieve this goal, we designed large, exter- support, nal primary caches with the ability to hide • branches with 22-bit displacements, memory latency in hardware.
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Service Handbook
Service Handbook J Class Workstation HP Part No. A2876–90041 Edition E0498 Update to Service Handbook J Class Workstation HP Part No. A2876–90040 R Hewlett–Packard Company 3404 E. Harmony Rd., Ft. Collins, CO 80528–9599 NOTICE The information contained in this document is subject to change without notice. HEWLETT–PACKARD WARRANTY STATEMENT HP PRODUCT DURATION OF WARRANTY J Class Workstation one year 1. HP warrants HP hardware, accessories and supplies against defects in materials and workmanship for the period specified above. If HP receives notice of such defects during the warranty period, HP will, at its option, either repair or replace products which prove to be defective. Replacement products may be either new or like–new. 2. HP warrants that HP software will not fail to execute its programming instructions, for the period specified above, due to defects in material and workmanship when properly installed and used. If HP receives notice of such defects during the warranty period, HP will replace software media which does not execute its programming instructions due to such defects. 3. HP does not warrant that the operation of HP products will be uninterrupted or error free. If HP is unable, within a reasonable time, to repair or replace any product to a condition as warranted, customer will be entitled to a refund of the purchase price upon prompt return of the product. 4. HP products may contain remanufactured parts equivalent to new in performance or may have been subject to incidental use. 5. The warranty period begins on the date of delivery or on the date of installation if installed by HP.
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Hp Server Rp7400
an hp white paper february 2002 hp server rp7400 This white paper describes the design goals and system system architecture architecture of the HP server rp7400 and provides recommendations for implementing business-critical and design guide solutions. table of contents introduction .......................................................................................................................3 overview of the hp server rp7400 ...................................................................... 3 the hp enterprise server product line ................................................................... 4 performance .................................................................................................... 5 design philosophy—balanced high performance.................................................. 6 binary compatibility.......................................................................................... 7 architecture .......................................................................................................................7 twin system bus ................................................................................................ 8 very low latency memory access ........................................................................ 9 speeds and feeds ........................................................................................... 10 I/O subsystem design ..................................................................................... 11 scalability.....................................................................................................
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739250-1.Pdf
Eindhoven University of Technology MASTER Modeling and analysis of a cache coherent interconnect Wiener, U. Award date: 2012 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Eindhoven University of Technology Faculty of Electrical Engineering Electronic Systems Group Modeling and Analysis of a Cache Coherent Interconnect Thesis Report submitted in partial fulﬁllment of the requirements for the degree of Master of Science in Embedded Systems Supervisors: by: Prof. Kees Goossens Uri Wiener Dr. Andreas Hansson v2.2, August 2, 2012 Abstract System on Chip (SoC) designs integrate heterogeneous components, increasing in number, performance, and memory-related requirements. Such components share data using distributed shared memory, and rely on caches for improving performance and reducing power consumption.
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Independent PA-RISC and Itanium Reference Book
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Sensory Information Processing
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