Sensory Information Processing
Analysis of Avalanche’s Shared M em ory Architecture Ravindra Kuramkote, John Carter, Alan Davis, Chen-Chi Kuo, Leigh Stoller, Mark Swanson UUCS-97-008 * Computer Systems Laboratory University of Utah ' A bstract In this paper, we describe the design of the Avalanchemultiprocessor’s shared memory subsys tem, evaluate its performance, and discuss problems associated with using commodity worksta tions and network interconnects as the building blocks of a scalable shared memory multiprocessor. Compared to other scalable shared memory architectures, Avalanchehas a number of novel fea tures including its support for the Simple COMA memory architecture and its support for multiple coherency protocols (migratory, delayed write update, and (soon) write invalidate). We describe the performance implications of Avalanche’s architecture, the impact of various novel low-level design options, and describe a number of interesting phenomena we encountered while developing a scalable multiprocessor built on the HP PA-RISC platform. 1 9 Analysis of Avalanche’s Shared M em ory Architecture Ravindra Kuram,kote, John Carter, Alan Davis, Chen-Chi Kuo, Leigh Stoller, Mark Swanson Computer Systems Laboratory University of Utah 1 Introduction , The primary Avalanchedesign goal is to maximize the use of commercial components in the creation of a scalable parallel cluster of workstation multiprocessor that supports both high performance message passing and distributed shared memory. In the current prototype, Avalanchenodes are composed from Hewlett-Packard HP7200 or PA-8000 based symmetric multiprocessing worksta tions, a custom device called the W idget, and Myricom’s Myrinet interconnect fabric [6]. Both workstations use a main memory bus known as the Runway [7], a split transaction bus supporting cache coherent transactions.
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