10BASE-T1S Learn To Run Supported by Embedded Software
V1.1 | 2021-06-11 Agenda
1. All IP Car
2. Extensions in AUTOSAR
3. Areas of Investigation
4. Evaluation SW Setup Based on the Infineon Evaluation Kit
2 All IP Car 10BASE-T1S as Replacement for Lower Bandwidth Networks
IP as
well-known common “language”
proven in use technology
enabler for E/E architecture trends and service-based communication and Ethernet is the naturally associated Network Access Layer
3 All IP Car Introducing an Additional Network Access Layer
It’s more than just physical layer compliance The digital eco-system must be “ready”
Tools, data models and databases
SW AUTOSAR
…
4 Extensions in AUTOSAR 10BASE-T1S Within AUTOSAR Classic Platform
10BASE-T1S was introduced as new concept in R20-11
Further refinement is currently ongoing within AUTOSAR
It’s Ethernet the upper layer stack remains untouched Utilize the benefits of the strictly layered architecture
Encapsulate the changes in the MCAL layer
Ethernet Driver
Ethernet Switch Driver
Ethernet Transceiver Driver
Eth EthSwt EthTrcv
5 Areas of Investigation Extension of the Existing MICROSAR Solution
Ethernet Transceiver Driver Ethernet Driver
10BASE-T1S specific initializations Depending on actual Transceiver device Timeline is depending on documentation and device availability
Diagnostic Interface
Error and State Management Transmit Buffer Management 6 Evaluation SW Setup Based on the Infineon Evaluation Kit Specific SIP – Software Integration Package
Fixed Compile Environment Infineon TriBoard TC377 plus specific 10BASE-T1S transceiver Subset of available MICROSAR components Tools
Necessary extensions to specific MICROSAR components
Used for internal investigations
SIP available on demand
7 10BASE-T1S Learn To Run – Supported by Embedded Software
Vector Automotive Ethernet Symposium 2021 Josef Nöbauer, Harald Zweck Evaluation Kit 10Base-T1S Building Blocks at Board Level
o Microcontroller board • Controller AURIX™ TC377TX • 2 x Ethernet MAC • CAN • FlexRay
o PHY board • 10BT1S Transceiver • PoDL* logic • Connector for wire o AutoSAR SW o See Vector
o Cable & connectors
*PoDL: Power over Data Line
2021-06-15 2 Evaluation Kit 10Base-T1S System Configuration Options Option MII Option SPI Option 3-Pin o Interface options o Option MII Controller Board Controller Board Controller Board • Microcontroller provides Ethernet Ethernet Ethernet − Ethernet MAC FlexRay CAN FlexRay CAN FlexRay CAN • PHY provides AURIX™ AURIX™ AURIX™ − PLCA logic MII SPI 3-Pin − analog Front End (FE) Connector Connector Connector o Option SPI Connector Connector
PHY Board Connector PHY Board • PHY provides PHY Board − Ethernet MAC MII MII MII ETH MAC
PLCA PHY Analog FE PHY
− PLCA logic PHY Analog FE PLCA − Analog Front End (FE) Discretes Analog FE Discretes Connector o Option 3-Pin interface Connector Discretes • Microcontroller provides Connector wires − Ethernet MAC, PLCA logic wires • PHY provides wires − Analog Front End (FE)
2021-06-15 3 Evaluation Kit 10Base-T1S System Configuration Options Option MII Option SPI Option 3-Pin o Interface options o Option MII Controller Board Controller Board Controller Board • Microcontroller provides Ethernet Ethernet Ethernet − Ethernet MAC FlexRay CAN FlexRay CAN FlexRay CAN • PHY provides AURIX™ AURIX™ AURIX™ − PLCA logic MII SPI 3-Pin − analog Front End Connector Connector Connector o Option SPI Connector Connector
PHY Board Connector PHY Board • PHY provides PHY Board − Ethernet MAC MII MII MII ETH MAC
PLCA PHY Analog FE PHY
− PLCA logic PHY Analog FE PLCA − Analog Front End Discretes Analog FE Discretes Connector o Option 3-Pin interface Connector Discretes • Microcontroller provides Connector wires − Ethernet MAC, PLCA logic wires • PHY provides wires − Analog Front End
2021-06-15 4 Evaluation Kit 10Base-T1S Building Blocks at Functional Level AURIX™ Microcontroller o Controller cores & SW Stack(s) CPU & RAM • CPUs Ethernet Stack • RAM • Flash Ethernet MAC o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) Transmit Receive DMAs/Queues DMAs/Queues • Queues for sending & receiving • Shapers in the transmit path Credit Based Address & Tag Shaper Filters • Filters in the receive path • Time stamping units for 802.1AS 802.1AS 802.1AS
o MII interface to / from PHY MII • MII interface for data transfer • MDC/MDIO interface for PHY control & status MII o PHY PCS/PMA PLCA PCS/PMA • PCS/PMA logic (IEEE 802.3) Analog FE PCS: Physical Coding Sublayer • PLCA collision avoidance 10Base-T1S PHY PMA: Physical Medium Attachment • Analog front end PLCA: Physical Layer Collision Avoidance
2021-06-15 5 Evaluation Kit 10Base-T1S Building Blocks at Functional Level AURIX™ Microcontroller o Controller cores & SW Stack(s) CPU & RAM • CPUs Ethernet Stack • RAM • Flash Ethernet MAC o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) Transmit Receive DMAs/Queues DMAs/Queues • Queues for sending & receiving • Shapers in the transmit path Credit Based Address & Tag Shaper Filters • Filters in the receive path • Time stamping units for 802.1AS 802.1AS 802.1AS
o MII interface to / from PHY MII • MII interface for data transfer • MDC/MDIO interface for PHY control & status MII o PHY PCS/PMA PLCA PCS/PMA • PCS/PMA logic (IEEE 802.3) Analog FE PCS: Physical Coding Sublayer • PLCA collision avoidance 10Base-T1S PHY PMA: Physical Medium Attachment • Analog front end PLCA: Physical Layer Collision Avoidance
2021-06-15 6 Evaluation Kit 10Base-T1S Building Blocks at Functional Level AURIX™ Microcontroller o Controller cores & SW Stack(s) CPU & RAM • CPUs Ethernet Stack • RAM • Flash Ethernet MAC o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) Transmit Receive DMAs/Queues DMAs/Queues • Queues for sending & receiving • Shapers in the transmit path Credit Based Address & Tag Shaper Filters • Filters in the receive path • Time stamping units for 802.1AS 802.1AS 802.1AS
o MII interface to / from PHY MII • MII interface for data transfer • MDC/MDIO interface for PHY control & status MII o PHY PCS/PMA PLCA PCS/PMA • PCS/PMA logic (IEEE 802.3) Analog FE PCS: Physical Coding Sublayer • PLCA collision avoidance 10Base-T1S PHY PMA: Physical Medium Attachment • Analog front end PLCA: Physical Layer Collision Avoidance
2021-06-15 7 Evaluation Kit 10Base-T1S Building Blocks at Functional Level AURIX™ Microcontroller o Controller cores & SW Stack(s) CPU & RAM • CPUs Ethernet Stack • RAM • Flash Ethernet MAC o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) Transmit Receive DMAs/Queues DMAs/Queues • Queues for sending & receiving • Shapers in the transmit path Credit Based Address & Tag Shaper Filters • Filters in the receive path • Time stamping units for 802.1AS 802.1AS 802.1AS
o MII interface to / from PHY MII • MII interface for data transfer • MDC/MDIO interface for PHY control & status MII o PHY PCS/PMA PLCA PCS/PMA • PCS/PMA logic (IEEE 802.3) Analog FE PCS: Physical Coding Sublayer • PLCA collision avoidance 10Base-T1S PHY PMA: Physical Medium Attachment • Analog front end PLCA: Physical Layer Collision Avoidance
2021-06-15 8 Evaluation Kit 10Base-T1S Building Blocks at Functional Level AURIX™ Microcontroller o Controller cores & SW Stack(s) CPU & RAM • CPUs Ethernet Stack • RAM • Flash Ethernet MAC o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) Transmit Receive DMAs/Queues DMAs/Queues • Queues for sending & receiving • Shapers in the transmit path Credit Based Address & Tag Shaper Filters • Filters in the receive path • Time stamping units for 802.1AS 802.1AS 802.1AS
o MII interface to / from PHY MII • MII interface for data transfer • MDC/MDIO interface for PHY control & status MII o PHY PCS/PMA PLCA PCS/PMA • PCS/PMA logic (IEEE 802.3) Analog FE PCS: Physical Coding Sublayer • PLCA collision avoidance 10Base-T1S PHY PMA: Physical Medium Attachment • Analog front end PLCA: Physical Layer Collision Avoidance
2021-06-15 9 Evaluation Kit 10Base-T1S Data Flow through Functional Building Blocks AURIX™ Microcontroller o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) MICROSAR • Queues for sending & receiving Ethernet Stack Transceiver Driver • Shapers in the transmit path • Filters in the receive path • Time stamping units for 802.1AS DMAs DMAs Queues Queues o MII interface to / from PHY • MII interface for data transfer Shaper Filters • MDC/MDIO interface for PHY control & status
Ethernet MAC 802.1AS 802.1AS MDC/MDIO o PHY • PCS/PMA logic (IEEE 802.3) MII • PLCA collision avoidance • Analog front end MII PCS/PMA PLCA PCS/PMA Analog FE 10Base-T1S PHY
2 10 Evaluation Kit 10Base-T1S Data Flow through Functional Building Blocks AURIX™ Microcontroller o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) MICROSAR • Queues for sending & receiving Ethernet Stack Transceiver Driver • Shapers in the transmit path • Filters in the receive path • Time stamping units for 802.1AS DMAs DMAs Queues Queues o MII interface to / from PHY • MII interface for data transfer Shaper Filters • MDC/MDIO interface for PHY control & status
Ethernet MAC 802.1AS 802.1AS MDC/MDIO o PHY • PCS/PMA logic (IEEE 802.3) MII • PLCA collision avoidance • Analog front end MII PCS/PMA PLCA PCS/PMA Analog FE 10Base-T1S PHY
2 11 Evaluation Kit 10Base-T1S Data Flow through Functional Building Blocks AURIX™ Microcontroller o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) MICROSAR • Queues for sending & receiving Ethernet Stack Transceiver Driver • Shapers in the transmit path • Filters in the receive path • Time stamping units for 802.1AS DMAs DMAs Queues Queues o MII interface to / from PHY • MII interface for data transfer Shaper Filters • MDC/MDIO interface for PHY control & status
Ethernet MAC 802.1AS 802.1AS MDC/MDIO o PHY • PCS/PMA logic (IEEE 802.3) MII • PLCA collision avoidance • Analog front end MII PCS/PMA PLCA PCS/PMA Analog FE 10Base-T1S PHY
2 12 Evaluation Kit 10Base-T1S Data Flow through Functional Building Blocks AURIX™ Microcontroller o Ethernet MAC (10MBaud / 100MBaud / 1GBaud) MICROSAR • Queues for sending & receiving Ethernet Stack Transceiver Driver • Shapers in the transmit path • Filters in the receive path • Time stamping units for 802.1AS DMAs DMAs Queues Queues o MII interface to / from PHY • MII interface for data transfer Shaper Filters • MDC/MDIO interface for PHY control & status
Ethernet MAC 802.1AS 802.1AS MDC/MDIO o PHY • PCS/PMA logic (IEEE 802.3) MII • PLCA collision avoidance • Analog front end MII PCS/PMA PLCA PCS/PMA Analog FE 10Base-T1S PHY
2 13 Evaluation Kit 10Base-T1S Controller / PHY Interface Microcontroller o MII Transmit direction MII
• Data lines TXD • Transmit enable and error TX_EN, TX_ER • Transmit clock TX_CLK TX_CLKTX_ER TX_EN TXD0..TXD3 • For 10Base-T1S the transmit clock runs at 2.5MHz MII 10Base-T1S PHY
o MII Receive direction Microcontroller • Data lines RXD MII • Receive data available and error RX_DV, RX_ER • Reveive clock RX_CLK • For 10Base-T1S the receive clock runs at 2.5MHz RX_CLKRX_ER RX_DV RXD0..RXD3
MII 10Base-T1S PHY
2021-06-15 14 Evaluation Kit 10Base-T1S Controller / PHY Interface
o Data flow control
• Half duplex signals COL & CRS Microcontroller • PHY pushes back MAC transmitting data if the media (cable) is not available MII
• For 10Base-T1S the PHY PLCA logic uses the signals to hold the MAC • The PHY PLCA logic releases the MAC if the transmit opportunity window is valid COL CRS
MII 10Base-T1S PHY
2021-06-15 15 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Power over Data Line (PoDL) PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Common mode choke PoDL
o Stubs
Connector to wires
2021-06-15 16 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Power over Data Line (PoDL) PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Common mode choke PoDL
o Stubs
Connector to wires
2021-06-15 17 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Power over Data Line (PoDL) PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Common mode choke PoDL
o Stubs
Connector to wires
2021-06-15 18 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Common mode choke PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Power over Data Line (PoDL) PoDL
o Stubs
Connector to wires
2021-06-15 19 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Common mode choke PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Power over Data Line (PoDL) PoDL
o Stubs
Connector to wires
2021-06-15 20 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Common mode choke PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Power over Data Line (PoDL) PoDL
o Stubs
Connector to wires
2021-06-15 21 Evaluation Kit 10Base-T1S Building Blocks PHY Board
o Connectors Connector to AURIX Board
• Interface to AURIX controller MII
• Interface to medium (wires) MDC MDIO
o 10Base-T1S PHY MII PCS/PMA PLCA PCS/PMA o Common mode choke PHY Analog FE
o Capacitors for AC coupling Choke PHY Board o Power over Data Line (PoDL) PoDL
o Stubs
Connector to wires
2021-06-15 22 Evaluation Kit 10Base-T1S System Configuration Example Central power supply
o Daisy chain configuration PHY Board Connector AURIX™ Board o Stubs location in the middle PHY AURIX™
PoDL MII Connector
Power over Data Line (PoDL) Connector o Power and data PHY Board Connector AURIX™ Board PHY AURIX™
PoDL MII Connector Power Connector and data PHY Board Connector AURIX™ Board PHY AURIX™ MII PoDL Connector Connector
2021-06-15 23 10Base-T1S Standardization Overview (as of begin of 2021)
Microcontroller
Ethernet › SW components for PLCA: AutoSAR AutoSAR Driver & Stack
Ethernet › PLCA: IEEE 802.3cg, Clause 148 IEEE 802.3cg PLCA-MAC Interface › SPI interface MAC to PHY: OPEN TC6/TC14 JWG › Analog PHY interface MAC to PHY: OPEN TC14 OPEN TC6 / TC14 › MII interface: IEEE Standard Interface
› 10Base-T1S: IEEE 802.3cg, Clause 147 IEEE 802.3cg Ethernet 10Base-T1S PHY › Test suite 10Base-T1S: OPEN TC14 OPEN TC14 10Base-T1S › EPL*: IEEE 802.3cg, Clause 147 IEEE 802.3cg › Extended functionalities (diagnosis etc.) OPEN TC14 To / from Bus *EPL: Electrical Physical Layer *PLCA: Physical Layer Collision Avoidance
2021-06-15 24 For more information about Vector and our products please visit
www.vector.com
Author: Nöbauer, Josef Vector Germany Zweck, Harald Infineon
8 © 2021. Vector Informatik GmbH. All rights reserved. Any distribution or copying is subject to prior written approval by Vector. V1.1 | 2021-06-11