DOCSLIB.ORG

Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) www.ti.com Table of Contents Application Report Ethernet PHY Configuration Using MDIO for Industrial Applications Garrett Ding, Pratheesh Gangadhar TK, David Zaucha ABSTRACT As a bridge of the link layer device medium access controller (MAC) and physical medium such as copper cable, the Ethernet physical layer device (PHY) integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. Proper PHY configuration using management data input/output (MDIO) is fundamental during the prototype stage, and also crucial to meeting the requirements of lowest deterministic latency and fastest link detection in industrial Ethernet applications such as EtherCAT®. This application report provides guidance on the Ethernet PHY configuration using the MDIO module within the Programmable-Realtime Unit Industrial Communications Sub-System (PRU-ICSS) in the Sitara™ device from TI, for industrial applications, by dissecting the PHY DP83822 configuration in EtherCAT on the AMIC110 Industrial Communications Engine (ICE). The goal of this application report is to expedite the development of industrial Ethernet applications on custom boards with migration and troubleshooting guides for the PHYs [1] [2] [3]. Table of Contents 1 PHY Selection and Connection............................................................................................................................................. 2 2 PHY Reset and Address.........................................................................................................................................................4 3 PHY Speed, Duplex, and More...............................................................................................................................................6 4 Enhanced Link Detection.....................................................................................................................................................10 5 Add PHYs in Processor SDK............................................................................................................................................... 14 6 Conclusion............................................................................................................................................................................ 16 7 References............................................................................................................................................................................ 16 8 Revision History................................................................................................................................................................... 17 List of Figures Figure 1-1. Ethernet PHY Connection With MAC and Physical Medium.....................................................................................2 Figure 1-2. DP83822 Functional Block Diagram......................................................................................................................... 3 Figure 2-1. PHY Reset Signal......................................................................................................................................................4 Figure 3-1. MDIO Registers in Code Composer Studio...............................................................................................................9 Figure 5-1. Board Library in PDK...............................................................................................................................................14 Figure 5-2. AMIC110 ICE Board Library.................................................................................................................................... 15 Figure 5-3. Adding New Board and PHY................................................................................................................................... 16 List of Tables Table 2-1. PHY Reset Control Register (PHYRCR).....................................................................................................................5 Table 3-1. MDIOUSERACCESS0 Register Field Descriptions....................................................................................................8 Table 4-1. LEDs Configuration Register 1 (LEDCFG1)..............................................................................................................11 Table 4-2. PHY Registers in EtherCAT...................................................................................................................................... 13 Table 4-3. Data Link Status Register in EtherCAT.....................................................................................................................13 Trademarks Sitara™ and Code Composer Studio™ are trademarks of Texas Instruments. Cortex™ is a trademark of ARM Limited. EtherCAT® is a registered trademark of Beckhoff Automation GmbH. ARM® is a registered trademark of ARM Limited. All trademarks are the property of their respective owners. SPRACC8A – DECEMBER 2017 – REVISED MAY 2021 Ethernet PHY Configuration Using MDIO for Industrial Applications 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated PHY Selection and Connection www.ti.com 1 PHY Selection and Connection Many industrial Ethernet applications require PHY to comply with IEEE 802.3 100BaseTX or 100BaseFX, support 100-Mbps full-duplex links, use auto-negotiation, and support MDI/MDI-X auto-crossover in 100BaseTX mode. Moreover, link loss reaction time is also a key benchmark to ensure that link sensitivity is faster than 15 µs for redundancy operation. Although most PHYs support several media-independent interfaces with different pin counts and data rates to communicate with the MAC, the MII is recommended, because it reduces the additional forwarding delay caused by the TX FIFO in RMII. Figure 1-1 shows a typical Ethernet PHY connection with MAC and physical medium. MII DP83822 MAC 10/100 Mbps Magnetics RJ-45 pr1_mii0_rxlink Ethernet PHY 25 MHz/50 MHz Status LEDs Clock Source Copyright © 2017, Texas Instruments Incorporated Figure 1-1. Ethernet PHY Connection With MAC and Physical Medium The AMIC110 Industrial Communications Engine (ICE) is a development platform targeted for industrial communications and industrial Ethernet in particular. The AMIC110 ICE is the Sitara AMIC110 System-on-Chip (SoC) that features the ARM® Cortex™-A8 processor, with the PRU-ICSS, which enables the integration of real-time industrial protocols, without needing ASIC or FPGA. The power-saving DP83822 device (see Figure 1-2) was selected in the AMIC110 ICE. The DP83822 not only meets the requirements of IEEE 802.3u, but also maintains high margins in terms of cross-talk and alien noise. The DP83822 device is a fully featured, single-port Physical Layer transceiver for 10BASE-Te, 100BASE-TX, and 100BASE-FX signaling, and its signals fall into the following categories: • MAC interface • Serial management interface • Clock interface • GPIO and LED interface • Media-dependent interface • Power and ground pins • Other pins 2 Ethernet PHY Configuration Using MDIO for Industrial Applications SPRACC8A – DECEMBER 2017 – REVISED MAY 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com PHY Selection and Connection MII / RGMII Option RMII Option Serial Serial Management Management TX_CLK TX_EN / TX_CTRL TX_D[3:0] MDIO MDC COL CRS / CRS_DV RX_ER RX_DVRX_CTRL / RX_D[3:0] RX_CLK TX_EN TX_D[3:0] CRS / RX_DV RX_ER RX_DV (optional) RX_D[3:0] MDIO MDC MII / RGMII / RMII Interface TX RX TX_CLK RX_CLK Data Data MII 10BASE-Te Registers 10BASE-Te and and 100BASE-TX/FX 100BASE-TX/FX Auto-Negotiation Wake-on-LAN Energy Efficient Ethernet Transmit Block Clock Receive Block Generation DAC ADC BIST LED Cable Diagnostics Auto-MDIX Driver Reference TD± RD± LEDs Clock Figure 1-2. DP83822 Functional Block Diagram Beckhoff provides a comprehensive PHY selection guide to assist in PHY selection and configuration[1]. This document lists a variety of PHYs from TI, such as the DP836x, DP838x, TLK10x, and TLK11x. SPRACC8A – DECEMBER 2017 – REVISED MAY 2021 Ethernet PHY Configuration Using MDIO for Industrial Applications 3 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated PHY Reset and Address www.ti.com 2 PHY Reset and Address PHY bootstrap configurations, which place the device into the desired operation mode, are performed at power up or hardware reset. A hardware reset is accomplished by applying a low pulse, with a duration of at least 10 µs (T1), to the RESET pin in the DP83822 PHY. This pulse resets the device so that all registers are reinitialized to default values, and the hardware configuration values are relatched into the device (see Figure 2-1). T1 Hardware RESET_N Figure 2-1. PHY Reset Signal Because the bootstrap pins have alternative functions after the reset is deasserted, to minimize interference during bootstrap pin signal sampling the PRU-ICSS MII multiplexing should not occur until after the PHY RESET is released on the AMIC110 ICE. If these bootstrap pins are not configured, they will be GPIO and High-Z as soon as the reset is released. The hardware reset sequence implementation in the TI EtherCAT looks as follows: Board_init(BOARD_INIT_MODULE_CLOCK); Board_phyReset(2); /* mux PRU MII after PHY reset in case PRU drives signals * on the pins and interfere with the PHY bootstrap configurations */ #ifdef ENABLE_UART_PRINT Board_init(BOARD_INIT_UART_STDIO|BOARD_INIT_ICSS_PINMUX); #else Board_init(BOARD_INIT_ICSS_PINMUX);
Load more

Recommended publications
  • 10BASE-T1S Learn to Run Supported by Embedded Software
    10BASE-T1S Learn To Run Supported by Embedded Software V1.1 | 2021-06-11 Agenda 1. All IP Car 2. Extensions in AUTOSAR 3. Areas of Investigation 4. Evaluation SW Setup Based on the Infineon Evaluation Kit 2 All IP Car 10BASE-T1S as Replacement for Lower Bandwidth Networks IP as well-known common “language” proven in use technology enabler for E/E architecture trends and service-based communication and Ethernet is the naturally associated Network Access Layer 3 All IP Car Introducing an Additional Network Access Layer It’s more than just physical layer compliance The digital eco-system must be “ready” Tools, data models and databases SW AUTOSAR … 4 Extensions in AUTOSAR 10BASE-T1S Within AUTOSAR Classic Platform 10BASE-T1S was introduced as new concept in R20-11 Further refinement is currently ongoing within AUTOSAR It’s Ethernet the upper layer stack remains untouched Utilize the benefits of the strictly layered architecture Encapsulate the changes in the MCAL layer Ethernet Driver Ethernet Switch Driver Ethernet Transceiver Driver Eth EthSwt EthTrcv 5 Areas of Investigation Extension of the Existing MICROSAR Solution Ethernet Transceiver Driver Ethernet Driver 10BASE-T1S specific initializations Depending on actual Transceiver device Timeline is depending on documentation and device availability Diagnostic Interface Error and State Management Transmit Buffer Management 6 Evaluation SW Setup Based on the Infineon Evaluation Kit Specific SIP – Software Integration Package Fixed Compile Environment Infineon TriBoard
    [Show full text]
  • Physical Layer Compliance Testing for 1000BASE-T Ethernet
    Physical Layer Compliance Testing for 1000BASE-T Ethernet –– APPLICATION NOTE Physical Layer Compliance Testing for 1000BASE-T Ethernet APPLICATION NOTE Engineers designing or validating the 1000BASE-T Ethernet 1000BASE-T Physical Layer physical layer on their products need to perform a wide range Compliance Standards of tests, quickly, reliably and efficiently. This application note describes the tests that ensure validation, the challenges To ensure reliable information transmission over a network, faced while testing multi-level signals, and how oscilloscope- industry standards specify requirements for the network’s resident test software enables significant efficiency physical layer. The IEEE 802.3 standard defines an array of improvements with its wide range of tests, including return compliance tests for 1000BASE-T physical layer. These tests loss, fast validation cycles, and high reliability. are performed by placing the device under test in test modes specified in the standard. The Basics of 1000BASE-T Testing While it is recommended to perform as many tests as Popularly known as Gigabit Ethernet, 1000BASE-T has been possible, the following core tests are critical for compliance: experiencing rapid growth. With only minimal changes to IEEE 802.3 Test Mode Test the legacy cable structure, it offers 100 times faster data Reference rates than 10BASE-T Ethernet signals. Gigabit Ethernet, in Peak 40.6.1.2.1 combination with Fast Ethernet and switched Ethernet, offers Test Mode-1 Droof 40.6.1.2.2 Template 40.6.1.2.3 a cost-effective alternative to slow networks. Test Mode-2 Master Jitter 40.6.1.2.5 Test Mode-3 Slave Jitter 1000BASE-T uses four signal pairs for full-duplex Distortion 40.6.1.2.4 transmission and reception over CAT-5 balanced cabling.
    [Show full text]
  • Wifire: Medium Access Control (MAC) and Physical Layer (PHY) Specifications
    WiFiRe Specifications, Aug 2006 draft Broadband Wireless for Rural Areas -- WiFiRe : Medium Access Control (MAC) and Physical Layer (PHY) Specifications Release 2006 (This document is - Aug 2006 draft) Center of Excellence in Wireless Technology (CEWiT) 1 Copyright © 2006 CEWiT, Some rights reserved WiFiRe Specifications, Aug 2006 draft About CEWiT The Centre of Excellence in Wireless Technology (CEWiT), India , has been set up under a public-private initiative with the mission of making India a leader in the research, development and deployment of wireless technology. It is an autonomous institution temporarily headquartered at IIT Madras. Broadband wireless technology has great potential in the coming years. Emerging standards can be leveraged to build a system that specifically meets India’s broadband access needs. CEWiT will play a pro-active role in engaging with academic and industry research groups in India to focus research on areas with strong potential. CEWiT will also foster collaboration with similar efforts worldwide. CEWiT seeks to actively participate in International standards bodies, and to assist government and public institutions in policy-making, spectrum management and regulation. CEWiT Std, WiFiRe, 2006 Edition CEWiT standards are developed within the Technical Committees of CEWiT. Members of the committees serve voluntarily and without any compensation. The standards developed within CEWiT represent a consensus of the broad expertise of the subject. The existence of a CEWiT standard does not imply that there are no other ways to provide services related to the scope of the standard. Furthermore, a standard is subject to change brought about through developments in the state of the art and comments received from the users of the standard.
    [Show full text]
  • Structure of IEEE 802.11 Packets at Various Physical Layers
    Appendix A: Structure of IEEE 802.11 Packets at Various Physical Layers This appendix gives a detailed description of the structure of packets in IEEE 802.11 for the different physical layers. 1. Packet Format of Frequency Hopping Spread-spectrum Physical Layer (FHSS PHY) The packet is made up of the following elements (Figure A.1): 1.1 Preamble It depends on the physical layer and includes: – Synch: a sequence of 80 bits alterning 0 and 1, used by the physical circuits to select the correct antenna (if more than one are in use), and correct offsets of frequency and synchronization. – SFD: start frame delimiter consists of a pattern of 16 bits: 0000 1100 1011 1101, used to define the beginning of the frame. 1.2 Physical Layer Convergence Protocol Header The Physical Layer Convergence Protocol (PLCP) header is always transmitted at 1 Mbps and carries some logical information used by the physical layer to decode the frame: – Length of word of PLCP PDU (PLW): representing the number of bytes in the packet, useful to the physical layer to detect correctly the end of the packet. – Flag of signalization PLCP (PSF): indicating the supported rate going from 1 to 4.5 Mbps with steps of 0.5 Mbps. Even though the standard gives the combinations of bits for PSF (see Table A.1) to support eight different rates, only the modulations for 1 and 2 Mbps have been defined. – Control error field (HEC): CRC field for error detection of 16 bits (or 32 bits). The polynomial generator used is G(x)=x16 + x12 + x5 +1.
    [Show full text]
  • Embedded Ethernet Solutions
    Embedded Ethernet Solutions Gautam Kotwal © 2006 Microchip Technology Incorporated. All Rights Reserved. WebSeminar Title Slide 1 Hello and welcome to today’s Ethernet Webinar. My name is Gautam Kotwal, product marketing manager for Microchip Technology. Today our discussion will focus on embedded Ethernet solutions from Microchip Technology. 1 Agenda Why Ethernet Networking with Ethernet Markets Ethernet Portfolio Software Library – TCP/IP stack Development Tools Summary © 2006 Microchip Technology Incorporated. All Rights Reserved. WebSeminar Title Slide 2 The agenda for today’s presentation, I will discuss the needs of Ethernet, networking with Ethernet, potential markets, Microchip’s Ethernet portfolio, software library and development tools. 2 Why Ethernet? • Ethernet is the most widely deployed network in offices and industrial buildings • Ethernet’s infrastructure, interoperability and scalability ensure ease of development • Once equipment is connected to a Ethernet network, it can be monitored or controlled through the Internet • Low Latency – “Real Time” Remote Delivery © 2006 Microchip Technology Incorporated. All Rights Reserved. WebSeminar Title Slide 3 So why would you want to choose Ethernet? 1. Ethernet is the most widely deployed network in offices and industrial buildings. Thus Ethernet is ubiquitous. 2. Ethernet is based on standards (IEEE802.3) that ensure reliability of network connections and data transmission. This ensures interoperability 3. Ethernet networks are scalable from the simplest to most complex networks or up to 2^48 network nodes 4. Once equipment is connected to a Ethernet network, it can be monitored or controlled through the Internet removing any distance barrier that may have inhibited remote communication previously. 3 Networking with Ethernet Monitor, control or access devices over internet using Ethernet Controllers Internet Ethernet Controller Buffer Ethernet PIC MCU Local Bus Ethernet MAC Ethernet PHY © 2006 Microchip Technology Incorporated.
    [Show full text]
  • KSZ8081MNX/RNB Data Sheet
    KSZ8081MNX/RNB 10BASE-T/100BASE-TX Physical Layer Transceiver Features Applications • Single-chip 10Base-T/100Base-TX IEEE 802.3 • Game console compliant Ethernet transceiver • IP phone • MII interface support (KSZ8081MNX) • IP set-top box • RMII v1.2 Interface support with a 50 MHz refer- •IP TV ence clock output to MAC, and an option to input •LOM a 50 MHz reference clock (KSZ8081RNB) • Printer • Back-to-back mode support for a 100 Mbps copper repeater • MDC/MDIO management interface for PHY register configuration • Programmable interrupt output • LED outputs for link, activity, and speed status indication • On-chip termination resistors for the differential pairs • Baseline wander correction • HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option • Auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full) • Power-down and power-saving modes • LinkMD TDR-based cable diagnostics to identify faulty copper cabling • Parametric NAND Tree support for fault detection between chip I/Os and the board • HBM ESD rating (6 kV) • Loopback modes for diagnostics • Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V • Built-in 1.2V regulator for core • Available in 32-pin (5 mm × 5 mm) QFN package 2016-2018 Microchip Technology Inc. DS00002202C-page 1 KSZ8081MNX/RNB TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs.
    [Show full text]
  • Ethernet Explained
    Technical Note TN_157 Ethernet Explained Version 1.0 Issue Date: 2015-03-23 The FTDI FT900 32 bit MCU series, provides for high data rate, computationally intensive data transfers. One of the interfaces used for this high speed communication is Ethernet. This application note discusses some of the key features of an Ethernet link and how the FT900 assists in establishing the link. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold FTDI harmless from any and all damages, claims, suits or expense resulting from such use. Future Technology Devices International Limited (FTDI) Unit 1, 2 Seaward Place, Glasgow G41 1HH, United Kingdom Tel.: +44 (0) 141 429 2777 Fax: + 44 (0) 141 429 2758 Web Site: http://ftdichip.com Copyright © 2015 Future Technology Devices International Limited Technical Note TN_157 Ethernet Explained Version 1.0 Document Reference No.: FT_001105 Clearance No.: FTDI# 442 Table of Contents 1 Introduction .................................................................................................................................... 3 1.1 Scope ....................................................................................................................................... 3 2 What is Ethernet? ........................................................................................................................... 4 2.1 Speeds ....................................................................................................................................
    [Show full text]
  • Industrial Ethernet PHY Datasheet
    TLK100 www.ti.com SLLS931B–AUGUST 2009–REVISED DECEMBER 2009 Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Check for Samples: TLK100 1 Introduction 1.1 Features 1 • Temperature From –40°C to 85°C • Bus I/O Protection - ±16kV JEDEC HBM • Low Power Consumption, < 200mW Typical • IEEE 802.3u PCS, 100BASE-TX Transceivers • Cable Diagnostics • Enables IEEE1588 Time-Stamping • Error-Free Operation up to 200 Meters Under • IEEE 1149.1 JTAG Typical Conditions • Integrated ANSI X3.263 Compliant TP-PMD • 3.3V MAC Interface Physical Sublayer with Adaptive Equalization • Auto-MDIX for 10/100 Mb/s and Baseline Wander Compensation • Energy Detection Mode • Programmable LED Support Link, 10/100 Mb/s • 25 MHz Clock Out Mode, Activity, and Collision Detect • MII Serial Management Interface (MDC and • 10/100 Mb/s Packet BIST (Built in Self Test) MDIO) • 48-pin TQFP Package (7mm) × (7mm) • IEEE 802.3u MII • IEEE 802.3u Auto-Negotiation and Parallel 1.2 Applications Detection • Industrial Controls and Factory Automation • IEEE 802.3u ENDEC, 10BASE-T • General Embedded Applications Transceivers and Filters 1.3 General Description The TLK100 is a single-port Ethernet PHY for 10BaseT and 100Base TX signaling. It integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. This device supports the standard Media Independent Interface (MII) for direct connection to a Media Access Controller (MAC). The TLK100 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V, 1.8V, and 1.1V power supplies for reduced power operation.
    [Show full text]
  • MPC5606EPB: MPC5606E Microcontroller Product Brief
    Freescale Semiconductor Document Number: MPC5606EPB Product Brief Rev. 2, 08/2014 MPC5606E Microcontroller Product Brief The MPC5606E microcontroller is the newer member of Contents the Qorivva 32-bit microcontroller family built on Power 1 Block diagrams . 2 Architecture(R) technology and integrates MPC5604E 1.1 MPC5604E block diagram. 2 1.2 BMC89810 block diagram . 5 device with the Broadcom(R) BCM89810 single-port 2 Application examples . 6 BroadR-Reach™ 100 Mbps automotive Ethernet 2.1 CMOS vision sensor gateway . 6 2.2 Audio source gateway . 10 transceiver. This device is targeted at the chassis and 2.3 Low cost audio output gateway . 12 safety market segment visual-based driver assistance, 2.4 High quality audio output gateway. 14 especially the CMOS Vision Sensor Gateway, Radar 2.5 RADAR to Ethernet gateway . 16 3 Features . 18 Sensor Gateway, and Infotainment Network Gateway. 3.1 BMC89810 architectural features . 18 3.2 MPC5606E feature summary . 18 The MPC5606E microcontroller is a gateway system 3.3 Critical performance parameters . 19 designed to move data from different sources via 3.4 Module feature list . 19 4 Developer environment . 32 Ethernet to a receiving system and vice versa. The 4.1 Software tools summary . 32 supported data sources and sinks are: 4.2 Application summary . 33 5 Package Information . 33 • Video data (with 8/10/12 bits per data word) • Audio data (6 stereo channels) • RADAR data (2 12 bit with <1s per sample, digitized externally and read in via DSPI) • Other serial communication interfaces including FlexCAN, LINFlex, and DSPI © 2014 Freescale Semiconductor, Inc. Block diagrams The Ethernet has a bandwidth of 10/100 Mbits/sec supporting precision time stamps (IEEE1588).
    [Show full text]
  • Ethernet Theory of Operation
    AN1120 Ethernet Theory of Operation Author: M. Simmons However, with ubiquitous deployment, internet Microchip Technology Inc. connectivity, high data rates and limitless range expansibility, Ethernet can accommodate nearly all wired communications requirements. Potential INTRODUCTION applications include: This document specifies the theory and operation of • Remote sensing and monitoring the Ethernet technology found in PIC® MCUs with • Remote command, control and firmware updating integrated Ethernet and in stand-alone Ethernet • Bulk data transfer controllers. • Live streaming audio, video and media • Public data acquisition (date/time, stock quotes, Ethernet technology contains acronyms and terms news releases, etc.) defined in Table 1. THEORY OF OPERATION APPLICATIONS Ethernet is a data link and physical layer protocol Ethernet is an asynchronous Carrier Sense Multiple defined by the IEEE 802.3™ specification. It comes in Access with Collision Detect (CSMA/CD) many flavors, defined by maximum bit rate, mode of protocol/interface, with a payload size of 46-1500 octets. transmission and physical transmission medium. With data rates of tens to hundreds of megabits/second, it is generally not well suited for low-power applications. • Maximum Bit Rate (Mbits/s): 10, 100, 1000, etc. • Mode of Transmission: Broadband, Baseband • Physical Transmission Medium: Coax, Fiber, UTP, etc. TABLE 1: ETHERNET GLOSSARY Term Definition CRC Cyclic Redundancy Check: Type of checksum algorithm used when computing the FCS for all Ethernet frames and the hash table key for hash table filtering of receive packets. DA Destination Address: The 6-octet destination address field of an Ethernet frame. ESD End-of-Stream Delimiter: In 100 Mb/s operation, the ESD is transmitted after the FCS (during the inter-frame gap) to denote the end of the frame.
    [Show full text]
  • Single Chip Microcontroller
    AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Features Product Brief Supports Suspend mode and Remote Wakeup via Single chip USB 2.0 to 10/100M Fast Ethernet controller – Link-up, Magic packet, MS wakeup frame and external AX88772A pin Single chip USB 2.0 to MII, single chip MII to Ethernet and Optional PHY power down during Suspend mode USB Bridging controller in Dual-PHY mode (US Patent Pending) – AX88172A Versatile External Media Interface Optional MII interface in MAC mode allows AX88172A USB Device Interface to work with external 100BASE-FX Ethernet PHY or Integrates on-chip USB 2.0 transceiver and SIE HomePNA PHY compliant to USB Spec 1.1 and 2.0 Optional Reverse-MII or Reverse-RMII interface in Supports USB Full and High Speed modes with PHY mode allows AX88172A to work with external Bus-Power or Self-Power capability HomePlug PHY or glueless MAC-to-MAC connections Supports 4 or 6 programmable endpoints on USB Optional Reverse-MII interface in Dual-PHY mode (US interface Patent Pending) allows AX88172A to act as an Ethernet High performance packet transfer rate over USB bus PHY or USB 2.0 PHY for external MAC device that using proprietary burst transfer mechanism (US Patent needs Ethernet and USB in system application Approval) Supports USB to Ethernet bridging or vice versa in Supports 256/512 bytes (93c56/93c66) of serial EEPROM hardware (for storing USB Descriptors) Supports automatic loading of Ethernet ID, USB Fast Ethernet Controller Descriptors and Adapter Configuration from EEPROM after Integrates
    [Show full text]
  • 10BASE-T/100BASE-TX Physical Layer Transceiver
    KSZ8081MLX 10BASE-T/100BASE-TX Physical Layer Transceiver Features Target Applications • Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 • Game Consoles Compliant Ethernet Transceiver • IP Phones • MII Interface Support • IP Set-Top Boxes • Back-to-Back Mode Support for a 100 Mbps Cop- •IP TVs per Repeater •LOM • MDC/MDIO Management Interface for PHY Reg- • Printers ister Configuration • Programmable Interrupt Output • LED Outputs for Link and Activity Status Indica- tion • On-Chip Termination Resistors for the Differential Pairs • Baseline Wander Correction • HP Auto MDI/MDI-X to Reliably Detect and Cor- rect Straight-Through and Crossover Cable Con- nections with Disable and Enable Option • Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full) • Power-Down and Power-Saving Modes • LinkMD® TDR-Based Cable Diagnostics to Iden- tify Faulty Copper Cabling • Parametric NAND Tree Support for Fault Detec- tion Between Chip I/Os and the Board • HBM ESD Rating (6 kV) • Loopback Modes for Diagnostics • Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V • Built-In 1.2V Regulator for Core • Available in 48-pin 7 mm x 7 mm LQFP Package 2018 Microchip Technology Inc. DS00002264B-page 1 KSZ8081MLX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
    [Show full text]