Error Handling and Energy Estimation for Error Resilient Near-Threshold Computing Rengarajan Ragavan

Error handling and energy estimation for error resilient near-threshold computing Rengarajan Ragavan To cite this version: Rengarajan Ragavan. Error handling and energy estimation for error resilient near-threshold computing. Hardware Architecture [cs.AR]. Université Rennes 1, 2017. English. NNT : 2017REN1S038. tel-01654476 HAL Id: tel-01654476 https://tel.archives-ouvertes.fr/tel-01654476 Submitted on 4 Dec 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. No d’ordre : ANNÉE 2017 THÈSE / UNIVERSITÉ DE RENNES 1 sous le sceau de l’Université Bretagne Loire pour le grade de DOCTEUR DE L’UNIVERSITÉ DE RENNES 1 Mention : Traitement du Signal et Télécommunications École doctorale MATISSE présentée par Rengarajan RAGAVAN préparée à l’unité de recherche UMR6074 IRISA Institut de recherche en informatique et systèmes aléatoires - CAIRN École Nationale Supérieure des Sciences Appliquées et de Technologie Thèse soutenue à Lannion le 22 septembre 2017 devant le jury composé de : Edith BEIGNÉ Error Handling and Directrice de Recherche à CEA Leti / rapporteur Energy Estimation Patrick GIRARD Directrice de Recherche à CNRS, LIRMM / rapporteur Framework For Lorena ANGHEL Error Resilient Professeur à Grenoble INP, TIMA / examinateur Daniel MÉNARD Near-Threshold Professeur à INSA Rennes, IETR / examinateur Olivier SENTIEYS Computing Professeur à l’Université de Rennes 1 / directeur de thèse Cédric KILLIAN Maître de Conférences à l’Université de Rennes 1 / co-directeur de thèse To My Parents, My Brother, and My Teachers iii Acknowledgements I sincerely express my gratitude to my thesis supervisor Prof. Olivier Sentieys who gave me the opportunity to work him in prestigious INRIA/IRISA labs. His guidance and confidence in me gave extra boost and cultivated more interest in me to do this research work in a better way. His feedback and comments refined the quality of my research contributions and this thesis dissertation. I am very grateful to my thesis co-supervisor Dr. CédricKillian for his encour- agement and support. He was inspirational to me throughout my Ph.D. tenure. His suggestions and critical evaluation helped me to innovatively address various bottlenecks in this thesis work. I register my special thanks to Cédricfor his efforts in translating the long abstract of this thesis to French. I would like to thank my colleague Philippe Quémerais,Research Engineer, IRISA labs for his extensive support in configuring and tutoring various CAD tools. I acknowl- edge my fellow research student Benjamin Barrois for his help in modelling approximate arithmetic operators. I'm thankful to Mme. Laurence Gallas for her French lessons that helped me a lot during my stay in Lannion. Also, I would like to thank all the faculty members, researchers, and colleagues of ENSSAT who made my stay in Lannion most cherishable. This thesis work has seen the light of the day thanks to Universitéde Rennes 1, and IRISA laboratory for funding and facilitating this thesis work. Thanks are due to Nadia, Joelle, and Angelique for their support in administrative matters and during my missions abroad. I also express my gratitude to the entire jury panel for reading my thesis dissertation and taking part in the thesis defense. Also, special thanks to the reviewers for their valuable review comments that improved the quality of this dissertation. I offer my sincere thanks to all my friends and well-wishers who were supporting me all these years and looking for my betterment. Last but not least, I express my everlasting gratitude to my parents, my brother and almighty without them I cannot be what I am today. 10th October 2017 Rengarajan Lannion, France v Abstract Advancement in CMOS IC technology has improved the way in which integrated circuits are designed and fabricated over decades. Scaling down the size of transistors from micrometers to few nanometers has given the capability to place more tinier transistors in a unit of chip area that upheld Moore's law over the years. On the other hand, feature size scaling imposed various challenges like physical, material, power-thermal, technological, and economical that hinder the trend of scaling. To improve energy efficiency, Dynamic Voltage Scaling (DVS) is employed in most of the Ultra-Low Power (ULP) designs. In near-threshold region (NTR), the supply voltage of the transistor is slightly more than the threshold voltage of the transistor. In this region, the delay and energy both are roughly linear with the supply voltage. The Ion/Ioff ratio is higher compared to the sub-threshold region, which improves the speed and minimizes the leakage. Due to the reduced supply voltage, the circuits operating in NTR can achieve a 10× reduction in energy per operation at the cost of the same magnitude of reduction in the operating frequency. In the present trend of sub-nanometer designs, inherent low-leakage technologies like FD-SOI (Fully Depleted Silicon On Insulator), enhance the benefits of voltage scaling by utilizing techniques like Back-Biasing. However reduction in Vdd augments the impact of variability and timing errors in sub-nanometer designs. The main objective of this work is to handle timing errors and to formulate a framework to estimate energy consumption of error resilient applications in the context of near-threshold computing. It is highly beneficial to design a digital system by taking advantage of NTR, DVS, and FD-SOI. In spite of the advantages, the impact of variability and timing errors outweighs the above-mentioned benefits. There are existing methods that can predict and prevent errors, or detect and correct errors. But there is a need for a unified approach to handle timing errors in the near-threshold regime. In this thesis, Dynamic Speculation based error detection and correction is explored in the context of adaptive voltage and clock overscaling. Apart from error detection and correction, some errors can also be tolerated or, in other words, circuits can be pushed beyond their limits to compute incorrectly to achieve higher energy efficiency. The proposed error detection and correction method achieves 71% overclocking with 2% additional hardware cost. This work involves extensive study of design at gate level to understand the behaviour of gates under overscaling of supply voltage, bias voltage and clock frequency (collectively called as operating triads). A bottom-up approach is taken: by studying trends of energy vs. error of basic arithmetic operators at transistor level. Based on profiling of the arithmetic operators, a tool flow is formulated to estimate energy and error metrics for different operating triads. We achieve maximum energy efficiency of 89% for arithmetic operators like 8-bit and 16-bit adders at the cost of 20% faulty bits by operating in NTR. A statistical model is developed for the arithmetic operators to represent the behaviour of the operators for different variability impacts. This model is used for approximate computing of error resilient applications that can tolerate acceptable margin of errors. This method is further explored for execution unit of a VLIW processor. The proposed framework provides a quick estimation of energy and error metrics of benchmark programs by simple compilation in using C compiler. In the proposed energy estimation framework, characterization of arithmetic operators is done at transistor level, and the energy estimation is done at functional level. This hybrid approach makes energy estimation faster and accurate for different operating triads. The proposed framework estimates energy for different benchmark programs with 98% accuracy compared to SPICE simulation. Abbreviations AVS Adaptive Voltage sscaling BER Bit Error Rate BKA Brent-Kung Adder BOX Buried OXide CCS Conditional Carry Select CDM Critical Delay Margin CGRA Coarse-Grained Reconfigurable Architecture CMF Common Mode Failure CMOS Complementary Metal-Oxide-Semiconductor DDMR Diverse Double Modular Redundancy DMR Double Modular Redundancy DSP Digital Signal Processor DVFS Dynamic Voltage Frequency sscaling DVS Dynamic Voltage sscaling EDAP Energy Delay Area Product EDP Energy Delay Product FBB Forward Body Biasing FEHM Flexible Error Handling Module FF Flip-Flop FIR Finite Impulse Response FPGA Field-Programming Gate Array FDSOI Fully Depleted Silicon on Insulator FU Functional Unit GRAAL Global Reliability Architecture Approach for Logic HFM High Frequency Mode ix HPM Hardware Herformance Monitor IC Integrated Chip ILA Integrated Logic Analyzer ILEP Instruction Level Power Estimation ILP Instruction Level Parallelism IoT Internet of Things ISA Instruction Set Architecture LFBFF Linear Feed Back Flip Flop LFM Low Frequency Mode LFSR Linear Feedbacl Shift Register LSB Least Significant Bit LUT Look-Up Table LVDS Low-Voltage Differential Signaling LVT Low VT MMCM Mixed Mode Clock Manager MSB Most Significant Bit MSFF Master Slave Flip Flop NOP No OPeration NTR Near-Threshold Region PE Processing Element POFF Point of First Failure PUM Path Under Monitoring RBB Reverse Body Biasing RCA Ripple Carry Adder RTL Resistor- Transistor Logic RVT Regular VT SET Single Event Transients SEU Single Event Upset SNR Signal to Noise Ratio SNW Single N-Well SOI Silicon on Insulator SPICE Simulation Program with Integrated Circuit Emphasis SPW Single P-Well STA Static Timing Analysis STR Sub-Threshold Region SW Single Well TFD Timing Fault Detector TMR Triple Modular Redundancy UTBB Ultra-Thin Body and Box VEX ISA VEX Instruction Set Architecture VLIW Very Large Instruction Word VOS Voltage Over-Scaling Contents Acknowledgements v Abstract vii Abbreviations ix Contents 1 List of Figures 5 List of Tables 9 1 Résuméétendu 11 1.1 Introduction ..................................

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