Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 5, MAY 2013 695 Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors Sangyoung Park, Student Member, IEEE, Jaehyun Park, Student Member, IEEE, Donghwa Shin, Student Member, IEEE, Yanzhi Wang, Student Member, IEEE, Qing Xie, Student Member, IEEE, Massoud Pedram, Fellow, IEEE, and Naehyuck Chang, Fellow, IEEE Abstract—Dynamic voltage and frequency scaling (DVFS) has DVFS transition overhead may be negligible or significant been studied for well over a decade. Nevertheless, existing DVFS depending on how often we change the DVFS setting. Modern transition overhead models suffer from significant inaccuracies; microprocessors tend to change their DVFS setting rather for example, by incorrectly accounting for the effect of DC–DC converters, frequency synthesizers, voltage, and frequency change frequently in response to rapid changes in the application policies on energy losses incurred during mode transitions. Incor- behavior. In addition, DVFS is widely used for dynamic rect and/or inaccurate DVFS transition overhead models prevent thermal management (DTM), which requires frequent change one from determining the precise break-even time and thus forfeit of the DVFS setting (such as in a millisecond) to achieve some of the energy saving that is ideally achievable. This paper thermal stability. Incorrect DVFS transition overhead may introduces accurate DVFS transition overhead models for both energy consumption and delay. In particular, we redefine the cause failure in the thermal stability of the system. Correct DVFS transition overhead including the underclocking-related modeling of the DVFS transition overhead is not a trivial un- losses in a DVFS-enabled microprocessor, additional inductor dertaking since it requires detailed understanding of the DC– IR losses, and power losses due to discontinuous-mode DC–DC DC converter, frequency synthesizer, voltage and frequency conversion. We report the transition overheads for a desktop, transition policies, and so on. a mobile and a low-power representative processor. We also present DVFS transition overhead macromodel for use by high- Unfortunately, existing DVFS transition overhead models level DVFS schedulers. have limitations and are not applicable to modern DVFS setups. In particular, they are significantly simplified, contain Index Terms—Delay and energy overhead, dynamic voltage and frequency scaling (DVFS), macromodel. technical fallacies, or are limited to uncommon setups. In fact, among the 120 DVFS-related papers published in the last 10 I. Introduction years, only 17% of the DVFS papers have considered the tran- YNAMIC voltage and frequency scaling (DVFS) has sition overhead. The majority of DVFS studies simply ignore D proved itself as one of the most successful energy saving the transition overhead [3]–[5]. Among the 17% of DVFS techniques for a wide range of processors. DVFS is enabled by papers, 75% of papers are based on the analytical transition a programmable DC–DC converter and a programmable clock overhead models introduced in [6] and [7]. Some of the generator. These devices naturally incur overhead whenever previous work (e.g. [6], [8], and [9]) assume voltage controlled the system changes its voltage and frequency setting. Since oscillators for the clock generator, which is unusual in today’s the DVFS break-even time is strongly dependent on the DVFS microprocessors (or even in embedded microcontrollers). Sur- transition overhead [2], correct overhead estimation is crucial prisingly, more than a few prior work references have assumed in achieving the maximum DVFS benefit. that the microprocessor stops operation during the entire Manuscript received May 2, 2012; revised September 24, 2012; accepted voltage transition period, something that is neither desirable November 14, 2012. Date of current version April 17, 2013. This work was nor practical [10]. Most of all, a majority of the prior art papers supported under a grant from the Brain Korea 21 Project, and the National consider a DVFS transition overhead model that is based on Research Foundation of Korea (NRF) grant funded by the Korean Government (MEST), under Grant 20120005640. The ICT at Seoul National University incorrect assumptions. A recent work has raised this problem provided research facilities for this paper. Preliminary version of this paper and suggested the correct definition of DVFS transitions [1]. have been presented in part in the International Symposium on Lower Power Evidently, there is a strong need to construct a correct DVFS Electronics and Design (ISLPED) 2010 [1]. This paper was recommended by Associate Editor J. Cortadella. transition overhead model because even recent DVFS work is S. Park, J. Park, and N. Chang are with Seoul National University, still based on the previous models as shown in Section III. Seoul 151-744, Korea (e-mail: [email protected]; [email protected]; In this paper, we provide a formal definition of the DVFS [email protected]). D. Shin is with the Politecnico di Torino, Turin 10129, Italy (e-mail: transition overhead, analyze various components of the over- [email protected]). head, and finally construct a macromodel for DVFS transition Y. Wang, Q. Xie, and M. Pedram are with the University of Southern overhead. California, Los Angeles, CA 90089-2562 USA (e-mail: [email protected]; [email protected]; [email protected]). This paper takes into account all the major power and Digital Object Identifier 10.1109/TCAD.2012.2235126 performance loss components in the modern DVFS setups as 0278-0070/$31.00 c 2013 IEEE 696 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 5, MAY 2013 Fig. 3. Concept of underclocking loss and PLL lock time loss in a DVFS transition. scaling as shown in Fig. 3, which is a major source of Fig. 1. Breakdown of an upscaling DVFS transition overhead in energy and the delay overhead [92.4% of total delay overhead as delay. (Intel Core2 Duo E6850, upscaling from 1.05 to 1.3-V). (a) Energy shown in Fig. 1(b)]. overhead. (b) Delay overhead. 5) The microprocessor consumes static power even during the PLL lock time though it halts. This is another source of energy waste [3.2% of total energy overhead as shown in Fig. 1(a)]. The aforesaid observations are the key contributions of this paper, based on which we derive accurate, yet compact energy and delay overhead models for DVFS transitions. We present a relatively simple analytical model with parameters that can be easily acquired from the datasheets and/or passive component values (R, L and C values). We also provide case studies for three distinct and representative microprocessors, Intel Core2 Fig. 2. Upscaling and downscaling current flows. Duo E680, Samsung Exynos 4210, and TI MSP430. Some programmers who have no hardware knowledge may use the follows. numbers. Finally, we emphasize the importance of considering 1) Conventional DVFS transition models consider the PLL the DVFS transition overhead for a DTM example. lock time as the major delay (latency) overhead, and the energy required to charge and discharge the bulk II. Background capacitor as the energy overhead. Both assumptions are A. System Setup for DVFS incorrect (delay overhead due to PLL lock time accounts DVFS setups require a programmable voltage regulator for only 7.6% of the total delay overhead as shown in and a programmable clock generator. A microprocessor is Fig. 1). generally powered by a buck-type switching-mode DC–DC 2) Energy consumed for charging and discharging the bulk converter as shown in Fig. 2. The upper and lower MOSFETs capacitor does not fully account for the energy over- control the inductor current and the output voltage. The induc- head, especially for the discontinuous mode DC–DC tor current never changes abruptly, which results in adiabatic converters since they discharge the bulk capacitor by the charging and discharging to and from the bulk capacitor. In load current as shown in Fig. 2. The additionally stored other words, the bulk capacitor is not subject to switching loss energy to the bulk capacitor during the upscaling is that is proportional to the square of the terminal voltage. eventually used by the load during the next downscaling. DC–DC converters are subject to power loss aside from the 3) Voltage upscaling in a conventional DC–DC converter DVFS transition overhead, which includes conduction loss, requires more current to be fed through the inductor to switching loss, and controller loss [11]. Conduction loss is increase the bulk capacitor voltage as shown in Fig. 2. the IR loss in the MOSFET and inductor given by This in turn results in additional IR loss from the 2 · · − · inductor (78.2% of total energy overhead as shown in Pcdt = IO D RSW1 +(1 D) RSW2 + RL Fig. 1). 1 I 2 + · L · D · R +(1−D) · R +R +R (1) 4) During the DVFS transition, the microprocessor operates 3 2 SW1 SW2 L C at a higher supply voltage level than what is strictly where IO, D, RSW1, RSW2, RL, RC are output current, duty necessary. This results in energy waste. We call this ratio, upper switch on-resistance, lower switch on-resistance, phenomenon the underclocking-related loss, which is inductor resistance, and capacitor ESR, respectively. Switching a significant source of energy overhead during the loss is the power dissipation due to gate drive which is given mode change [energy overhead due to under clocking by accounts for 18.6% of total energy overhead as shown P = V · f · (Q + Q )(2) in Fig. 1(a)]. In addition, the underclocking causes the sw I s SW1 SW2 microprocessor to operate at a lower clock frequency where VI , fs, QSW1, and QSW2 are input voltage, switching than what is allowed during the voltage-frequency up- frequency, gate charges of the upper and lower MOSFET, PARK et al.: MODELING OF DYNAMIC VOLTAGE AND FREQUENCY SCALING IN MODERN MICROPROCESSORS 697 Fig.

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