Revision 6.03 December 22, 2015 Document Number: MD00091 Privileged Resource Architecture Privileged Resource Volume III: MIPS64® / microMIPS64™ III: MIPS64® Volume MIPS® Architecture For Programmers Programmers Architecture For MIPS® any warranty of any . any kind. of any warranty ged Resource Architecture, Rev. 6.03 ect to change without notice ‘as is’, and is supplied without me III: MIPS64® / microMIPS64™ Privile / MIPS64® me III: . This publication contains proprietary information which is subj which information proprietary contains publication . This MIPS® Architecture For Programmers Volu For Programmers Architecture MIPS® Public

32 ... 28 ...... 16 ...... 25 ...... 27 ...... 21 ...... 29 ...... 27 ...... 17 ...... 28 ...... 27 ...... 16 ...... 24 ...... 28 ...... 21 ...... 25 ...... 24 ...... 27 ...... 17 ...... 25 ...... 28 ...... 28 ...... 17 ...... 16 ...... 27 ...... 21 ...... 29 ...... 16 ...... 26 ...... 20 ...... 16 ...... 16 ...... 23 ...... 23 ...... 24 ...... 28 ...... 32 ...... 24 ...... 21 ...... Operating Mode...... ture...... (SEGBITS) ...... me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 3 ...... ess Size (PABITS)ess Size .. 4.1.4: Context Register ...... 4.1.5: Segmentation Control ...... 4.1.6: Enhanced Virtual Addressing...... 4.2.1: Address Space...... 4.2.2: Segment and Segment Size 4.2.3: Physical Addr 4.1.1: ...... 4.1.2: Physical Memory...... 4.1.3: Protection of Virtual Memory Pages...... 1.2.1: UNPREDICTABLE...... 1.2.2: UNDEFINED ...... 1.2.3: UNSTABLE ...... 3.5.1: 64- Address Enable...... 3.5.2: 64-bit Operations Enable ...... 3.5.3: 64-bit Floating-Point Operations Enable 1.1.1: Italic Text...... 1.1.2: Bold Text...... 1.1.3: Text Courier ...... 2.2.1: CP0 - The System Coprocessor ...... 2.2.2: CP0 Registers...... 3.5.4: 64-bit FPR Enable...... 3.5.5: Coprocessor 0 Enable...... 3.5.6: ISA Mode ...... 4.2: Terminology...... 4.3: Virtual Address Spaces ...... 4.4: Compliance...... 4.5: Access Control as a Function of Address and 4.1:ArchitecDifferencesof the between Releases 1.3: Special Symbols Pseudocode in Notation.... 3.2: Kernel Mode ...... 3.3: Supervisor Mode ...... 24 3.4: User Mode ...... 3.5: Other Modes...... 3.1: Debug Mode ...... 2.1: Introduction...... 1.1: Typographical Conventions ...... 1.2: UNPREDICTABLE and UNDEFINED ...... 1.4: For More Information ...... 2.2: The MIPS Coprocessor Model ...... MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Chapter 4: Virtual Memory Chapter ...... Chapter 3: MIPS64 and microMIPS64 Operating Modes...... and microMIPS64 3: MIPS64 Chapter 23 Chapter 2: The MIPS64 and microMIPS64 Privileged Resource ArchitectureResource Privileged microMIPS64 2: The MIPS64 and Chapter ...... 21 Chapter 1: About This Book This 1: About Chapter ...... 15 Table of Contents Table

56 .... 63 ..... 82 ..... 61 ...... 73 ..... 105 ...... 39 ...... 107 ...... 83 ...... 71 ...... 42 ...... 115 ...... 100 ...... 103 ...... 106 ...... 113 ...... 111 ...... 98 ...... 106 ...... 109 ...... 112 ...... 114 ...... 65 ...... 109 ...... 110 ...... 114 ...... 46 ...... 113 ...... 42 ...... 61 ...... 104 ...... 103 ...... 114 ...... 86 ...... 97 ...... 43 ...... 81 ...... 52 ...... kseg1 Segments..... 34 ...... 96 ...... 85 ...... ged Resource Architecture, Rev. 6.03 ...... = 0 = ...... 38 UX for the kseg0 and kseg0 for the ase 6 ...... = 1...... 37 ...... ...... 95 ERL = 1...... 38 DM ocks ...... ss Generation Function...... 42 nfiguration...... or Offsets for Vectored Segmentation Control ...... ing ...... lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ...... (NMI) Exception...... er ...... xception ...... and Cacheability-and-Coherency Attributes for xkphys the Segment ...... 35 rol ...... support ...... 66 ion and and CoherencyCacheability Attributes 4.12.1: Address Space Identifiers (ASID) ...... 4.11.1: Use Cases for Effective_Addre 4.12.2:Organization TLB ...... 4.12.3:Initialization...... TLB 4.12.4: AddressTranslation ...... 5.2.1: Access and Status Control Registers...... 6.1.1: Modes...... 6.1.2: Generation of Exception Vect 4.14.1: EVA Segmentation Control Co 4.14.2: Enhanced Virtual Address (EVA) Instructions...... 4.15.3: Hardware page table walk 4.15.3: Hardware page table 4.15.2:Directory PTEand Entry Format...... 4.15.1: Multi-Level 6.2.1: Exception Priority ...... 6.2.2: Exception Vector Locations...... 6.2.3:General Exception Processing...... 6.2.4: EJTAG Debug Exception ...... 6.2.5: Reset Exception...... 6.2.6: Soft Reset Exception...... 6.2.7: Non Maskable Interrupt 6.2.8: Machine Check Exception...... 6.2.9: Address Error E 6.2.10: TLB Refill and XTLB Refill Exceptions.... 4.13.1: Exception Behavior under 6.2.11: Execute-Inhibit Exception...... 6.2.12: Read-InhibitException...... 6.2.13: TLB Invalid Exception ...... 6.2.14: TLB Modified Exception . 6.2.15:Error Exception...... 6.2.16: Exception ...... 6.2.17: Integer Overflow Exception...... 6.2.18:Exception...... Trap 6.2.19: System Call Exception ...... 6.2.20: BreakpointException ...... 6.2.21: Reserved InstructionException ...... 4.9: Special Behavior for the kseg3 Segment when Debug 4.11: 32-bit Compatibility Addressing for Release 5 EVA, and Rele Release and 5 EVA, Addressing for 4.11: 32-bit Compatibility 4.12: AddressTranslationVirtual TLB-Based ...... 42 4.10: Special Behavior for Data References in User Mode with Status with Mode User in References Data for Behavior Special 4.10: 6.1: Interrupts ...... 5.1: CDMMBase Register...... 4.7: Address Translation 5.2: CDMM - Access Control and Device Register Bl 4.6: Address Translat 4.8: Address Translation for the kuseg Segment when Status 4.15: Walk Hardware Page Table 4.13: Cont Segmentation 6.2: Exceptions ...... 4.14: Enhanced Virtual Addressing ...... 4Vo For Programmers Architecture MIPS® Chapter 6: Interrupts and Exceptions...... 6: Interrupts and Chapter 85 Chapter 5: Common Device Memory Map...... Memory 5: Common Device Chapter 81

... 119 ... 127 .... 151 ..... 141 ..... 163 ...... 116 ...... 157 ...... 165 ...... 197 ...... 125 ...... 169 ...... 199 ...... 181 ...... 116 ...... 159 ...... 161 ...... 139 ...... 184 ...... 203 ...... 177 ...... 181 ...... 207 ...... 193 ...... 201 ...... 124 ...... 153 ...... 191 ...... 205 ...... 123 ...... 117 ...... 123 ...... 127 ...... 135 ...... 116 ...... 175 ...... 175 ...... 175 ...... 117 ...... 118 ...... 119 ...... 133 ...... 121 ...... 120 ...... 121 ...... 133 Selects 6 and 7) ...... 205 ...... lect 0) ...... ct 1)...... lect 1) ...... 0) ...... 1) ...... 2) ...... 0)...... 6)...... 7)...... 1) ...... 0)...... de...... n ...... Register 4, Select 3) ...... er 5, Select 5) ...... ster 8, Select 0) ...... ster 8, Select 2)...... 9, Select 0)...... me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 5 er 4, Select 0) ...... mmary ...... Sets...... 8.2.1: HazardsPossible Execution ...... 121 8.2.2: Possible Instruction Hazards...... 8.3.1: InstructionMIPS64 Encoding...... 8.3.2: microMIPS64 Instruction Encoding...... 6.2.22: Coprocessor Unusable Exception...... 6.2.23: MDMX Unusable Exceptio 6.2.24:Exception Floating-Point ...... 6.2.25: Coprocessor Exception...... 2 6.2.26: WatchException ...... 6.2.27:Exception...... Interrupt 9.18.1: xkphys access mode overri 8.3: Hazard Clearing Instructions and Events ..... 9.10: ContextConfig Register (CP0 Register 4, Sele 9.1: Coprocessor 0 Register Su 8.1: Introduction...... 7.1: Introduction to Shadow 7.2: Support Instructions...... 8.2: Types of Hazards ...... 9.2: Notation ...... 9.3: Writing CPU Registers...... 9.4: Index Register (CP0 Register 0, Select 0) 9.11: UserLocal Register (CP0 Register 4, Select 9.9: Context Register (CP0 Regist 9.5: VPControl (CP0 Register 0, Select 4) ...... 137 9.6: Random Register (CP0 Register 1, Select 9.7: EntryLo0, (CP0 Registers EntryLo1 2 and 3, Se 9.8: Global Number Register (COP0 Register 3, Se 9.12: Debug ContextID (CP0 Register 4, Select 4) 9.13: XContextConfig Register (CP0 9.14: PageMask Register Register (CP0 5, Select 9.15: PageGrain Register (CP0 Register 5, Select 9.22: Wired Register (CP0 Register 6, Select 0) 9.23: PWCtl Register (CP0 Register 6, Select 6) 9.28: Count Register (CP0 Register 9.29:Implementations (CP0 Reserved for 9, Register 9.30: EntryHi Register (CP0 Register 10, Select 9.16: SegCtl0 (CP0 Register 5, Select 2) ...... 9.17: SegCtl1 (CP0 Register 5, Select 3) ...... 9.18: SegCtl2 (CP0 Register 5, Select 4) ...... 9.24: HWREna Register (CP0 Register 7, Select 0) RegiRegister (CP09.25: BadVAddr Select Register9.26: (CP08, BadInstr Register 9.27: BadInstrP Register (CP0 Regi 9.19: PWBase Register (CP0 Regist 9.21: PWSize Register (CP0 Register 5, Select Register9.21: (CP05, PWSize Register 9.20: PWField Register (CP0 Register 5, Select Register9.20: (CP05, PWField Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Chapter 9: Coprocessor 0 Registers 0 9: Coprocessor Chapter ...... Chapter 8: CP0 Hazards8: CP0 Chapter ...... 121 Chapter 7: GPR Shadow Registers Shadow 7: GPR Chapter ......

. 243 ... 255 .... 321 .... 253 .... 345 ..... 323 ...... 263 ...... 267 ...... 271 ...... 279 ...... 285 ...... 295 ...... 259 ...... 233 ...... 247 ...... 257 ...... 331 ...... 211 ...... 333 ...... 335 ...... 339 ...... 319 ...... 311 ...... 249 ...... 235 ...... 229 ...... 337 ...... 317 ...... 329 ...... 241 ...... 343 ...... 213 ...... 341 ...... 341 ...... 225 ...... 307 ...... 347 ...... 321 ...... 309 ...... 350 ...... 347 ...... 243 ...... PS16e ASE or or PS16e ASE ...... MIPS16e ASE or microMIPS64 MIPS16e ASE or microMIPS64 ged Resource Architecture, Rev. 6.03 ement the MI ct 2)...... 305 ...... Selects 6 and 7) ...... 211 Selects 6 and 7) ...... 293 all Selectvalues)...... 315 ocessors that Implement Processors That Impl ...... lect 1) ...... lect 2) ...... lect 3) ...... lect 4) ...... lect 5) ...... lect 0) ...... 3)...... 0) ...... 3) ...... 0)...... 2) ...... 2)...... 2)...... 0) ...... (CP0 Register 14, Select 2) ...... 245 ster 15, Select 3)...... Register 14, Select 0) ...... gister (CP0 Register 17, Select 1) ...... 298 gister Index (CP0 Register 17, Sele ster 15, Select 2) ...... lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ster 31, Selects 2 to 7) ...... er 31)...... gister 17, Select 0) ...... ster 11, Select 0)...... ster 11, Select ster 12, Select 3) ...... er 15, Select 1)...... er 23, Select 0)...... , Select0) ...... gister 15, Select 4) .. the DEPC Register in the EPC Register in Pr the EPC Register on (CP0 Register Select 15, 0) ...... P0 Register12, Select 1) ...... 9.39.1: Special Handling of 9.39.1: Special Handling Base Architecture...... A.1.1: Fixed Address Translation...... A.1.2: Cacheability Attributes...... 9.70.1: Special Handling of the ErrorEPC Register in Processors That Implement the MIPS16e ASE or microMIPS64 Base Architecture ...... 9.62.1: Special Handling of 9.62.1: Special microMIPS64 Base Architecture ...... 9.47: Configuration Register 1 (CP0 Register 16, Se 9.44: CMGCRBaseRegi (CP0 Register 9.45: BEVVA Register (CP0 Re 9.46: Configuration Register (CP0 Register 16, Se 9.43:Regi CDMMBase(CP0 Register 9.40: Nested Exception Program Counter9.40:Program Nested Exception 9.41: Identificati Processor 9.63: Performance Counter RegisterCounter9.63: (CP0 Performance 25) Register ...... 9.64:Select(CP0 ErrCtl Register 26, Register 9.65: CacheErr Register (CP0 Register 27, Select 9.48: Configuration Register 2 (CP0 Register 16, Se 9.39: Program CounterException (CP0 9.37: Cause Register (CP0 Register 13, Select 0) ...... 9.38: NestedExc (CP0 Register 13, Select 5) ..... Regist9.42: EBase(CP0 Register A.1: Fixed Mapping MMU ...... 9.36: SRSMap Register (CP0 Regi 9.31: RegisterCompare Regi (CP0 9.66: TagLo Register (CP0 Register 28, Select 0, 9.69: DataHi Register (CP0 Register 29, Select 1, 9.72: KScratchn Registers (CP0 Regi 9.49: Configuration Register 3 (CP0 Register 16, Se 9.32:Implementations (CP0 Reserved for 11, Register 9.33: Register Status (CP Register 12, Select 0) ...... 9.34:( IntCtl Register 9.35: SRSCtl Register (CP0 Register 12, Select 9.67: DataLo Register (CP0 Register 28, Select 1, 9.68: TagHi Register (CP0 Register 29, Select 0, 9.70: ErrorEPC (CP0 Register 30 Register9.70: ErrorEPC (CP0 Regist (CP0 9.71: DESAVE Register 9.50: Configuration Register 4 (CP0 Register 16, Se 9.61: Debug2 Register (CP0 Register 23, Select 6)...... 9.62: DEPC Register (CP0 Register 24) ...... 9.51: Configuration Register 5 (CP0 Register 16, Se 9.56: WatchLoRegister (CP0 Register18) ...... 9.57: WatchHiRegister (CP0 Register19)...... 9.58: XContext Register (CP0 Register 20, Select 9.52:Implementations (CP0 Reserved for 16, Register Address (CP0Linked 9.53: Re Load Accessibility9.54: Memory AttributeRe Accessibility9.55: Memory AttributeRe 9.59:Implementations (CP0 Reserved for 22, Register Regist9.60:(CP0 Debug Register 6Vo For Programmers Architecture MIPS® Appendix A: Alternative MMU Organizations MMU A: Alternative Appendix ...... 347

... 353 ...... 351 ...... 353 ...... 357 ...... 361 ...... 356 ...... 355 ...... 353 ...... 351 ...... 352 ...... 351 ...... me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 7 Fixed-Page-Size TLBs...... A.2.1: BAT Organization ...... A.2.2: Address Translation...... ...Register the CP0 Changes to A.2.3: A.1.3: Changes to the CP0 Register Interface...... A.3.1: MMU Organization...... A.3.2: Programming Interface ...... A.3.3: Changes to the TLB Instructions ...... A.3.4: Changes to the COP0 Registers ...... A.3.5: Software Compatibility...... 358 A.2: Block Translation Address . A.3: Dual Variable-Page-Size and A.3: Dual MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Appendix B: Revision History B: Revision Appendix ...... ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 8Vo For Programmers Architecture MIPS®

41 68 42 ..... 94 ...... 176 ...... 176 ...... 177 ...... 165 ...... 165 ...... 191 ...... 91 ...... 35 ...... 83 ...... 161 ...... 63 ...... 164 ...... 151 ...... 158 ...... 197 ...... 72 ...... 72 ...... 199 ...... 181 ...... 169 ...... 203 ...... 159 ...... 183 ...... 186 ...... 139 ...... 67 ...... 137 ...... 201 ...... 194 ...... 192 ...... 43 ...... 135 ...... 30 ...... 62 ...... 62 ...... 72 ...... 144 ...... 146 en Accessed using MFC0 and and MFC0 using Accessed en ...... & COP0 fields...... Control Select 2)...... TC=0 and Config3SM=0...... 153 lease 3 of the Architecture when Accessed with with DMFC0 & Accessed when 3 of Architecture the lease ...... er 5, t Segment ...... me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 9 er Format in Release 1 of the Architecture...... 1 er Format in Release 2 of the Architecture...... 1 (CP0 Register 5, Select 3)...... (CP0 Register 5, Select 4)...... (CP0 Regis when Config3CTXTC=1 or Config3SM=1...... Config3CTXTC=1 or when 154 configuration...... rmat if ConfigBPG=0rmat if ...... rmat if ConfigBPG=1rmat if ...... r External Interrupt Controller Interrupt Mode...... Format...... Format...... Format ...... for Vectored Interrupt Mode...... ster Format...... Format ...... Format...... Format ...... Format...... Figure 9.29: BadInstr Register Figure 9.30: BadInstrP Register Figure 9.22: PWField Register Figure 9.23: PWSize Register Figure 9.24: Wired And Random Entries In The TLB ...... Figure 9.25: Wired Register Format...... Figure 9.26: PWCtl Register Format...... Figure 9.27: HWREna Register Format ...... Figure 9.28: BadVAddr Register Format...... Figure 6.2: Interrupt Generation fo Figure 9.2: VPControl Register Figure 9.3: Random Register Format ...... 9-4: EntryLo0, EntryLo1 RegistFigure Figure 9.1: Index Register Format ...... Figure 4.7: Page Table Walk Process ...... Figure 4.8: Page Table Walk Process (without Base Dir) Figure 4.5: EVA addressability...... Figure 4.6: Legacy to EVA address Figure 4.4: Legacy Figure 4.4: Legacy addressability ...... MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Figure 4.2: Address Figure 4.2: Address Interpretation for the xkphys Figure 4.3: Contents of a TLB Entry ...... Figure 9.19: SegCtl1 Register Format Figure 9.20: SegCtl2 Register Format Figure 9.21: PWBase Register Format ...... Figure 4.1: Virtual Figure 4.1: Virtual Address Space...... List of Figures List of Figure 9-5: EntryLo0, EntryLo1 RegistFigure Figure 5.2: Access Control Status and Register ...... 83 Figure 6.1: Interrupt Generation Figure 4.9: 8- Leaf PTE...... Figure 4.10: 8-Byte Non-leaf PTE Options ...... Figure 4.11: 8-Byte Rotated PTE Formats...... Figure 5.1: Example Organization of CDMMthe .... Figure 9.15: PageMask Register Fo Figure 9-6: EntryLo0, EntryLo1 Register Format in Re Format Register EntryLo1 9-6: EntryLo0, Figure DMTC0 Instructions ...... wh Architecture Release 3 of the in Format Register EntryLo1 EntryLo0, 9-7: Figure MTC0 Instructions...... Figure 9.8: Global Number Regi Figure 9.9: Context Register Format when Config3CTX Figure 9.10: Context Register Format Figure 9.11: ContextConfig Register Format ...... Figure 9.12: UserLocal Register Figure 9.13: Debug ContextID Register Format ..... Figure 9.14: XContextConfig Register Format.... Figure 9.16: PageMask Register Fo Figure 9-17: PageGrain Register Figure 9.18: SegCtl0 Register Format

... 311 ... 313 ...... 300 ...... 326 ...... 323 ...... 295 ...... 279 ...... 295 ...... 213 ...... 279 ...... 349 ...... 350 ...... 213 ...... 333 ...... 245 ...... 305 ...... 233 ...... 241 ...... 345 ...... 211 ...... 257 ...... 255 ...... 307 ...... 309 ...... 341 ...... 271 ...... 253 ...... 249 ...... 250 ...... 229 ...... 285 ...... 263 ...... 267 ...... 235 ...... 205 ...... 207 ...... 259 ...... 243 ...... 247 ...... 351 ...... 352 ...... 225 ...... ged Resource Architecture, Rev. 6.03 VH=0...... 300 VH=1...... 300 TXTC=0 ...... TXTC=1 ...... d after)...... 5)...... ter Formatter ...... ster Format...... Regis lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: t if PageGrainELPA=0 ...... at ...... Format...... Format...... at...... Format ...... Format...... rmat ...... rmat ...... rmat...... Format...... rmatfor Pre-Release 6...... rmat for 6Release ...... Format...... rmat ...... Format ...... Entry...... ditions...... Format...... Format if and Config5MPageGrainELPA=1 Format if and Config5MPageGrainELPA=1 Counter Counter Regi Counter Counter Counter Control Performance Figure 9.53:6) Config4 Register Format (Pre-Release ...... Figure 9.54: Config4 Register Format (Release 6) ...... Figure 9.55: Config5 Register Format...... Figure 9-56: LLAddr Register Format (pre Release Figure 9-57: LLAddr Register Format (Release 5 an Figure 9.58: MAAR Register Forma Figure 9-59: MAAR Register Figure 9.50: Config1 Register Format...... Figure 9.51: Config2 Register Format...... Figure 9-52: Config3 Register Format ...... Figure 9.49: Config Register Figure 9-60: MAAR Register Figure 9.47: CMGCRBase Register...... Figure 9.48: BEVVA Register Form Figure 9.61: MAARI Index Register Figure 9.63: WatchHi Register Figure 9.64: XContext Register Format when Config3C Figure 9.39: Cause Register Fo Figure 9.40: NestedExc Register Figure 9.41: EPC Register Form Figure 9.42: NestedEPC Register Format ...... Figure 9.43: PRId Register Format ...... Figure 9.44:Register EBase Fo Figure 9.45:Register EBase Fo Figure 9.46: CDMMBase Register ...... Figure 9.62: WatchLo Register Figure 9.65: XContext Register Format when Config3C Figure 9.69: ErrorEPC Register Figure A.2: Memory when ERLMapping = 1 ...... Figure A.3: Config Register Ad Figure 9.67: Performance Figure 9-68: Example TagLo Register Format...... Figure 9.70: KScratchn Register Figure A.1: Memory when ERLMapping = 0 ...... 10Vo For Programmers Architecture MIPS® Figure 9.37: SRSCtl Register Format ...... Figure 9.38: SRSMap Register Figure 9.31: Count Register Fo

Figure 9.32: EntryHi Register Format ...... Figure 9.33: Register Compare Format ...... Figure 9.34: Status Register Fo Figure 9.36: IntCtl Register Format...... Figure 9.35: Status Register Fo Figure A.4: Contents of a BAT Figure 9.66:

5 .. 63 . 101 ...... 65 ...... 64 ...... 87 ...... 83 ...... 17 ...... 149 ...... 96 ...... 90 ...... 127 ...... 158 ...... 95 ...... 151 ...... 158 ...... 120 ...... 159 ...... 99 ...... 137 ...... 139 ...... 31 ...... 135 ...... 98 ...... 121 ...... 152 ...... 123 ...... 64 ...... 144 ...... 133 ...... 123 ...... 99 ...... 147 ...... 100 ...... 97 ...... 86 ...... d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 11 Operating Mode ...... 32 ...... ase 3 of the Architecture when when with Architecture Accessed ase 3 of the e instructions ...... Attributes for the and kseg0 Segmentskseg1 ...... 34 ...... in Release 3 of the Architecture when when using Architecture Accessed 3 of the in Release s in Rele an Exception...... n Config3CTXTC=0 and Config3SM=0...... 153 EHB ...... terrupts...... d Descriptions...... ions ...... Interrupt Mode...... me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me TLB Refill Selection as a Function of 3GB EVA in 32-bit Compatibility region ...... or for ordinary load/stor Field Descriptions...... Cacheability Attributes for the xkphys Segment...... 3 vior for EVA load/store instructions ion Operation Statements...... ion Operation Descriptions when Config3CTXTC=1 or Config3SM=1...... Descriptions when 154 rviceCompatibilityMode in Interrupt ...... s in Numerical Order ...... as a Function of PABITSof as a Function ctions...... ss Spaces...... ng Shadow Sets ...... on, Cacheability and Coherency upt Priority for Vectored upt Priority Table 6.5: Interrupt State Changes Made Visible by Table 6.5:Interrupt State Table 6.4: Exception Vector Offsets for Vectored In Table 6.9:Exception VectorOffsets ...... Table 6.10:Vectors Exception ...... Table 9.4: VPControl Register Field Descriptions...... Table 9.5: Random Register Field Descriptions...... Table 9.6: EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture ...... 141 Table 9.7: EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture ...... 142 Table 6.6: Priority of Exceptions ...... Table 6.7:ExceptionCharacteristics Type ...... Table 6.8: Exception Vector Base Addresses...... Table 8.1:HazardsPossible Execution ...... Table 8.2:Possible InstructionHazards ...... Table 8.3: Hazard Clearing Instructions...... Table 6.11: Value Stored in EPC, ErrorEPC, or DEPC on ErrorEPC,in EPC,Table 6.11: Value Stored Table 7.1: Instructions Supporti Table 9.1: Coprocessor 0 Register Table 9.2: Read/WriteBit Field Notation...... Table 9.3: Index Register Field Descriptions ...... Table 9.8: EntryLo0, EntryLo1 Register Field Descriptio Table 4.8: Address translation beha Table 4.9: Address translation behavi Table 6.3: Relative Interr Table 5.1: Access and Status Control Register Fiel Table 6.1:Interrupt Modes...... Table 6.2: Request for Interrupt Se Table 9.11: Cacheability and Coherency Attributes...... 150 RegisterNumberTable 9.12: Global Table 9.13: Deriving Unique VPNum ...... when Table 9.14:Field Descriptions Register Context ContextTable 9.15:Register Field ContextConfigTable 9.16: DescriptField Register Table 9.17:ContextConfig RecommendedValues...... Table 9.18:Descriptions...... UserLocalField Register Table 9.19:Descriptions...... Register Debug ContextIDField ...... 161 Table 9.9: EntryLo0, EntryLo1 Register Field Descriptions MFC0 and MTC0Instructions ...... Widths Field Table 9.10: EntryLo MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For DMFC0 and DMTC0 Instructions...... Table 1.1: Symbols Used in Instruct List of Tables List of Table 4.5: Generation...... 51 Table 4.6: Segment Configuration for Table 4.7: EVA Load/Store Instru Table 4.7: Table 4.1: Virtual Memory Addre Table 4.2: Address Space Access and Table 4.3: Address Translati Table 4.4: Address and Translation

9 .... 251 ...... 177 ...... 179 ...... 178 ...... 195 ...... 195 ...... 255 ...... 196 ...... 253 ...... 164 ...... 245 ...... 224 ...... 165 ...... 197 ...... 233 ...... 241 ...... 169 ...... 181 ...... 199 ...... 211 ...... 186 ...... 257 ...... 203 ...... 176 ...... 177 ...... 183 ...... 198 ...... 250 ...... 250 ...... 176 ...... 229 ...... 201 ...... 235 ...... 238 ...... 263 ...... 267 ...... 271 ...... 279 ...... 286 ...... 194 ...... 208 ...... 243 ...... 247 ...... 259 ...... 192 ...... 214 ...... 225 ...... 188 ...... ged Resource Architecture, Rev. 6.03 state...... 17 rrupt ...... 230 itioning of MIPS64 address space...... 179 Be Zero ...... gions ...... iption...... ations...... ptions...... lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: on an Exception or Inte bit Compatibility Region) legacy reset scriptions ...... eld Descriptions ...... n in Directory Levels ...... MaskX1 Fields of the PageMask Register ...... 166 CSS AccessModes Control ...... eld Descriptions...... y part Segment Configuration Table 9.55: Cause Register Field Descriptions...... RegisterTable 9.55: Field Cause Descriptions...... RegisterTable 9.58: Field EPC Table 9.59:Descriptions NestedEPCRegister Field . DescriptionsRegister Field Table 9.60: PRId ...... Table 9.61:Descriptions EBase RegisterField ...... Table 9.62:Descriptions EBase RegisterField ...... MustTable 9.63: Conditions Under Which EBase15..12 Table 9.54: SRSMap Register Field Descriptions...RegisterTable 9.54: Field SRSMap RegisterTable 9.56: ExcCodeField...... Cause Table 9.57:Descriptions NestedExcRegister Field Table 9.64:Descriptions. CDMMBaseField Register Table 9.65: CMGCRBaseFi Register Descriptions....RegisterTable 9.67: Field Config Field Descriptions.....RegisterTable 9.68: Config1 Table 9.69: Config2 Register Field Descriptions.....RegisterTable 9.69: Config2 Field Descriptions.....RegisterTable 9.70: Config3 Field Descriptions.....RegisterTable 9.71: Config4 Field Descriptions.....RegisterTable 9.72: Config5 Table 9.26: SegCtl2 Register Field Descriptions . Table 9.27: XR indexing of xkphys MIPS64 re address Table 9.25: SegCtl1 Register Field Descriptions . Table 9.24: RegisterSegCtl0 Field Descriptions 12Vo For Programmers Architecture MIPS® Table 9.22: the Maskand Valuesfor DescriptionsTable 9.23: PageGrainRegister Field Table 9.21: DescriptionsField Register PageMask ... Table 9.20: XContextConfigTable 9.20:Descri Field Register

Table 9.66: BEVVA Register Field De Table 9.29: Segment ConfigurationTable 9.29: Segment Table 9.28: CFG (Segment Configuration)Field Descr Table 9.30: Segment Configuration (32- ConfigurationTable 9.30: Segment Table 9.33: PWField Register Field Descriptions.... Register Field Table 9.33: PWField Descriptions Register Field Table 9.34: PWSize .... Table 9.35: PS/PTEW Usage ...... Table 9.36:Field Descriptions..... Wired Register Table 9.37:Field Descriptions...... PWCtl Register Table 9.31: 32-bit CompatibilitTable 9.31:32-bit Field DescriptionsRegisterTable 9.32: PWBase ... configur Table 9.38:RegisterField PWCtl XK/XS/XU Table 9.53:Sources forSRSCtl new Table 9.39: HugePg Field and Huge Page configurations...... Huge Page and Table 9.39: HugePg Field representatio Page Table 9.40: Huge Descriptions.Register Field Table 9.44: BadInstr DescriptionsRegisterTable 9.46: Field Count ...... 205 Table 9.47: EntryHiField DescriptionsRegister ..... Descriptions....Table 9.49:Register Field Status Generation Address5 EffectiveTable 9.50: Release Table 9.51:Descriptions.. IntCtlField Register Table 9.41: HWREna Register Field DescriptionsRegisterTable 9.41: HWREna ..... Table 9.42: RDHWRRegister Numbers ...... Register Fi Table 9.43: BadVAddr DescriptionsRegisterTable 9.45: Field BadInstrP Table 9.48:Field Descriptions Compare Register .. Table 9.52:Field DescriptionsRegister SRSCtl .....

3 ... 327 .... 324 ..... 311 ...... 296 ...... 295 ...... 291 ...... 333 ...... 303 ...... 305 ...... 341 ...... 345 ...... 307 ...... 309 ...... 303 ...... 301 ...... 351 ...... 352 d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 13 ...... PerfCnt CP0 Register...... 323 Config3CTXTC=1 ...... 31 ...... TXTC=0 ...... l Addresses...... 347 s...... me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Descriptions (pre Release 5)...... (pre Release Descriptions and after)... (Release 5 Descriptions ation for MAAR Pair...... Table 9.89:DescriptionsRegister KScratchn Field Table A.1: Physical Address Generation from Virtua Table 9.85: Performance CounTable 9.85:ter Control Register Performance Descriptions Field ...... Table A.2: Config Register Field Descriptions ..... Table 9.84: Example Performance UsageCounter of the Register Field Descriptions...... CounterCounterTable 9.86: Performance Table 9.87: TagLo RegisterExample Field Descriptions...... Table 9.88: ErrorEPC Register Field Descriptions Table A.3: BATTable A.3: Entry Assignments...... MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Table 9.78:Speculate MAARPair Determination for Table 9.79: MAARI Index Register Field Description Register Field Table 9.79: MAARIIndex Table 9.73: SegmentSegCtl0K CCA Determination ... Table 9.74: LLAddr Register Field Field RegisterTable 9.74: LLAddr Field RegisterTable 9.75: LLAddr Determin Table 9.77: Valid Table 9.76: MAAR Register Field Descriptions...... Table 9.76: Field MAARRegister Descriptions...Table 9.80:Register Field WatchLo Descriptions....Table 9.81:Register Field WatchHi Table 9.82: XContext Register Fields when Config3C DescriptionsXContextRegisterTable 9.83: when Field ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 14Vo For Programmers Architecture MIPS®

chitecture 32® Architecture and the and 32® Architecture the MIPS® Ar MIPS® the MDMX and MSA can not be imple- MSA can MDMX and S64™ Privileged Resource Architec- S64™ Privileged d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 15 ocessor implementation to the MIPS64® Architecture and e MIPS® Architecture itecture the microMIPS64™ instruction the microMIPS64™ instruction Privileged Privileged Resource Architecture which defines and fic ExtensionMIPS64® to the Architecture. Beginning MIPS® Architecture MIPS® Arch e document set, and provides an introduction to the n-Specific Extension to n-Specific Extension n-Specific Extension to the MIPS® Architecture included in a MIPS® pr is the preferred solution for smaller code size. itecture Module to th eachinstruction in the MIPS64® instruction set Volume III: MIPS64® III: / microMIP Volume Module to the P Module tothe e Architecture, MDMX is deprecated. riptions riptions of each instruction in me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Architecture microMIPS64™. With Release 5 of th microMIPS64™. With governs the behaviorprivileged of theresources microMIPS of the Architecture, 3 with Release mented at the same time. not applicablethemicroMIPS32™is to MIPS64® Architecture and document nor the microMIPS64™ set docu- ment set. MIPS64® Architecture microMIPS64™ •MIPS16e™ Application-Speci the describes IV-a Volume • describesExtension MDMX the ™ Application-Specific IV-b Volume • describesApplication-SpSmartMIPS® the MIPS ecific Extension to the IV-d Volume • describes the MIPS® MT IV-f Volume •describes the MIPS-3D® Applicatio IV-c Volume •describes the MIPS® DS IV-e Volume •desc detailed II-B provides Volume •MIPS64®the III describes microMIPS64™ and Volume • describesMCUApplicatioMIPS® the IV-h Volume • II-A provides detailed descriptions of Volume •describes I-B conventions used throughoutthe document set, and providesan introduction the to Volume • Module describes to the theMIPS® MIPS® Virtualization Architecture IV-i Volume • describesSIMDArchMIPS® the IV-j Volume The MIPS® For Programmers Architecture consistsfollowing of theture documents: • I-A describes conventions used throughout th Volume MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For About This Book About Chapter 1 Chapter

, S, D register). , such as as , such , which are dress bits used by an that internal state operations can cause Status register es of code and instructiones indicates numbers 5 through operations executed in user 5..1 ged Resource Architecture, Rev. 6.03 ective (for instance, ad ective (for instance, UNPREDICTABLE contents of memorycontents of or results mustnot depend on any datasource floating point instruction formats UNPREDICTABLE uncached ent processor mode. on the and for exampl screen, fonts in this book. and results or operations. behavior, as defined below. behavior, UNDEFINED are used throughout thisbook to describethe behavior of the pro- , write, or modify the the modify or write, , om a hardware perspective (for instance, om a hardware perspective cached courier and UNPREDICTABLE is For instance, is indicated by an ellipsis. and results or results operationshave several implementationrestrictions: accessible in the curr accessible behavior or operations. Conversely, both privileged and behaviorUNDEFINED or operations. Conversely, bold and registers), and various various and registers), and , behavior or operationsonlyof canresult executingas theinstructions occur in lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: , that are important from a software persp , that are important defined ble only to hardware) processor mode. For example, italic UNPREDICTABLE and UNDEFINED that are important fr important that are registers operations must not read operations must UNPREDICTABLE , fields UNDEFINED operationscan causeresultgenerated not. a to be or UNPREDICTABLE fields and , bits emphasis UNPREDICTABLE fixed-widthtextusedis displayed font thatfor is PS is inaccessible in the current UNPREDICTABLE (memory or internal state) that is in or internal state) (memory software, programmable and fields and not programmable but accessi programmable not 1 • • Implementations of operations generating arbitrary exceptions. arbitrary exceptions. pseudocode. a privilegeda theor withMode,usable mode(i.e., in Kernel Mode or Debug CP0 bit set in the UNPREDICTABLE The terms cessor in certain cases. Courier •is used for for used •is •is used for bits for used •is •that is being term a represents •is used for for used •is This section describes the use of describes This section • as such types, the memory access used for is • used is for ranges of numbers; the range Unprivileged softwarecause can never unprivileged software can cause • used to emphasize is 1.2.1 UNPREDICTABLE 1.1.3 Courier Text 1.1.2 Bold Text 1.1.1 Text Italic 16Vo For Programmers Architecture MIPS® 1.2 and UNDEFINED UNPREDICTABLE 1.1 Conventions Typographical About This Book This About

is less y e 100 256). (decimal restore restore the processor to an onment inwhich execution e 100 (decimal 256). If the "b#" 256). If (decimal e 100 Kernel Mode or Debug Mode or in or Debug Kernel Mode d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 17 e hexadecimal valu ation bit (rightmost is 0) is used. If . 1.3 Special SymbolsPseudocode in Notation toenter a state from which thereno is exit other x they can create an envir on, subtraction. y of the reset signals must of the reset signals y Meaning as pseudocode in a high-level language notation resembling . Little-endian bit not x ltiplication (both used for either). for used (both ltiplication arithmetic: additi arithmetic: y (zero length) bit string. length) bit y (zero rnal state that is only accessible in accessible that is only rnal state of bit string z cimal value 100, 2#100 100, 2#100 represents decimal value the the represents instance 10#100 b. For represents the binary value 100 (decimal 4). 0b100 example: 2. For th represents example: 0x100 16. For copies of the single-bit value the copies of y operations or behaviorcause can dataloss. ble in the current processor mode. me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ss-than comparison. through through n in base n in base n in base y operationsnot mustor haltprocessor. hang the UNDEFINED , this expression is an empt z -bit string formed by y Table 1.1 Table Statements Operation Instruction in Used Symbols Tests for equality, inequality. for equality, Tests concatenation. string Bit complement or floating-point 2’s than than Assignment. bits of Selection mu complement or floating-point 2’s A 10. is base the default is omitted, prefix division. Floating-point le complement 2’s comparison. complement greater-than 2’s binary value 16#100 represents 100 (decimal and the hexadecimal 4), valu lists the special symbols used in thesymbolsin pseudocode lists the specialused notation.    y another process. UNPREDICTABLE mode must not access memory or an inte an memory or access not mode must   , ,   y z x  div complement integer division. 2’s 0bn A constant value b#n A constant value 0xn A constant value   x *, mod modulo. complement 2’s Symbol • Algorithmic descriptions of an operation are described Pascal. Table 1.1 valueresults in a legal transientvalue thatwas at some correcttimeprior to thesam- UNSTABLE an of A sampling results mustnot depend on any data source (memory pling. Implementationsoperations of generating UNSTABLE which is inaccessi internal state) or UNDEFINED operations or behavior can have no impoact, or than poweringthan down The assertion the of an processor (hang). operational state. operations ormustcause operations behavior notUNDEFINED processor the can no longer continue.can no longer 1.2.3 UNSTABLE 1.2.2 UNDEFINED 1.3 Symbols in Pseudocode Notation Special MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

is RE LLbit the endianness of the the endianness CPU can be computed as be computed CPU can y exception return instruc- return y exception lable in User mode only. It mode only. in User lable as (SR can be computed ic read-modify-write. ic read-modify-write. . ged Resource Architecture, Rev. 6.03 1 for big-endian). In In User mode, this endi- 1 for big-endian). COC[1] . , x] register. Thus, BigEndian register. onal store. It is cleared (b onal is always zero. In Release 2 of the Architecture, tions that provide atom tions that provide ructions. This feature is avai is feature This ructions. CSS x Status register. Thus, ReverseEndian Thus, register. x. Meaning copies of the CPU general-purpose registers can be imple- of the registers copies CPU general-purpose GPR[0] . ore to the is no ore location longer atomic. s Status into the corresponding 32-bit GPR number. GPR 32-bit corresponding into the has the same value as x general-purpose registers. general-purpose bit in the bit in the , register s RE . . and StoreMemory pseudocode function descriptions), and the endian- and descriptions), function pseudocode and StoreMemory tested by the conditi by the tested x SGPR[ SRSCtl x. x bit of the

x . The content of x RE unit 1), general register unit 1), general in zeros at left-hand-side). in zeros n or equal comparison. and store instructions (0 for little-endian, little-endian, (0 for instructions store and in zeros at right-hand-side). in zeros lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: gured 1 Specifies at chip big-endian). for reset (0 for little-endian, endianness of load and store inst and load endianness of refers to GPR set condition condition . , control register , general register x,register select , general (32 or 64), of the CPU of the 64), or (32 z 2, general register z z erand register erand register state used to specify operation for instruc to specify operation state used SGPR[s,x] virtual s complement less-tha s complement memory interface (see LoadMemory memory interface ness of Kernel mode execution. and Supervisor setting the be switched by anness can set when a linked load occurs and is linked a set when when a st operation, CPU other tions) during is implemented by setting the the by setting is implemented (BigEndianMem XOR (BigEndianMem XOR ReverseEndian). Translation of GPR number the MIPS16e Translation Bitwise logical OR. logical Bitwise 2’ unit Coprocessor Logical shift left (shift register CPU general-purpose 2’s complement greater-than-or-equal comparison. greater-than-or-equal complement 2’s for notation is a short-hand GPR[x] and User mode). and User Bit of mented. op Floating-point Floating-point Floating-point condition code CC. FCC[0] Floating-point (coprocessor (coprocessor Floating-point unit Coprocessor Coprocessor unit Coprocessor Logical shift right (shift Logical shift right Table 1.1Table (Continued) Statements Operation in Instruction Used Symbols   or << >> not Bitwise inversion. norxor NOR. logical Bitwise XOR. logical Bitwise and Bitwise logical AND. &&AND. Logical (non-bitwise) LLbit Xlat[x] FPR[x] FPR[x] GPR[x] COC[z] Symbol CCR[z,x] GPRLENlength, in bits The FCC[CC] SGPR[s,x] multiple Architecture, the of 2 on Release From CPR[z,x,s] CP2CPR[x] unit Coprocessor CP2CCR[x] unit Coprocessor 2, control register ReverseEndian Signal to reverse the BigEndianCPU endianness for load The BigEndianMem Endian mode as confi 18Vo For Programmers Architecture MIPS® About This Book This About

during the PC address of the instruc- . implementations have a implementations ess space. If 40 virtual 40 s the instruction time dur- time s the instruction quences of statements for next instruction. Such an next instruction. Such time is determined by assign- tion. Within one pseudocode one pseudocode tion. Within ograms must not depend on a must not depend ograms = 2 = pseudocode appears to occur. pseudocode appears to occur. in which 64-bit data types are are types data 64-bit which in h the is processor executing. register. . In MIPS32 Release 1, the FPU bytes. appears to occur “at the same the same “at to occur appears 1 36 during an instruction time by any + register. If this bit is a 0, the proces- the 0, this bit is a If register. I ion or the microMIPS base architec- the microMIPS or ion SEGBITS Status = 2 h are significant during a memory ref- symbol PABITS. If 36 physical address symbol PABITS. d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 19 that writesthe result registersection in a Status struction, this is the is the this struction, e stated, all effects of the current instruction current instruction the of effects e stated, all PABITS is always a 0. MIPS64 0. always a is struction, or into a Coprocessor 0 register on an an on register 0 into a Coprocessor or struction, in a segment of the addr ble indirectly, such as when the processorstoresa indirectly, ble ons as a label. It indicate ons as a label. 1.3 Special SymbolsPseudocode in Notation instruction. No label is equivalent to a time label of of label time a to is equivalent No label instruction. Meaning ither earlier or later (during ither earlier or later (during the instruction time of e stored in even-odd pairs of FPRs. In MIPS64 (and, (and, pairs of FPRs. In MIPS64 e stored in even-odd by 2 either (in the case of a 16-bit MIPS16e instruc- for the following instruc I order. However, between between se However, order. not available until after the there is no defined order. Pr there is no defined order. , in which the effect of that , in which the effect I Meaning determines the mode in whic If no value is assigned to PC value is If no bit floating point registers (FPRs) FP32RegistersMode xecute.” Unless otherwis Unless xecute.” lease 3), the FPU has 32 64-bit FPRs ent, the size of the segment 2 is segment of the size the ent, ction operation description ction operation description ll 64-bit address, all bits of whic bits of 64-bit address, all ll for the current instruction labelled for the current is computed from FR in the from the bit is computed address bits implemented al address bits implemented by the by bits implemented address al the physical is address space 2 is computed from the FR bit in the the in FR bit the from is computed description lines and functi and lines description ssor 0 register on an exception. register on ssor 0 ruction time. A taken branch assigns the target address to the to the address the target assigns A branch taken time. ruction 01 32-bit MIPS instructions. instructions. microMIPS or MIIPS16e tion such sections. between eudocode statements labeled eudocode value.instruction During the an in time of is a single-bit register that Encoding 1 implementations, 1 implementations, Operation me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me during an instruction time. time. during an instruction FP32RegistersMode 1. ISA Mode FP32RegisterMode + I tes whether the FPU has 32-bit or 64- Program Counter Program . Sometimes, effects of an instructionSometimes,.appear of effects to occur e stored in any FPR. Release In MIPS32 64-bit thirty-two with operates processor the 1, is a bit this If FPRs. 32-bit thirty-two had it as if sor operates FPRs. The value of address are bits implemented in a segm This iss a prefix to a prefix This iss ing to ing which “e the pseudocode appears optionally, in MIPS32 Release2 and Re Release2 and in MIPS32 optionally, has thirty-two 32-bit FPRs in which 64-bit data types ar data types FPRs in which 64-bit has thirty-two 32-bit In implementation. MIPS32 a were it if FPRs as the references processor the which in mode compatibility case, this time” as the effect of ps of the effect as time” appear to occur during the instruction time of the current of the current time the instruction occur during appear to I tion operation is written in sections labeled with the the with labeled in sections is written the operation tion this happens, instruc another When instruction). instruction current the to relative time instruction example,For an instructionhave can a result thatis has the of the instruction portion instru different instructions that occur “at the same time,” time,” same the “at occur that instructions different particular order of evalua labeled labeled of pseudocode statements The effect in place take of the statements effects the sequence, next instruction during the that occurs the instruction The address of tion word. a value to PC ing pseudocode statement,pseudocode is it automatically incremented tion) or 4 before the next inst before the or 4 tion) instruction time of the instruction in the branch delay slot. delay branch the in of the instruction time instruction the restart stores processor as when the such indirectly, visible is only PC the value MIPS Architecture, In the address into a GPR on a jump-and-link in or branch-and-link exception. The PC value contains a fu The The bits are implemented, the size of combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link on a jump-and-link or branch-and-link Mode into a GPR the upper bits of PC and the ISA value of combined Coproce a into or instruction, In the MIPS Architecture, the ISA Mode value is only visi only ISA Mode value is the the MIPS Architecture, In erence. the tures, Table 1.1Table (Continued) Statements Operation in Instruction Used Symbols :, n: :, I PC I- I+n PABITS Represents the number of physic Symbol SEGBITS Represents the number of virtual ISA ModeExtens Specific In processors Application that implement the MIPS16e FP32RegistersMode Indica MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. [email protected] state.The valuefalse isif ed in the delay slot of a branch of the delay slot in ed static ged Resource Architecture, Rev. 6.03 rn from this pseudocode function; the function; this pseudocode from rn r as the type of exception, and the argument and the argument r as the type of exception, immediately or jump, but branch which is not immediately follows a Meaning statetheof instruction,thenot ing the exception paramete dynamic the was execut Counter address Program chitecturethis document, or send email to specific argument. Control does not retu specific argument. the point of the call. of the the point lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Causes an exception Causes an exception to be signaled us parameter as an exception- signaled at exception is Indicates whether the Indicates whether instruction at executed in delay slot of a branch or jump. the or jump. This or jump. This the condition reflects a branch or occurs to an jump whose PC instruction Table 1.1Table (Continued) Statements Operation in Instruction Used Symbols http://www mips.com laySlot Symbol Various MIPS RISC processor manuals additional and informationproductsbefound about at the MIPS MIPS can Various URL: For commentsor questions on the MIPS64® Ar tion, argument) tion, InstructionInBranchDe- SignalException(excep- 20Vo For Programmers Architecture MIPS® 1.4 More Information For About This Book This About

Chapter 9, components of the components s, as well as specific well as s, as ous instructions such as the system copro- the as such s the mechanismsmanage to the e effects of some e effects nts are visible nts are visible only to the operating ed as such in the architecture docu- such ed as d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 21 CP0 is through vari e CP0 registers are described in 0, the system coprocessor, is required. CP0 is the CP0 is required. is 0, the system coprocessor, r extendsr the functionalityISA, while of the MIPS the CPU. Some coprocessors, the CPU. Some coprocessors, the interaction with them makeupmuch the PRA.of ontrol of the processor state and modes. state and of the processor ontrol l, with one exception: CP ed Resource Architecture (PRA) provide Architecture (PRA) ed Resource critical resources. The interface to critical resources. The interface andard parts of the ISA and are specifi the ISA of andard parts caches, exceptions, and user contexts. contexts. Th caches, and user exceptions, coprocessors. coprocessors. A coprocesso out, Many other componeare user-visible. me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me opcode, including register CP0 the ability the to movefrom, data to, and COP0 ments. Coprocessors are generallyments. Coprocessors are optiona ISA interface to the PRA and provides full c “Coprocessor 0 Registers” on page“Coprocessor 127. cessor and the floating-point unit,are st The CP0 registers provide the The CP0 registers provide the interface between the the ISA and PRA. Th resources of the CPU: virtual memory, virtual memory, resources of the CPU: sharing the instructionfetch andexecution control logic of ing system: , memory handling, : exception an to support of the functions necessary abstraction provides an CP0 management, scheduling, and control of The MIPS ISA provides for upto four The MIPS64 and microMIPS64 Privileg MIPS64 microMIPS64 and The PRA, such as the virtual memory lay PRA,memory such as the virtual to and system kernel systems programmers. encoded with the functionsthat modify The CP0 registers CP0 state. and 2.2.2 CP0 Registers 2.2.1 CP0 - The System Coprocessor MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 2.2 Model MIPS Coprocessor The 2.1 Introduction Architecture Architecture The MIPS64 and microMIPS64 Privileged Resource Resource Privileged microMIPS64 and The MIPS64 Chapter 2 Chapter

ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 22Vo For Programmers Architecture MIPS® The MIPS64 and microMIPS64 Privileged Resource Architecture

reg- Debug form virtual tempt to reference a 64- ties of the processor, as processor, ties of the as a flat, uni as a three conditions are false, ailable to Kernel Mode oper- Kernel ailable to ext switch between processes. ext switch between enabled by 64-bit operations ocessor implements Debug implements ocessor d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 23 Supervisor Mode and EJTAG Debug Mode and EJTAG Supervisor upt, exception, or error. The processor upt, exception, or error. e support for 32-bitthis programs. They do by pro- access is not enabled, an at ided by the ISA, as well by the ISA, as ided register is 0 (if the pr mer can access the full capabili full the mer can access ions that previously were tion, results in an exception. ss to all resources that are av to all resources ss Mode when all of the previous the when all of Mode Debug system environment,system and cont bit in bit the two operating modes: User Mode and Kernel Mode. In User Mode, the DM and 64-bit operations. If wer-up, or as the result of an interr wer-up, plementationtwo additional of modes: register contains 0b00. me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ecture added support for 64-bit coprocessors (and, in particular, 64-bitfloating-pointadded ecture support for coprocessors 64-bit (and,inparticular, Status registeris 1. register is 1. that implements a 64-bit opera Status Status field in the CP0 field in bit inthe bit in the KSU EXL ERL • The The processor is in Kernel Mode is The processor when the For processors that implement EJTAG, the processor is operating in Debug Mode if the DM bit in the CP0 For processors that implement EJTAG, units)Thus, with certainCPUs. 32-bit floating-point instruct The MIPS64 and microMIPS64 PRA requires that are prov CPU and FPU registers the programmer can access Mode, program the system In Kernel space. as changewell thevirtual memory mapping, control the The MIPS PRA also supports the im specification for a description of Debug Mode. Mode. See the EJTAG Release 2 of the MIPS64 Archit on a MIPS64 processorenablednew64-bit by noware floating-point operations. Release 3 introduced the micro- instructionMIPS set, allowing all microMIPS processors to implementfloating-pointa 64-bit unit. The MIPS64 andPRA provide microMIPS64 backward-compatibl viding enables for both 64-bit addressing bit address, or an instruction Mode), and any of the following is true: • The leaves Kernel Mode and enters User Mode or Supervisor Supervisor leaves Kernel Mode and enters User Mode or The processor enters Kernel Mode at po enters Kernel Mode processor The • The ister is 1. If the processor is in Debug Mode, it has full acce in Debug Mode, it has full is 1. If the processor is ister usuallyERET instruction.result of an as the ations. MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 3.2 Mode Kernel 3.1 Mode Debug MIPS64 and microMIPS64 Operating Modes Operating and microMIPS64 MIPS64 Chapter 3 Chapter

. If 64- 1 bit, notthe bit, by UX register is 1. is register register register is 1. register is 1. Status ged Resource Architecture, Rev. 6.03 enables. That is, a reference to user That is, a reference enables. If 64-bit addresses are enabled for the Status Status rmined by the 64-bit address enable the 64-bit address rmined by bit in the the in bit SX bit in the . bit in the KX UX Table 4.2 cessor implements Debug Mode). Debug cessor implements Debug Mode). cessor implements er any of the followinger any of conditions: when all of the following are true: the following are of all when rence, the TLB Refill Vector is used. used. is Vector rence, the TLB Refill register are both 0. register are both 0. the Exception Vector is also dete is the Exception Vector cessor is notis relevantcessor to 64-bit address lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Status Status address space occurs, and the register contains 0b10. contains register register contains 0b01. contains register register is 0 (if register the pro register is 0 (if register the pro Status Status Debug Debug bits in the bits in the ERL ERL field in the field in field in the field in and and bit in the bit in the KSU EXL DM DM KSU EXL bit. • The • The • and the space occurs, address supervisor to a reference legal A reference, the XTLB Refill Vector is used. Refill Vector reference, the XTLB bit addresses are not enabled for the refe are addresses bit Instructions thatoperations perform 64-bit are legalanyfollowing of the under conditions: KX Access to 64-bit addresses are enabled und 64-bit addresses to Access • A legal reference to a kernel The processor is operating in User Mode is operating in User The processor • The The processorisoperatingThe Supervisor in Mode (if that optional mode is implemented thebyprocessor) when of all the following are true: • The • The • The Note that the operating mode of the pro mode of the that the operating Note address made while the processor space is operating in Kernel Mode is controlled by the state of the An attempt to reference a 64-bit address space when 64-bit addresses are not enabled results in an Address Error in an Address results are not enabled addresses 64-bit space when address 64-bit to reference a An attempt ExceptionAdEL (either or AdES, depending on the typeof reference). When a TLB miss occurs, the choice of • A address legal reference to and occurs, a the 1. 2 of see Note For ksseg/sseg access while mode, in supervisor 3.5.2 Operations Enable 64-bit 3.5.1 Address Enable 64-bit 24Vo For Programmers Architecture MIPS® 3.5 Modes Other 3.4 Mode User 3.3 Mode Supervisor MIPS64 MIPS64 and microMIPS64 Operating Modes

bit in the the in bit F64 3.5 Modes Other register is 1. register is are contained in even- not enabledresults ina Status processors. From Release 3 From Release processors. r. In Release 2 of the Architecture, In Release 2 of the Architecture, r. bit is 1, the FPRs are interpreted as 1, the FPRs are is bit uding all microMIPS processors. As of of As processors. microMIPS all uding d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 25 FR e, 64-bit data types =1 is required; that is, the64-bit FPU, with the FR en such instructions are en such instructions bit is 0, the FPRs are interpretedare thebit as thirty-two FPRs is 0, 32- FR register. If the If register. , 64-bit floating-point operations are enabled if the F64 for both MIPS32 and MIPS64 and MIPS64 MIPS32 both for Status under the followingconditions: rvisor Mode, or Debugrvisor Mode, above. Mode, as described =0 32-bit FPU register model32-bit FPUregister =0 continues to be required. FR bit inthe FR the Architecture,the64-bit floating-point operations are enabled64-bit only if also implementfloating-point the Release datatype. 3 introduced the are supported for all processors, incl all processors, for supported are FPRs are supportedprocesso in a MIPS64 rforms64-bit operations wh me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me oating-point is implemented, then UNPREDICTABLE contain a 32-bit (W, S). In this cas In this S). (W, data type a 32-bit contain register is 1. int Operations Enableint Operations register is 1. register Status Status register is 1. FIR bit in the the in bit bit is 0, and an odd register is referenced by an instructionregister is datatypewhoseis 0, and an oddbits. bitis64 bit is 0, 64-bit operations bit is 0, 64-bit operations are enabled, and a floating-point instruction is executed whose datatype is L or register. CU0 FR FR register is 1. The processor must The register is 1. PS. FIR microMIPS instruction set; on all microMIPS processors bit in the in the bit operations enabled. Status =1 64-bit=1model, FPU register The is required. • The bit registers, any of which can of which any registers, bit odd pairs of registers. the Architecture , 64-bit Release1 of In The operation of the processor is operation The • The thirty-twothatregisters can containIf the 64-bittype. any data Access to Coprocessorto Access 0 registers are enabled under anyfollowing of the conditions: • The processorisrunningKernel in Mode or Debug above. Mode, as defined • The FR Access to 64-bit FPRs is controlled by the to Access Instructions that are implementedbya 64-bit floating-pointlegalunitare underthe following any of conditions: • an implementation In of 1 of Release • The processor is operating in Kernel Mode, Supe • In an implementation of Release 2 or later of the , 64-bit floating-point operations are enabled if the • The PX bit in the Reserved Instruction Reserved Instruction Exception. Trying to execute an instruction that pe an instruction that execute to Trying • The processor is operating in User Mode, as described above, and the UX bit in the The lastThe two bullets implythat 64-bit legal operationsare in User Modewhenthe either is UX bit1 in the PX bit or the 64-bit FPRs are supported in a 64-bit floating-point unit, if fl Architecture, Release 5 of the and later of theand later Architecture, of 64-bit FPRs 3.5.5 Coprocessor 0 Enable 3.5.4 FPR Enable 64-bit 3.5.3 Floating-Po 64-bit MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

For processors that Mode Switch” for a Mode processors that implement processors as GPR31 when writtenas GPR31 when a by ged Resource Architecture, Rev. 6.03 zero selects MIPS64. zero selects , Section 5.3, “ISA instruction set family, microMIPS64. can Devices instruction set family, 1 selects microMIPS64. For 1 selects microMIPS64. use when decodinguse when normallyThis bit instructions. is not a jump target address, such a jump target a of second branch the and microMIPS64) or onlymicroMIPS64)and one branch. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: gister for a JR instruction. gister for t the MIPS64 the ISA, ISA Mode bit value of ASE, the ISA Mode bit value of 1 selects MIPS16e. A processor is not allowed to implement both implement both to not allowed is MIPS16e. A processor selects bit ASE, the ISA Mode value of 1 ™ Volume II-B: Introduction to the microMIPS64 Instruction to the Set II-B: microMIPS64 Introduction Volume implement the microMIPS64 ISA, the Mode ISA bit value of the MIPS16e JAL instruction, or the re source For that implemen processors MIPS16e and microMIPS. read Please implement both ISA branches (MIPS64 both ISA branches implement specify to used is whichISA Mode bit ISA branch to The visible to software. Its value is saved to any GPR used as Release 3 of the Architecture introduced introduced of the Architecture Release 3 detailed description of ISA mode switching between the ISA branches and the ISA Mode bit. 3.5.6 ISA Mode 26Vo For Programmers Architecture MIPS® MIPS64 MIPS64 and microMIPS64 Operating Modes

EntryLo1 (Read Inhibit) (Read and RI is expected to be in to be is expected registers for PTE soft- bit. ). EntryLo0 ). ELPA bit. MaskX ESP EntryLo1 ecificationnot do overlap. VPN2X and PageGrain field to the left by two bits, when 1 kB d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 27 on is optional because several operating SP PageGrain EntryLo0 ler than 4 kB. Such usage the SmartMIPS™ ASE specification, but bits the SmartMIPS™ ASE specification, but Config3 field in the the in field nded, or suggested, to replace the default 4 kB page size; to or suggested, nded, ion to the architecture to ease 2 added an optionalarchitecture extension to the by the SmartMIPS ASE sp bit and by the enabled PFN LPA LPA bit; it is enabledbythe rol bits are added to each TLB entry. These bits, These bits, entry. each TLB added to bits are rol SP SP registers to shift the Config3 for two lower-order physical address bits. physical for two lower-order field must done with be an explicitenable. (and subsequent optional releases), support for 1 kB pages was added for Config3 MIPS processors require more than 36 bits of physical address (for example, PFN ly into these registersTLB Refillcompatibility exception. on a for Thus, with EntryLo1 eases of the Architecture eases of the ess for MIPS64 processors. This extensi register to enable writes to, and use of, bits 12..11 ( to enablewritesregister to, and use of, bits 12..11 e minimumas with optionalsize was 4 kB, page pages supportfor as large me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me and register to enable writes to, and use of, bits 12..11 ( bits 12..11 of, use and to, enable writes to register ed bits to the left of the the of left the to bits ed register. This register is also used by register. EntryHi PageMask EntryLo0 , allow more types of protection to be used for virtual pages, including write-only pages and PageGrain (Execute Inhibit) used by Release 2 of the Architecture and those used those Architecture and used by Release 2 of the page support is enabled, to create space is enabled,page support XI • Modification of the Support for extended is denoted PFNs by the • Modification of the non-executable pages. and In Release In Release 3 of the Architecture, two optional cont conjunction with a default page size of 4 kB and is not inte is not default page size of 4 kB and conjunction with a Architecture,theInRelease the 1 of physical addresswas size limitedthe by theformat of 256Architecture the 2 of Release MB. In In Release In Release 1 of the Architecture, th require access to pages smal access to that require use in specific embedded applications registers to 36 bits. Some applications of Rel Thus, are expected. others and networking), high-end provideup to 59 bits of physical addr systems currently use the reserv • Modification of the ware ware flags. The flags are loaded direct existing software, the extensionof the rather, toaugment it. rather, Support for 1 kB pages involves thefollowing changes: • Additionthe of Support for 1 kB pages is denoted by the 4.1.3 Memory Pages Protection of Virtual 4.1.2 Physical Memory 4.1.1 Memory Virtual MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 4.1 between Rel Differences Virtual Memory Virtual Chapter 4 Chapter

registers can register, then register, is a configuration bytes, but may be may but bytes, 62 bytes, depending on EntryHi igurations. Six Seg- bits. bits. 31 XI / or 2 or RI 29 Context/XContext ers containinga address pointer ted, the actual size of the Segment is ted, the actual size ged Resource Architecture, Rev. 6.03 (EVA) feature. EVA feature. EVA (EVA) lowing direct access to user-mode memory to user-mode lowing direct access the Release 3 version of the base architec- fied by Segment Conf set of memory regions specified by Segment specified of memory regions set is used to represent the actualofthe number bits is used to represent med to define two address ranges, a three-GB two address define med to generated for generated a particular addressing mode. There atible virtual address space. hing a virtual address to the region specified in a in Seg- specified region the to address a virtual hing , such as an entry in the page table entry (PTE) array. In as an entry , such in the page (PTE) table entry array. SEGBITS -kernel access modes, and a one-GB address range with range one-GB address and a modes, access -kernel modified original from the definition.SmartMIPS For bits can be separately implemented. For the Release 3 ver- re instructions al xed-sizedstructure 16-byte in array memory within a linear XI registers are a read/write regist and the 64-bit Address Space and is no larger than 2 than is no larger and Address Space the 64-bit RI Compatibility Address Space that is mapped into a subset of the 64-bit subset of the into a is mapped Space that Compatibility Address Compatibility Address Space and is either 2 Compatibility Address 40 virtual address bits are implemen 40 virtual address bits rence and access behavior. A 32-bit and access behavior. reference self-consistent has Space that ss are used when a TLB access does not obey the access does not TLB when a used are entation Control is program is entation Control optional Enhanced Virtual Addressing optional Enhanced Virtual lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Context/XContext d, fully mapping the 32-bit Comp d, fully mapping the 32-bit set of kernel mode load/sto kernel mode set of and attributes of each region are also speci also and attributes of each region are e virtual address space is definable as the definable as is space virtual address e ure includes an optional programmable segmentation feature. This improves the flexibil- e SmartMIPS ASE. Thisoptionale feature is in is feature, each is feature, of the is the range of all possible addresses that can be addresses possible all of is the range bytes. Software can determine the value of SEGBITS by writing all ones to the 40 is a defined subset of an Addre subset defined is a = 2 = Address Space Address Segment SEGBITS Compatibility Segment is part of the 32-bit Segment is part of the Compatibility ture. smaller on an implementation-dependent basis. The symbol implemented in each 64-bit Segment. So, if range with mapped-user, mapped-supervisor, and unmapped mapped-supervisor, range with mapped-user, mode. mapped-kernel access A An is one 64-bit Address Space and one 32-bit Space Address is one 64-bit Address Space. In Release 3 of the Architecture has an In Release 3 of the Architect space. virtual address of the MIPS ity SegmentationControl, address translationbegins by matc With ment Configuration. Thus, th In Release 3 of the Architecture, the the In Release 3 of the Architecture, behavior The Configurations. This feature originatedSmartMIPS in thebeenbut ASE has the Release 3 version of th the Release sion of this feature, new exception codes codes this feature, new exception of sion be used more generally. be used more generally. in th This feature originated the specific Segment.Segmentof A 64-bit is part to an arbitrary power-of-two alignedto arbitrary an data power-of-two structure inmemory pointerReleases 1 and 2, this was defined to reference a fi Release Thethe 3 version of containingeven/odd an entry for eachpair. page virtual 2 of Segmentation Control and a Segmentation of Segm In EVA, mode. from kernel space ment Configurations are define 4.2.1 Address Space 4.2.2 Segment and Segment Size (SEGBITS) 4.1.6 Addressing Enhanced Virtual 4.1.5 Control Segmentation 4.1.4 Context Register 28Vo For Programmers Architecture MIPS® 4.2 Terminology Virtual Memory Virtual

-byte 32 bytes. The format of the bytes. The format of fields to calculate the fields to calculate the 36 Fill 4.3 Virtual AddressSpaces . As such,if 36 physical gments selected by bits 63..62 = 2 Address Spaces, including the Address 4 architecture implicitly defines, 4 architecture implicitly defines, and icroMIPS32 processors, a 2 icroMIPS32 processors, bytes. Software can determine the determine Software can bytes. PAB IT S PABITS PFN 36 d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 29 ace is ace is sub-divided similarly into Seg- registers, then reading the back. Bits read value as shows the layout of the shows the MIPS64/microMIPS6 is is sub-divided into four Se field allow software todetermine theboundary between the EntryLo1 two non-contiguousin rangesthethe which upper 32 bits of or Figure 4.1 r 32-bit programs and MIPS32/m EntryLo0 of the physical address space would be 2 space would be of the physical address bit 31. The Compatibility Address Sp segmentation of each Address Space. of each Address segmentation me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me culate the valueculate the of SEGBITS. a 64-bit virtual Address Space; th Address 64-bit virtual a registers implicitly limits the physical address to 2 size field allowsoftware to determine the boundary the between EntryLo1 PFN and

of the virtual address. To provide compatibility fo of the virtual address. To address bits were implemented, the size bits were implemented, address With support for 64-bit operations and address calculation, With The numberphysicaladdressThe of bits implemented isrepresented by the symbol EntryLo0 for, support and provides reading the value back. Bits read as “1” from“1”reading the VPN2 value the as back. Bits read VPN2 and Fill fields to cal to fields Fill VPN2 and value of PABITS by writing all ones to theto by writingones all ofvalue PABITS CompatibilityAddress Space into is defined, separated 64-bit address are the sign extension of extension the sign address are 64-bit ments selected by bits 31..29 of the virtual address. “1” from the “1” from value of PABITS. Compatibility Address Space and the and Space Address Compatibility 4.2.3 Physical Address Size (PABITS) MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 4.3 Address Spaces Virtual

ible ible ible ible ible Type Segment Segment SX 64-bit UX 64-bit KX 64-bit KX 64-bit 64-bit 64-bit Always 32-bit Compat- Always 32-bit Compat- Always 32-bit Compat- Always 32-bit Compat- Always 32-bit Compat- Enable t is referenced. For exam- Address modes (User, Supervisor, Supervisor, modes (User, that or a more privileged more that or a 4.3 Virtual AddressSpaces )

1 ) Mode is not accessible when 31 62 31 ror Exception. The “Reference ror 1 1 -2 - 2 - bytes ing in a less privileged mode than less in a ing bytes bytes bytes bytes bytes regions regions PAB IT S 1 bytes bytes 31 29 29 29 29 Actual d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 31 2 2 2 2 2 8 2 SEGBITS SEGBITS Segment Segment can be referenced legally. en the processor is running in User, is runningprocessor en the in User, byte SEGBITS byte Segment within2 the (2 2 (2 Segment Size ess Size (PABITS)” ess Size for an explanation of the symbols e three processor operating Kernel Kernel Kernel Kernel the processor is running in running is the processor Mode(s) Supervisor Supervisor e mode from which the Segmen Reference Legal from er mode, while the Segment name “kuseg” denotes a refer- t associated with Supervisor t associated User User User User Kernel Kernel Kernel Kernel Kernel Kernel Kernel Kernel Kernel Kernel Supervisor Supervisor Supervisor Supervisor with Mode Associated 4.2.3 Addr “Physical is not accessible if the processor is runn if the processor accessible is not and ed with User Mode is accessible wh Mode is accessible User ed with ssociated with one of th e 4-2 lists the modes from which each modes from the 4-2 lists e me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Table 4.1Table Spaces Address Memory Virtual gment. For example, a Segmen gment. For example, a through through through through through through through through through ent Size (SEGBITS)” ent Size 0xFFFF FFFF FFFF FFFF FFFF FFFF 0xFFFF 0000 FFFF E000 0xFFFF 0xFFFF FFFF DFFF FFFF FFFF DFFF 0xFFFF 0000 FFFF C000 0xFFFF 0x0000 0000 7FFF FFFF 0000 7FFF 0x0000 0000 0000 0000 0x0000 0x3FFF FFFF FFFF FFFF FFFF FFFF 0x3FFF 0000 0000 8000 0x0000 0xBFFF FFFF FFFF FFFF FFFF FFFF 0xBFFF 0000 0000 0000 0x8000 0x7FFF FFFF FFFF FFFF FFFF FFFF 0x7FFF 0000 0000 0000 0x4000 0xFFFF FFFF BFFF FFFF FFFF BFFF 0xFFFF 0000 FFFF A000 0xFFFF FFFF FFFF 9FFF 0xFFFF 0000 FFFF 8000 0xFFFF FFFF FFFF 7FFF 0xFFFF 0000 0000 0000 0xC000 , respectively. lists the same information lists the same tabularin form. sseg useg PA BI T S ksseg suseg kuseg kseg1 kseg0 xkseg xsuseg xksseg xkuseg Name(s) Range Address Maximum Segment and Supervisor, or Kernel Modes. A Segment Supervisor, If a Segment has more than one name, each name denotes th ple, the Segment name “useg” denotes a reference from us ence to the same Segment from kernel mode. kernel from ence to the same Segment that associated with the Se Er a reference results in an Address such the processor is running in User Mode, and Tabl column in Mode(s)” Legal from Each Segment of an Address Space is a Table 4.1 mode. For example, mode. For example, a Segment associat or Kernel). A Segment with associated a mode is accessible if 4.2.2 “Segment and Segm 63..62 0b11 kseg3 0b00 xuseg 0b10 xkphys 0b01 xsseg SEGBITS VA MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 1. See

. : 2 ). Ref- = 1. DM Section 4.9 Section 4.6 Mapped ior when when ior Uncached Table 4.1 TLB (KX=0) TLB TLB (KX=0) TLB Refill Vector: Refill Debug Refill Vector Refill XTLB(KX=1). XTLB(KX=1). See See See for special behav- special for : 2 ed from Operating Operating from ed ace as a function of the pro- Mode Mode Kernel Mode ) are enabled only if the appro- if the only ) are enabled able” column of able” column Supervisor TLB (KX=0) TLB XTLB(KX=1). Refill Vector ion also must implement the kseg3 implement ion also must ged Resource Architecture, Rev. 6.03 1 Table 4.1 Action when Referenc Action when Address Error Mapped , and the “64-bit En sseg ksseg kseg3 Error Address Error Address Mapped kseg1 Error Address Error Address Unmapped, ement thefollowing Compatibility 32-bit Segments: Name(s) Segment sor using translat TLB-based address = 40, = 36 UserMode n in the “Segment Type” column of n in the Type” “Segment lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: through through through Assuming PABITS behavior is listed for each reference. listed for each reference. is vector and other special behavior TLB Refill ection of SEGBITS Segments are always Segments enabled. 0xFFFF FFFF E000 0000 FFFF E000 0xFFFF 0xFFFF FFFF FFFF FFFF FFFF FFFF 0xFFFF 0xFFFF FFFF C000 0000 FFFF C000 0xFFFF 0000 FFFF A000 0xFFFF 0xFFFF FFFF DFFF FFFF FFFF DFFF 0xFFFF FFFF FFFF BFFF 0xFFFF able is on (see Section 3.5.1(see able is on 24 on page Virtual AddressVirtual Range lists the action taken by the processor for each section of the 64-bit Address Sp Address the 64-bit section of for each the processor by lists the action taken through through through Symbolic 32-bit Compatible Segment. Table 4.2 A MIPS64/microMIPS64 compliant processor must impl • useg/kuseg •kseg0 •kseg1 A MIPS64/microMIPS64-compliant proces The sel operating mode. cessor’s References toSegments 64-bit (as show References priate 64-bit Addresspriate 64-bit En erences to 32-bit Compatible erences to Table 4.2Table Mode of Operating a Function as Selection TLB Refill and Access Space Address 0xFFFF FFFF E000 0000 FFFF E000 0xFFFF 0xFFFF FFFF FFFF FFFF FFFF FFFF 0xFFFF 0xFFFF FFFF C000 0000 FFFF C000 0xFFFF 0000 FFFF A000 0xFFFF 0xFFFF FFFF DFFF FFFF FFFF DFFF 0xFFFF FFFF FFFF BFFF 0xFFFF 32Vo For Programmers Architecture MIPS® 4.5 Address and Operating Mode of as a Function Control Access 4.4 Compliance Virtual Memory Virtual

. . XTLB. XTLB. Section 4.6 Section 4.7 SX = 0. SX = 1. KX = 0. KX = 1. Segment. Mapped if Mapped if Unmapped. tain address Refill Vector: Refill Refill Vector: Refill See See See See Address Error if Error Address ranges within the KX = 0, or in cer- ed from Operating Operating from ed Mode Mode Kernel Mode XTLB. SX = 1. SX if SX = 0. SX = if Mapped if Supervisor Refill Vector: Refill 1 d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 33 Action when Referenc Action when Address Error Error Address Address Error Error Address Error Address Address ErrorError Address Error Address Address Error Error Address Error Address xsseg xkseg Address Error Error Address Address Error if kseg0 Error Address Error Address Unmapped xksseg xkphys Address Error Error Address Address Error if Name(s) Segment 4.5 AccessControl as a Function of Address and Operating Mode = 40, = 36 UserMode through through through through through through through me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Assuming PABITS SEGBITS 0xC000 00FF 7FFF FFFF 00FF 7FFF 0xC000 0000 0000 0000 0xC000 0x8000 0000 0000 0000 0000 0000 0x8000 0xBFFF FFFF FFFF FFFF FFFF FFFF 0xBFFF 0x4000 0100 0000 0000 0100 0000 0x4000 FFFF FFFF FFFF 0x3FFF 0000 0100 0000 0x0000 0x7FFF FFFF FFFF FFFF FFFF FFFF 0x7FFF 0xC000 00FF 8000 0000 00FF 8000 0xC000 0xFFFF FFFF 7FFF FFFF FFFF 7FFF 0xFFFF 0xFFFF FFFF 9FFF FFFF FFFF 9FFF 0xFFFF 0000 FFFF 8000 0xFFFF 0x4000 00FF FFFF FFFF 00FF FFFF 0x4000 0000 0000 0000 0x4000 31 - 1 Virtual AddressVirtual Range - 2 31 - 1 S - 2 - SEGBITS SEGBITS through through through through through through through SEGBIT 2 2 SEGBITS Symbolic 2 FFFF 8000 0000 FFFF 8000 SEGBITS + 2 2 0x3FFF FFFF FFFF FFFF FFFF FFFF 0x3FFF 0xC000 0000 0000 0000 0000 0000 0xC000 0x8000 0000 0000 0000 0000 0000 0x8000 0xBFFF FFFF FFFF FFFF FFFF FFFF 0xBFFF 0xFFFF 0xFFFF FFFF 9FFF FFFF FFFF 9FFF 0xFFFF 0xC000 0000 0000 0000 0000 0000 0xC000 0xFFFF FFFF 7FFF FFFF FFFF 7FFF 0xFFFF 0x4000 0000 0000 0000 0000 0000 0x4000 0x7FFF FFFF FFFF FFFF FFFF FFFF 0x7FFF + 0000 0000 0000 0x0000 + 0000 0000 0000 0xC000 + 0000 0000 0000 0x4000 + 0000 0000 0000 0x4000 Table 4.2Table Mode (Continued) Operating of a Function as Refill and TLB Selection Access Space Address MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. =1. =1. =0. ERL ERL ERL Section 4.8 XTLB. Section 4.8 UX = 0. UX = 1. Mapped if Mapped if Status Status Unmapped if Status TLB (UX=0) TLB Refill Vector: Refill Refill Vector: Refill tion dependent tion dependent behavior when XTLB(UX=1). See See See for implementa- Address Error if Error Address rency attribute of ed from Operating Operating from ed d coherency attribute for d coherency Uncached bytes of physicalmemory; Mode 29 Mode Kernel Mode XTLB. done, as well as the source of as done, UX = 1. Mapped if UX = 0. Mapped if Supervisor TLB (UX=0) TLB Refill Vector: Refill Refill Vector: Refill Address Error Address Error XTLB(UX=1). ged Resource Architecture, Rev. 6.03 1 cacheability and cohe and cacheability XTLB. UX = 1. Mapped if UX = 0. Mapped if Action when Referenc Action when TLB (UX=0) TLB Refill Vector: Refill Refill Vector: Refill Address Error Address Error XTLB(UX=1). register. The cacheability an register. through Address Cache Attribute useg suseg xuseg kuseg y and Coherency Attributes for the y and Coherency Attributes xsuseg xkuseg Config Name(s) Generates Physical Segment 0x0000 0000 1FFF FFFF 0000 1FFF 0x0000 0000 0000 0000 0x0000 describes howthistransformation is s for data references s for data references when the processor and the UX is in User Mode running = 40, = 36 UserMode Table 4.3 or other address translation unit. The unit. translation address other or lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: through through Assuming PABITS SEGBITS through 0x0000 00FF FFFF FFFF 00FF FFFF 0x0000 0000 0000 8000 0x0000 0x0000 0000 0000 0000 0000 0000 0x0000 0x0000 0000 7FFF FFFF 0000 7FFF 0x0000 0xFFFF FFFF A000 0000 FFFF A000 0xFFFF 0xFFFF FFFF BFFF FFFF FFFF BFFF 0xFFFF Virtual AddressVirtual Range - 1 for the special treatment of the of the addres treatment special for the kseg1 through through SEGBITS Symbolic 2 Segment Name Address Virtual Range the kseg1 Segment is always Uncached. always is the kseg1 Segment the cacheability and coherency attributes for each Segment. The kseg0 and kseg1 Unmapped Segments provide a window into the least significant 2 these are not translated using the TLB using translated these are not the kseg0 Segment is supplied by the K0field of the CP0 Section 4.10 bit is bit zero. 0x0000 0000 8000 0000 0000 8000 0x0000 0x0000 0000 0000 0000 0000 0000 0x0000 0x0000 0000 7FFF FFFF FFFF 7FFF 0000 0x0000 + 0000 0000 0000 0x0000 Table 4.2Table Mode (Continued) Operating of a Function as Refill and TLB Selection Access Space Address 2. SX bit. not the KX bit, the of state by the is determined to sseg/ksseg for references Vector Refill that the Note 1. See Table 4.3Table Segments kseg1 and Cacheability Address kseg0 the for Translation, Attributes and Coherency 34Vo For Programmers Architecture MIPS® kseg0 and kseg1 Segments 4.6 and Cacheabilit Translation Address Virtual Memory Virtual

. 0 N/A into the entire Table 9.11 Uses encoding Uses encoding 7 of Register. + ess Error Exception occurs, occurs, Error Exception ess From K0 field of Config From K0 field shows the interpretationthe shows of the h provides a window h provides - 1 - d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 35 Table 4.4 through and has the same encodingthesame and has shownin as that PABITS Address Cache Attribute Physical Address 2 Address Error Address Error N/A 61..59 Generates Physical nd-Coherency Attributes for the nd-Coherency through are non-zero. If no Addr Address Cache Attribute 0x0000 0000 0000 0000 0000 0x0000 0x0000 0000 0000 0000 PABITS Generates Physical 58.. 0x0000 0000 1FFF FFFF 1FFF 0000 0x0000 0000 0000 0000 0x0000 virtual address field. oherency Attributes for the kseg0 and kseg1 Segments kseg1 and kseg0 the for Attributes oherency -1..0 -1..0 = 36 s eight address ranges, each of whic of ranges, each s eight address PA BI T S through through through PABITS PABITS PABITS-1 Assuming PABITS ncy attribute is taken from VA me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me through 0xB800 0000 0000 0000 0000 0xB800 0000 0000 0010 0xB000 0xB800 0010 0000 0000 0010 0xB800 FFFF FFFF 000F 0xB800 FFFF FFFF FFFF 0xB7FF 0xBFFF FFFF FFFF FFFF FFFF 0xBFFF 0xFFFF FFFF 8000 0000 FFFF 8000 0xFFFF 0xFFFF FFFF 9FFF FFFF 9FFF FFFF 0xFFFF Figure 4.2Figure Segment xkphys the for Interpretation Address 4.7 Address Translation and Cacheability-and-Coherency Attributesthe for xkphys Segment Virtual AddressVirtual Range - 1 . An Address Error ExceptionError VA . An Address if occurs PABITS PABITS kseg0 bytes of bytes physical memory;it as such, is not translated the using TLB or other address translation unit. For this 2 2 through through through PABITS Table 4.4 Table Segment xkphys the for Attributes Cacheability and Translation Address 2 Symbolic Segment Name Address Virtual Range 10 CCA Address Error if Non-Zero PA BI T S 2 various fieldsvirtual of the address when referencing the xkphys Segment. Table 9.11 The xkphys Unmapped The xkphys Unmapped Segment comprise the physical address is taken from the VA is taken the physical address Segment, the cacheability and cohere and Segment, the cacheability 63 62 61 59 58 0xB7FF FFFF FFFF FFFF FFFF FFFF 0xB7FF 0xBFFF FFFF FFFF FFFF FFFF FFFF 0xBFFF 0xB800 0000 0000 0000 0000 0000 0xB800 0xB000 0000 0000 0000 + 0000 0000 0xB000 0xB800 0000 0000 0000 + 0000 0000 0xB800 + 0000 0000 0000 0xB800 Table 4.3Table Cacheability AddressTranslation, and C MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 4.7 and Cacheability-a Translation Address xkphys Segment xkphys

. . . N/A N/A Table 9.11 Table 9.11 Table 9.11 3 of Table3 of 9.11). Uses encoding Uses encoding 5 of Uses encoding Uses encoding 6 of Uses encoding 4 of Cacheable (see encoding encoding (see Cacheable + + + ged Resource Architecture, Rev. 6.03 - 1 - - 1 - 1 - - 1 - PABITS through through through through PABITS PABITS PABITS Address Cache Attribute 2 2 2 + 2 Address Error Address Error Address Error N/A Generates Physical 0x0000 0000 0000 0000 0000 0x0000 0x0000 0000 0000 0000 0000 0000 0000 0x0000 0x0000 0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 = 36 through through through through through through through Assuming PABITS lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 0x9800 0000 0000 0000 0000 0x9800 0xA000 0000 0000 0000 0000 0xA000 0000 0000 0010 0x9800 FFFF FFFF 000F 0x9800 0xA800 0000 0000 0000 0000 0xA800 0000 0000 0010 0xA000 FFFF FFFF 000F 0xA000 FFFF FFFF FFFF 0x9FFF 0xB000 0000 0000 0000 0000 0xB000 0000 0000 0010 0xA800 FFFF FFFF 000F 0xA800 FFFF FFFF FFFF 0xA7FF 0xB000 000F FFFF FFFF 000F 0xB000 FFFF FFFF FFFF 0xAFFF Virtual AddressVirtual Range - 1 - 1 - 1 - 1 PABITS PABITS PABITS 2 2 2 through through through through through through through PABITS PABITS PABITS PABITS Table 4.4 Table Segment xkphys the for Attributes Cacheability and Translation Address 2 2 2 2 Symbolic 0xA7FF FFFF FFFF FFFF FFFF FFFF 0xA7FF 0xAFFF FFFF FFFF FFFF FFFF FFFF 0xAFFF FFFF FFFF FFFF 0x9FFF 0x9800 0000 0000 0000 0000 0000 0x9800 0xA000 0000 0000 0000 0000 0000 0xA000 0xA800 0000 0000 0000 0000 0000 0xA800 0xB000 0000 0000 0000 0000 0000 0xB000 0xA000 0000 0000 0000 + 0000 0000 0xA000 0xA800 0000 0000 0000 + 0000 0000 0xA800 0000 + 0000 0000 0x9800 + 0000 0000 0000 0xB000 0000 + 0000 0000 0xA800 0000 + 0000 0000 0xA000 + 0000 0000 0000 0x9800 36Vo For Programmers Architecture MIPS® Virtual Memory Virtual

= 1 ERL . . N/A Table 9.11 Table 9.11 code to operate = 1 2 of Table2 of 9.11). Uses encoding Uses encoding 1 of Uses encoding 0 of Uncached (see encoding encoding (see Uncached ERL + + + he error exception uncached Segment, similar to the to Segment, similar uncached - 1 - 1 - - 1 - d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 37 through through through PABITS PABITS PABITS Address Cache Attribute 2 2 2 Address Error N/A Address Error N/A Address Error Generates Physical 0x0000 0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 0000 0000 register. This allows the cac This allows register. = 36 4.8 Status when Segment kuseg the for Translation Address Status e kuseg Segment when Status through through through through through through Assuming PABITS me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me 9000 0000 0000 0000 0x9000 0000 0x8000 0010 0000 0000 0010 0x8000 0000 0000 0000 0x8000 0x8800 0010 0000 0000 0010 0x8800 0000 0000 0000 0x8800 FFFF FFFF FFFF 0x87FF FFFF FFFF 000F 0x8000 0x9000 0010 0000 0000 0010 0x9000 FFFF FFFF FFFF 0x8FFF FFFF FFFF 000F 0x8800 0x97FF FFFF FFFF FFFF FFFF 0x97FF FFFF FFFF 000F 0x9000 bit is set inthe bit is ERL Virtual AddressVirtual Range - 1 - 1 - 1 PABITS PABITS PABITS 2 2 2 through through through through through through PABITS PABITS PABITS Table 4.4 Table Segment xkphys the for Attributes Cacheability and Translation Address 2 2 2 Symbolic uncached using GPR R0 as a base register to save other GPRs before use. to save other GPRsregister before a base using GPR R0 as uncached kseg1 Segment, if the kseg1 Segment, To support the cache error handler, Segment the kuseg becomes an unmapped, support the cache error handler, To 0x87FF FFFF FFFF FFFF FFFF FFFF 0x87FF 0x8000 0000 0000 0000 0000 0000 0x8000 0x8800 0000 0000 0000 0000 0000 0x8800 0x9000 0000 0000 0000 0000 0000 0x9000 0x97FF FFFF FFFF FFFF FFFF FFFF 0x97FF 0x8FFF FFFF FFFF FFFF FFFF FFFF 0x8FFF 0x8000 0000 0000 0000 + 0000 0000 0x8000 + 0000 0000 0000 0x9000 0000 + 0000 0000 0x8800 + 0000 0000 0000 0x9000 0x8800 0000 0000 0000 + 0000 0000 0x8800 0x8000 0000 0000 0000 + 0000 0000 0000 0x8000 4.8 for th Translation Address MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

= 0 UX 0xFFFF FFFF

= 1 case is not done for instruc- case is not done for cessors must implement the ple given above, it cleans up DM TAG specification for details onthis TAG ged Resource Architecture, Rev. 6.03 addresses (those in whicha 31 bit is al memory-mappedregion. Mode with Status equal zero, and the 32-bit virtual address is is virtual address and the 32-bit zero, equal , inclusive, , inclusive, a as memory-mapped special 31 64-bit Processor or Mode with the appropriate 64-bit address enable off e sufficient. Unfortunately, there are cases in which a are there Unfortunately, sufficient. e instructionmust be sign-extended bit from 31into bits ddress that isddress thatlegal in 32 bits, but whichisnot appropri- for instruction references) when the processor is running l data addresses. In the exam e TLB or cache. This special- TLB or cache. This e 0xFFFF FFFF 8000 0000 8000 FFFF 0xFFFF FFFC 7FFF FFFF 0xFFFF code, MIPS64 compliant pro ded to the sign-extended displacement as a 64-bit quantity. 64-bit quantity. as a displacement sign-extended ded to the +0xFFFF FFFF FFFF FFFC FFFF FFFF +0xFFFF is zero)a full 64-bit into doesnot address. This meanthe normal register. register. 31 EJTAG blocktreat must the virtual address range EJTAG an address thatproperly is notan addresssign-extended. Status les can apply in some cases. See the EJ les can apply in some 0xFFFF FFFF FF3F FFFF FFFF FF3F 0xFFFF sign-extended address for all illegal data all illegal address for sign-extended is address calculation results in a valid useg address. However, on a 64-bit on pro- calculationvalid address useg address.is in However, a results lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: e kseg3 Segment when Debug Segment e kseg3 by a load, store, or prefetch by references (and explicitly not 0x7FFF FFFC 0x7FFF 0x8000 0000 0x8000 +0xFFFF FFFC +0xFFFF 32-bit Processor 64-bits. For example: is included in the speci FFFF is included in the 0xFFFF FFFF FFFF la 0x80000000 r10, lw -4(r10) r10, and FF20 0000 tion references. This results in a properly zero-extended for all address lega the address. This results in a properly properly in a This results the address. one). Coderunning Kernel Mode, or SupervisMode, in Debug 63..32 of the fulladdress, 64-bit ignoring63..32 of previous the contents 63..32 of bits of the address,addressfinal before the th or used to access exceptions error is checked for address The effective address calculated address effective The sign-extended (really zero-extended, because VA On a 32-bit processor, the result of th On a 32-bit processor, ad register is in the base cessor the sign-extended address backward provide compatibility Mode withUser 32-bit To The results of executing this address calculation on 32-bit and 64-bit processors with UX = 0 is shown below: When the processor is running in User Mode, legal addresses have VA This results in a carry-out of bit 31, producing If EJTAG is implemented on the processor, the implemented is on the processor, If EJTAG in User Mode andModezero in thethe UX bit in User is address boundssign-extended checks on the ar 64-bit address program runningcan generatedataprocessor a a on a 32-bit into sign-extended ately following special case for data 0xFFFF FFFF FF20region in Debug Mode. A MIPS64/microMIPS64 must: compliant implementation that also implements EJTAG through 0000 • explicitly range-check the address range as given, that the entire and not assume region between •Debugmode. mappingthis region for onlyEJTAG in special enablethe EJTAG Even in Debug mode, normal memory ru mapping. 38Vo For Programmers Architecture MIPS® 4.10 in User References Data Behavior for Special 4.9 th Behavior for Special Virtual Memory Virtual

=0. KX is also appli- Section. 4.10 Status address is pro-address is address, This is Enhanced Virtual Enhanced Virtual gn-extension. Canon- legal put addresses to a canoni- to put addresses . to the target address after to the target ruction addresses. Release 5 Release ruction addresses. e a canonical address, which . If such an applies applies all to architectural may be a be may definitionfor further detail. de with StatusUXde with = 0” lt of canonical si d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 39 Status to canonical happens if the resultant resultant to canonical happens if the uses a 64-bit instruction when UNPREDICTABLE control flow instruction. The Address Error 0x8000_0000 0x8000_0000 thisexample, the resultant64-bitis cor- address to 2 inputs of address generation in Release 5 or prior, lease 5 onwards), which means a legal base address legal base address lease 5 onwards), which means a checklimited is toa singleinput as indexed addressing User) and both data and inst CD, CACHE, PREF, SYNCI (and EVA extensions such SYNCI (and EVA CD, CACHE, PREF, ferences ferences User Mo in cal checkcal is performed on the inputthe effec- operands of there is a carry-out of bit 31 case is Release 6 Jump Immediates (JIC/JIALC), where it Immediates (JIC/JIALC), where 6 Jump Release is case e canonical error is propagated rred to as DMEMREFrred to as in the pseudo-code below. ibility regions - software must avoidsuchcases. nced Virtual Addressing (EVA), where user modedata where Addressing (EVA), nced Virtual gn-extended immediate and creat l Addressingl the default to behavior described in ADDIUPC, ALUIPC, AUIPC, LWPC, LWUPC, LDPC. LWUPC, ADDIUPC, ALUIPC, AUIPC, LWPC, for Release 5 EVA, and Release 6 and 5 EVA, for Release In Release 6, or Release 5 implementations that support EVA, the Release6, 5 implementations or In Release that support EVA,

=0. UX ferences in User Mode with StatusUX = 0” User in ferences duced in Release 5. In 5. Release duced in atible virtual address range as a resu 4.11Compatibility 32-bit Addressing for Release and 5 EVA, Release 6 describe the new behavior. See CP0 describe the new behavior. Status

n if, for example, kernel software that the 32-bitthat the base address of me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me 64-bit instructions. 64-bitIf the input is non-canonical, thenan AddressError mustbesig- 32-bit compatibilityapply to: instruction itself, or at the target of a of a the target or at instruction itself, KX/SX/UX undetected.non-canonicalconversion This of Status ”, a MIPS32 feature intro Section 4.10 “Special Behavior for Data Re as LWE). These instructions are generically refe instructions These LWE). as • An instructionfetch address. •LLD/S LL/SC, Load/Store, instruction such as a An • instructions : Branch, Release 6 PC-relative • PC-region instructions : Jump, Jump and Link, Jump and Link Exchange • Control-transfer Jump Register instructions. •address generation. Walker Page Table Hardware rectly placed in the lower 2GB 32-bit comp 2GB rectly placed in the lower address generation. The only exception for the control-flow is possible for the non-canonicalto be added base to a si Error is Address the means address crosses the boundary betweenthecompat 32-bit The canonical sign-extensioninputscould check of apply up to which supportthe indexed In Release 6, memory references. has been eliminated. addressingThe extensions for exception is able to be taken at the target itself because th itself because betaken exception is able to at the target cable to Release 5 with EVA except EVA 5 with Release cable to implementations withEnhanced no support for Virtua duced, the operationthe instruction of generating such an address is Addressing (EVA) Addressing above 2GBabovebegenerated can by user software. User The Segmentmay be extended by virtue of “ because the MIPS32 User Segment can exceed 2GB (from Re because the MIPS32 User Segment can ical sign-extensionisgeneration thea 64-bit of sign-extension address byfrom bit 31. ReleaseAll 6 implementations must support newthe addressing extensionscompatibility. for 32-bit Forimplementations all the canoni supportingthis behavior, in non-canonical aliasing of accidental prevent the The check is to address generation. tive address, which can happe cal effective Kernel mode can always execute addressing naled, either by the The example in Release 5 extensions of same sign-extensionapplies to all modes (Kernel/Supervisor/ releasesReleaseto prior 5, and Release 5 withoutEnha addresses are sign-extended only when are sign-extended addresses Section 4.10 Re “Special Behavior for Data is prohibitedwhich address in from generatingeffective an MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 4.11 Addressing 32-bit Compatibility

, EPC so the change takes

canonically compli- ate value to CP0 ate KX/SX/UX For the latter case, software must . Status ged Resource Architecture, Rev. 6.03 is typically always is iting an inappropri C, LWPC, LWPUPC, LDPC donot LWPUPC, LWPC, C, applies to such instructions. PC-Regionalso Jumps =1)) e 6, as the pseudo-code excludes instructionsas the pseudo-code excludes 6, e in Release For speculativeinstruction therules forfetch addressing EVA instruction and data addressing instructions. It can be ication of effective_address() willofformer the takecare ication of effective_address() ess generation includes speculative non-instructionbased and in its absence, the PC is sign-extended. the its absence, in and JALR.HB) after the MTC0 that changes changes are identical to the rules for control flow instruction execution : the for controlthe rules execution flow instruction to identical changes are =1 and Config5 =1 and address generation, as the PC itself the generation, as address describes the new scheme for effective address generation for 32-bit compati- generation for address for effective new scheme the describes AR lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: to be canonically non-compliant by wr function effective_address() function effective_address() that is incompatible with the current state of PC

e Release e Release 6 ADDIUPC, ALUIPC, AUIP (decode(DMEMREF)) and decode(INDEXED DMEMREF)) and canonical_error(offset)) ) canonical_error(offset)) and DMEMREF)) and decode(INDEXED =1 AR ea = base + offset base + ea = Error cause Address load/store) (eg insts memory // data target. error at take instructions addressing // Other endif + offset) sign_extend(base ea = KX/SX/UX Indexed DMEMREF only applies pre-Release 6 pre-Release applies only Indexed DMEMREF Status >= 2 or (Config >= 2 else offset = base + ea

AR or (EffKSU=0b01 and Status.SX=0) and (EffKSU=0b01 or ) Status.UX=0) and (EffKSU=0b02 or SignalException(AddressError) // 32-bit Compatible Addressing? 32-bit Compatible // ( if and Status.KX=0) (EffKSU=0b00 // 64-bit Addressing // 64-bit else endif EVA not 6 and Not Release // Config ((Config if not canonical. is or offset when base No sign-extension // by MMU. ea is translated on when later may occur error An address // // endif ( if or canonical_error(base)

elseif EffKSU = EffKSU() EffKSU 5) (Release present or EVA 6 (always) Release // if ( require canonical checks of the inputs to checks canonical require it is required that the ant. However, instructions. PC-relative of category same the into fall errantly cause the PC Software may Instruction fetch and Hardware Page Table Walker addr Walker Instruction Table Page Hardware fetch and addressingwhich to32-bit the compatibility rules also apply. due to sequential fetch and control-flow fetch PC be checked must for Address Error, and PC-relativBranch instructions execute an instruction hazard barrier (e.g., an instruction hazard barrier execute or writing a value to 5 if Enhanced Virtual Addressingnot supported. is Enhanced5 if Virtual applied to all mentioned instructions in 5Release and Releas effect no later than the target of the hazard barrier. Appl barrier. of the hazard target than the no later effect case. The pseudo-code for effective_address pseudo-codeble addressing. is applied The to specifically 40Vo For Programmers Architecture MIPS® function effective_address(base, offset) effective_address(base, function Virtual Memory Virtual

d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 41 =1) EXL efetch/Load-Linked/Store-Conditional/SyncI) =1 or Status =1 or =0 and decode(DMEMREF) ) =0 decode(DMEMREF) and EXL UX 4.11Compatibility 32-bit Addressing for Release and 5 EVA, Release 6 KSU ive_Address Generation Function me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ) is to be used by specific instructions classes in the manner described below. =1 or Status =1 or DM Status Debug ea = base + offset + = base ea return true return false return true return false return ((addr[31] = 0) and (addr[63:32] != 0x0)) ) != 0x0)) (addr[63:32] = 0) and ((addr[31] else endif else endif itype input if (opcode=itype) else data input {{32{data[31]}},data[31:0]} return input addr input or != 0xFFFFFFFF)) and (addr[63:32] = 1) ( ((addr[31] if // pre-Release 5 special user handling with UX=0... with handling user 5 special pre-Release // if ( EffKSU=0b10 and Status and ( EffKSU=0b10 if effective_address(GPR[index],offset) • (Load/Store/Cache/Pr Reference Memory Data + offset) sign_extend(base ea = // Effective // Effective KSU EffKSU sub The function effective_address( endsub type. specific is of opcode instruction whether Determine // decode(itype) sub endsub 31 bit from Sign extend // sign_extend(data) sub endsub endsub 31. bit from sign-extended value is 64-bit whether Determine // (addr) canonical_error sub endif

4.11.1 Use Cases for Effect

DMEMREF)) (decode(EVA if ( 0b10 elseif return endif 0b00 else return return MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For endfunction

e ASID comparison comparison e ASID translation section cludes themapping region . There are two entries in the trans- in entries . There are two ged Resource Architecture, Rev. 6.03 e ASID, the G(lobal) bit, and a recom- Release 2 and subse- mber (PFN, and in Release Table 9.11 anslation” on page descriptions of alterna- 351 for ASIDs to each process, and the TLB keeps track of keeps and the TLB ASIDs to each process, 1 The comparison section in section The comparison ation mechanism. Sufficient TLB entries must be imple- TLB entries mustation mechanism. Sufficient try. The physical The single entry. sizes with a page different ical translation section. operating system assigns the valid encodings are given in which over-rides a global (G) bit whichth includes over-rides this, the TLB lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ich contains the physical page frame nu op on load and store instructions.loadop on and store diate (Release 6 JIC/JIALC) of virtual pages, and the pair of phys- each TLB entry maps an aligned pair of virtual pages, because l Address Translation effective_address(GPR[index],offset) effective_address(PC,offset) effective_address(PC,immediate) effective_address(GPR[index],GPR[index]) effective_address(GPR[index],0) • PC-Relative (Branch/ADDIUPC/ALUIPC/AUIPC/LWPC/LWUPC/LDPC) • PC-Region (J/JAL/JALX) • Load/Store/Prefetch) 6 Indexed (pre-Release Memory Reference Data Indexed • Jump Register with no Immediate • Jump Register with Imme A.1 page MMU” on “Fixed Mapping A.2 347 and Address Tr “Block specifier (R) and the virtual(VPN2 and, in Release 2 and subsequent page numberVPNX, releases, which is the vir- th tual page number/2 entry maps twophysicalsince pages)each of the entry, mendedfield that maskmapping allows each of wh entries, pair of contains a quent PFNX),valid releases, a dirty (D) bit,bit, a (V) optionally read-inhibitandandbits, XI) execute-inhibit & (RI a cache coherency field (C) for which lation section for each TLB entry ical translation entriesto corresponds the even and odd pair. pages of the tive MMU organizations. each ASID during address translation. In certain circumstances, the operating system may want to associate the same to associate may want the operating system certain circumstances, translation. In each ASID during address addressvirtualall with processes; for during translation. logical compo- two structure for translating virtual Each entry contains fully-associative addresses. TLB is a The nents: a comparison section, and a phys The TLB-based translation mechanism supports translation TLB-based The Address Space Identifiers to uniquely identifythe same virtual The processes. different across address This sectiondescribes the TLB-based virtual address transl lo mented to avoid a TLB exception 1. See 4.12.2 TLB Organization 4.12.1 Identifiers (ASID) Address Space 42Vo For Programmers Architecture MIPS® 4.12 TLB-Based Virtua Virtual Memory Virtual

EntryLo1 , and V1 V0 must beable must to handle ocess. In processors that ocess. In processors EntryLo0 D1 D0 , XI1 ASID EntryHi , RI1 . Similarly, odd come page entries . Similarly, inates, the possibility of the exception. the inates, Architecture that report multiple TLB d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 43 port multipleoneither TLB matches a lease 1 of the Architecture. the 1 of lease C1 C0 G PageMask EntryLo0 TLB to enable more secure access of memory of access enable more secure TLBto 4.12 TLB-Based Virtual Address Translation

Maskx VPN2X cal addresses. Neithercal addresses. of set extensions in an is present the TLB during the power-up pr power-up the TLB during the addressfrom size36-bit the limit inRelease 1. Light Mask ssor implementations are limited to reporting multiple TLB the fields in the CP0 most implementationsmost of Re ) or a TLB read (TLB access or TLBR or TLBP instructions). In Release Release or TLBP instructions). In TLBRor (TLB access ) or a TLB read Binitialization routine that, on implementations2(and subse- of Release tion algorithm that minimizes, elim or minimizes, that algorithm tion inatesthe possibility of reporting a machine check during TLB initialization. on implementations of Release 1 of the ght that are requiredghtsupport toare that 1 kB page sizes. Medium grey fields denote cessor implementations can detect and re detect implementations can cessor PFN0 PFN1 VPN2 the TLB (such as PFN0) come from as PFN0) come the TLB (such me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Figure 4.3Figure a TLB Entry of Contents ure, the RI and XI bits were added to the to were added bits RI and XI the ure, e 1 of the Architecture. . Optional Release 3 features added for additional security. additional for added 3 features Release Optional physical addresses. larger to 2 required suport Optional Release features Optional Release 2 features required to support 1 kB to support Release 2 features required pages. Optional R shows the logical arrangement of a TLB entry, includingoptional the support added Release 2 of the in theshows logical a TLB arrangemententry, of PFNX PFNX EntryLo1 2 (and subsequent releases) of the Architecture, proce write;of onlymatchesa TLB on this is also true TLB write (TLBWI or TLBWR instructions (TLBWI or TLB write The following code example shows a TL of the Architecture, elim quent releases) effect equivalent an This example has registers. The even page entries in from In many processor implementations, software must initialize The fields of the TLB to correspond exactly entry pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, and no-execute access write-only, bits (along pages. These with the Dirty bit) allow the implementation of read-only, policies for mapped pages. Figure 4.3 Architecturepage sizes and for 1 kB in the increase physical grey fields denote extensions ri to the extensions to the left that are required to supportphysi larger multipledetect TLB matches, and signal assumption, this throughmachine-check software a such an exception or use a TLB initializa In Release 1 of the Architecture, pro In Revision 3 of In Revision the architect implementation of Releas 4.12.3 TLB Initialization MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. =0x0 IE Config4 other implementations. The ged Resource Architecture, Rev. 6.03 ty of such an on exception lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: va += Page_Size; va += dmtc0 C0_EntryHi t0, TLBP_Write_Hazard()tlbpTLBP_Read_Hazard()mfc0bgez C0_Index t1, 10b t1, */ candidate VA /* Write R1/2) */ in (ssnop/ehb hazard EntryHi /* Clear */ in R1/2) (ssnop/ehb hazard Index /* Clear */ match check for flag to back /* Read */ an entry duplicate about to if /* Branch */ a match for TLB to check the /* Probe dmtc0 C0_EntryLo0 zero, dmtc0 C0_EntryLo1 zero, dmtc0 C0_PageMask zero, la */ valid bits PFN and out /* Clear A_K0BASE t0, * mask register out /* Clear */ == 0xFFFF.FFFF.8000.0000 /* A_K0BASE * InitTLB * entries all that guaranteeing state, to a power-up the TLB Initialize * and invalid. unique are * * * Arguments: ** * Returns: a0** =* Restrictions: No value of C0_Config1) field MMUSize (from index TLB Maximum ** * Algorithm: space in unmapped called must be routine This *** va = kseg0_base; * { 0, entry--) entry >= max_TLB_index; (entry = for { (TLB_Probe_Hit(va)) while PFN values are off, bits that valid so and EntryLo1 EntryLo0 Clear PageMask, * is used. page size default and the are zero, * */ if if is to see the TLB and probe EntryHi to VA candidate Write the * a machine may cause to the TLB a write is, it there. If already * try again. page and by one the VA candidate just increment check, so * */ *} **} * * Notes: 0, 0, 0); va, TLB_Write(entry, *** -* appropriate to the expand code below in the used Hazard macros The * the 1 of of Release an implementation in of SSNOPs number */ of 2 of Release in an implementation an ehb and to Architecture, 121 for on page Hazards,” , “CP0 See Architecture. the information. additional more 10: /* InitTLB: /* TLB */ of the the VA part for of kseg0 address the base Start with /* /* exceptionsonly write and minimizes on a TLB the probabili followingexampledonotis that for processors implement TLB invalidate instructions, that is: 44Vo For Programmers Architecture MIPS® Virtual Memory Virtual

=1), =1), SC Config3 he VPN2 field) of the TLB the TLB of field) he VPN2 d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 45 4.12 TLB-Based Virtual Address Translation esses to be writtenVPN2 to the field of the TLB entry ented. Instead, use the TLB ented. Instead, TLB feature. The invalidate ble Entry held in the TLB entry is valid. This Valid bit theble Entry heldin TLB entry This is valid. Valid whether the virtual address (t whether the virtual tion Control is implemented and is required for FTLB/ ny unmapped address regions. For this reason, theabove ations with the TLB. For MIPS64 processors running 32-bit /* Use this as next TLB index */ index TLB as next this /* Use */ in R1/2) (ssnop/ehb hazard Index /* Clear */ TLB entry the /* Write to do */ entries more TLB if /* Branch index the TLB /* Decrement caller */ to /* Return esses. When esses. Segmentation Control is implemented ( bit set. register. If this bit is is bit this If visible throughthe EntryHi theEHINV field of register. field is marked as invalid, the entry is ignoredmatchinvalid, fieldthe on address for entry is is marked as EHINV VPN2 ), there are three ways to initialize a TLB entry: the TLBINV, TLBINVF, and and TLBINVF, there are three), to initialize ways TLBINV, TLB entry: the a IE EntryHi me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me implement TLB invalidatethe instructions, code to initializethe TLB is much simpler: entry has been initialized. Config4 entry with the mtc0TLBW_Write_Hazard() C0_Index a0, tlbwi bneaddiu zero, 10b a0, -1 a0, mtc0dmtc0 C0_Index zero, C0_EntryHi zero, jrnop ra daddiu (1<

form the virtual page form the virtual page quent releases) implementa- ged Resource Architecture, Rev. 6.03 Comment s, and larger physicaladdresses.in For clarity the dis- larger and s, tions that 1 support kB pages concatenate the fields to VPN2 and VPN2X number for a 1 kB page. kB a 1 for number neral sense to include the new Release 2 features: neral sense VPN2  VPN2X Release 2 (and subse lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: VPN2 This routine must be called in unmapped space in unmapped called must be routine This dmtc0 C0_EntryLo0 zero, dmtc0 C0_EntryLo1 zero, mtc0ori C0_PageMask zero, dmtc0 zero, 0x400 t0, C0_EntryHi t0, */ valid bits PFN and out /* Clear mtc0TLBW_Write_Hazard() C0_Index a0, tlbwi */ register mask out Clear /* bneaddiu zero, 10b a0, -1 a0, field */ VPN2 bit, Clear EHINV /* Set */ in R1/2) (ssnop/ehb hazard Index /* Clear */ index TLB as next this /* Use mtc0dmtc0 C0_Index zero, C0_EntryHi zero, jr to do */ entries more TLB if /* Branch nop raindex the TLB /* Decrement */ TLB entry the /* Write caller */ to /* Return Term Used BelowTerm Release 2 Substitution * Restrictions: * for all constant state leave the to simply and EntryHi Clear Index * * returns */ * Clear PageMask, EntryLo0 and EntryLo1 so that valid bits are off, PFN values off, are bits that valid so and EntryLo1 EntryLo0 PageMask, Clear * is used. page size default and the are zero, * */ * Algorithm: ** * Notes: with EntryHi.EHINV=1 entry Each TLB Write *** -* appropriate to the expand code below in the used macros Hazard The * the 1 of of Release an implementation in SSNOPs of number */ of 2 of Release in an implementation an ehb to and Architecture, 121 for page on Hazards,” , “CP0 See Architecture. the information. additional more 10: /* InitTLB: /* Release 2 ofintroduced the ArchitectureRelease 2 support for 1 kB page cussion below, take the following take the in terms the ge below, cussion 4.12.4 Address Translation 46Vo For Programmers Architecture MIPS® Virtual Memory Virtual

). This ))) and SP Mask stored within the register at the time Config3 the final physical address eld in the TLB entry, or the eld in theTLB entry, d the reference was a store, a itecture thatitecture includes 1 kB PageMask ion fetch, a TLB invalid (or N fields to form the form the to N fields physical addresses con- addresses physical C, V, and D bits (and optionally RI C, V, its that are in the set Mask fields. offield the VPN2 ds in each entry by ignoring each bit in each entry ds quent releases) implementa- and not (TLB[i] and equent releases) equent releases) implementa- ent process ASID are presented to the presented ASID are ent process Comment d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 47 try and no dirtyand exception, the PFN s s a load, a TLB Invalid (or TLBRI) excep- of the two PFN entries is read is a function 4.12 TLB-Based Virtual Address Translation register is register is not implemented, the TLB operation is -1..13 SEGBITS bits of the address to form ed. If the dirty an bit is off tions that larger support PF and PFNX catenate the page physical number. tions that 1 support kB pages the concatenate care Mask and fields to form the MaskX don’t mask for 1 kB pages. )) then register) matches the register) matches ASID fi equent releases) of the Arch of the releases) equent PageMask ASID nd the reference was an instruct was reference nd the )) = (va )) EntryHi Mask separated intosets of pseudo two code: fferent page size, as page size, as determined by the fferent its is determined by the Mask fiel ght of the section masked with the Mask entry. masked with the ght of the section itten with the encoding for a 4 kB page. kB 4 for a the encoding itten with VPN2 field corresponding to those b = EntryHi = lease 1 of the Architecture, or an implementation of Release 2 (and subse- Release of implementation Architecture, or an lease 1 of the ge number match the corresponding bits ASID ed, the virtualtheand page number curr ) and me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me multaneously formatch, a which occurs when all of thefollowing conditions are true: 63..62 e translation section of the TLB entry. Which of the e translation section TLB entry. and not (TLB[i] and VPN2 or (TLB[i] G PFN PFNX || PFN Release 2 (and subs Mask Mask  MaskX 2 (and subse Release (TLB[i] if (TLB[i]R = va if (TLB[i]R ((TLB[i] Term Used BelowTerm Release 2 Substitution This lets each entry each entry This lets of the TLB support a di in the virtualin the page number and the TLB TLB entry. The “appropriate” number of b “appropriate” number of The TLB entry. G bit is set in the TLB entry. set in the is G bit that the TLB entry was written. If the recommended instanceis called the “4 kB TLB Lookup”. page support. calledis This instance the “1 kB TLB Lookup”. found  0 found i in 0...TLBEntries-1 for as if the PageMask register had been wr register if the PageMask as quent releases) of thequent Architecture of not releases) does that includedenoted 1 kB page supportby(as • Bits 63..62address of the virtualthe match region R field of the TLB entry. the code in • Theof appropriate bitsvirtual the pa 2.an implementation One used by subs of Release 2 (and The 4 kB TLB Lookup pseudo code is: When an address translation is is request When an address translation si are checked entries TLB. All • The current ASID (as obtained process from the The valid and dirty bits (and optionally RI and XI bits) determine the final success of the translation. If the valid bit is the entryoff, is not valid, and a TLB Invalid exception is rais If a TLB entry matches the address If a TLB entry matches the address and ASID presented, the corresponding PFN, th from read are and XI bits) of the virtual address bit immediately to the ri 1.an implementation One used by of Re TLB Modified exception is raised. If there match with a valid en is an address TLB exception is raised. If there Modified offset-within-page the appended to are the cache coherency bits with attributes.wa If and the reference the set, RI bitis and implis emented tionraised. If theXIis bit implemented is andset, a is TLBXI) exception is raised. thelookup TLB processes have been For clarity, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. Table 4.5 on page 51 e not page shown. The larger ged Resource Architecture, Rev. 6.03 es feature (1 GB and larger) es ar feature (1 GB and larger) ) then ) then ) SM SM ) then ) 2 = 0) = 0) SM IEC = 0) = 0) it 30 for the EvenOddBit, 4 GB use bit 32. See IEC RI1 XI1 RI0 XI0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: or Config3 or Config3 UNDEFINED PFN0 PFN1 RXI RXI C1 D1 V0 C0 D0 V1 or Config3 SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBRI, = 0 then = 0 TLB[i] TLB[i] TLB[i] TLB[i] RXI Mask # PC relative loads are allowed where execute is allowed execute where allowed are loads relative # PC if (PageGrain else endif ri  ri  and (IsPCRelativeLoad(PC)) = 0) if (xi else xi  xi  endif if (PageGrain EvenOddBit if (ri = 1) and (reftype = load) then = load) and (reftype (ri = 1) if c  TLB[i] d  TLB[i] if (Config3 endif reftype) SignalException(TLBInvalid, v  TLB[i] c  TLB[i] d  TLB[i] if (Config3 endif  TLB[i] pfn v  TLB[i] 12 /* 4KB page */ /* 4KB 12  EvenOddBit 0000 0000: 0000 0b0000 */ page /* 16KB 14  EvenOddBit 0000 0011: 0000 0b0000 */ page /* 64KB 16  EvenOddBit 0000 11xx: 0000 0b0000 */ page /* 256KB 18  EvenOddBit 0011 xxxx: 0000 0b0000 page */ /* 1MB 20  EvenOddBit 11xx xxxx: 0000 0b0000 page */ /* 4MB 22  EvenOddBit xxxx xxxx: 0011 0b0000 */ page /* 16MB 24  EvenOddBit xxxx xxxx: 11xx 0b0000 */ page /* 64MB 26  EvenOddBit xxxx xxxx: xxxx 0b0011 */ page /* 256MB 28  EvenOddBit xxxx xxxx: xxxx 0b11xx otherwise: endif then = fetch) and (reftype (xi = 1) if pfn  TLB[i] pfn he page size in the matching TLB entry. Not all page sizes need sizes page all entry. Not TLB matching in the size he page # EvenOddBit selects between even and odd halves of the TLB as a function of a function TLB as the of odd halves and even between selects # EvenOddBit # t endif v = 0 then if endif if (Config3 endcase if va else # be implemented on all processors, so the case below uses an ‘x’ to uses an below so the case all processors, on implemented # be would select implementation actual cases. The don’t-care # denote sizes page the with compatible is that a way bit in even-odd # the implemented. # actually TLB[i] case sizes follow the sizes follow same pattern: 1 GB pages use b 2. page sizes available through the larger BigPag the For brevity, 48Vo For Programmers Architecture MIPS® Virtual Memory Virtual

))) and . Mask Table 4.5 on page 51 e not page shown. The larger and not (TLB[i] and d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 49 4.12 TLB-Based Virtual Address Translation -1..13 SEGBITS EvenOddBit-1..0 )) then PABITS-1..12 ASID es feature (1 GB and larger) es ar feature (1 GB and larger) )) = (va )) || va ) then ) SM Mask 3 it 30 for the EvenOddBit, 4 GB use bit 32. See = EntryHi = ASID RI0 XI0 ) and or Config3 UNDEFINED corresponds to pa to corresponds PFN0 me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me RXI alException(TLBXI, reftype) alException(TLBXI, V0 C0 D0 = 0 then = 0 63..62 TLB[i] TLB[i] Mask and not (TLB[i] and SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, Sign -1-12..EvenOddBit-12 PABITS VPN2 or (TLB[i] ri  xi  endif else G EvenOddBit PABITS-1-12..0 pfn v  TLB[i] c  TLB[i] d  TLB[i] if (Config3 endif 10 /* 1KB page */ 1KB page  10 /* 00: EvenOddBit 0000 0000 0000 0b0000 */ 4KB page  12 /* 11: EvenOddBit 0000 0000 0000 0b0000 */ 16KB page  14 /* xx: EvenOddBit 0000 0011 0000 0b0000 */ 64KB page  16 /* xx: EvenOddBit 0000 11xx 0000 0b0000 */ 256KB page  18 /* xx: EvenOddBit 0011 xxxx 0000 0b0000 */ 1MB page  20 /* xx: EvenOddBit 11xx xxxx 0000 0b0000 */ 4MB page  22 /* xx: EvenOddBit xxxx xxxx 0011 0b0000 */ 16MB page  24 /* xx: EvenOddBit xxxx xxxx 11xx 0b0000 */ 64MB page  26 /* xx: EvenOddBit xxxx xxxx xxxx 0b0011 */ 256MB page  28 /* xx: EvenOddBit xxxx xxxx xxxx 0b11xx otherwise: endif SignalException(TLBModified) pfn  TLB[i] pfn else endcase if va pa   1 found break endif then = store) (reftype (d = 0) and if endif # pfn # EvenOddBit selects between even and odd halves of the TLB as a function of a function as the TLB of odd halves even and between selects # EvenOddBit need sizes all pages entry. Not TLB matching in the page size # the ‘x’ to uses an below so the case all processors, on implemented # be would select implementation actual cases. The don’t-care # denote sizes the page with compatible that is a way bit in even-odd # the implemented. # actually TLB[i] case (TLB[i] if (TLB[i]R = va if (TLB[i]R endif reftype) SignalException(TLBMiss, ((TLB[i] found  0 found i in 0...TLBEntries-1 for endfor if found = 0 then endif sizes follow the sizes follow same pattern: 1 GB pages use b The 1 kB TLB Lookup pseudo code is: 3. page sizes available through the larger BigPag the For brevity, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

or Gener- EntryLo0 (PABITS-1)..0 e page size of the TLB entry that entry of the TLB e page size ged Resource Architecture, Rev. 6.03 ected PFN and the offset-in-page bits bits theected PFNand offset-in-page indicates which virtual address bit is used to EvenOddBit-1..0 PABITS-1..10 || va ) then ) SM ) then ) = 0) = 0) SM ess is generated as a function of tha function of ess is generated as IEC = 0) = 0) cal address is generated from the sel generated is cal address IEC RI1 XI1 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: or Config3 corresponds to pa to corresponds PFN1 RXI C1 D1 V1 or Config3 SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBRI, e “Even/Odd Select” column of Table 4.5 e “Even/Odd TLB[i] TLB[i] RXI # PC relative loads are allowed where execute is allowed execute where are allowed loads relative # PC if (PageGrain SignalException(TLBInvalid, reftype) SignalException(TLBInvalid, reftype) SignalException(TLBXI, else endif -1-10..EvenOddBit-10 PABITS ri  and (IsPCRelativeLoad(PC)) = 0) if (xi else xi  else endif endif if (PageGrain PABITS-1-10..0 pfn pfn  TLB[i] pfn then = load) and (reftype (ri = 1) if c  TLB[i] d  TLB[i] if (Config3 endif reftype) SignalException(TLBInvalid, v  TLB[i] endif SignalException(TLBModified) endif then = fetch) and (reftype (xi = 1) if pa   1 found break endif v = 0 then if endif if (Config3 endif then = store) (reftype (d = 0) and if endif # pfn demonstrates how demonstrates the physical addr endif reftype) SignalException(TLBMiss, registers, has one of two and ranges: bit endfor if found = 0 then endif EntryLo1 Table 4.5 matches the virtual address. Th The “PA select betweenthe even (EntryLo0) odd (EntryLo1) or matching entrythe inentry. TLB ated From” columns specify how the physi how the ated From” columns specify virtualin the column, address. In thisthe physical PFN is page number as loaded into the TLB from the 50Vo For Programmers Architecture MIPS® Virtual Memory Virtual

47 0  21 0 23 0 25 0 27 0 29 0 31 0 33 0 35 0 37 0 39 0 41 0 43 0 45 0 9 0 11 0 13 0 15 0 17 0  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA

-1)-10 0 -1)-10 2 -1)-10 4 -1)-10 6 -1)-10 8 -1)-10 38 -1)-10 10 -1)-10 12 -1)-10 14 -1)-10 16 -1)-10 18 -1)-10 20 -1)-10 22 -1)-10 24 -1)-10 26 -1)-10 28 -1)-10 30 -1)-10 32 -1)-10 34 -1)-10 36 (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS PFN PFN d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 51 PFN PFN PFN or Release 2 (and sub- 2 (and Release or PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN entation without support without entation Release 2 (and subsequent) withSupport 1 kB Page Enabled omment C Generated From: Generated 4.12 TLB-Based Virtual Address Translation -1)..0 47 0 21 0 23 0 25 0 27 0 29 0 31 0 33 0 35 0 37 0 39 0 41 0 43 0 45 0 11 0 13 0 15 0 17 0 19 0  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA  VA (PABITS

PA Release 1 implementation, Release 1 sequent releases) implem for 1 kB pages implementa- subsequent releases) (and Release 2 enabled kB pages 1 support for with tion -1)-12 0 -1)-12 2 -1)-12 4 -1)-12 6 -1)-12 8 -1)-12 36 -1)-12 10 -1)-12 12 -1)-12 14 -1)-12 16 -1)-12 18 -1)-12 20 -1)-12 22 -1)-12 24 -1)-12 26 -1)-12 28 -1)-12 30 -1)-12 32 -1)-12 34 subsequent) Not Applicable (Release 1) or(Release 1) (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS (PABITS -1 12 -1 10 =1. =1. Disabled (Release 2 & PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN PFN BPG PABITS PABITS 1 kB Page Support Unavailable1 kB Page Support PA PA me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Table 4.5Table Generation Address Physical 40 42 44 46 48 22 24 26 28 30 32 34 36 38 10 12 14 16 18 20 VA VA VA VA VA VA VA VA VA VA VA VA VA VA VA VA VA VA VA Select -1)-12 0 -1)-10 0 Even/Odd Even/Odd (PA B I T S (PA B I T S N PFN Range Range PA PF PFN 1 1 1 1 1 1 1 1 1 1 1 kB VA 4 kB 1 MB 4 MB 16 kB 64 kB 1 TB 4 TB 1 GB 4 GB 64 MB 64 16 MB 16 16 TB 64 TB 256 kB 16 GB 64 GB 256 MB 256 TB 256 GB 256 Page Size 1. only if Config3 .This page size is available MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

remain for an

Config5 UX and the

1XAM Status SX, es of segments are segments of es SegCtl ble for these controls Status KX, e. Coprocessor 0 registers 0 registers Coprocessor e. backward compatible with backward Status at address space, or used to alter the or used to alter space, at address ged Resource Architecture, Rev. 6.03 fied by Segment Configurations. Six Configurations. Segment fied by MT or under Segmentation Control” e set of by memory regions specified Seg- and cacheability attribut and cacheability Config well as various configuration fields. tributes with programma tributes hing a virtual address to the region specified in a in Seg- specified region the to address a virtual hing xed while kseg0/1 have their cacheability and mappa- Table 9.29 onfigurations are always activ onfigurations are always e MIPS64 virtual address space. virtual address e MIPS64 = 1), addressing control bits

=1 Table 9.30 Table SC ingCompatibility the 32-bit address virtual space. ERL registers,andreset the BEVexceptions may use another segment which ws into the physical space. address Section 4.13.1 “Exception Behavi used to implement to implement a fully used translated fl virtualin themap MIPS CPUfrom prevents address being a fully virtual- Status Config3 attributes of each region are also speci of each attributes lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: its mappability attribute fi SegCtl* contain six Segment Configurations as ual address space is therefore definable as th definable as therefore space is ual address proves the flexibility of proves the th mapping disabledis 64 virtual address memory map, the mappability memory map, the mappability 64 virtual address l is implementedl is ( n access control modes are specified in modes control n access fixed. Segmentation Control at replaces these fixed register fields.

2XR ment Configuration. The virt ment Configuration. The attributes. Control system can be The Segmentation ized. Another use of Segmentation Control is to remove the unmapped segments from the virtual address map. Future supportfor CPU virtualization wouldSegmentation require Control. SegmentationControl, address translationbegins by matc With bility attributes bility attributes The existence of the segments unmapped In the traditional MIPS mostly fixed. Foruseghas example, uncached windo and relative size of cached Besides the segments controlled by explanationexceptions on how interact with programmable segmentation. MIPS64The xkphysmemory is divided into8regions, these regions are configurable via the If SegmentationIf Control is implemented, the Segment C ment Configurations. The behavior and ment Configurations. SegmentConfigurations are defined, fully mapp When Segment Contro SegCtl • Cache attribute when mapping is disabled • uncached when to unmapped, Force •when address Physical contains additional controlandconfiguration fields. are: The attributes of a Segment Configuration • modes supervisor and kernel, user, from permissions Access • Enable mappingtranslation) (address the using MMU specified in SegCtl0, SegCtl1, and SegCtl2 As an optionalAs an alternative fixed memory to segmentation,programmable a segmentation controlfeature has been im 3. This to Release added is active only in kernel mode. Please read Please only in kernel mode. is active On reset, SegmentConfiguration default is implementationspecific. A configuration MIPS64 legacy fixed segmentation is defined by Segment configuratio active. 52Vo For Programmers Architecture MIPS® 4.13 Control Segmentation Virtual Memory Virtual

the processor is operating is the processor 4.13 Segmentation Control ), KERNEL (AM = UK, MK orMK (AM = UK, ), KERNEL d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 53 are used together with the xkphys access con- the xkphys access together with used are field. Table 9.29 XAM bit is set. is bit Status SX, Control. Thexkphys memory regions are enabled by the SegCtl1 of KERNEL are allowed when KERNEL are allowed when of Status bitsof UX and SX , bit is set. is bit KS USER (AM = MUSK, MUSUK or UUSK). MUSUK or MUSK, USER(AM = KX ciated minimum privilege level ( bit is set. me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me on Control is described below: described is Control on UX Status  SegCtl0.CFG0  SegCtl0.CFG1  SegCtl1.CFG2  SegCtl1.CFG3  SegCtl2.CFG4  SegCtl2.CFG4  SegCtl2.CFG5 Status return xkphysRegionLookup(vAddr, pLevel, IorD, LorS) IorD, pLevel, xkphysRegionLookup(vAddr, return then >= 0x0000_0000_7FFF_FFFF) vAddr LorS) IorD, pLevel, legacyAddressTranslation(vAddr, return 7:6:5: CFG 4: CFG 3: CFG 2: CFG 1: CFG CFG CFG field. endif only mode Compatability # #32-Bit AND 0xFFFF_FFFF_8000_0000 (vAddr <= if endif  vAddr[31:29] Index  vAddr pAddr Index case # xkphys region lookup region # xkphys then = 2) (vAddr[63:62] if Xr * vAddr* Address - Virtual pLevel* KERNEL USER, SUPER, level - - Privilege IorD* LorS* or DATA - INSTRUCTION type - Access * or STORE - LOAD type - Access * Outputs mapped is mapped * - segment pAddr* unmapped) when (valid address - physical CCA* * unmapped) when (valid attribute - cache Error Address Exceptions: * */ subroutine SegmentLookup(vAddr, pLevel, IorD, LorS) : LorS) IorD, pLevel, SegmentLookup(vAddr, subroutine /* Inputs trol mode. The xkphystrol mode. access control the modeis set with Access to xkphys regions with a minimum privilege level of USER are allowed when the processor is operating at any privilegeand level the The access control mode has an asso access control The MIPS64 xkphys regionsbe controlled maySegmentation via SegCtl2 Access to xkphys regions with a minimum privilege level of SUPERVISOR are Access to xkphysallowed regionswhen with the processor is a oper- minimum privilege level of SUPERVISOR KERNEL or privilege and the atingSUPERVISOR with For enabled MIPS64theregions, xkphys Operation of MIPS64 Segmentati with KERNEL privilege and the the and privilege KERNEL with XKP), SUPERVISOR (AM = MSK) or XKP), SUPERVISOR Access to xkphys regions with a minimum privilege level MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 KERNEL KERNEL SUPER USER USER KERNEL SUPER =1) then =1) # uncached # unmapped ERL gCtl2.CFG5 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III:  Se  TLBLookup(vAddr)  CFG.AM  CFG.EU  CFG.PA  CFG.C  C isMapped(AM, pLevel,IorD, LorS) pLevel,IorD, isMapped(AM,  2  0 SegCtl1.XAM MK:MSK:MUSK:MUSUK:  min_pLevel  min_pLevel XKP:  min_pLevel  min_pLevel USK:  min_pLevel  min_pLevel PA >> 1  PA >> pAddr[35:30]  PA pAddr[35:29] UK:  min_pLevel 0: CFG CCA mapped CCA  mapped bit. low order drop the (1GB) segment, a large # in if (Index < 4) then else endif (CCA,pAddr) LorS) segmentError(IorD, AM  checkAM(AM,pLevel,IorD,LorS) level privelege minimum # Check AM case EU PA C checkAM(AM,pLevel,IorD,LorS) ERL=1 when region - Error-Unmapped case # Special and (Status (EU = 1) if else endif use unmapped address for # Physical if (mapped = 0) then else endif CCA) pAddr, (mapped, return  vAddr[61:59] xkphysIndex is raised error exception address # An is non-zero vAddr[58:PABITS] # if then != 0 ) ( vAddr[58:PABITS] if endif  SegCtl2.XR[xkphysIndex] regionEnable then if (regionEnable=1) endcase AM endsub lookup region # xkphys IorD, LorS) pLevel, xkphysRegionLookup(vAddr, subroutine 54Vo For Programmers Architecture MIPS® Virtual Memory Virtual

4.13 Segmentation Control d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 55 USER  TLBLookup(vAddr) me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me =0 and min_pLevel=SUPER) or or and min_pLevel=SUPER) =0 then and min_pLevel=USER)) =0 =0 and min_pLevel=KERNEL) or min_pLevel=KERNEL) =0 and SX UX KX (Status LorS) segmentError(IorD, (CCA,pAddr) CCA) pAddr, (mapped, return (Status UUSK:  min_pLevel case endif  isMapped(AM,pLevel) mapped if (mapped=1) then endif UK:MK:MSK:MUSK: KERNEL) !=  (pLevel seg_err MUSUK: KERNEL) !=  (pLevel seg_err USER) =  (pLevel seg_err USK:  0 seg_err  0 seg_err UUSK:default:USER) =  (pLevel seg_err  UNDEFINED seg_err  0 seg_err LorS) segmentError(IorD, UK:MK:MSK:MUSK:  0 mapped MUSUK:  1 mapped  1 mapped USK:  1 mapped KERNEL) !=  (pLevel mapped UUSK:default:  0 mapped  UNDEFINED mapped  0 mapped  FETCH reftype if ((Status end endif unmapped or disabled, lookup #region for xkphys do today # what we  vAddr[61:59] CCA  vAddr[PABITS-1:0] pAddr pAddr, CCA) (0, return AM case endcase != 0) then (seg_err if endif AM case endcase mapped return if (IorD = INSTRUCTION) then else endsub check mode # Access LorS) IorD, pLevel, checkAM(AM, subroutine endsub LorS) pLevel,IorD, isMapped(AM, subroutine endsub LorS) segmentError(IorD, subroutine MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. =0 BEV 4.3 on page 29 se virtual address. Instead virtual address. se Status thin KSEG1, which ensures implementation-specific. In Section 9.49 “Configuration ged Resource Architecture, Rev. 6.03 these terms are used: used: are these terms of the virtual memory system. memory virtual of the register. See register. Config3 or does not have to be derived from the virtual address e for the Reset/BEV vector ba for the vector location when the vector location for vector base are considered set/BEV vector region are wi set/BEV vector fixed at virtual address 0xFFFF.FFFF.BFC0.0000 and phys- virtualatfixed 0xFFFF.FFFF.BFC0.0000 address . EBase nder Segmentation Control, they are dealt with by the rest are they gment is DSEG which is part of the EJTAG debug architecture and is only gmentDSEG whichpart is is of the EJTAG . =1 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Cacheability and Map-ability RegisterSelect 2)” 5, gment with these properties: gment with these properties: ProbeEn indicated by the SC field in the the SC field in by indicated fic execution modes. modes. fic execution ECR type  LOAD ref STORE  reftype if (LorS = LOAD) then LOAD) (LorS = if else endif endif reftype) SignalException(AddrError, •only active Is speci in endsub • managedhardware, by not software programmable. Totally • Intercepts memory requests before Section 9.16Section (CP0 “SegCtl0 the virtual addresses and physical addresses for Reset/BEV and unmapped. uncached region are always to this the accesses SegmentationphysicaltheControl, address of Reset/BEV vect otherallowed. mappingsare by droppingVA[31:29], Reset and BEV exceptions - Re to the memory accesses legacy memory map, the the In Non-Reset Exceptions - exceptions which would use Legacy Memory map - A MIPS64 Virtual/Physical memoryas described system Section by Legacy Memory map - A MIPS64 Virtual/Physical For thissection discussing exceptionu behavior In the legacytheIn memory vector map, the Reset/BEV base is 0x0000.0000.1FC0.0000.ical address In contrast, Segmentation Control does not define a fixed valu The presence of this is facility See Overlay Segment - A memory se inactive DebugMode. and A pre-existing example of an overlay se of an A pre-existing example Register 3 (CP0 Register 16, Select 3)”RegisterSelect 3 (CP0 Register 16, Debugbehavior mode is retained in dseg. 4.13.1.1 Terminology 4.13.1.2 Control Segmentation under Addresses Base and BEV Vector Reset 4.13.1 Control Exception under Behavior Segmentation 56Vo For Programmers Architecture MIPS® Virtual Memory Virtual

=kernel). KSU mappability attri- Status vector physical address vector physical address =1 or 4.13 Segmentation Control t for the Reset/BEV vectorReset/BEVt for the are implementation-specific. ERL t would give cached and unmapped Status ly choose much larger sizes for the ly choose much larger ed and unmapped, overlay segments and unmapped, ed d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 57 cached views made available through cached views the cacheability and =1 or ERL rantee these conditions: rantee these conditions: Status EV vector location, it must deal with memory requests forreset and BEV exceptions. ception is taken, the overlay segmentmemorythe handles t at least one overlay segmen t at least one overlay ay segment for the Reset/BEV for ay segment e virtual address space as well as the physical address well as space virtual address e size of this overlay segment segment overlay size of this em. After reset, one overlay segment would be given ry and potentially other IO devices. IO devices. other ry and potentially if the system can gua system the if as uncached and unmapped for kernel mode. mode. kernel for as uncached and unmapped reset and exceptions whilekernel mode. in cache-ability and mappability attribute. ectors while ectors while the other overlay segmen y segment does not have to be derived from the virtual address of the overlay the virtual address from to be derived y segment does not have kB insize. Implementations would like y aligned both in th gments is to mimic the cached and un mimic the cached and to is gments without reserving one segment as uncach e overlay segment attributes e overlay attributes over-rides segment out accessing the caches and TLB during during caches and TLB the without accessing regions to be accessed set/BEV uncached and unmapped for kernel mode. and uncached ssible while in kernel-mode ( me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me meet these requirements: meet these en no special support is needed support is en no special uncached and unmapped access to these v KSEG0in and KSEG1 segmentsmemory legacy the syst access to the vectors. The two overlay segments must requests for that vector region and th for requests reset and BEV exceptions. That is, when a reset or BEV ex is, That reset and BEV exceptions. location.there is only If one overlay segment for the Reset/B must be naturall overlay segments The as uncached and unmapped. uncached and as Segments for Overlay 2 - Requirements Solution startingThe starting virtualaddress, physical address and overla of the space. The physical address otherallowed. mappingsare by droppingVA[31:29], at least 2 be must overlay segment The overlay segment to access non-volatile memo overlay segment to access acce be must overlay segment The Solution 2 - Option A - Two Overlay Segments for KSEG0/1 legacy behavior KSEG0/1 legacy for Segments Overlay A - Two 2 - Option Solution An implementationmay optionallysupportsecond overl a region. The purpose of two overlay se are introduced in Segmentation Control for are introduced in re allow the segments overlay These butes of the regular segment control register. SolutionnotIf implemented, 1 is CPU mustthe implemen s vector to a memory region which is uncached and uncached is region which a memory to vector s and BEV exception reset that the requires The architecture unmapped. available always Segment Unmapped and Uncached 1 - Solution can be satisfied This architecture requirement To meet the architecture requirement the architecture meet To 1.up always powers the segments of One 2.as kept always segment is That 3.alwaysthe reside in abovereset and BEV vectors The mentioned segment. met, th If these conditions are BEV and exceptions Reset for Segments 2 - Overlay Solution Not all systems may want to maintain the conditions for Solution 1, since Segmentation Control allows for any of the segments to be programmed with any valid MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

seg-

CFG3 (virtual

must be reset

CFG3 K0 SEGCTL1 lent to legacy KSEG1 Config cacheability of their SEGCTL1 cacheability attribute from attribute cacheability rammable through the leg- rammable through ers. For such transitional e the BEV vector base address base e the BEV vector =0. If the overlay segment K ited from legacy systems, but the vir- ged Resource Architecture, Rev. 6.03 the have been initialized. caches Code Config5 fields fields to control KU must be set by hardware byset must be to uncached CCA (virtual addresses equiva (virtual addresses to an address more appropriate for the non-leg- EG0 segment)overlaythe and other segment register is onlyregister is meant for systems using legacy CFG2 Config fixed by hardware or prog by hardware or fixed is enabled coming out of reset, locationresides mustcome of out mem- treating reset

and Config K0 ddress maps, the recommendation is to disable the legacy the is to disable maps, the recommendation ddress r the overlay segment to get get its to segment overlay r the =1, it is allowed to relocat the cache coherency of the overlay segment wouldcache the be K23 K23 K e Segmentation Controlregist SEGCTL1 Config register. If the BEV/Reset vector resides in a overlayvector BEV/Resetinsegment If the resides a register. Config , Config5 to the same physical address space. physical address same to the K0 rlap in the virtual address space. Config is modified, code executionshould not be within the of reset. This is whenin effect viors, oneviors,overlay segment would be locatedwithin the addresses which memory accesses as unmapped. as unmapped. memory accesses K0 Config the boot firmware to be run cached after the non-Reset BEV exceptions lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: (see next section). (see register field. Config register. ) within the register field, then that register field register field, then that register coherency fields within the the within fields coherency KU Config , Config Config Config K23 (virtual addresses equivalentlegacyto KS

, K0 CFG3 bit can be used for this purpose. If thisbit purpose. can be used for exceptions. K SEGCTL1 acy register fields in acy register fields in ory accesses as uncached. ory accesses Config5 •segments must point The two overlay • size. the same segments are of The two overlay • cannot ove segments The overlay two •of each overlay segment can be coherency The cache • overlay must Both treat segments • The segment overlay in which the BEV/Reset vector addresses which belong to to belong which would be located within the addresses virtual address maps. For systems using non-legacy virtual a coherency fields withinthe resides in one of these segments, it is optionally allowed fo value upon reset. The use of these register fields allows should not be executing within the overlay while segment changingthrough writing the to the uncached CCA value. When CCA value. uncached to the segment). Fields Register Control Coherency legacy using Segments B - Overly 2 - Option Solution Segmentation Controlallows legacy the For example, if the Reset/BEVoverlay segmentsresides within thesegment controlled by addresses equivalenttoand segment) legacy KSEG0 Solution 1 or Solution 2 - Option C - Relocation of non-Reset BEV exception vectors after Reset after vectors BEV exception non-Reset of C - Relocation 1 or Solution 2 - Option Solution There might be transitional devices in which the physical address map was inher ment. of these legacy NOTE: This use for non-reset This feature wouldfashion: be used in this which controlledis by that To mimic the legacy KSEG0/KSEG1 beha the legacy KSEG0/KSEG1 mimic To belong to the appropriate field ( respective non-legacy segments coming out respective non-legacy segments tual addresstualis set up by programmingbeused map to th devices, it might be useful to relocate to useful be it might devices, map.addressacy virtualcapability Such is allowed by Segmentation Control. The 58Vo For Programmers Architecture MIPS® Virtual Memory Virtual

KU Config =Kernel or and KSU K23 Config Status , K0 these memory requests as 4.13 Segmentation Control eability attribute of the overlay eability attribute =0 and ( Config =1. A second overlay is segment DM DM source of the vector base address is is address base the vector source of d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 59 source of the vector base address is address the vector base of source Debug ector must use uncached and unmapped must use uncached ector Debug ess (EffectiveBEV_VA). ess (EffectiveBEV_VA). =1 and the overlay deals with segment ProbeEn register field to control the cach

ECR ors are located at virtual address (EffectiveBEV_VA + 0x200+ off- + ors are located(EffectiveBEV_VA address at virtual Config located at virtual addr located at virtual ed to new ed to new address non-legacy map. vector offset is unchanged while the vector offset vector offsets are unchanged while the vector offsets cated at (EffectiveBEV_VA + 0x480). cated at (EffectiveBEV_VA me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me segment is active when is segment the following names are used: the following names are used: =1)). EXL lowed for the appropriate Status =0 =1 during other exceptions, the vect =0 and the overlaythe=0 andinresides a segment is controlled thatthe by one of K =1 or BEV ERL ProbTrap As compared to a legacy system, the system, a legacy As compared to changed. exceptionThe debug lo vector is Segments 2 - Overlay Option for Requirements The sole debugoverlay not allowed for Debug exceptions. new location. • vector reset/BEV address of the - the virtual EffectiveBEV_VA Status Config5 If implemented,If the second overlaytimeas the firstsamesegmentthe BEV/Reset overlay at is active segment. If there are two v overlay segments, the one which contains the reset/BEV behavior coming out of reset. Both overlay segments must use unmapped coherency. comingbehaviorBoth of out reset. overlayunmapped segments must use coherency. If register fields, it is al it is register fields, unmapped and uncached. The overlay segment is active in Kernel mode ( The overlay segmentand uncached. is unmapped set). Segments 2 - Overlay Option for Requirements there is onlyIf one overlay segment for BEV/Reset, then Status changed. For Reset/Soft-Reset/NMI, the reset vector is 1. boots Device up using location legacy resetvirtual (e.g. address 0xFFFF.FFFF.BFC0.0000) 2. Segmentation Registers are programm 3.exceptions Non-Reset BEV would nowuse this movedto vector base new location BEV using this capability. Forofthe rest this section, the system, a legacy to As compared If segment. ECR 4.13.1.3 Control Segmentation under BEV Exceptions 4.13.1.4Control Segmentation under Exceptions Debug MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Probe- and Figure EBase K23 Config , register are now also register are now also K0 l the cacheability attribute l the cacheability Ebase Config ken directly fromken directly the gment is ECR gment is active when e region. uncached kseg1 ged Resource Architecture, Rev. 6.03 precedence over the other overlay seg- precedence comes uncached and unmapped when and unmapped comes uncached the followingadditions. [31:12] || 0x000 + offset). These virtual[31:12] || 0x000 + offset). .FF20.0200. This virtual address is the ese memory requests as uncached. as memory requests ese Ebase register field to contro register

ception vector in th e exception vector is ta F.FFFF. This se overlay This F.FFFF. Config Debug overlay segment, which covers the Virtual address Debug overlay segment, which covers the Virtual to be located anywhere in the address space. See address to be located anywhere in the =1) then base architecture, with architecture, base ent by that is controlled one of the CV bit. When EU=1, the segment be segment the bit. When EU=1, system (except system nowtheupper 2 bits of the 2 then located at virtual address ( located at virtual address  behavior requires thatof bit 29 the exceptionis set truewhen vector =1. This DSEG overlay segment takes overlay =1. This DSEG deals with th overlay the segment ese memory requests ese memory as unmapped.  0x100 ongside SegmentConfiguration EU fieldscode to ensure thatfrom is executed lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: DM 63..12 =1 =1) and (Config5 =1) and Debug ent of a Cache Error exception. ent of a Cache SC En register is present. This places the ex present. This is register EBase ation contains an EU =1 and EBase En = 1 then /* Use full value of EBase */ EBase value of Use full /* PC  =1 allowsto this behavior be overridden - th BEV =0 and the overlay resides in a segm ECR CV 0xFFFF FFFF BFC0 0200 + 0x100 0200 + FFFF BFC0 0xFFFF K =1 and ECR and =1 if (Config3 register fields, it is allowed for the appropriate for the appropriate allowed fields, it is register 5 =0, then exception vectors are then exception =0, register is modified to allow exception vectors register is KU =0 and the =1. On reset, this bit is set for segments coveringfor bit thisreset, =1. On is set 0x00000000_00000000 the range to PC  if ArchitectureRevision if ArchitectureRevision BEV =1 and Config5 Config BEV ERL ProbTrap EBase of the overlay Otherwise, segment. if Status The overlay segment deals with th with deals segment The overlay Config If The debug exceptionThe debug 0xFFFF.FFFF located at virtual address vector is 0xFFFF.FFFF.FF3 to 0xFFFF.FFFF.FF20.0000 of region same as in the legacy system. the in same as The memoryrequests to that region are handled by the else Trap ments. Status ECR 0x00000000_7FFFFFFF, to match kuseg behavior. 0x00000000_7FFFFFFF, On a Cache Error exception, the legacy Status Status writable. memoryThe requests to that region handled are appropriatethe by programmable segment. Register) (EBase Placement Vector Exception Extended The addresses addresses are the same as those in the legacy 9.45. the as defined in Exception operates CacheError The Each Segment Configur register. This feature should be used al register. region in the ev an uncached The exception vector is computed as follows: computed exception vector is The If Setting 4.13.1.6 Control Segmentation under Error Exceptions Cache 4.13.1.5Control Segmentation under Exceptions EBase 60Vo For Programmers Architecture MIPS® Virtual Memory Virtual

Section tation limits and access to user memory access to user memory chitecture provide the ability chitecture provide 4.14 Enhanced Virtual Addressing d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 61 ess space limited user addressable mem- user addressable space limited ess ctions allowing direct ctions allowing virtual address space. virtual address  0x100 instructions to the MIPS ar mmed to define two address ranges, a 3 GB rangemmedto with defineranges, two address 28..12 configuration of Segmentation Control (refer to EBase  2 t Compatibility region -bit Compatibility region virtual addr -bit Compatibility . ignored, resulting PC always in kseg1 */ kseg1 in always PC resulting ignored, me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me sor and unmapped-kernel access modes and sor and unmapped-kernel access modes a 1 GB address range with mapped-kernel 31..29 31..29 Figure 4.4 0xFFFF.FFFF  101 0xFFFF.FFFF 0xFFFF FFFF A000 0000 + 0x100 + 0000 FFFF A000 0xFFFF /* EBase PC  endif PC  else else endif endif • UnmappedKernel Supervisor, Mapped Mapped 3.0GB User, • Mapped Kernel 1.0GB 32 the segmentation of legacy fixed The shown inory to 2.0GB as EVA is a 2 section partitioning of the 32-bi partitioning a 2 section is EVA The addition of Segmentation Control and kernel load/store e 32-bit Compatibility region that exceed prior fixed segmen prior that exceed region the 32-bit Compatibility ranges in virtual address to configure mode. from kernel address space user to access feature is a Addressing (EVA) The Enhanced Virtual 4.13 “Segmentation load/store instru of kernel mode Control” ) and a set Segmentation Control is progra kernelfrommode. In EVA, mapped-user, mapped-supervi mapped-user, access mode. access 4.14.1 Control Configuration Segmentation EVA 4.14 Addressing Virtual Enhanced MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

1 1 1 0 1 0 CFG5 EU CFG4 CFG3 CFG2 CFG1 CFG0

r as are programmed o is v l r l e e e mentation Control” on

n n CFG r p r e u e S K K , d r d e e s e p p address access user virtual to p U p a d a e M m 3 3 3 3 3 p 3 p n C 4.14 Enhanced Virtual Addressing a U

M of each fields d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 63 EU physical address space by using these space by using physical address and 0.0 GB 2.5 GB 1.0 GB 3.0 GB 2.0 GB 3.5 GB EVA Segmentation Control configuration Control Segmentation EVA 4.0 GB d (CFG (defined in “Seg d (CFG (defined PA, C , om user space can be conveniently changed by replac- by conveniently changed be om user space can itchingbut(kernel to user) is an alternative modesis this e used to allow the kernel allow the e used to AM PA 0x007 0x005 0x004 0x002 0x000 0x006 Segment Configuration fiel AM MK MK MUSUK MUSUK MUSUK MUSUK me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ontrol to implement EVA, the the EVA, to implement ontrol Figure 4.6 Figure configuration address EVA to Legacy kseg1 kseg0 useg ksseg kseg3 Virtual Address Space Address Virtual Legacy 32-bit statically partitioned statically Legacy 32-bit Table 4.6Table region Compatibility in 32-bit EVA for 3GB Configuration Segment nel Supervisor, Supervisor, Unmapped Kernel Region 0.0 GB 4.0 GB 3.0 GB 3.5 GB 2.5 GB 2.0 GB 01 1GB Mapped Ker- 23 3GB Mapped User, 4 5 page 52)) must be initialized to define the overall memory map to support a unmapped3GB (mapped user/supervisor, kernel) memory segment. C configure Segmentation To follows in the following table. the following in follows EVA defines a number of new load/store instructions that ar instructions of new load/store a number defines EVA normaling load/store instructions withSw these instructions. space while executing in kernel mode executing in kernel while space space to kernel from user address data For example, the kernel can copy fr Kernel system-calls addresses. instructions with user virtual To support the EVA configuration, each EVA the support To CFG Description 4.14.2 Instructions Address (EVA) Enhanced Virtual MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

= Kernel, = User StatusKSU ere is penalty a performance COP0 Unusable Excpt COP0 Unusable Excpt register field.

ged Resource Architecture, Rev. 6.03 EVA mode (defined by Config5 rown ifinstructionrown the executedother in is than Kernel Supervisor pped) performed by EVA load/store instructions accord- instructions load/store performed by EVA pped) Prefetch EVA Load Byte Load EVA Store Byte EVA Store possible, else unmapped. More simply, a TLB based a TLB based possible,else unmapped. More simply, Load Word EVA Word Load used by the kernel. Further, th kernel.used by the Further, Store Word EVA Word Store Load-Linked EVA Load-Linked COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt Instruction Name Load Halfword EVA Load Halfword Store Halfword EVA Halfword Store Load Word Left EVA Left Word Load Store Word Left EVA Word Store Load Word Right EVA Load Word Store Word Right EVA Word Store Store Conditional EVA Conditional Store Load Byte Unsigned EVA Byte Unsigned Load ce manual for further information on the EVA Load/Store Load/Store informationfurther ce manual for on the EVA Load Halfword Unsigned EVA Load Halfword Perform Cache Operation EVA access mode is access mode is not allowed. igured with (AM). a User access mode and processor execution Kernel lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: e instructions are indicated by the are indicated e instructions SBE SCE LLE SHE LBE Table 4.7Table Instructions Load/Store EVA LHE LWE SWE Address Error Excpt Address Error Excpt Address Error LBUE LHUE LWLE SWLE LWRE SWRE PREFE CACHEE Instruction Mnemonic Table 4.8Table Address load/store translation instructions behavior for EVA UK MK lists the type of address translation (mapped/unma lists the type of address lists kernel load/store instructions. lists kernel load/store address translation is preferred. • The address translation selected will be mapped if • OnlyKernel usable from execution mode. •conf usable on a memory segment Only AM- Access Mode in context-switching. instructions load/storeare as follows: LimitationsEVA of the on use Referen Architectural MIPS of the II to Volume Refer instructions. The availability of thes Table 4.8 ing to Segmentation Control access mode (AM) Table 4.7 an issue the if same virtual address is being simultaneously mode. An Address mode. An Address Error exception is thrown if the Supervisoror User). A Coprocessor 0 unusable exception is th 64Vo For Programmers Architecture MIPS® Virtual Memory Virtual

= Ker- = StatusKSU User User e entry format, as follows: e entry format, This mechanism is effective mechanism is effective This cal page size is used. Unfortu- used to replace the software replace used to Address Error Excpt Error Address Excpt Error Address Address Error Excpt Error Address Excpt Error Address COP0 Unusable Excpt COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt memory. Hardware acceleration memory. 4.15 HardwarePageTable Walker =1. registers can provide the address of a can provide the registers PW d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 65 Config3 XContext XContext apped unmapped and mapped unmapped s enhancements to page tabl page to s enhancements Supervisor Supervisor , use different page sizes, and store TLB entries TLB entries page sizes, and store in 8, 16 , use different a Page Table Base address. Page Table a pped) performedpped) by ordinary load/store instructions bytes in size, and a 4k physi Address Error Excpt Address Error Excpt Address Error rown if the access mode is not allowed in the current exe- in mode is not allowed if the access rown Entry (PTE) is located in located Entry (PTE) is Context COP0 Unusable COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt COP0 Unusable Excpt and processor execution mode (defined by mode and processor execution chitecture. The mechanism can be chitecture. The mechanism leaf levels of the Page Table hierarchy), and Base Page Size for the (Pagefor thePage Size hierarchy), Base and oflevels the Page Table leaf Kernel Kernel mapped mapped Walking feature is denoted when Walking unmapped unmapped me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Address Error Excpt Address Error Excpt Address Error Address Error exception is th Address Error exception an optional feature an optional in the feature ar Table 4.8Table Address load/store translation instructions behavior for EVA UK MK mapped USK USK MSK MSK UUSK unmapped unm UUSK unmapped MUSK mapped mapped mapped MUSK mapped Table 4.9Table instructions load/store ordinary for behavior translation Address MUSUK unmapped mapped mapped lists the type of address translation lists the type (mapped/unma of address MUSUK erarchy). This is the baselineThis hi definition.erarchy). Inferred size Entry (PTE) levels (leafthe PageTable levels of Table supported at non-leafare PTEs levels. AM- Access Mode AM - Access Mode cution mode. 2. A reservedThisis addedfield forbeen fieldextensions.future to PTEs. has 1. HugePage support indirectories (non- The Hardware Page Table Walker feature additionally include feature Walker Table Hardware Page The TLB entry - calculatedfromTLB entry - the faulting address virtual and modern operating systems use multi-level page tables nately, andbyte forms. 32-byte Page the Hardware existence of The when the OS page table is single level, the TLB entry is 16 nel, Supervisor or User). An nel, Supervisor or User). Page Table Walking is the process by which a Page Table Table Page by which a the process is Walking Table Page handlerRefill for the TLB or XTLB Refillmechanism condition.thisThis hardware han- fast-pathused is onlyfor This hardware mechanismnot used for is the TLBInvalid handler (or slow-path handler). dler. MIPS PrivilegedThe Resource Architecture (PRA) mechanisms includes intendedfor rapid handlingexcep- of TLB tions in software. Following a TLB-related exception, the Table 4.9 according to Segmentation Control access mode (AM) is walking for page table 4.15 Walker Table Hardware Page MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

and Context pairs in the Page Table Table in the Page pairs tional if Huge Pages are sup- Pages tional if Huge ectories. A Directory consists ectories. A Directory consists acent directory entry is used acent directory entry register specifies the per-VPE register specifies the per-VPE d to the size of the page (which is of the size d to the EntryLo1 ged Resource Architecture, Rev. 6.03

physical are both addresses derived and =1 PWBase DPH lling the TLB, independentof the EntryLo0/1 her Directory or to a Page Table. Table. a Page Directory or to her EntryLo0 EntryLo0 PWCtl =1. If an ImplementationsupportsHuge Pages inthe port Huge Pages in the directory levels, then the Adja-inthe then the directory levels, port Huge Pages ges which have ges which physical adjacent virtual and addresses. dress space. This is the default method that is supported er. These registers also configure registers the separation These between er. r the even page and the adj the even page and the r lowest (leaf) elements of which are Page Tables. A Page Page Tables. of which are (leaf) elements lowest ngle directory entry. The memory region is divided evenly ngle directory entry. . The Dual Page method is op . The Dual Page Page Tables are knownas Dir Page Tables since the since Hugepg be adjacent to each other. If since each PFN to be adjacent does not have to each other. PWCtl within the directory entry is aligne is within the directory entry The physicaladdressalignedThe held withinthe to entry is directory 2 x cal address. They may also have differing page page physical have differing They may also not address. in virtual, but . registers specify address generation for up to five levels table. of page The cessor 0 registers are added. The Adjacent Pages a multi-level page table structure. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: stem specifies a mechanism for refi a mechanism stem specifies r in a Directory is either to anot PWSize forms a tree structure - the - tree structure forms a and pport the Adjacent Page method ge Table support ge Table PWField registers.Four additional copro register controls the behavior of the Page Table Walk register controls the behavior of the Page Table

for the odd page. The physicalheld address knownpowerThis method Dual Pagesa of 4). is as an implementationsupporttochooses HugePages in the directory levels,the thenPage method Dual is an addi- tional option. from one entry and to behave adjacent in the physical ad by thisspecification. If animplementation chooses tosup methodcent Page implemented. must be used fo one directory entry is this case, For Table. Page between the even page and the odd page the and between the even page Since the even page and the odd page are derived from a single directory entry, they will theyboth inherit the same Sincefromderivedthe the even page and a singleare odd pagedirectory entry, attributes and but all one of the address bits from the si size of theThis is distincta power4).(which page from is of which are only guaranteed to be adjacent guaranteed to be only are which attributes. This methodis knownas The next figure shows example of an Table is an array of Page Table Entries. Levels above the Entries. Levels above Table is an array of Page Table of an array of pointers. Each pointe Examples of power-of-4 regions (start withregionsmultiplykBand1 (start ofof times):Examples number power-of-4 by 4 a MB,4 256 MB, 1 MB, 161GB.256 MB, MB, 64 MB, regionskB (start withofExamples 2x power-of-4 1 and multiplyof by4a number times; thenmultiple by 2) 5122GB.512128 MB, MB, MB, 32 MB, 8 MB, 2 MB, HugePage Support is optionalandindicated is by 2.the Page in Base a manner as page, it is handled in exactly the same power-of-4 Page is itself a a Huge Where Page Table Entries(PTEs) in memory and post-load shiftingof PTEs. PageTable A multi-level page table system The hardware pagewalking table sy XContext PWCtl A Huge Page may logically mayA HugePage in two be specified ways: 1. A Huge pa Page composed of two is a region power-of-4 page table base. The directory levels, it must su ported. The implementationported. The Dual Pagemethod of indicated is by 4.15.1 Multi-Level Pa 66Vo For Programmers Architecture MIPS® Virtual Memory Virtual

. This is the optionalthe . This is BDI for either 32 bit or 64 bit for either 32 bit PWField Directories are treated as 32 or 64 as 32 or are treated Directories 4.15 HardwarePageTable Walker ns resulting from accesses ns resulting from accesses to mapped d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 69 validate the single duplicate andthenwrite detected, abort. register e if entry is PTE. If PTEVld bit is set, write Huge e if entry is PTE. If PTEVld bit is set, write Huge tableaborted walk, the HW walkingprocess is =0, skipnext to the step. field - either 4 bytes (32 bits) or 8 bytes (64 bits) bits) (64 8 bytes or bits) (32 4 bytes - either field do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of fill or XTLB Refill exception will taken,be as appropri- hardwarethe is walk, HW walking page table process PS PWBase taken, as appropriate. This includes synchronousexcep- Resource Architecture document for details. it case the same as a TLBWR. Assuming that the write by the write that Assuming TLBWR. a as same the it case PWDirExt used to accelerate TLB refills used to accelerate ge table walk reads from mapped regions of the Virtual ge table walkmappedof reads fromregions the Virtual =0, skipnext to the step. an exception is PWSize PWCtl GDW field controlsfield whether pointers within ddress in the temporary pointer, ofreturned The the nativesize. pointer theddress in temporary pointer, fill exception is determined from the faulting address and the UX, SX and PWSize PS mporary pointer. If mporary pointer. PWSize me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me bitsfaulting from thebit addre ss, with least-significant cates, then a preferred implementation is to in implementation is preferred a cates, then Directory is disabled by BDW B followingTLB write. a register. Privileged See the MIPS64 register. s exceptionis detectedthe during hardware page PWSize Status Page into (detailsread TLB pseu left out for brevity, after Hugeplete Page is written to TLB. Pageinto TLB (detailsread pseu left out for brevity, after Hugeplete Page is written to TLB. Base DirectoryBase index after (Bindex). multiplying Logical ORonto (shifting) thetemporarypointer, by the nativepointerresultsize. The pointer is a a location to within Directory. the Base value is placed into the te • Extract • Huge If Pages are supported, check PTEVld bit to determin •from the a a memory read Perform • Huge If Pages are supported, check PTEVld bit to determin tions such as Address Error, Precise Precise Debug Data Break and other TLB exceptio tions such as Address Error, regions. If an asynchronou and asynchronousand the exception taken. includesis This exceptions asynchronous such as NMI, Cache Error, Interrupts.alsoincludes It theasynchronous MachineCheck exception whichfrom results multiple matchingentries beingin present the TL Implementations are not requiredto support hardware pa aborted and a TLB Refill or XTLB Refill exception will be doesspace. If an implementation notAddress support reads from mapped regions, an attempted access during a page table walk will cause the process to be aborted, and a TLB Re the TLB. A Machine Check Machinethe TLB. A exception TLB. or lookupsubsequently may of TLBP on taken be a a synchronousIf exception conditionduring is detected the ate. walk can be hardware page table On 64-bit machines, the address regions,butboth. not The bit addresses. bit addresses. between The selection TLB and XTLB Re inKX bits the 2.pointer The nativedetermined size is from the 3. If the (optional) Base design cannot detect all dupli The hardware page walk write should treat multiple-h the treat should write walk page hardware The Hardware pagetable walking as follows: is performed 1.the of A temporarycontents loaded pointer with the is 4.thedisabled Global If by Directory is MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. This is the Global. This is . This is the Middle . This is the Upper Upper the is . This GDI UDI MDI This is the Page Table This is the Page Table PTI PWField PWField PWField PWField ged Resource Architecture, Rev. 6.03 e Page Table Entry. If an exception is Entry. Table e Page -1. PTEI detected, abort. detected, abort. detected, abort. e if entry If is PTE. PTEVld bit is write set, Huge e if entry is PTE. If PTEVld bit is set, write Huge pointer, after multiplying (shifting)by the native pointer, pointer, after multiplying after (shifting)by the nativepointer, PWField do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of do-code at end of this section). Page Walking is com- Page Walking this section). do-code at end of =0, skip to the next step. bits. This is the first half of the Page Table Entry. If an excep-an If Entry. Thisofis the first the PageTable bits. half =0, skipnext tothe step. an exception is an exception is an exception is PTEI MDW UDW after multiplyingonto the (shifting)temporary pointer, by the native a location within the Upper Directory. bits. This is the second half of th secondis the bits. This half ddress in the temporary pointer, ofreturned size. The the native pointer theddress in temporary pointer, ddress in the temporary pointer, of returned the nativesize. The pointer theddress in temporary pointer, ddress in the temporary pointer, ofreturned The the nativesize. pointer theddress in temporary pointer, ddress in the temporary pointer, of returned the nativesize. The pointer theddress in temporary pointer, ddress in the temporary pointer, ofreturned The the nativesize. pointer theddress in temporary pointer, PWSize PWField PWSize PTEI lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: . mporary pointer. If mporary pointer. mporary pointer. If mporary pointer. mporary pointer. If mporary pointer. PWField PTEW bits from the faulting address, with least-significant bit bits from the bits from faulting with address, least-significant bit bits from bits the faulting address, with least-significantbit UDW GDW MDW bits from bits the faulting address, with least-significantbit PWSize PTW PWSize PWSize PWSize PWSize Page into read TLB (details pseu left out for brevity, after Hugepleteis written Page to TLB. Page into (detailsread TLB pseu left out for brevity, Hugeafter plete Page is written to TLB. Directory indexDirectory (Gindex).Logical OR onto temporary the pointer size. The result is result a pointersize.pointerlocationa to The within Global the Directory. value is value is into the placed te Directory index (Mindex). Logical OR is a pointerresulta location tosize.withinpointer The Middle the Directory. value is placed into the te value isbyvalue shifted right Directory index (Uindex).Logical OR onto the temporary pointer size. The result is a pointeris result to size.pointer The value is value is placed into the te detected, abort. tion is detected,tion is abort. value is logically shifted right by • Extract • Extract •from the a a memory read Perform •from the a a memory read Perform index (PTindex). Multiply (shift) byindex the (PTindex). native pointer size, then multiply (shift) by the size of the Page Table in specified Entry, • Entry. The temporarynow pointer contains of the second halfPage Table of the the address •from the a a memory read Perform •from the a a memory read Perform • Entry. The temporarynow pointerof contains of the first the Page Table the addre half ss •from the a a memory read Perform • Extract • Huge If supported, Pages are check PTEVld bit to determin • Huge If Pages are supported, check PTEVld bit to determin • to be used. The temporarynow pointerof the PageTable contains the address 5.disabledbythe Upper Directory is If 7. Extract 6.the Middle If disabled Directory by is 8. set Inthe the bit temporary located pointer, at bit location 70Vo For Programmers Architecture MIPS® Virtual Memory Virtual

, field. If non-leaf PTE h is configured by the com- Psn placed right of the RI bit in EntryHi, PageMask, EntryLo0 , PWCtl 4.15 HardwarePageTable Walker feature requires the RI bit to be placed placed be to the RI bit feature requires d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 71 for Software-onlyflags. Thefollowing of entries inof entriesdefinition: the baseline Direc- values. These operations are used to operations values. These BadVAddr register field indicates whetherPage Huge EntryLo1 =10 and a Base Page Size of 4k for simplicity. In this =10 and a Base Page Size of 4k for simplicity. HugePg bit withinDirectory the ofanyPointer those field, as d of an entry. For all but the lastlevel dtable of (leaf an level),entry. and PTEI ift bitsift 31:30 to 63:62ifto/from the move is EntryLo0/1. B or XTLBexceptions refillB or the are unused by hardware is required that the XI bit to be e, the entry is always a PTE is always and 1 for PTEs. In the leaf table, the entry e software TLB handler to distinguish non-leaf PTE entries PWCtl igured to pointthatto software bit withinPTE. the PWField EntryLo0 . =0, Psn . Similarly, it . Similarly, is always 64b in the page walker. This instruc- is in contrast to mtc0/mfc0 64b in the page walker. always is -2 (shifting in zeros at the most significant bit) and then rotated right by 2 =0. In this example, 8 bits are used =0. In this example, 8 is 32b-compatibleor64b, native the RI/XIwill bitsalways end up inbits inferred size, and leaf PTE of base size. For options other than baseline, the BadVPN2 PWCtl PTEI ppropriate to be used to distinguishnon-leafppropriate to be used toorDirectory a betweenPointer a PTEW me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Context emory data structures. There are three types three types are There emory data structures. PWField PWSIze ill already be a bit used by th ill already be a bit used e implemented and enabled, the HW Page e implemented and enabled, the HW Page Walker and =1 and PS BadVPN2 e implemented. PWSize random) instruction. non-leaf PTEs ar non-leaf PTEs All PTEs are shifted right byPTEs are shifted rightAll bits before formingbitsbefore the page-walker equivalentsof example, the figures a PTE figures assume format based on removeSoftware-only theplacingand bits the RI and XI protectionproper bitsthe in location bit writing before the TLB. If the RI and XI bits ar right of the G bit in the PTE memory format the PTE memory format. operation mode of the that whether Note rotate the PTE because rotated 63:62 of the tionsusedby the software refill handler which explicitly sh Refer to instruction descriptions for MTC0 and MFC0 in Volume II for II more information. toRefer instruction descriptions for MTC0and MFC0in Volume Notethat the bit position of PTEvldis not fixed0. atbecan Itprogrammed bythe and the PTEvld bit is not used by Hardware Walker. The Walker. PTEvldand thenotis bit Hardware used by tory Pointer, Huge Page non-leafPTE of tory Pointer, entry typeis a function of the tablefiel PTEvldthe level and the PTEvld bit is 0 for directory pointers to the next table All entries are read from in-m read are entries All page table walkingpage table and by ers regist The process. fields used software are EntryLo1, XContext 9. Entry into the TLB, using samethe semantics as the TLBWR (TLB the two write halves of the Page Table Write 10. Continue with program execution. onwhich TL software are used by 0 registers Coprocessor entries are available, there w the PTEvld bit fromis directoryconf pointers. Normally, programmingA possible to avoid error is placingPTEvld the mayaddress bits be set and thus not a PTE. The following figures show widt an example The 8-byte of 8-byte entries. pointers or PTE bination of 4.15.2 PTE Directory Entry Format and MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

as synthesizedfrom Comment values. When the

reted by HW Page which are just left of thewhich of just left are Walker Comment Comment Comment EntryLo1 Page Size=Base, HW Page Walker EntryLo1 Page Size=HgPgSz. Page Size=HgPgSz.

and PTE format in memory format PTE PTE format in memory

and ged Resource Architecture, Rev. 6.03 at interpreted by at interpreted Directory Ptr form PTE format interp EntryLo0 ificant bit) and rotatingfields the RI andXI occur with just one entry (Adjacent Page just one entry (Adjacent with occur 1 EntryLo0 vel by the Hardware Page Walker. vel by the Hardware Page Walker. =1 =0 C D V G Page Size=HgPgSz

PTEvld PTEvld 7..0 7..0 6 5. 3 2 1 0 by In the non-Leaf PTE, the 4-bits In the non-Leaf represent represent adjacent physical pages.

UnUsed Hardware Rsvd ). However, non-leaf PTEs (ones which occur in the non-leafin upper(ones which occur PTEs ). However, 0 ferred fromferredinthe directory levelthe which Huge Page (must be 0) EntryLo1

EntryLo1 and

12 11 and , then the Adjacent Page Method is used. is Method then the Adjacent Page , r a PTE in a directory, the least significant bit above thepageis 0 forsize r a PTE in a directory, Figure 4.9Figure PTE Leaf 8-byte EntryLo0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: TEs are read le from the directory (if Dual Page method is enabled) or enabled) is (if Dual Page method single non-leaf PTE represent both single C D V G RI XIC S/W Use DVGRIXI hod, the size of each individual PTE in EntryLo0 C D V G RI XI S/W Use (7..0) out (shifting in zeros at the most sign Figure Figure 4.11 PTE Formats Rotated 8-Byte Figure 4.10Figure Options PTE Non-leaf 8-Byte That is, 16 15..13 12 11 10 9 8 Rsvd Rsvd (must be 0) (must be 0) EntryLo1.

PFN 63 62 52..30 61..53 29..10 9..6 5. 3 2 1 0 Dir Pointer 63..12 and 1 for Comment 63 62 52..30 61..53 29 63 Leaf PTE RI XI FILL PFNX PFN C D V G Page Size=Base walker populates the EntryLo registers fo walker populates the EntryLo registers After shifting the software bits ( pairs always occur in Leaf PTEs into bits 63:62, the PTE matches the EntryLo register format. future features. for C field are reserved For the Dual Page method, thetwo P directories) can occur either in pairs method). For the Adjacent Page method, the EntryLo0 the single Huge Page is always half the inferredsize. thealwaysthe single half Huge Page is 2 x power-of-4 is page size the inferred If For HugePage handling,inthe Huge Page is size of the Page Met For the Adjacent resides. 63..40 19..16 39..20 15..13 12 11 10 9 8 7..1 0 63..40 19..16 39..20 15..13 12 11 10 9 8 PFNX PFN PFNX PFN Non-leaf PTENon-leaf RI XI FILL PFNX PFN 63..40 39 PFNX 72Vo For Programmers Architecture MIPS® Virtual Memory Virtual

specific whether the PTEVld whether the PTEVld specific of the typical 512 entries. ) = 2^31EntryLo0/1 = 2GB. Each) = Note that the index into PMD has the index into PMD Note that 4.15 HardwarePageTable Walker PTI d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 73 PWField ) * 2^12( ) = 2^21 = 2 MB. Each EntryLo0/1 page is 1 MB,Each EntryLo0/1 page is 1 = 2 MB. ) = 2^21 =1), it is implementation- PTI thus has 1K entries instead PTW DPH Page Method is used (if the Dual Page Method is imple- memory for writing the second TLB The recommendedpage. PWCtl PWField PWSize gister 5, Selectgisterpage181 5)" on . a It assumes leaf PTE size of 4 kB. ) * 2^9 ( ) * 2^9 ) * 2^12 ) ( MDW PTW er-of-4, and the Dual Page Methodsthe and Dual Page implemented,is not er-of-4, it is implementation- me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ster (CP0 Register 5, Select 7)" 184 page on 7)" 5, Select Register (CP0 ster PWSize PWSize register field is used to differentiate between different types of Machine exceptions. of types Check between different field is used to differentiate register

MCCause * level. privilege the KERNEL using performed are Memory accesses * exit a silent cause accesses memory on detected exceptions Synchronous * exception. Refill or XTLB in a TLB resulting table walking, from page * * memory table walk page to support not required are Implementations * access is an unsupported When regions. memory from mapped accesses * exception. XTLB Refill TLB or in a resulting is taken, exit a silent attempted, * * or LoadMemory by AddressTranslation is caused if an exception Note that * is taken, silent exit a is not taken, the exception functions, * exception. Refill XTLB or in a TLB resulting * * widths. of different PTEs deal with does not pseudo-code this For readability, * PTE the different deal with have to will implementations In reality, * widths. pointer and directory * */ and would use the Adjacent Page and would use the Adjacent Page method. page is 1GB, which is a power-of-4 been extended to 10 bits from 9 bits. Each PMD table subroutine PageTableWalkRefill(vAddr) : PageTableWalkRefill(vAddr) subroutine /* Perform hardware page table /* Perform hardware page table walk which is a power-of-4 and use the Adjacent Page method. Page the Adjacent and use a power-of-4 which is Section9.20, "PWField Register Register (CP0 6)"Select on page 181 5, Section 9.21, "PWSize Regi Section 9.19, "PWBase Register (CP0 Re Section 9.23, "PWCtl Register (CP0 Register 6, Select 6)" on page 193 page on 6)" Select 6, Register (CP0 Register "PWCtl 9.23, Section •2^10 ( PUD Huge Page = The hardwareThe walking page table is described process in pseudocode as follows: If the inferred page size is a power-of-4, then the Dual then a power-of-4, is page size inferred the If PageGrain mented).Page method If the Dual is implemented ( • • See also: • bit checked is for the second PTE when it is read from behavior is to check this second PTEVld bit and if it is not set, a Machine Check exception is triggered. The specific whether a Machine Check is reported. Machine Check specific whether a HugeAn example Pagehandling of follows • PMD Huge Page = 2^9 ( If the inferred Huge Page sizeHugethe is pow Page inferred If • 4.15.3 walking process table Hardware page MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

>0) then >0) MDW )-1)} GDW )-1)} )-1)} >0|PWSize ged Resource Architecture, Rev. 6.03 BDW GDW UDW =0)) then XU >0|PWSize GDW ) and ((1<0) then >0) XS BDI GDI BDW >0)|PWSize ,PWCtl =1) then XS BDW HugPg =0 & PWCtl ,PWCtl XK DSize * 2 2 32 3 64 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: XK      =1 and PWSize =1  {(vAddr>>PWField =1 & PWSize return (0) return (0) return if (vAddr[63] or vAddr[62])=1 then or vAddr[62])=1 if (vAddr[63] endif  tempPointer Gindex then and vAddr[62])=1 if (vAddr[63] endif & 1, tempPointer}  {(vAddr>>62) Gindex =1 and PWCtl =1 and = 0) then PWDirExt =0) then False False false false =0) then =1 & (PWCtl False PW PWDirExt =1) then case 001case only # xuseg 011case & xsseg # xuseg PTEW PS PS PS PWEn DSize DSize  {(vAddr>>PWField Bindex   switch ({PWCtl switch NativeShift NativeShift DSize NativeShift DSize  {(vAddr>>PWField Gindex tempPointer tempPointer PWSize if (PWCtl return (0) # no segment to map no segment (0) # return values # Initial return (0) # no structure to walk to no structure (0) # return else return (0) # walker is disabled # walker (0) return return(0) # walker is unimplemented walker # return(0) endif address faulting from computed # Indices if (PWCtl found encMask   HugePage  HgPgBDhit  HgPgGDhit  HgPgUDhit  HgPgMDhit size pointer # Native if (PWSize if (Config3 if ( else endif directory of double-wide the case reads for for Directory DSize # Adjust because adjustment get a different leaf-tables pseudo-code, Later in # entries. Huge Pages. contain do not # they if (PWSize if !((PWCtl if (PWCtl 74Vo For Programmers Architecture MIPS® Virtual Memory Virtual

)) )) )) HugPg HugPg HugPg )) +1) )-1) 4.15 HardwarePageTable Walker PTEW GDW d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 75 PTEW )-1) )-1) )-1) and PWCtl and PWCtl and PWCtl and UDW MDW PTW PTEW PTEW PTEW =1) then # PTEvld is set # PTEvld =1) then Hugepg ) and( (1<0 SW-only PTE, entire 2 // shift - GDI ) and ((1<> 6 // align PA[12] into EntryLo* register bit 6 register EntryLo* into align PA[12] 6 //  (1<> return (0) return UNPREDICTABLE vAddr >> PWField vAddr > 0) then UNPREDICTABLE = 1) then =  ROTRIGHT(t, 2) // 64-bit rotate to place RI/XI bits place RI/XI to rotate 64-bit 2) //  ROTRIGHT(t, endif & 1, tempPointer}  {(vAddr>>63) Gindex tempPointer} and 3,  {(vAddr>>62) Gindex (0) return   pw_EntryLo1 pw_EntryLo1 lsb pw_EntryLo0 if (~vAddr[6 t >> PWField  t BDW vAddr >> PWField vAddr >> PWField vAddr >> PWField vAddr + PWSize << (NativeShift >> 1) PTindex  PToffset0 OR (1 << (NativeShift + PWSize << (NativeShift OR (1 PToffset0 Gindex << (NativeShift + (PWSize << (NativeShift Gindex + (PWSize << (NativeShift Uindex + (PWSize << (NativeShift Mindex UNPREDICTABLE UNPREDICTABLE if ((PWField  t w  (PWField            case 111case xkseg xsseg, # xuseg, default elseif (PWCtl elseif // generate adjacent page from same PTE for odd TLB page PTE for odd same from page adjacent // generate case 101case & xkseg xuseg # HugePage  true HugePage  true HgPgBDHit t PWDirExt PWBase BadVPN2 BadVPN2 Boffset Boffset vAddr CCA) (pAddr, t (t and (1<

ged Resource Architecture, Rev. 6.03 ) BDI =1) then # PTEvld is set # PTEvld =1) then ) GDI - 2 // shift entire PTE entire // shift 2 - Hugpg - 2 // shift entire PTE entire 2 // shift - PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) DATA, AddressTranslation(vAddr2,  t  t  t  t - 2 // shift entire PTE entire - 2 // shift PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) DATA, AddressTranslation(vAddr2,  t  t (1 << PWField ) && PWCtl PTEI and 0x1)=1) // check if index is odd e.g. 2x power of 4 power e.g. 2x is odd index if // check 0x1)=1) and vAddr xor Oddness vAddr xor Psn = 1) t and not lsb # lsb=0 even page; note FILL fields are 0 FILL fields note even page; # lsb=0 not lsb  t and odd page # lsb=1  t or lsb )-1 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: GDI DPH GDI vAddr xor OddPageBit vAddr xor pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t bits RI/XI place to 64-bit rotate 2) //  ROTRIGHT(t, pw_EntryLo0 pw_EntryLo1 vAddr or Goffset  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, (1<> 6  (1<> pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t if (vAddr and OddPageBit) OddPageBit) and if (vAddr else endif  vAddr2  CCA2) (pAddr2, t t t OddPageBit) and if (vAddr else endif ERROR goto OddPageBit = OddPageBit > 0) then > 0) ROTRIGHT(t, 2) // 64-bit rotate to place RI/XI bits place RI/XI to 64-bit rotate 2) //  ROTRIGHT(t, OddPageBit) and if (vAddr else endif  vAddr2  CCA2) (pAddr2, t t // load second PTE from directory for other TLB page TLB other for directory PTE from second // load else endif REFILL goto  t vAddr // Dual Pages - figure out whether even or odd page loaded first loaded page or odd even out whether - figure Pages // Dual t >> PWField  t pw_EntryLo1 (1 << PWField = OddPageBit lsb pw_EntryLo0 GDW t w  (PWField ( ( PWField if TLB page other for directory PTE from load second // else endif HugePage  true HugePage  true HgPgGDHit t (PWCtl elseif first page loaded or odd even out whether - figure Dual Pages // // generate adjacent page from same PTE for odd TLB page PTE for same from page adjacent generate // endif vAddr CCA) (pAddr, t (t and (1<

4.15 HardwarePageTable Walker d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 77 =1) then# PTEvld is set PTEvld =1) then# ) UDI Hugpg - 2 // right-shift entire PTE entire 2 // right-shift - - 2 // right-shift entire PTE entire - 2 // right-shift PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) DATA, AddressTranslation(vAddr2,  t  t  t  t  t  t ) && PWCtl PTEI Psn = 1) and 0x1)= 0x1) //check if odd e.g. 2x power of 4 2x power e.g. if odd //check 0x1)= 0x1) and t and not lsb # lsb=0 even page; note FILL fields are 0 FILL fields note even page; # lsb=0 not lsb  t and odd page # lsb=1  t or lsb )-1 DPH UDI UDI vAddr xor OddPageBit vAddr xor me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me vAddr or Uoffset  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, (1<> 6 // align PA[12] into EntryLo* register bit 6 register EntryLo* into align PA[12] 6 //  (1<> pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t bits place RI/XI to rotate 64-bit 2) //  ROTRIGHT(t, pw_EntryLo0 pw_EntryLo1 pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 pw_EntryLo0  R > 0) then > 0) ROTRIGHT(t, 2) // 64-bit rotate to place RI/XI bits place RI/XI to 64-bit rotate 2) //  ROTRIGHT(t, OddPageBit) and if (vAddr else endif  vAddr2  CCA2) (pAddr2, t t t OddPageBit) and if (vAddr else endif ERROR goto else endif ERROR goto OddPageBit) and if (vAddr bits RI/XI place to 64-bit rotate 2)// OTRIGHT(t, t OddPageBit = (1 << PWFIELD = OddPageBit t >> PWField  t lsb pw_EntryLo0 pw_EntryLo1 UDW t w  (PWFIELD if ( (PWFIELD page odd TLB for directory PTE from load second // else endif REFILL goto  t vAddr else endif REFILL goto  t vAddr // Dual Pages - figure out whether even or odd page loaded first page loaded or odd even out whether - figure Dual Pages // HugePage  true HugePage  true HgPgUDHit t odd TLB page PTE for same page from adjacent generate // (PWCtl elseif else endif else endif vAddr CCA) (pAddr, t (t and (1<

) PTEW ged Resource Architecture, Rev. 6.03 =1) then# PTEvld is set is PTEvld =1) then# ) MDI Hugpg - 2 // right-shift entire PTE entire 2 // right-shift - - 2 // right-shift entire PTE entire - 2 // right-shift PTEI AddressTranslation(vAddr2, DATA, LOAD, KERNEL) LOAD, DATA, AddressTranslation(vAddr2,  t  t  t  t ) && PWCtl PTEI Psn DSize * 2 = 1) and 0x1)= 0x1) // check if odd e.g. 2x power of 4 2x power odd e.g. if // check 0x1)= 0x1) and )-1 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III:  DPH MDI MDI vAddr xor (1 << (NativeShift + PWSize (NativeShift (1 << vAddr xor t # note FILL fields are 0 are fields FILL  t # note t and not lsb # lsb=0 even page; note FILL fields are 0 FILL fields note even page; # lsb=0 not lsb  t and odd page # lsb=1  t or lsb vAddr OR Moffset OR  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, LoadMemory(CCA2, DSize, pAddr2, vAddr2, DATA) vAddr2, pAddr2, DSize,  LoadMemory(CCA2, >> PWField  t bits place RI/XI to 64-bit rotate 2) //  ROTRIGHT(t, pw_EntryLo0 pw_EntryLo1 pw_EntryLo1 pw_EntryLo1 pw_EntryLo0 vAddr or PToffset0  vAddr KERNEL) DATA, LOAD,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, > 0) then > 0) rectory (pAddr2, CCA2)  CCA2) (pAddr2, t t t OddPageBit) and if (vAddr else endif ERROR goto ROTRIGHT(t, 2) // 64-bit rotate to place RI/XI bits RI/XI place to 64-bit rotate 2) //  ROTRIGHT(t, OddPageBit) and if (vAddr else endif  vAddr2 t >> PWField  t (1 << PWField = OddPageBit MDW =1) then else endif REFILL goto  t vAddr t pw_EntryLo0 w  (PWField if ( (PWField page odd TLB for directory PTE from load second // DSize DSize HugePage  true HugePage  true HgPgMDHit t pw_EntryLo1 (PWCtl elseif first page loaded or odd even out whether - figure Dual Pages // // generate adjacent page from same PTE for odd TLB page PTE for same page from adjacent generate // bit 6 register EntryLo* into PA[12] align 6 //  (1<> lsb pw_EntryLo0 PTEW else endif vAddr CCA) (pAddr, t (t and (1<

4.15 HardwarePageTable Walker d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 79 ASID ftware attempts to use the invalid TLB entry, a ftware attempts touse the invalid entry, TLB - 2 // right-shift entire PTE entire right-shift - 2 // PTE entire right-shift - 2 // will still fill the page into the TLB. Software can point to PTEI PTEI PTEI ))-1 ))-1 ))-1 ))-1 BDI GDI UDI MDI are not mapped. When the So are not me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me )-1 m>>12 PTI vAddr or PToffset1 or vAddr  (1<<(PWField (1<<(PWField (1<<(PWField (1<<(PWField AddressTranslation(vAddr, DATA, LOAD, KERNEL) LOAD, DATA,  AddressTranslation(vAddr, DATA) vAddr, pAddr, DSize,  LoadMemory(CCA, >> PWField  temp0  ROTRIGHT(temp0, 2) // 64-bit rotate to place RI/XI bits RI/XI to place rotate // 64-bit 2)  ROTRIGHT(temp0, >> PWField  temp1 bits RI/XI to place rotate // 64-bit 2)  ROTRIGHT(temp1, Mask m  m  m  m  case 0100 case 0010 case 0001 case case 1000 case (1<>12) 4KB as smallest to mask field Normalize step: # 2nd pw_PageMask TLBWriteRandom(pw_EntryHi, pw_EntryLo0, pw_EntryLo1, pw_PageMask) pw_PageMask) pw_EntryLo1, pw_EntryLo0, TLBWriteRandom(pw_EntryHi, return(found) table on a page detected is condition an error/exception # If found=0. exits with this function access, memory # walk # OnError: temp1 temp1 into TLB pair Table Entry Page # Load temp0 (pAddr, CCA) (pAddr, if (HugePage) if (HugePage) then # Leaf Level Page Table - Second half of PTE pair of PTE half - Second Page Table Level # Leaf vAddr EntryHi 0xfff )| and not = ( vaddr pw_EntryHi pw_EntryLo0 temp1 pw_EntryLo1  1 found m  endsub # The hardware page walker inserts a page into the TLB in a manner in a the TLB page into a walker inserts page hardware # The handler refill software by the executed as instruction to a TLBWR # identical REFILL: TLB invalid exception will be generated. invalid PTEs to represent regions that If a page is marked invalid, the hardware refill handler MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 80Vo For Programmers Architecture MIPS® Virtual Memory Virtual

(CP0 reg- , An example is the CDMMBase tiated once per VPE, but the VPE, tiated once per pped to correspond to the control and status information in that is reserved for mapping IO reserved is that region. For that reason, the memory For region. as part of the CPU. as part d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 81 ccupies a maximum of 32 kB in the a maximum ccupies cached memory transactions. Accessing Accessing transactions. memory cached CDMMis implemented by readingthe behavior. behavior. virtual address segments (kseg1 or xkphys). User-mode wed, this region could be ma wed, ces and their ACSRs are instan and their ACSRs ces the base physical address of the CDMMaddress physical the base UNPREDICTABLE defined by a coprocessor 0 register called0 defined by a coprocessor Rs), followed by IO device registers. Rs), followed by IO pping using an uncached coherency. coherency. pping using an uncached Blocks’ (DRBs). Each block has access Blocks’ (DRBs). Each block has access the architecture. Software detects if r these device registers. The CDMM o registers. r these device maintain cache coherence for the CDMMcache maintain region be accessed must only using un me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me mory-mapped IO devices that are packaged that IO devices mory-mapped ion of the memory address space. It also enables the use of access control and mem- of access the use enables address also the memory It space. ion of - A new Coprocessor 0 register that sets register 0 - A new Coprocessor register field (bit 3). register is shared among the VPEs. the among register is shared CDMM CDMMBase access control and status registers (ACS and status control access aligned blocks called ‘Device Register Each of these blocks are nowof described these blocksare detail.Each in mapped registers located within this these register using a cacheable CCA may result in result cacheable CCA may these register using a physical address map. The CMDMM is of an optional feature Implementations are not required to Two blocks are defined for the CDMM- Two • ister 15, select 2). This address must be aligned to a 32 kB boundary. must be aligned addressThis to a 32 kB boundary. select 2). 15, ister On a 64-bit core with a TLB-based MMU, this region would most likely be mapped to a physical address which can be accessed through one of the kernel unmapped, uncached ma TLB could be allowed through a access MMU,a FMT thatwould use the regionOn cores most likely be mappedthe to MB and made lower 512 accessible is allo access user-mode if Alternatively, via kernel mode. The physicaladdress for the CDMM facility base is CDMMBase Config3 MIPS processors may include me processors MIPS probemove pins to to data communicationEJTAG the that device uses DebugFastwhich Channel, is a UART-like world. the external space physical address a region of Device Memory Map (CDMM) is Common The The CDMMdevice configuration helps registersaggregate withinvarious devicea MIPS mappings processor. into one area, preventing fragmentat ory address translation mechanisms fo •ControlDevice CDMMand Access kBCDMMThe 32 Register region- Block is divided into smaller 64-byte For implementations that have multiple VPEs, the IO devi kuseg physical address segment.kuseg physical address MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 5.1 CDMMBase Register Common Device Memory Map Memory Device Common Chapter 5 Chapter

shows the organization organization the shows RBs), Each device occupies device RBs), Each registersubsequent and any ing modified. Reading any of modified. ing Figure 5.1 Figure (ACSRs) that are (ACSRs) that are start found at the If user mode access is allowed, If user mode the ged Resource Architecture, Rev. 6.03 register. register. t offset 0x0 from the is CDMMBase) t offset CDMMBase de when such accesses are not allowed, de when such accesses region would be mapped to a physical be mappedregion would to its’ ACSR. ACSRs are only accessible in are only accessible ACSRs its’ ACSR. CDMMBase ‘Device Register Blocks’ (D ‘Device Register Blocks’ nored and the register not be l zeros being returned. Writing any of thel ACSR being zeros returned. Writing registers a ‘Access Registers’ Control Status and for the descriptionthe of or kseg2/3 (using uncached coherency). (using uncached or kseg2/3 itionalspace,address it can occupy multiple contiguous64-byte e.g., blocks, n only increment, the devices must be n only increment, space in a spe- allocated in the memory e physical address map. For each device, device type identification and access device type identification and access each device, map. For e physical address kernel mode access is allowed, the is allowed, mode access kernel located at the address pointed by the pointed the address located at r to the start of the next device and device next start of the r to the register, the first DRBof the CDMM (a register, lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: xt available adjacent DRB. xt available adjacent ce with the lowest physical address. lowest physical address. with the ce the DRB allocated for the devi cated in CDMMBASE Section 9.43 on page 253 bit is set intheset bit is CI address region reachable through kseg1 through reachable region address coherency. uncached an entry must use useg BAT refer to Please reserved for implementation specific use. The CDMMdividedThe is 64-byte into aligned segmentsnamed On cores that use a BAT MMU, if only MMU, if a BAT that use On cores of the DRBsizedevicetheThe ACSR forthethe of the IO address. holds allocated device with a of for the lowest physical a pointe act as also device, and hence kernel mode. The ACSR is followed by the data/control registers for the IO device. device is device is allocated in the ne If the at least one DRB. If a device needs add needs a device at least one DRB. If are adjacent in th multiple DRBs which control information is lo Access control information is specified vi of the CDMM. mo supervisor in either usermode or registers IO device the Reading any of any IO device of the registers in eitherresults in all usermode zeros being returned. or supervisor mode Writing when results in the write being ig allowed, are not such accesses mode results in al kernel the ACSR registers while not in while not inkernel mode results in thewrite being ignoredandbeing the ACSR not modified. Since the ACSR act as a pointer that ca The first device must be cific manner. 82Vo For Programmers Architecture MIPS® 5.2 Blocks Control and Device Register CDMM - Access Common Device Memory Map

State Compliance Reset ged Resource Architecture, Rev. 6.03 R PresetR Required Preset Required R 0 Required R/W 0 Required R/W 0 Required R/W 0 Required R/W 0 Required Write Read / ster Field Descriptions (Continued) Descriptions Field ster that access is disabled. An disabled. is access that that access is disabled. An disabled. is access that k. A device is limited to 4 device A k. read access to this device is This also determines the the determines also This eld to denote the specific eld to denote the write access to this device device to this access write s that accessenabled. is A 1 indicates that access is lue of 0 indicates that only that indicates of 0 lue 1 indicates that access is ss is disabled.An attempt to ss is disabled. attemptAn to isor-mode write isor-mode access to this vision of device. This field is device. of vision number of extra 64-byte blocks blocks 64-byte number of extra Description e. Ignored on write; returns zero e. on write; returns zero on Ignored e ed is ignored. ed is ignored. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: device is A value enabled. of enabled. A value of 0 indicates mode in supervisor while device to the to write attempt with access disabl location of the location next device bloc allocated to this device. allocated to this device. A va allocated. is block one 64-byte kB of memory. fi DevType the with combined device revision. enabled. A value of 0 indicates attemptdevice to read from the whilemode in supervisor with access disabl read. device is A value enabled. of value of 0 indicates that acce dis- with access mode in user while device from the read ignored. abled is enabled. A value of 1 indicate is enabled. A value of 1 indicates that access is enabled. A is enabled. access that A 1 indicates of value is enabled. value of 0 indicates that acce dis- access mode with in user while to the device write ignored. abled is 1 This bit indicates if superv 2 indicates if user-mode bit This 3 This bit indicates if user-mode 0read access isor-mode to this This bit indicates if superv Table 5.1 Table Regi Status and Control Access Fields 0 11:4 63:32, us future Reserved for Sr Ur Sw Uw Name Bits DevRev 15:12the re This field specifies DevSize 21:16th specifies field This 84Vo For Programmers Architecture MIPS® Common Device Memory Map

registers, intro- registers, . Software was en software register is not register IV Count architecture that sup- architecture that Cause ritized by the processor and ritized by the interrupts were combined combined were interrupts introduced wh with GPR shadow GPR shadow with cycles required to process an inter- ically disable or enable interrupts. d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 85 ocessing of Exceptions and Interrupts: and Exceptions of ocessing e Release 1 interrupt e Release 1 , based on the value, based on the of register is required. ces of interrupts are prio definitionthe coprocessor of 0 register fields associ- in its name, it is more correctly described as an NMI described correctly more is it name, its in terrupt controller. This can supportmany more priori- controller. terrupt be used to clear hazards clear hazards used to be EBase bitsinterrupt inthe handler prologue. interrupt mode thatsupports the use of an external inter- er and performance counter er and performance IP e interrupt system state. mechanismto include two optional interruptmodes: register to denote pendingandtimerinter- performance counter Cause interrupt vector(0x200) Cause equals 0. The register, which allows the exception vector base address which allows the to be modified register, significantly reduces the number of controlled by the processor interrupt system. interrupt the processor controlled by a dedicated handler. When combined When a dedicated handler. BEV following features related to the pr support for twosoftware interrupts,hardwaresix interrupts, and twospecial- EBase Status bits in the me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me register for highly applications registerin the which power-sensitive PCI register which affects th which affects register adds an upward-compatible extension to th the interruptarchitecture. Count and rrupts as a function of the as a rrupts TI each interrupt is vectored directly to vectored directly is each interrupt mode this chapter, in the next duced rupt. ated with interruptssupport changesto an external in tized interrupts, while still providing the ability to vector an interrupt directly to a dedicated handler and take GPR shadow registers. the advantage of • External Interrupt Controller (EIC) mode, in which the used, or for reduced power mode. This change is required. is power mode. This change or for reduced used, are required. instructions Both •Interrupt (VI)mode, in whichthe various sour Vectored writes to a coprocessor 0 coprocessor writes to a rupts. This change is required.Thisrupts. change is for exceptions that occur when • The addition of the DI and EI instructions which provide the ability to atom • The additionof the Release 2 of the Architecture Release 2 rupt controller bychanging Although“interrupt”(NMI) includes a Non-MaskableInterrupt ports vectored interrupts. In addition,Release 2 adds a new is it nor not affect, does it exception because • The ability tostop the • The extension of theRelease 1 interrupt control •can sequence which hazard of an execution The addition required to prioritize inte Release 1 of the Architecture included included of the Architecture Release 1 purpose interrupts: timer and performance counter. The tim purpose interrupts:timer counter. and performance Release 2 of the Architecture added the of the Architecture Release 2 • The addition of the 0Coprocessor with hardwarewith Interrupts were handled interrupt eithergeneralthe through 5 in an implementation-dependent manner. the special 0x180) or exception vector (offset MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 6.1 Interrupts Interrupts and Exceptions Interrupts Chapter 6 Chapter

register Debug bit in the bit in DM register. The final interruptThe request register. ions of Release 1 of the Architecture. ions of Release 1 ged Resource Architecture, Rev. 6.03 entation of Release 1 of the Architec- the 1 of entation of Release Status register. e way in which interrupts are handled to provide full functionthethat coprocessor 0 register fields of can bit of the Config3 register are zero, and the register are zero, and IE ring interrupt processing. This modeis optional and its des. Inclusion of the optionalthedes. Inclusion of modes donebe may selec- ioritizationvectoring and This mode of interrupts. is Interrupt Mode y always be implemented and be dynamically enabled based Status y implement up to interruptthree modes: register. ocessors implementing EJTAG) implementing ocessors bit in the the in bit rrupt Controller VEIC error, non-debugmode, processing respectively. error, Config3 bits in the dds the abilitytoprioritize and vector interrupts toa handler dedicated to ERL re is fully compatible with implementat with compatible fully is re register are both zero. e 2of the Architecturee must implement interruptcompatibility mode, and

Table 6.1Table Modes Interrupt VEIC Config3 microMIPS64™ Privile / MIPS64® lume III: and

Status

of the Architecture ma Architecture of the VINT EXL Config3

register is a zero (for pr a zero (for is register

VS register is a one. a register is IntCtl 0 x0 x 10 Compatibility 0 x Interrupt Vectored 1 External Inte

  

IV

Debug Cause bits in the

Status

BEV ERL Status 1 xx 0 xxx x x01 x x01 Compatibility x Compatibility and bit in the bit in the shows the current interrupt modeof theprocessor as a DM EXL IE ture. This modeThis is required.ture. du use for GPR shadow set a and to assign interrupt, that presence is denoted by the VInt bit in the supportfor an external interrupt controller handling pr optional and its presence is denoted bythe A compatible implementation Releas of mayoptionally implementbothvectored one or interrupt mo Table 6.1 the mode. affect tively in the implementation or they ma of the processor, reset statecontrolisinterrupt to0processor of theon coprocessor bits. The compatibility mode such that an imple- of the Architectu mentation of Release 2 Logically, the request for interrupt ANDedis service with the Logically, An implementationof Release 1 of the only Architectureimplements interrupt compatibility mode. of Release 2 An implementation • Interrupt (VI)mode, which a Vectored An interruptis onlywhen taken following all of the true: are •for interruptrequest as a functionservice is made, A specific interruptof the mode, described below. • The • Interruptcompatibility mode, whichidentically acts to that in an implem • The is zero, correspondinga non-exception,to non- is then asserted only if both the • External Interrupt Controller (EIC) mode, which redefines th • The 6.1.1 Interrupt Modes 86Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.1 Interrupts IM6 IM5 IM4 IM3 IM2 IM1 IM0 IM7 y read of the register (not just after and Status and Status and Status and Status and Status and Status and Status and Status = 1). This mode is in effect if any = 1). of This mode is in effect IV IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 87 CalculatedFrom deasserted between the time the processor between the deasserted Interrupt Request Cause Controller mode are are imple- mode Controller SW0 Cause SW1 Cause ts are not implemented,are ts or have been disabled. HW5 Cause HW3HW2 Cause HW1 Cause HW0 Cause Cause HW4 Cause is zero if neither Vectored Inter- Vectored neither if is zero Source mode, interrupts are non-vectoredinterrupts and dispatched mode,are though Interrupt VS Interrupt Mode and the default interrupt mode for a Release 2 processor. interrupta Release 2 processor. and the default for mode e in Interrupt Compatibility Mode e in Interrupt Compatibility . = 0) or vector offset = 0)0x200 or vector (if offset

IV rupt nor External Interrupt rupt nor External Interrupt mented.

methat the software interrupt handler runs. The software interrupt handler

VEIC Config3

me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me

VINT Cause Table 6.2 Config3 ed). Note that an interrupt request may be

Table 6.1Table (Continued) Modes Interrupt

VS IntCtl 0 0 0 Allowed Not - IntCtl Interrupt Type

IV Cause = 1 (if it were zero, the interrupt exception would have to would have exception the interrupt zero, it were = 1 (if

IV BEV Status “x” denotes don’t care “x” denotes don’t 01 = 1 = Hardware Interrupt, Timer Interrupt, or Perfor- Hardware Interrupt, Timer mance Counter Interrupt Software Interrupt Hardware Interrupt Hardware = 0 = 0, which would be the case if vectored interrup case if vectored the be which would = 0, Table 6.2Table Request for Interrupt Servic IV BEV VS /* Assumptions: * - Cause * Cause Status IntCtl This is the only interrupt mode for a Release 1 processor a Release 1 processor interrupt mode for the only This is • This mode is entered when a Reset exception occurs. In this occurs. exception entered when a Reset is This mode 0x180 (if exception vector offset The current interrupt requests are visible via the IP field in the Cause register on an are visible via the The current interrupt requests an interrupt exception has occurr exception an interrupt ti the interrupt exception and the starts for interruptrequest A mustbeprepared to handle this condition bysimply returningthe from interrupt via ERET. isservice generated as shown in A typical softwarefor interrupt handlercompatibility might mode look as follows: the following conditionstrue: are • • 6.1.1.1Mode Compatibility Interrupt MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

*/ VS ged Resource Architecture, Rev. 6.03 bits so that “lower” priority interrupts are interrupts priority “lower” so that bits IM /* and mask with IM bits */ with IM mask /* and */ 16..23 k0 = IP7..IP0; bit set, first /* Find IntCtl software emulate to /* Shift /* Jump to specific exception routine */ routine exception to specific /* Jump lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: eret */ code interrupted to /* Return beqclz zero, Dismiss k0, xori k0 k0, sll */ interrupt - spurious bits set /* no k0, 0x17 k0, k0, VS k0, */ 7..0 => /* 16..23 mfc0mfc0 C0_Cause k0, andi C0_Status k1, and k0, M_CauseIM k0, */ from Cause IP bits only /* Keep k0, k1 k0, */ bits IP for register Cause /* Read bits */ for IM register Status and /* laaddujr VectorBase k1, k0, k1 k0, nop k0 */ vectors of 8 interrupt base /* Get */ offset base and from target /* Compute here) * type. of this an example below is routine NestedInterrupt The disabled. also */ SimpleInterrupt: /* request the interupt and clear here interrupt the device Process * to be may need registers some do this, to order In at the device. * an ERET that is such 0 state The coprocessor restored. saved and * code. interrupted to the return will simply * */ NestedException: /* registers, and Status the EPC saving require typically Nested exceptions * disabling routine, exception the nested by modified be that may any GPRs * loop, putting an interrupt to prevent Status bits in IM the appropriate * code The sample interrupts. re-enabling and mode, kernel in the processor * only intended and is this processing of all nuances cover below cannot * * be isolated from the general exception vector before getting before vector exception the general from isolated be * * * - GPRs k0 and k1 are available (no shadow register switches invoked in invoked switches register shadow (no are available and k1 k0 - GPRs * mode) compatibility * SW1..SW0) (HW5..HW0, is IP7..IP0 priority software - The * * base exception 0x200 from Offset Location: * */ IVexception: /* analogous interrupt, a specific processes routine processing Each interrupt * routine processing each Since mode. EIC interrupt in VI or reached to those * know to the context it has line, interrupt particular to a is dedicated * further to look may need routine Each processing was asserted. which line * requests interrupt multiple if the interrupt of actual source the to determine * the performed, task is that line. Once IP on a single together are ORed * ways: of two in one processed may be interrupt * * The interrupt). simply UART a level (e.g., at interrupt - Completely * this type. of an example below is routine SimpleInterrupt * this In interrupts. other re-enabling and state sufficient - By saving * during disabled are interrupts which determines model software case the * single the is either this Typically, interrupt. of this the processing * or some being processed, the interrupt to corresponds bit that StatusIM * Status of other collection * 88Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.1 Interrupts the interrupt handler. Vectored Inter- Vectored the interrupt handler. d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 89 to a dedicated handler routine. This handler dedicated to a mode by adding a priority encoder to prioritize pending /* Clear bits in copy of Status */ of Status in copy bits /* Clear k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* /* Get restart address */ address restart /* Get */ in memory /* Save */ bit the IM at least include this must /* */ include and may interrupt, current for the /* */ others /* */ be required - may not interrupts /* Disable */ and EPC /* */ and EPC /* */ interrupt the /* Dismiss each interrupt which can be directed mapped to a GPR shadow set for use by use for GPR shadow set mapped to a me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me = 0 = = 1 = 0 = 0 = 1 Save GPRs here, and setup software context */ context software setup here, and Save GPRs  VInt VEIC

IV BEV lVS /* dmfc0 C0_EPC k0, sdmfc0sw EPCSave k0, C0_Status k0, li StatusSave k0, ~IMbitsToClear k1, */ value Status Get /* */ interrupt for this to clear Im bits /* Get and */ in memory /* Save ins k0, k1 k0, (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* interrupt. device clearing here, including interrupt Process * in running a done with may be this environments In some * of scope beyond the is well an environment Such user mode. kernel or * this example. * */ di lwldmtc0 StatusSave k0, dmtc0 EPCSave k1, C0_Status k0, C0_EPC k1, /* Restore GPRs and software state */ eret */ EXL set) (including Status saved /* Get */ value original the /* Restore * to demonstrate the concepts. the to demonstrate * */ Status Config3 IntCt Cause Config3 /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ interrupts interrupts and to generate a vector with to be each interrupt mode also allows theif following all of conditionsrupt in mode are true: effect is • Vectored Interrupt mode builds on the interrupt compatibility Vectored • • • • 6.1.1.2 Interrupt Vectored Mode MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

interrupts at a priority a priority interrupts at is 1, and if interruptsis1, and if are 1 0 7 6 5 4 3 2 , respectively) to providethe d a priority encoder scans the val- priority encoder d a Generated by by Generated IPPCI Vector Number Vector Priority Encoder ged Resource Architecture, Rev. 6.03 entway with the hardware interrupts IntCtl IM2 IM1 IM0 IM6 IM5 IM4 IM3 IM7 and IPTI upt and places the software upt and places bits. If any of these valuesthese bits. If any of and Status and and Status and Status and Status and Status and Status and Status and Status IntCtl IM IP7 IP7 IP2 IP1 IP0 IP6 IP5 IP4 IP3 retedas individualinterrupt hardware requests. The timer Calculated From Calculated Interrupt Request = 0), an interrupt is signaled an ERL HW4HW3 Cause HW2 Cause HW1 Cause HW0 Cause Cause Source Status Interrupt the priority encoder finds the highest priority pending interrupt, it outputs the calculation of the handler for that interrupt, as described below. Thisis the calculation of the handler interrupt, for thatas described below. ity on each hardware interr each hardware ity on combined in an implementation-depend combined lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: . = 0, and = 0, . they are combined indicated by indicated they are combined Type EXL Software SW1 Cause Interrupt bits with the corresponding Status Table 6.3 IP Status Figure 6.1 Cause = 1, Table 6.3Table Mode Interrupt Vectored for Priority Interrupt Relative IE Priority Relative Lowest Priority SW0 Cause Highest Priority Hardware HW5 Cause Status and performance counterand performance interrupts are (with theinterrupt with which In VI interruptInthe mode, six hardware interruptsinterp are The priority order places a relative prior lowerhardware thanall interrupts. When an vector number encoded that is used in in pictorially shown ues in the order shown in enabled ( appropriate relative priority relativeappropriate of theseinterruptThe processor interruptshardware interrupts.of thelogicwith that the each of ANDs 90Vo For Programmers Architecture MIPS® Interrupts and Exceptions

), the timer inter- ), the timer is in effect if all of the in effect is IP1..IP0 the the processor vector Cause here */ here PSS ) to the external interrupt controller, to the external interrupt) controller, ged Resource Architecture, Rev. 6.03 PCI Cause interrupt. interruptEIC mode s, and directly supplying to ller is responsibleprioritizing for all interrupts, including /* Clear KSU, ERL, EXL bits in k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* /* Clear bits in copy of Status */ of Status in copy bits /* Clear /* Disable interrupts - may not be required */ be required - may not interrupts /* Disable */ and EPC /* */ and EPC /* */ hazard /* Clear */ interrupt the /* Dismiss /* this must include at least the IM bit */ the IM at least include must this /* */ include and may interrupt, current for the /* */ others /* a system-dependent way with other hardware interrupts. The interrupt control- lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ), and the performance counter interrupt ( request TI = 1 = = 0 = 0 Cause 0 C0_SRSCtl k0, */ sets shadow if changing SRSCtl /* Save = 1  VEIC

IV BEV VS ins (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* target above, write KSU clear only sets, shadow If switching * switch clear EXL, to eret an do execute to EPC, and address * routine jump to and shadow sets, * */ */ interrupt device clearing here, including interrupt Process /* di lwldmtc0 StatusSave k0, lw EPCSave k1, C0_Status k0, dmtc0 C0_EPC k1, mtc0 */ EXL set) (including Status saved /* Get SRSCtlSave k0, ehb C0_SRSCtl k0, */ value original the /* Restore eret */ SRSCtl saved /* Get */ sets shadow /* Restore swmfc StatusSave k0, */ memory in Save /* swliSRSCtlSave k0, ~IMbitsToClear k1, */ interrupt for this to clear Im bits /* Get and to SRSCtl value write new sets, shadow If switching /* k0, k1 k0, /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ Cause Status Config3 IntCtl • External InterruptControllerwayinterrupt the Mode redefinesprocessor theconfigured that logic is to providesup- Theinterrupt contro port for an external interrupt controller. hardware, software, timer, and performancecounter interrupt hardware, software, timer, number (and optionally the priority level) of thehighest priority where it prioritizes these interrupts in where • • rupt request ( In EIC interrupt mode, the processor sends the state of the software interrupt requests ( followingconditions are true: • 6.1.1.3 External Interrupt Controller Mode 92Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.1 Interrupts when the inter- the when CSS SRSCtl , and interrupts are enabled ) and signals the external registers. This allows the This allowsregisters. codedin value EIC interrupt to determine if the requested IPL IPL is only loadedby the processor IP7..IP2 Status RIPL entations may choose to use the RIPL Status stem environment and needs. stem environment d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 93 dicates that no interrupt requests are no interrupt requests dicates that Cause Cause interrupt processing. The vector number that . , which is copiedto EICSS terruptWhen is currently the interruptserviced). being ing (or designing) the interrupt controller to provide the Figure 6.2 ted. Whented. the processor loadsaninterrupt requestinto t (63) RIPL for the interrupt to be serviced. The interrupt s, which are treated as an en an which are treated as s, le based on control status and control on le based (which overlays (which register is not in thismode,register is used and themappingthe of SRSCtl questsand produces the prioritylevel the and vector num- is strictly greater than than strictly greater is iority level, called the RequestedInterrupt Priority Level service routines is located. routines is the interrupt service where to determine VS RIPL ral as a functionof the sy offset along with the RIPL to the processor. along with the RIPL to the processor. offset IntCtl e as the vector number for the processor. number for the processor. the vector e as SRSMap Cause tions available for the vector offset: tions available for the vector offset: = 0) an interruptrequest is signaledpipeline. to the When the processor ERL ) is interpreted as the Interruptwhichis Priorityatprocessor the Level (IPL) range 0..63, inclusive.A value of 0 in range 0..63, upt, the processor compares RIPL with RIPL compares upt, the processor y software visible register. Some implem y software visible register. the request is being serviced. Because serviced. request is being the me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me Status IM7..IM2 signaled, it is available to software during signaled, it is available to software during than the current IPL. If RIPL IPL. If than the current Status this is not a requirement. = 0, and EXL Status , it also loads the GPR shadowthealsoloads, it GPR set number into (whichoverlays = 1, 1, = IE RIPL IPL 1.valufirst option The is to treat the RIPL 2. The second option is to send a separate vector number along with the RIPL to the processor. 3. A third optionto sendanentirevector is Status startsinterrupt the exception, it loadsRIPL into ( as the vector number, but as the vector number, In EIC interrupt mode, the external interrupt controller is also responsible for supplying the GPR shadow set number servicingto use when the interrupt.such, the As The vector number is not stored in an currently operatingzero indicating (within a value of no that controller requests service for an interr interrupthas higher priority rupt is serviced. operationThe of EIC interrupt mode is shownpictorially in pending. The values 1..63 represent the lowest (1) to highes controllerthistheon value 6 hardware passes interruptline Cause Status mode. There are several mode. There are several implementation op ler can be a hard-wiredcan logicler block,or be configurab it can interrupt controller to notify it that vectored interrupta GPR to shadow set is done by programm correct GPR shadow set number when an interrupt is reques set number correct GPR shadow when an interrupt exception is when an interrupt exception is the into the core is combined with the EIC passes (RIPL), is a 6-bit(RIPL), is a value encoded the in interruptcontroller to be more specificor more gene externalThe interrupt controllerprioritizes interrupt its re the highestof priorityber interruptto be serviced. The pr MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

6.1 Interrupts which is added to 0x200 to cre- here */ here PSS (the default reset state), the vector reset(the default d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 95 Field VS tive subset of the vector numbers and values of - options 1 & 2), a vector number is produced by the inter- to create the interrupt offset, to create the interrupt offset, Value of IntCtl Value VS    /* Clear KSU, ERL, EXL bits in k0 */ bits in ERL, EXL KSU, /* Clear */ interrupts re-enable /* IntCtl ector locations. If this value is zero is this value ector locations. If s to Interrupt Compatibility Mode. A non-zerovalue enables vectoredinter- 0x0280 0x0300 0x0400 0x0600 0x0A00 0x09E0 0x11C0 0x2180 0x4100 0x8000 0x02E0 0x03C0 0x0580 0x0900 0x1000 0x09C0 0x1180 0x2100 0x4000 0x7E00 0x02C0 0x0380 0x0500 0x0800 0x0E00 0x09A0 0x1140 0x2080 0x3F00 0x7C00 0x02A0 0x0340 0x0480 0x0700 0x0C00 0b00001 0b00010 0b00100 0b01000 0b10000 me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me 0123 0x02004 0x02205 0x0200 0x02406 0x0240 0x0200 0x02607 0x0280 0x0280 0x0200 0x02C0 0x0300 0x0300 0x0380 0x0200 0x0400 0x0400 0x0500 0x0600 0x0800 61 62 63 shows the exception vector offset for a representa the exception vector offset shows Table 6.4 Table Interrupts Vectored for Offsets Vector Exception k0, k1, S_StatusIPL, 6 /* Set IPL to RIPL in copy of Status */ copy of RIPL in to IPL 6 /* Set k1, S_StatusIPL, k0, Vector Number Vector field. field. Table 6.4 swins StatusSave k0, ins */ memory in Save /* (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, /* target above, write KSU clear only sets, shadow If switching * switch clear EXL, to eret an do execute to EPC, and address * routine jump to and shadow sets, * */ */ mode, to kernel switch IPL, /* Modify */ interrupt device clearing here, including interrupt Process /* mfc0sw C0_SRSCtl k1, to SRSCtl value new write sets, shadow If switching /* SRSCtlSave k1, */ sets shadow changing if SRSCtl /* Save VS field specifies the spacing between v VS /* above. for VI mode shown to that identical code is completion The interrupt * */ IntCtl IntCtl For vectored interrupts (in either VI or EIC interruptForor vectored interrupts EIC VI modeeither (in rupt control logic. This number is combined with . For VI interrupt. For VI mode,vector theoffset EIC number in0..7,For inclusive.vector the range is ate the exception interruptmode, the vector isthe number in range 1..63, inclusivebeing (0“noencoding the interrupt”). for The spacing is zero and the processor revert zero is spacing rupts, and the 6.1.2 Interrupts for Vectored Offsets Generation of Exception Vector MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

external interrupt). Whenexternal interrupt). an re the change to the interrupt state to re the change 1 0 IE ged Resource Architecture, Rev. 6.03 state to resume the interrupted instruc- to resume the interrupted state Modified Event Count Event “CP0 Hazards” on page on “CP0 Hazards” . In Release 1 of 121 n occurs. Such events can be generated as a by- generated as can be Such events n occurs. CP0 Register Field(s)  0b00000)) added, andadded, this instruction soft- can be used by VS to the interrupt state (either enabling interrupts which tion handler. The saved state and the address tionof the handler. soft- (IntCtl of exception, and the current state of the processor. of the processor. state and the current of exception, instruction execution (e.g., an execution (e.g., instruction d in the chapter d in the /* Disable interrupts */ interrupts /* Disable hazard */ the /* Clear field is made field visible is by an EHB: IM PerfCnt Control PerfCnt Counter offset for a vectored interrupt is: a vectored interrupt for offset sed the interrupt state change and befo and change state the interrupt sed e, the EHB instruction was register fields may changefields mayregister the conditions underinterruptwhich an is taken. ds is modified by the listed instruction, makes the change to the interrupt terrupts which were previously enabled). urally-definedmethod for boundingof the number instructions which would lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: azard, as describe ops processingsaves sufficient instructions, , and starts a software excep a and starts , struction are made visible by an EHB: are struction EI, DIEI, Status IE MTC0MTC0 Status Cause IM, IPL,ERL, EXL, IE IP MTC0 MTC0 Table 6.5Table EHB by Visible Made Changes State Interrupt Instruction(s) CP0 Register Written lists the CP0 register fields which can cause a change lists the CP0 register di mfc0ins C0_Status k0, mtc0 1 zero, S_StatusIM4, k0, ehb C0_Status k0, */ instruction this later than seen no is state the interrupt Change to /* */ IM field 4 of the bit /* Clear ehb */ instruction this later than seen no is state the interrupt Change to /* */ the register /* Re-write hazard */ the /* Clear 0x200 + (vectorNumber  + (vectorNumber  0x200 vectorOffset An EHB, executed after one of these fiel after one executed An EHB, state visibleinstruction than the no later followingEHB. the change to the Cause following example, a the In were previously disableddisabling or in ware to clear the hazard. clear to ware Table 6.5 the Architecture, there was no architectnothe Architecture, was there be after the instruction executed which cau was seen. In Release 2 of the Architectur Software writes to certain 0 coprocessor 0 (CP0) h coprocessor This creates a Normal executionwhen an exceptio of instructions may be interrupted Similarly, the effects of an DI in the effects Similarly, product ofproduct instruction execution(e.g., an integer overflow instruction caused by an add TLB missor caused by a a loadinstruction), or byaneventdirectly not related to exception occurs, the processor st Mode Kernel enters tion , ware exceptionhandlerfunctiontheof both type are a The general equation for the exception vector equation general The 6.1.2.1 Hazardsand Software the Interrupt System 96Vo For Programmers Architecture MIPS® 6.2 Exceptions Interrupts and Exceptions

Reset Type 6.2 Exceptions Debug Debug Debug Debug Debug Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 97 e other exceptions, on was asserted. sserted. Prioritized sserted. Prioritized teger overflow, trap, overflow, teger ocessor 2 exception. ocessor 2 highest to lowest. highest was one when the when the excep- was one went to zero. went to that one can into single-step EXL EXL struction. If any two exceptions was illegal: Coprocessor Unus- priority over the Reserved Reserved over the priority leted because it was not allowed allowed it was not because leted match) conditi rted to the processor rted to the valid TLB entry which the XI bit had TLB entry which valid d. Prioritized abov d. Prioritized the Coprocessor Unusable Unusable the Coprocessor and eak condition was asserted. condition eak Description Brk Brk or DINT) was asserted. eak on load/store (address match only) or a match only) (address load/store eak on ception occurred: In exceptions to allow break on exceptions illegal instruc- , floating-point, copr break condition was a ncy was detected by the processor. tive priority of each, priority tive zero in the TLB entry mapping the address refer- address the mapping entry TLB the in zero was asserted to the processor. ception, deferred because because ception, deferred tion fetch matched a rd-aligned address was loaded into PC. loaded into address was rd-aligned t signal was asserted to the processor the to asserted was signal t rror occurred on an instruction fetch. an instruction occurred on rror B miss an instruction on occurred fetch. instruction could comp instruction not be Table 6.6Table Exceptions Priority of n imprecise EJTAG data br n imprecise EJTAG me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me The Rese The A watch address match was detected on an instruction fetch. Priori- fetch. instruction an on detected was match address watch A An instruction-based ex instruction-based An An enabled interrupt occurred. An enabled tion was detected,was tion was asserted after including asynchronous exceptions, so exceptions, asynchronous including interrupt handlers. asynchronous) (or other An EJTAG instruction instruction EJTAG An A precise EJTAG data br precise A EJTAG A watch ex watch A An EJTAG interrupt interrupt (Ejtag An EJTAG fetch above instruction tion addresses. tized above instruction tized above fetch exceptions to allow watch on illegal instruction addresses. enced by an instruction fetch. set. store (address+data on break data able, MDMX Unusable, Reserved In instruction, same on the occur take MDMX Unusable Exceptions Exception. Instruction system call, breakpoint data illegal on break to allow exceptions fetch data above Prioritized addresses. access to the required resources, or required resources, access to the An instruc An An internal inconsiste internal An An EJTAG SDBBP instruction was instruction executed. SDBBP An EJTAG The Cold Reset signal was asse signal Cold Reset The occurre Single Step An EJTAG lists all possible exceptions, and the rela the and exceptions, lists all possible Exception Table 6.6 Interrupt Watch Deferred Debug Interrupt Data BreakImprecise Debug Check Machine A Debug Instruction Break Nonmaskable Interrupt (NMI) Interrupt Nonmaskable NMI signal The Reset Soft Reset Debug Single Step Watch - Instruction fetch Instruction - Watch Address Address Error - fetchInstruction fetchRefill - TLB/XTLB Instruction non-wo A TL A TLB Invalid - Instruction fetch Execute-Inhibit TLB valid bit was The Precise Debug Data Break Cache Error Cache Error - Instruction fetch fetchBus Error - Instruction SDBBP fetch. cache A on error occurred an instruction bus A e Instruction Validity ExceptionsInstruction Validity An Execution Exception 6.2.1 Exception Priority MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

or Type Synchronous Synchronous Asynchronous e table above considers e table there is a relative priority priority is a relative there ly to instruction execution. execution. ly to instruction to allow watch to allow watch ged Resource Architecture, Rev. 6.03 her exceptions because of the of her exceptions because ously to instruction execution. instruction ously to lt of instruction execution, and execution, instruction lt of exceptions as between occurring . EJTAG . EJTAG 0xFFFF.FFFF.BFC0.0000 explains of each excep- the characteristics nously to instruction execution. to the previous instruction, or the relative spectively, in the EJTAG_Control_register. in the EJTAG_Control_register. spectively, iority to guarantee that the processor can can the processor that to guarantee iority tion that caused the exception. These excep- the that caused tion rity than synchronous exceptions mainly for mainly for rity than synchronous exceptions Table 6.8 Table ion. The ordering of th of The ordering ion. entry mapping the address refer- presence of other exceptions, both asynchro- of other presence entry mapping the address refer- address mapping the entry ion execution, and is instruction execution, of as a result ta fetch exceptions Characteristics Description s detected on the address referenced by referenced s detected a on the address d a valid TLB entry whose RI is bit set. priority with respect to ot to respect with priority w other types of exceptions, but s referenced, by a load s referenced, by a load or store instruction d on a load or store data reference bove other synchronous exceptions to allow entry exceptions to Debug synchronous bove other exception that occurs asynchron d on a load or store data reference exception that occurs asynchronous ug exception that occurs as a resu a as ug exception that occurs ce. If one thinks of asynchronous exception that occurs asynchro , 0xFFFF.FFFF.BFC0.0480 or to location ns are always vectored to location vectored to are always ns lid bit was zero in the in the TLB zero lid bit was lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: dirty bit was zero in the TLB ligned address, or an address that was inaccessible in the cur- in the inaccessible was that address an or address, ligned una An load or store. Prioritized above da store. Prioritized or load illegal data addresses. on rent processor mode wa processor rent store instruction or by a load enced enced by a store instruction by a store enced A watch address match wa match address watch A The va A data read access matche A A bus error occurre A cache error occurre describes the typeof exception. Table 6.7Table Characteristics Type Exception Table 6.6Table (Continued) of Exceptions Priority Denotes any other exception that occurs any other Denotes Denotes any other type of type other any Denotes of synchronous exceptions with each other. exceptions with synchronous of Mode, even in the presence of other exceptions. to the respect instruc with precisely reported tions tend to be prioritized belo highest priority relative highest priority to the next instruct way. second the in them These the exception. caused that to the instruction with respect precisely is reported prioritized a exceptions are instructions, they are either the lowest priority the lowest either are they instructions, These exceptions always have the highest pr highest the have always exceptions These always be placed in a runnable state. placed in a runnable be always high exceptions have very These desire to enter Debug Mode, even in the desire to enter nous and synchronous. These exceptions are shown with higher prio shown with higher exceptions are These notational convenien ectored to location ectored to Table 6.7 Exception Exception Type Synchronous Synchronous Debug deb an EJTAG Denotes Asynchronous Asynchronous Reset a reset-type Denotes Asynchronous Asynchronous Debug debug an EJTAG Denotes Asynchronous Debug exceptions are v if the ProbTrap bit is zero or one,zero bit is re if the ProbTrap 0xFFFF.FFFF.FF20.0200 The Reset, Soft Reset, and NMI exceptio Reset, and NMI Reset, Soft The The “Type” column of The “Type” tion type. Watch access - Data Watch Address error - Data access error Address TLB Read-Inhibit TLB/XTLB Refill - Data - accessData Refill TLB/XTLB access Data Invalid - TLB access on a data occurred A TLB miss TLB Modified - Data access Data - Modified TLB The Cache Error Cache Error - Data access Bus Error Bus Error - Data access 6.2.2 Locations Exception Vector 98Vo For Programmers Architecture MIPS® Interrupts and Exceptions

reg- reg- bit in the the in bit equals 0. 0. equals Status EBase IV BEV 6.2 Exceptions contains zeros in Status 15..12 is 0. is function of the state that VS bit is setin the gives the offset from the from gives the offset lease 1 of the architecture in lease 1 of the architecture EBase tuation can only occur when a IntCtl BEV or base address. In Release 1 of the In Release 1 or base address. Table 6.4 er than the general exception vector. vector. exception the general er than d Resource Architecture, Rev. 6.03Resource Architecture, Rev. d 99 0xFFFF.FFFF.BFC0.0200 0xFFFF.FFFF.BFC0.0200 BEV itecture (and subsequent releases), software is releases), (and subsequent itecture 1 

0x000 

Status Vector Offset Vector ssible vector addresses as a as vector addresses ssible the vector address value assumes the assumes that the vector address value 31 12 31 30 have the t in the vector offset. This si in the vector offset. t ss as a function of the exception. Note that the Note the exception. a function of ss as have the 0xFFFF.FFFF.BFC0.0000 0xFFFF.FFFF.BFC0.0480 0xFFFF.FFFF.FF20.0200 EBase EBase = 1. For implementations of Re  0x000 register for exceptions that register for occur when

 IV  31 30 01 31 30 0x000 28 12 were 0. were EBase VS Cause EBase EBase not changed notitsfrom state reset and that  IntCtl function of the exception and whether the the exception and function of if this condition if not is met. 0xFFFF.FFFF.8000.0000 0xFFFF.FFFF.A000.0000 dedicated exception vector offset, rath vector offset, dedicated exception = 0 and 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF For Release 1 of the architecture: For Release 2 of the architecture: Note that EBase fixed value 0b10 fixed For Release 1 of the architecture: For Release 2 of the architecture: fixed value 0b10 fixed Note that BEV me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me = 0 Table 6.9Table Offsets Exception Vector Status Exception UNDEFINED FFF is generatedFFF whenwith an interrupt VI occurs or EIC interrupt modeenabled. The ease 2 of the Architecture (and subsequent releases), subsequent (and Architecture of the 2 ease Table 6.8Table Addresses Base Vector Exception tion. To avoid complexity in the table, tion. To base address was fixed. In Release 2 of the arch was fixed. In address base TLB Refill, EXL Exception = 1, the vector offset is as = if the 1, vector offset gives the offsets from the vector base addre from the base vector the gives offsets Reset, NMI IV combines these two tables into one that contains all po combines these two gives the vector base address as a as the vector base address gives Cause register causes Interrupts to use a to use Interrupts causes register Table 6.9 Other EJTAG Debug (with ProbTrap = 0 in Debug (with ProbTrap EJTAG the EJTAG_Control_register) = 1 in Debug (with ProbTrap EJTAG the EJTAG_Control_register) Cache Error Reset, Soft

which Table 6.10 architecture, the vector architecture, via the base address specify the vector allowed to Cause mbination of a vector offset and a vect and a Addresses for offset are a all other exceptions of a vector combination In Release 2 of the Architecture (and In Release 2 of the Architecture releases), software must subsequent guarantee that Table 6.8 ister, as implemented in Release 2 devices, is ister, ister. ister. vector offset greater than 0x greater than vector offset operation of the processor is operationis processor of the all bit positions less thanorto equal the most significant bi Forimplementations Rel of can affect the vector selec can affect base address in the case where base address in the case MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

= 0 VS Vector = 0) 0xFFFF.FFFF.BFC0.0300 0xFFFF.FFFF.8000.0180 0xFFFF.FFFF.8000.0200 0xFFFF.FFFF.BFC0.0380 0xFFFF.FFFF.BFC0.0400 0xFFFF.FFFF.8000.0180 0xFFFF.FFFF.BFC0.0380 0xFFFF.FFFF.A000.0100 0xFFFF.FFFF.BFC0.0380 0xFFFF.FFFF.BFC0.0380 0xFFFF.FFFF.8000.0180 0xFFFF.FFFF.BFC0.0200 0xFFFF.FFFF.BFC0.0280 0xFFFF.FFFF.8000.0000 0xFFFF.FFFF.8000.0080 0xFFFF.FFFF.BFC0.0000 0xFFFF.FFFF.BFC0.0480 0xFFFF.FFFF.FF20.0200 0xFFFF.FFFF.8000.0180 BEV assumes that EBase retains its its assumes thatEBase retains reset state and thatIntCtl reset state For Release 2 Implementations, ged Resource Architecture, Rev. 6.03 g exceptions, which have their own spe- Status x x x x x x x x x x x x 1 0x080 0x100 0x180 EJTAG EJTAG Vector Offset Vector ProbTrap IV (In Release 2 0x200 implementa- (In Release interrupt table when interrupt table tions, this is the base of tions, this is the base of the vectored 0 1 0 1 x x x x x x x x x Cause ‘x’ denotes don’t care don’t ‘x’ denotes ns have the same basic processing flow: processing basic same the have ns EXL 0 0 0 0 1 1 0 0 x x x x x lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: set, NMI, cache error, and EJTAG Debu and EJTAG set, NMI, cache error, Table 6.10Table Vectors Exception = 1 IV Status Exception Cause Table 6.9Table (Continued) Offsets Vector Exception BEV 0 0 1 1 1 0 0 1 0 1 1 0 x Reset, Soft Reset, NMIReset None (Uses Address) Base Cache error Exception General Interrupt, 64-bitXTLB Refill, 0 EXL = Status l 11xx l 10xx l 00xx l 01xx l l l l i i i i f f f f e e e e cial processing as described below, exceptio cial processing as described below, With the exception of Reset, Soft Re With

R R R R Exception B B B B L L L L 6.2.3 General Exception Processing T T T T Interrupt Interrupt Interrupt Interrupt All others All others Cache Error X Cache Error X X TLB Refill X TLB Refill Reset, Soft Reset, NMIReset, Soft Reset, DebugEJTAG Debug EJTAG xTLB Refill x xTLB Refill x x x x 0 100Vo For Programmers Architecture MIPS® Interrupts and Exceptions

= BEV Status 6.2 Exceptions ). The value loaded ). The value loaded from the appropri- from the loaded ASE, and whetherASE, and the shows the value stored in stored the value shows bitchanged is not inthe register unless it wishes to registerchanged. is not BD PC at which executionPC at which will be es appropriateexception. to theThe Cause in the 32-bit ISA Mode), SRSCtl Table 6.11 Table ease 2 of the Architecture ease 2 of the if bit Table 9.55 onTable 9.55 page 235 bit in the the in bit in EPC/ErrorEPC/DEPC BD ISA Mode bit field, and the CSS value is value field, and the CSS r implements the r implements MIPS16 register (see register (see PSS ISA Mode registerwith is loaded the register is not loaded and the and not loaded is register Cause /* PC of instruction */ of instruction /* PC EPC EPC with the the MIPS16 ISA MIPS16 Mode the and PC-4 with the combined . For implementations of Rel registers are loaded with registers the valu nor SRSCtl are modified */ modified are nor SRSCtl Release 2 of the Architecture, the the Architecture, the of 2 Release EPC BD Cause No Address of the instruction No combined instruction, of the the address of bits 63 Upper Software need not look at the Yes of Address the branch or jump instruction (PC-4) Yes in instruction (PC-2 jump or the branch bits of 63 Upper register. on that actually caused the exception. on that actually register is copied to the register is copied to me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 101 Delay Slot?Delay stored Value register is set, the register is set, register is zero, the register is In Branch/Jump Status SRSCtl represents the restart address for the exceptionnot and need be modified by exception d at the exception vector. exception d at the fields of the of the fields Status Status bit is set appropriately in the set appropriately is bit registers, including registers, including is 1, all exceptions go through the general exception vector */ vector exception general the go through 1, all exceptions is  1  0 EPC BD EXL BD BD = 1 then ExcCode registerdependent is processothe on whether EXL field in the No No bit in the bit in the Yes Yes EPC  restartPC EPC Cause restartPC/* PC of branch/jump */ of branch/jump PC  restartPC/* EPC Cause bitin is set the Table 6.11Table in EPC, ErrorEPC, or Stored DEPC on an Exception Value EPC MIPS16 , and register. For implementationsof register. CSS EXL EXL CE EXL else endif vectorOffset  0x180 vectorOffset then if InstructionInBranchDelaySlot Implemented? field is loaded, fieldnot but is defined, for any exceptionthan type a coprocessor other unusable exception. restarted and the restarted and if Status into the /* If Status CE Cause ate source. If the 0, the else /* and neither EPC nor Cause EPC nor and neither /* instructionjumpbranch or delayhas is in the which of a slot delay slots. each of the CP0 PC each of the handler software in the normal case. • The identify the address of the instructi Note that individual exception types may load additional information into other registers. This is noted in the descrip- type below. tion of each exception Operation: •If the the •If • The is starte processor The value loaded into value loaded The • The . MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

= 0) then = BEV  0b00000)) VS ged Resource Architecture, Rev. 6.03 (IntCtl = 0) then */ = 0) 4 0) and (Status 0)  VS  HSS  0x000 4+3..IPL  = 0) then = 0) 31..12 forces the base to be in kseg0 or kseg1 */ or kseg1 in kseg0 be base to the forces VS EICSS IPL /* Assume exception, Release 2 only */ 2 only Release exception, /* Assume RIPL 31..30 = 1) or (IntCtl = 1) 2) and (SRSCtl 2) and BEV  2 then  = 1 then = 0) then */ = 0) then ESS CSS IV lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: VEIC = 1) or (IntCtl = 1) or = 1 then */ = 1 then VecNum  EIC_VecNum_Signal VecNum VecNum  Cause VecNum BEV 0xFFFF.FFFF  EBase 0xFFFF.FFFF 0xFFFF.FFFF.8000.0000 EXL SRSCtl NewShadowSet = 0) then elseif (EIC_option2) elseif endif  SRSCtl NewShadowSet  VIntPriorityEncoder() VecNum  SRSMap NewShadowSet  EIC_VectorOffset_Signal vectorOffset  + (VecNum  0x200 vectorOffset if (EIC_option1) 0xFFFF.FFFF.BFC0.0200 IV   vectorOffset  0x200 vectorOffset if Config3 else endif if (EIC_option3) else endif PSS CSS = 1 then 1  ExceptionType vectorOffset  0x180 vectorOffset if (Status else endif /* if (Status /* if endif BEV  vectorBase  vectorBase  vectorBase else SRSCtl vectorOffset  0x000 vectorOffset  0x080 vectorOffset if (Cause /* The fixed value of EBase value of The fixed /* endif /* if (Cause /* if endif SRSCtl  FaultingCoprocessorNumber  SRSCtl ShadowSet EXL CE ExcCode else endif endif /* Compute vector offsets as a function of the type of exception */ exception of type of the a function as offsets vector Compute /* New then */ = Interrupt) (ExceptionType /* elseif endif */ of implementation for an set information shadow Update the /* /* Release 2 of the architecture */ if (ArchitectureRevision if ExceptionType = TLBRefill then = TLBRefill ExceptionType if then = XTLBRefill) (ExceptionType elseif then = Interrupt) (ExceptionType elseif if ArchitectureRevision if ArchitectureRevision vectorBase  vectorBase endif endif /* if Status /* if endif Cause */ address base the vector Calculate /* if Status Cause else Status 102Vo For Programmers Architecture MIPS® Interrupts and Exceptions

register 6.2 Exceptions ErrorEPC instructions from 0xFFFF FFFF FF20 FFFF 0xFFFF ; ing aborting state machines, ing aborting state machines, Random register is deprecated in . Note that thisvalue mayor may to a specified state. to ) nditions is met. Refer to the EJTAG EJTAG the to Refer met. is nditions ich it can execute 29..0 ing registers have defined state: Table 6.11 Table EJTAG_Control_register reset initialization,includ e result of powere result being of appliedbecauseprocessorthe to register are initialized register are serted to the processor. This exception is not maskable. processor. serted to the + vectorOffset Status register interrupt enables are cleared. are interrupt enables register 29..0 some implementations, loaded the value into bit is zero in the mber of TLB entries minus one. The mber of TLB entries registers are initialized withstate. boot their one of a number of EJTAG-related co one of a number of EJTAG-related fields of the fields of /* No carry between bits 29 and 30 */ bits 29 and between carry /* No a Reset Exception, only the follow only a Reset Exception, Config3 ProbTrap )

ERL me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 103 , and  (vectorBase Performance Counter , and have zeros in each bit position less than or */ less than bit position in each have zeros NMI , Config2 63..30 , s of this exception. of s 0xFFFF FFFF BFC0 0000. 0xFFFF SR bit is one. 15..12 , register is loaded with the restart PC, as described in the restart PC, as loaded with is register TS register is initialized to the nu , Config1

, register is initialized to zero. BEV ProbTrap , register enables and register enables ErrorEPC Wired Config RP Random offsets > 0xFFF (vectored or EIC interrupts only), require */ require only), interrupts EIC or 0xFFF (vectored > offsets  vectorBase 0xFFFF FFFF BFC0 0000 TLBEntries - 1  TLBEntries Random Watch /* that EBase Release 6. may notmaypredictable be Reset or Soft Reset Exception. on either a /* Exception PC is the sum of vectorBase and vectorOffset. Vector */ Vector vectorOffset. and vectorBase sum of PC is the Exception /* /* /* equal to the most significant bit position of the vector offset */ vector of the position bit significant the most equal to /* PC PCmay have nota valid valuein that case. In not be predictable was taken as not be predictable if the Exception Reset th • • The if the 0200 if the Entry Vector Used Entry Vector the 0480 if FFFF BFC0 0xFFFF Specificationdetail for A Reset Exception occurs when the Cold Reset signal is as Reset when the Cold A Reset Exception occurs An EJTAG Debug Exception occurs when An EJTAG a full occurs, the processor performs a Reset Exception When y placing the processor in a state in wh a state in in processor the establishing critical y placing and generall state, • The • The Operation • loaded with is PC ExcCode Value Register Cause None Saved Additional State None Used Entry Vector Reset ( • The • The uncached, unmapped address space. On space. uncached, unmapped address 6.2.5 Reset Exception 6.2.4 Exception Debug EJTAG MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Reset Exception is typically ssor may reset the same state is exception is not maskable. to a specified state. to other processor state may be incon- may state other processor ged Resource Architecture, Rev. 6.03 tions is in actual use. The is in actual use. tions a subset of the full reset initialization.Although a Soft register are initialized register are sserted to the processor. Th to the processor. sserted l problem. As such, the proce the As such, l problem. n of any state saved by software mayn of any state different. software be very saved by followingestablished state is onReset a Soft Exception: Status address space. Since bus, Since space. tions from unmapped address uncached, # Suggested - see Config register description register - see Config # Suggested # This bit becomes reserved in Release 6 Release in reserved bit becomes # This 6 Release in reserved bit becomes # This # 1KB page support implemented support page # 1KB implemented support page # 1KB implemented page support # 1KB # Large physical address implemented address physical # Large implemented address physical # Large implemented address physical # Large # For all implemented Watch registers all implemented # For Watch registers all implemented # For Watch registers all implemented # For pted, portions of the cache, memory, or cache, memory, pted, portions of the fields of the fields of lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ERL rily change the state of the processor, it may be forced to do so in order to place to forced to do so in order may be it of the processor, state rily change the , and  0 registers PerfCnt all implemented # For IE NMI  0 ,

SR ,  0  0  0  0  0  0  0  0 0 0 0 1 0 1 HighestImplementedShadowSet  0

TS I R W , ELPA ESP        MaskX PFNX PFNX 2  0  0   0  0 VPN2X  0 BEV ESS PSS CSS K0 RP BEV TS SR NMI ERL VS HSS , DC ExceptionBase RP restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xFFFF FFFF BFC0 0000 FFFF BFC0  0xFFFF SRSCtl SRSCtl  0 SRSMap Cause EBase  ConfigurationState Config1  ConfigurationState Config2  ConfigurationState Config3 WatchLo[n] Status Status IntCtl SRSCtl Status Status Status SRSCtl EntryLo0 then if InstructionInBranchDelaySlot else endif PC PageGrain  0 Wired  0 HWREna EntryHi Status  ConfigurationState Config Config EntryLo1 PageMask PageGrain WatchLo[n] WatchLo[n] PerfCnt.Control[n] sistent. between the Reset and Soft Reset Excep The primary difference cache, or other operations may be interru may or other operations cache, Reset Exception does not unnecessa Reset Exception does not instruc a state in which it can execute the processor in When a Soft Reset Exception occurs, the processor performs whileSoft the Reset Exception typicallyused to initialize from is a non- recover used topower-up, the processor on The semantic is provided to allow boot difference software to save critical coprocessor 0 responsive (hung) processor. or other register state to assist in debugging the potentia interpretatio but the signal is asserted, reset either when Inaddition toanyhardware initialization required, the • The A Soft Reset Exception occurs when the Reset signal is a is when the Reset signal A Soft Reset Exception occurs 6.2.6 Reset Exception Soft 104Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.2 Exceptions zation. The state of the cache, the following exceptions: the following . Notevalue that thisor may may . to a specified state. to a rdware initiali Table 6.11 Table 6.11 is asserted to the processor. to the is asserted are initialized register register register interrupt cleared. enables are Status # Suggested - see Config register description register - see Config # Suggested 6 Release in reserved bit becomes # This 6 Release in reserved bit becomes # This # Large physical address implemented address physical # Large implemented address physical # Large implemented page support # 1KB # Large physical address implemented address physical # Large implemented page support # 1KB implemented page support # 1KB # For all implemented Watch registers all implemented # For Watch registers all implemented # For Watch registers all implemented # For ) fields fields of the me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 105 on occurs when the NMI signal signal when the NMI on occurs ERL Performance CounterPerformance  0 registers PerfCnt all implemented # For daries, so does not do any daries, reset or other ha IE , and NMI 0xFFFF FFFF BFC0 0000. 0xFFFF 0xFFFF FFFF BFC0 0000. 0xFFFF ,  0  0  0  0  0  0  0  0 0 1 1  0

register is loaded with restart PC, as described in PC, loaded with restart is register register is loaded with the restart PC, as described in PC, as with the restart loaded is register SR I R W , ELPA ESP    PFNX PFNX MaskX 2  0  0   1 TS VPN2X , SR NMI ERL K0 RP BEV TS register enables and register ErrorEPC BEV ErrorEPC restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xFFFF FFFF BFC0 0000 FFFF BFC0  0xFFFF 0xFFFF FFFF BFC0 0000 0xFFFF FFFF BFC0 Status WatchLo[n] Status Status Status Status Status if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif PC EntryLo0 Watch EntryLo1 PageMask PageGrain PageGrain EntryHi Config notbe predictable. WatchLo[n] WatchLo[n] PerfCnt.Control[n] Although described as an interrupt, it is more correctly described as an exception because it is not maskable. An NMI Although described as an interrupt, it is occurs only at instruction boun is consistent state andand other processor with all regist ers are preserved, memory, • The • The A nonmaskable interruptexcepti • • loaded with is PC Operation • loaded with is PC Value ExcCode Register Cause None Saved Additional State None Used Entry Vector Reset ( • The 6.2.7 Non Maskable Interrupt (NMI) Exception MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

register field is used to dis- register field is used MCCause ged Resource Architecture, Rev. 6.03 PageGrain feature is supported and the methodPage Dual is also scriptions above. bit set and the second PTE accessed has PTEVld entry a TLB-based MMU.If the Hardware Page Table Walker Walker Table the Hardware Page a TLB-based MMU.If # This bit becomes reserved in Release 6 Release in reserved bit becomes # This ocessor detects an internal inconsistency. exception. See the de exception. ) ) lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: under the following circumstances: 1 1 1    0   0 Table 9.56 onpage238 ERL BEV TS SR NMI restartPC # PC of branch/jump # PC of restartPC  ErrorEPC instruction # PC of restartPC  ErrorEPC 0xFFFF FFFF BFC0 0000 FFFF BFC0  0xFFFF 0xFFFF FFFF BFC0 0000 0xFFFF FFFF BFC0 if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif PC Status Status Status Status Status ary. feature is implementedthe andHuge Directory-level page supported, and if the first accessed has PTE entry PTEVld bit clear. An address error exception occurs An address • A loador store doubleword instructionwhich is executedinaddressnot the aligned is ona doubleword bound- The followingThe conditions exception: a machine check cause • Detection of multiple matchingentries TLB in the in A machine check exception occurs when the pr occurs when the A machine check exception Register ExcCode Value Register Cause MCheck (See Operation Saved Additional State the caused on the condition that Depends Register ExcCode Value Register Cause None Saved Additional State None Used Entry Vector Reset ( If there are multiple causes for the machine check exception, then the for the If there are multiple causes tinguishwhich condition caused theexception. Used Entry Vector 0x180)General exception vector (offset 6.2.9 Address Error Exception 6.2.8 Machine Check Exception 106Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.2 Exceptions Compatibility Address Space Compatibility Address Value failing address UNPREDICTABLE UNPREDICTABLE UNPREDICTABLE an Address Error is generated is implementation-depen-Addressan Error B Invalid exception occurs. Refill exceptions have distinct register. Note that this is distinct from the case in which register. an ted 64-bit address whentedaddress 64-bit 64-bit address references are B-based when MMU to no TLB entryreference matches a a point at the unaligned instruction address. Status R of the MIPSthe Architecture of documentation set. BadVAddr XContext and Register State Volume I-A VPN2 bit is zero in the the in zero is bit EPC VPN2 R me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 107 VPN2 EXL LB Refill Exceptions LB Refill rences are not enabled. not are rences . EntryHi XContext EntryHi EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddr Context . Therefore, both when 64-bit address refe 64-bit address when enabled. Table 9.56 onpage238 •unimplemenundefinedan A reference is made to or Release 6 supports misalignedRelease 6 load/store handling.Whether dent, as described in Appendix B of updatedPC is the before the con- Notethatcase of an instruction in the isfetch that not aligned word boundary, on a dition is detected A TLB Refill or XTLBexceptionA TLB RefillRefill a TL occurs in mapped address space and the mapped address • An instructionanaddressis from fetched aligned that is not onword a boundary. • A loador store word instructionis executed in whichis not the address alignedwordboundary. on a • A loador store halfword instructionisexecuted in which is not the address alignedhalfwordboundary. on a •or Supervisor Mode. Mode User space from a kernel address to reference is made A •from User Mode. space a supervisor address to made reference is A •of the 32-bit range the that is outside address a a 64-bit to reference is made A entry matches but has the valid in whichbit case a off, TL Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State Register ExcCode Value Register Cause or an instruction fetch a load AdEL: Reference was a store AdES: Reference was See 6.2.10 TLB Refill and XT MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

of = 0 at the time of exception. reg- = 0 at the time of exception. field field EXL 63 62 of the EXL field con- field

ged Resource Architecture, Rev. 6.03 BadVPN2 Context Status of thefailing Status , and the the , and VirtualIndex VirtualIndex 63 62 XContext BadVPN2 = 1 at the time of exception = 1 at the time of -1SEGBITS 13 -1 13 led 64-bit address space. led 64-bit of the failing address. EXL field contains VA R

eld contains the ASID of the ASID of the contains eld 63 62 S-1) of the virtual address SEGBITS Status Value virtual address that missed. virtual EntryHi register are loaded withhigh- the register are loaded withbits the field contains VA contains field bit is set, then the bits of the of the bits is then the bit set, the then is clear, bit bit is clear, then the the then is clear, bit bit is set, then the bits of the of the failing address the failing of VPN2 field contains VA field contains

R CTXTC CTXTC CTXTC CTXTC

31 13 ContextConfig ContextConfig EntryHi if 64-bit addresses are enabled and are enabled if 64-bit addresses 64-bit addresses are not enabled and Config3 Config3 Config3 Config3 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: that missed and the R field contains VA field the R and that missed order bits (starting order at SEGBIT If (starting at bit 31) of the the of at bit 31) (starting of the field to the field corresponding set bits of the ister corresponding to the set bits of the the the set bits of to corresponding ister of the failing address and the failing address. If field contains VA BadVPN2 that missed reference the failing address; the ASID fi failing the XContext tains VA t 0x180) in either case if . Register State EntryHi The XContext If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddrContext Failing address If Table 9.56 onpage238 Entry Vector Used Entry Vector • TLB Refill vector0x000) if (offset Additional State Saved Additional State Register ExcCode Value Register Cause fetch an instruction load or Reference was a TLBL: store a TLBS: Reference was See exception vector offsets: 0x000and 0x080(“XTLB”) refill.TLB Refillextended a 32-bitfor The for a 64-bitTLB exception vector offsets: an enab is made to whenever a reference refill handler is used XTLB • 0x080) XTLB Refill vector (offset • exception vector (offse General 108Vo For Programmers Architecture MIPS® Interrupts and Exceptions

XI 6.2 Exceptions

of reg- field field 63 62 of the field con- field

BadVPN2 Context reference matches a TLB entry whose reference matches of thefailing ction fetch matches a TLB entry whose a TLB entry whose matches ction fetch , and the the , and VirtualIndex VirtualIndex 63 62 BadVPN2 XContext -1SEGBITS 13 -1 13 of the failing address. field contains VA R

eld contains the ASID of the ASID of the contains eld 63 62 S-1) of the virtual address SEGBITS s are a special case and are not affected by the RI bit. by the not affected are and special case s are a Value virtual address that missed. virtual EntryHi register are loaded withhigh- the register are loaded withbits the field contains VA contains field bit is implemented withinthisis enabled, the TLB and is bit is clear, then the the then is clear, bit of the bits is then the bit set, the then is clear, bit bit is set, then the bits of the XI of the failing address the failing of VPN2 field contains VA field contains

R CTXTC CTXTC CTXTC CTXTC

31 13 ContextConfig ContextConfig the virtualthea memory address of load EntryHi Config3 Config3 Config3 Config3 that missed and the R field contains VA field the R and that missed order bits (starting order at SEGBIT If (starting at bit 31) of the the of at bit 31) (starting of the field to the field corresponding set bits of the ister corresponding to the set bits of the the the set bits of to corresponding ister of the failing address and the failing address. If field contains VA BadVPN2 that missed reference tains VA address; the ASID fi failing the XContext me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 109 bit. MIPS16 PC-relative load bit. . RIE XIE Register State EntryHi The XContext If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE BadVAddrContext Failing address If 0 TLBL == 1 TLBXI == PageGrain PageGrain IEC IEC Table 9.56 onpage238 PageGrain PageGrain denoted by the Register ExcCode Value ExcCode Register Cause if Entry Vector Used Entry Vector 0x180)General exception vector (offset if See Additional State Saved Additional State An Read-Inhibit exception occurs when An Read-Inhibit exception occurs RI bit is set. ThisRI bit exception is only typecan occur RI bit is implemented if the withinenabled,and is the TLB this is denoted by the en the virtual occurs when the virtual address of exception An Execute-Inhibit an instru bit is set. This exceptionThis set. is bitif the type can only occur 6.2.12 Read-Inhibit Exception 6.2.11 Exception Execute-Inhibit MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

bit is one EXL

of reg- field field field 63 62 of the R field con- field

BadVPN2 ged Resource Architecture, Rev. 6.03 BadVPN2 Context of thefailing VirtualIndex VirtualIndex 63 62 XContext BadVPN2 -1SEGBITS 13 to a mapped address space and the to a mapped address space ception, in the sense that both use the general excep- that both use in the sense ception, eld contains the ASID of the ASID of the contains eld S-1) of the virtual address , and the The only wayThe only to distinguishisprob- bycases these two Value tryHi R field contains VA tryHi R field -1 13 virtual address that missed. virtual register are loaded withhigh- the register are loaded withbits the field contains VA contains field bit is clear, then the the then is clear, bit of the bits is then the bit set, bit is set, then the bits of the bit is clear, then the bit XContextis clear, SEGBITS of the failing address. of the failing address the failing of VPN2

63 62 CTXTC CTXTC CTXTC CTXTC 31 13 ContextConfig ContextConfig EntryHi Config3 Config3 Config3 Config3 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: that missed and the R field contains VA field the R and that missed order bits (starting order at SEGBIT If (starting at bit 31) of the the of at bit 31) (starting of the field to the field corresponding set bits of the ister corresponding to the set bits of the the the set bits of to corresponding ister of the contains VA the En address, and failing address. If field contains VA contains field address; the ASID fi failing the reference that missed reference tains VA no TLB entry matches a reference no when a TLB entry matches a reference to a mapped address space, but the matched space, to a mapped address a reference TLB entry matches when a . Register State XContext If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE EntryHi The BadVAddrContext Failing address If == 1 TLBRI == 0 TLBL IEC IEC register is indistinguishablea TLBInvalid from Ex Status Table 9.56 onpage238 PageGrain PageGrain Entry Vector Used Entry Vector 0x180)General exception vector (offset See Additional State Saved Additional State if in the tion vector and supplyTLBS. an ExcCodeof value TLBL or theingmatching for TLB a entry (using TLBP). A TLB invalid exception occurs A TLB invalid thebit validentry has off. that the condition in which Note Register ExcCode Value Register Cause if 6.2.13 TLB Invalid Exception 110Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.2 Exceptions

of reg- field field field 63 62 of the R field con- field

BadVPN2 BadVPN2 Context of thefailing bit is clear, then this exception also this exception then clear, bit is IEC VirtualIndex VirtualIndex 63 62 XContext BadVPN2 -1SEGBITS 13 R field contains VA contains R field eld contains the ASID of the ASID of the contains eld S-1) of the virtual address , and the PageGrain e loads are a special case and are not affected by the RI the RI by not affected are case and special a are e loads t set on a memory load reference, or with the XI bit set set bit XI the with or reference, load a memory on set t Value -1 13 virtual address that missed. virtual EntryHi register are loaded withhigh- the register are loaded withbits the field contains VA contains field bit is clear, then the the then is clear, bit of the bits is then the bit set, bit is set, then the bits of the bit is clear, then the bit XContextis clear, SEGBITS of the failing address. of the failing address the failing of VPN2

63 62 CTXTC CTXTC CTXTC CTXTC reference to a mapped when the matching address TLB entry is valid, 31 13 ContextConfig ContextConfig EntryHi Config3 Config3 Config3 Config3 that missed and the R field contains VA field the R and that missed order bits (starting order at SEGBIT If (starting at bit 31) of the the of at bit 31) (starting of the field to the field corresponding set bits of the ister corresponding to the set bits of the the the set bits of to corresponding ister of the contains VA address and failing the address. If the failing address; the ASID fi failing the that missed reference field contains VA contains field tains VA me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 111 emented within emented within the TLB and the . tion occurs ona store Register State XContext If EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE EntryHi The BadVAddrContext Failing address If bit is zero, indicatingnotthe that writable. page is D Table 9.55 onpage235 A TLB modified excep A TLB modified If the RI and XI bits are impl bits are RI and XI the If Entry Vector Used Entry Vector 0x180)General exception vector (offset Additional State Saved Additional State occurs if a valid,foundif matching a withis TLB entry occurs bi the RI on an instructionmemory fetch PC-relativreference. MIPS16 bit. Value ExcCode Register Cause fetch an instruction load or Reference was a TLBL: store a TLBS: Reference was See but the entry’s but the entry’s 6.2.14 TLB Modified Exception MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

of reg- field field 63 62 of the field con- field

ged Resource Architecture, Rev. 6.03 BadVPN2 Context of the failing failing the of , and the the , and VirtualIndex VirtualIndex 63 62 XContext BadVPN2 -1SEGBITS 13 -1 13 of the failing address. R field contains VA contains R field eld contains the ASID of the ASID of the contains eld 63 62 S-1) of the virtual address SEGBITS ference detects a cache tag or data error, or a parity or error, data a cache tag or ference detects Value virtual address that missed. virtual EntryHi register are loaded withhigh- the register are loaded withbits the field contains VA contains field R field contains VA contains field bit is clear, then the the then is clear, bit bit is clear, then the the then is clear, bit of the bits is then the bit set, bit is set, then the bits of the of the failing address the failing of VPN2 field contains VA field contains

R CTXTC CTXTC CTXTC CTXTC

31 13 ContextConfig ContextConfig EntryHi Config3 Config3 Config3 Config3 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: that missed and the order bits (starting order at SEGBIT If (starting at bit 31) of the the of at bit 31) (starting of the field to the field corresponding set bits of the ister corresponding to the set bits of the the the set bits of to corresponding ister of the failing address and failing the the failing address; the ASID fi failing the that missed reference field contains VA BadVPN2 XContext tains VA address. If ) Register State EntryHi The EntryLo0EntryLo1 UNPREDICTABLE UNPREDICTABLE XContext If BadVAddrContext Failing address If ECC error is detected on the system bus ECC error is system bus when a cache This exception is not detected on the miss occurs. maskable. Because the error uncached address. an unmapped, to vector is the exception cache, in a was ExcCode Value Register Cause N/A A cache error exception occurs when an instruction or data re exception occurs when an instruction A cache error Entry Vector Used Entry Vector 0x180)General exception vector (offset Register ExcCode Value Register Cause on page235 Table 9.55 Mod (See Additional State Saved Additional State 6.2.15 Cache Error Exception 112Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.2 Exceptions tected during bus transactions during bus tected request (due to a cache miss or an unca- request (due to a cache  0x100 28..12 EBase r. Notedeerrors that parity r. and bit 29 forced to a 1 puts the */ to a 1 puts forced bit 29 and    31..30 31..30 2 then Register StateRegister Value  CacheErrErrorEPC state Error PC Restart rminated in an erro on, data, or prefetch access makes a bus makes a access on, data, or prefetch me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 113 tions, not bus error exceptions. . = 1 then 0xFFFF.FFFF  EBase 0xFFFF.FFFF 0xFFFF FFFF A000 0000 + 0x100 0000 + FFFF A000 0xFFFF 1 BEV  0xFFFF FFFF BFC0 0200 + 0x100 0200 + FFFF BFC0 0xFFFF /* vector in kseg1 */ vector in /* PC  PC  /* The fixed value of EBase value of The fixed /* ERL ErrorEPC restartPC # PC of branch/jump # PC of restartPC ErrorEPC instruction # PC of restartPC ErrorEPC else endif PC  if ArchitectureRevision if ArchitectureRevision if InstructionInBranchDelaySlot then if InstructionInBranchDelaySlot else endif if Status endif CacheErr  ErrorState CacheErr Status else Table 9.56 onpage238 Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset are reported as cache error excep are reported as ExcCode Value Register Cause IBE:DBE: Error onan instruction reference Error ona data reference See An integeroverflow exception complement overflow. occurs whenselected integer instructions result in a 2’s A bus error occurs when an instructi A bus error occurs te is and that request reference) cheable Entry Vector Used Entry Vector 0x100) Cache error vector (offset Operation Additional State Saved Additional State 6.2.17 Integer Overflow Exception 6.2.16 Bus Error Exception MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 a SYSCALL instructiona SYSCALL executed. is lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: instructionresults in a TRUE value. ) ) ) ) Table 9.55 onpage235 Table 9.56 on page238 Table 9.56Table on page 238 Table 9.56Table on page 238 A breakpoint exception occurs when a BREAK instruction is executed. occurs when a BREAK instruction A breakpoint exception ExcCode Value Register Cause Bp (See Register ExcCode Value Register Cause Sys (See Saved Additional State None Used Entry Vector 0x180)General exception vector (offset Saved Additional State None Used Entry Vector 0x180)General exception vector (offset A system call exception occurs when occurs exception A system call Register ExcCode Value ExcCode Register Cause (See Tr A trap exception occurs when a trap a when occurs exception A trap Saved Additional State None Used Entry Vector 0x180)General exception vector (offset Register ExcCode Value Register Cause Ov (See Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset 6.2.20 Breakpoint Exception 6.2.19 System Call Exception 6.2.18 Exception Trap 114Vo For Programmers Architecture MIPS® Interrupts and Exceptions

”  ” (reserved), ” (Module/ not allowed, a 6.2 Exceptions  ” that access to copro- to that access ations are not enabled, tationsprevious of ISAs ” (higher-order ISA), or an ISA), or (higher-order ”  a Floating-Point Exception, or PS and 64-bit operations or PS and 64-bit operations are are not enabled, assuming that are not enabled, assuming that the coprocessor is llowed. If access to the coproces- Someimplementations of previous opcode encoding of the function field register. lowed, a Coprocessor Unusable Excep- lowed, ” (EJTAG), assuming ” (EJTAG), processor Unusable Exception occurs Unusable processor opcode encoding of the function field when ” (reserved), “ ” (reserved),  FCSR ” (64-bit)operif 64-bit  opcode, some implementations of previous ISAs “ ” (64-bit) if 64-bitnotor enabled, ” are operations COP0  COP1 ccurs instead. Some implemen ccurs ISAs reported this case as opcode encodingof the function fieldis flagged that with opcode encodingof the function fieldis when S, D, or W rs opcodethe encoding rs field of that is flagged with “ opcode encoding when rs is L oding of thethatfieldoding opcode is flagged of with“ opcode when opcodeoperations 64-bit that access to coprocessor 1 is a to coprocessor that access ” (64-bit) if 64-bit operations are not enabled. COP1 REGIMM opcode encoding of the rt field that is flagged with “ COPz COP1X SPECIAL opcode encoding of the function field that is flagged with COP1  e coprocessor is allowed. to allowed. If access is e coprocessor ” (partner available), ” (partner  COP1X ” (64-bit) if 64-bitnot operationsare enabled, or anunimplemented “” ” (higher-order ISA), “ (higher-order ” Exception, setting the Unimplemented Operation bit in the Cause field of Exception, setting the Unimplemented Operation bit in the Cause field of   r Unusable Exception occurs instead. Exception occurs r Unusable If access to the coprocessor is not al  e coprocessor is not allowed, a Co not allowed, a is coprocessor e specifies an unimplemented SPECIAL2 specifies an unimplemented specifies an unimplemented ” (reserved), or an unimplemented “ or an ” (reserved), me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 115 ” (64-bit)64-bit operations if enabled, not are or an unimplemented “  ” (EJTAG). ” (Module/ASE), assuming that access to coprocessor 1 is allowed. If to coprocessor 1 is ” (Module/ASE), assuming that access access to the copro- ” (reserved), “ ” (reserved),  an unimplemented “ ” (Module/ASE), assuming ” (higher-order ISA), or “ (higher-order ” register.  ” (higher-order ISA), “ (higher-order ”  FCSR register. register. that is flagged with “ unimplemented “ CO (reserved), “ Table 9.56 on page238 ) FCSR FCSR ” (higher-order ISA), “ ” (higher-order ” ” (reserved), or any execution of the ” (reserved), or any execution of  ISAs reported this case as a Floating-Point Exception, as case this ISAs reported setting the Unimplemented Operation bit in the Cause thefield of cessor is not allowed, a Coprocesso not allowed, a is cessor an unimplemented “ that is flagged with “ (reserved). that is flagged with or an cessor 0 is allowed. If access to th If access allowed. cessor 0 is instead. reported this case as a Floating-Point as a reported this case the sor is not allowed,sor is not a Coprocessor Unusable Exception o ASE). “ reported this case as a Floating-Point as a reported this case the (reserved), “ that access to th (Module/ASE), assuming Coprocessor Unusable Exception occurs instead. For the “ setting the Unimplemented Operationin bit the Cause field of the rs is access to coprocessor 1 is allowed tion occurs instead.Someimplementations of previous not enabled,not or with a functionencodingfield is that flaggedwith “ unimplemented “ “ • that executed was instruction An •specifies a executed that was instruction An •a specifies that executed instruction was An • a specifies that executed was instruction An •specifies a executed that was instruction An Register ExcCode Value Register Cause RI (See A Reserved InstructionA Reservedfollowing Exceptionthe if of any conditions occurs true: is • an enc specifies that executed was instruction An •specifies a executed that was instruction An • An instructionwas executed that • An specifies a instruction was executed that 6.2.21 Exception Reserved Instruction MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

register is a register was a Status Status bit in the CU2 ged Resource Architecture, Rev. 6.03 MTC2, DMTC2, CTC2, MTHC2. MTC2, DMTC2, Value essor being referenced being essor instruction is executed and the MXof the instruction is executed and the bit register was register was a zero register was a zero. instruction was executed, and the instruction was Status anyof the following conditions is true: Status ) lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: unit number of the unit coproc operating system to save and restore the state of the MDMX accumulator on a on the MDMX accumulator state of and restore the to save system operating bit in the the in bit ) save and restore of the of FPRs). the restore and save ude MFC2, DMFC2, CFC2, MFHC2, CFC2, DMFC2, ude MFC2, bit in the the in bit CU0 CU1 CE Register State Cause Table 9.55 onpage235 zero. COP2 instructions incl was and the executed or Kernel Mode, the or Kernel and Entry Vector Used Entry Vector 0x180)General exception vector (offset Register ExcCode Value Register Cause CpU (See Table 9.55 on page235 Saved Additional State • SWC1, LDC1, or MOVCI (Special SDC1 functionfield opcode encoding) instruction LWC1, A COP1, COP1X, •SDC2 SWC2,LDC2, or LWC2, COP2, A A floating-point exception is initiatedby the floating-point coprocessor to signalfloating-point a exception. An MDMX unusable exception occurs if the MDMX if exception occurs An MDMX unusable A coprocessor unusable exception occurs if A coprocessor unusable Additional State Saved Additional State None Used Entry Vector 0x180)General exception vector (offset • A COP0 or Cache instructionwas executedthe while processor runninga modein was other Debug than Mode 0. Such an exception is used by the context(analogous switch tothe ExcCodeRegister Value MDMX (See Saved Additional State None Used Entry Vector 0x180)General exception vector (offset 6.2.24 Floating-Point Exception 6.2.23 MDMX Unusable Exception 6.2.22 Unusable Coprocessor Exception 116Vo For Programmers Architecture MIPS® Interrupts and Exceptions

6.2 Exceptions register to determine if the ch or cache instruction whose t is a one at the timea one at thewatch that t is a Cause registers.A watch exception is taken the exception actually occurred while in actually the exception bit in the bitchanged. is not WP WatchLo WP ity exception, the lower priority exception is taken. and on is triggered by a prefet triggered by is on Value register isexception set, and the until is deferred both the ting in Debug Mode. Should a watch register match while the floating-point exception the floating-point WatchHi Cause bit is zero. register are both zero. If either bi zero. register are both LL ssor 2 to signal a precise coprocessor 2 exception. coprocessor signal a precise 2 to ssor Software may use the Status bit in the the in bit register and a single instruction generates both a watch exception (which bits) and a lower-prior WP at caused the watch exception, or if the watch exception, or at caused ERL ) Status indicates the cause of me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 117 and ) ) bits of bits the register are zero. EXL ERL register address matchconditions.register triggered A watchor by SCD instruction a SC does so Status and Watch Register State EXL FCSR bits are one in the Table 9.55 onpage235 ERL bits in the or Table 9.55 on page 235 Table 9.55 on page 235 ERL EXL register points at the instruction th and kernel mode. If the immediately if the is deferred by the state of the is deferred the not complete because would the store even if ExcCodeRegister Value (See WATCH exception would normally be taken, the Watch exceptions are never taken if the processor is execu are never taken exceptions Watch the processor is in Debug Mode, the exceptionis inhibited the and It is implementation-dependent whether a data watch excepti whether a implementation-dependent is It address matches the EXL EPC The watch facility provides a software debugging vehicle by initiating a watch exception when an instruction or data the stored in information reference matches the address Register ExcCodeRegister Value C2E (See Saved Additional State Defined by the coprocessor Used Entry Vector 0x180)General exception vector (offset Entry Vector Used Entry Vector 0x180)General exception vector (offset A coprocessor 2 exceptionis initiated by coproce Additional State Saved Additional State Register ExcCodeRegister Value FPE (See 6.2.26 Exception Watch 6.2.25 2 Exception Coprocessor MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

for 6.1 on page 85 ged Resource Architecture, Rev. 6.03 register is zero. is register were zero. This bit directly bit directly This zero. were ion was until after deferred ERL Value Cause rrent handler execution. rrent handler register register is one. s that are pending. s that are Status and Cause bit in the EXL Status bit in the the in bit lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: IV an enabled request for interrupt is made. See Section service causes a watch exception, so software must clear this bit as bit as this clear must so software exception, a watch causes of the part exception to prevent a handler watch exception cu loop at the end of the indicatesinterrupt the Indicates that the watch except that the Indicates both ) IP WP Cause Register State Value Register State Cause Table 9.56on page 238 Entry Vector Used Entry Vector 0x180)General exception vector (offset The interrupt exception occurs when Additional State Saved Additional State Entry Vector Used Entry Vector 0x180)General exceptionthe vector IV if (offset Additional State Saved Additional State Interrupt vector (offset Interrupt0x200) if vector (offset the more information. ExcCodeRegister Value Int (See 6.2.27 Interrupt Exception 118Vo For Programmers Architecture MIPS® Interrupts and Exceptions

to to is set CSS SRSCtl CSS field, and all HSS the current mode. ered shadow set ered shadow register provides the , and SRSCtl , and PSS rence to GPRs work exactly GPRs work to rence SRSCtl r updating the fields in the ition. Privileged software may is copied back into SRSCtl to associate a shadow set with with shadow set a to associate PSS at are not visible in visible at are not field is zero, only the normal GPRs are are logically consid are logically registerthe providesthe number previ- of ne by writingtheESS field to the of is copied to SRSCtl to copied is conditionsthis case, steps 2 and 3 are true. In CSS SRSCtl rrupt mode, thebindingthe interrupt of toa specific el Mode entry condition, refe des with the same capability. This is done by des withintroducing the same capability. s. More precisely, the rules fo rules the precisely, More s. , and is configured in an implementation-dependent way. for thispurpose. The CSS field of the : NMI or cache error. cache : NMI or , and allowing privileged software allowing privileged , and ERL that can besubstitutedcan thattheGPRs normal on for entry to Kernel Mode via an Status er file, even specific er file, even specific shadow th registers source. On an ERET, the value of SRSCtl source. On an ERET, , inclusive must be implemented. If this ed interrupt to a shadow set is do is set shadow a to interrupt ed er set, and the PSS field of the field the PSS set, and er shadow sets implementation-dependent and may range from one (the normal GPRs) to an PSS HSS me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 119 or exception are as follows: or exception are as are redirected to registers that are dedicated to that cond are redirected to registers register is updated if any of the following m ofm 16. Thehighest number actually implementedis indicated by the SRSCtl SRSCtl = 1 = 1 is copiedSRSCtl to is BEV EXL register. If the is operating processor in EIC inte register. CSS Status Status register on an interrupt • are skipped. • The exceptionsets is one that •Debug Mode The exceptionentryinto causes EJTAG • SRSMap need to reference all GPRs in the regist all need to reference are used The RDPGPR and WRPGPR instructions implemented. ous shadow register set (that which was current before the last exception or interrupt occurred). If the processor is operating in VI interrupt mode, binding of a vectored interrupt to a shadow set is done by writing to the 2. SRSCtl rrupt occurs, the value of SRSCtl When an exception or interrupt occurs, the value register. restore the shadow set of the moderestoreset the shadow to which return control SRSCtl Shadow sets are new copies of the GPRs sets are Shadow interrupt or exception. Once a shadow set is bound to a Kern The capability in this at chapter removing is targeted the need to and save restore GPRs on entry to high priority inter- rupts or exceptions, and toprovide specified processor mo as one would expect, but they multiple copies of the GPRs, called entry to Kernel Mode via an interruptGPRs an The normal vector or exception. via entry to Kernel Mode to the value taken from the appropriate appropriate thefromto the value taken 1.the No field in shadow sets between 0 and SRSCtl number of the current shadow regist of the current number Binding of an exception or non-vector or of an exception Binding shadowset is provided by the externalinterrupt controller zero. is GPR shadow sets number of The architectural maximu MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 7.1 Introduction to Shadow Sets GPR Shadow Registers Shadow GPR Chapter 7 Chapter

= 1, 1, = with a IV 0, and EPC 

e which occurs VSS , loading PSS n or interrupt are as follows: or interrupt are as n = IntCtl1, No No IV for a vectored interrupt. ed exception or on exception or ed MIPS64 Only? ged Resource Architecture, Rev. 6.03 itions is true.In this case, step 2 is skipped. = 1 ster at the end of ster an exceptio BEV = 1. conditions These are the = 1). Status VInt register in any case of a nest of any case in register BEV Function register, based on IPL, if the exception on IPL, if based an interrupt, is Cause register, = 1 or Status Config3 SRSCtl ERL register if the exception is an interrupt, Cause an interrupt, is exception if the register register in any other This is the case. condition for a non-interrupt exception, or SRSMap lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Status = 0, and = 0, CSS SRSCtl VEIC SRSCtl register is updated if any of the following cond Table 7.1Table Sets Shadow Supporting Instructions Config3 = 1. These are thea vectored EIC interrupt. conditionsare for 1. These = 0, SRSCtl 

VEIC is updatedfrom one of the following is sources: is copied to is copied SRSCtl VSS RDPGPR Read GPR From Previous Shadow Set WRPGPR Set to Shadow GPR Write PSS CSS Mnemonic a non-vectored interrupt. IntCtl Config3 • DERET is executed A • ERET is executed with An • The ESS field of the • The appropriatethe field of • Thethe field EICSS of before the processor has been fullyinitialize ( Privileged software mayPrivileged switchsoftware shadow the currentby set writing newvalue a into SRSCtl 2. SRSCtl These rules have the effect of preserving the of the effect rules have These 3. SRSCtl target address, and doing an ERET. target 1. No field in the Similarly, the rules for updatingrules for fieldsthe the in the SRSCtl regi Similarly, 120Vo For Programmers Architecture MIPS® 7.2 Instructions Support GPR Shadow RegistersGPR Shadow

ndent cycle-based ndent cycle-based tion of another instruc- that eliminate hazards. To eliminate hazards. To that tion in cycles. It is for this It is for this cycles. tion in and software. As such, and software. new a way that they are backward- ne stages of a MIPS64/ EntryHi tion issues to cycles in a superscalar issued per cycle may be greater than may be greater issued per cycle e are no hardware interlocks. azards and instruction hazards. Both are hazards. and instruction azards implementation-depe act as explicit barriers act as fer to their Implementationtheirfer to documentationthe for y produce results that are noty produce results detectableare that subsequent by hardware interlock exists between one instruction that ns may be greater than the dura ns may be greater ns have been added in such e operation of various pipeli e operation of various rm compact between hardware exists. CP0 hazard inate these inate these hazards. Consumer On Hazard TLBR, TLBWI, TLBWR n, execution of one instructio and by the execu seen e SSNOP instruction to convert instruc e SSNOP instruction 2 of the architecture which architecture 2 of the entations, the number of instructions ure, CP0 hazards were relegated to were ure, CP0 hazards   fferent types of hazards: execution h execution hazards: types of fferent e architecture should re e required to elim me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 121 Table 8.1Table Hazards Execution Possible of execution cycles. When no cycles. When of execution e to a second instruction, to e a ation of the hazard in instructio the hazard ation of ting MIPS processors. ting MIPS Producer lists the possible execution hazards that might exist when ther might exist that execution hazards the possible lists Hazards Related to the TLB Related Hazards MTC0 Table 8.1 required instruction “spacing” that is required instruction “spacing” th defines that MIPS64 Release 1 reason design. Note that, for superscalar MIPS implem that, for superscalar Note one, and thus that the dur thus that one, and defined below. defined below. Release 1 of th using Implementations Execution hazards are those created by the by created are those Execution hazards tion. In privileged software, there are two di Because resources controlled via Coprocessor 0 affect th 0 affect via Coprocessor controlled Because resources microMIPS64 processor, manipulation of these resources ma resources of these manipulation processor, microMIPS64 instructions for some number causes an effect is visibl that causes an effect In Release In Release 1 the MIPS64®of Architect solutions,based primarilyon the SSNOP instruction. Since that time, it has becomeclearis that thisan insufficient practicemustwith that be addressed a fi and error-prone instructions have been added to Release instructions have been the extentpossibleit that was todoso,newinstructio the exis with compatible 8.2.1 Possible Execution Hazards MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 8.2 of Hazards Types 8.1 Introduction CP0 Hazards CP0 Chapter 8 Chapter

, IE , , , , IV IP IM IM IE IE ASID CU ASID EPC, Status Wired Index, EBase Count, Config SRSCtl Cause Status Status Status Status SRSMap WatchHi, WatchLo, Compare, EntryLo0, EntryLo1, EntryLo0, EntryLo1, PageMask ErrorEPC, TLB entry PageGrain PageMask, EntryHi ged Resource Architecture, Rev. 6.03 EntryHi PerfCnt Counter, PerfCnt Control CU Consumer On Hazard BWI, Interrupted InstructionInterrupted Cause TLBWR TLBWR TLBP, Instruction Load or Store MFC0, TLBWIMFC0 Index instruction Coprocessor EntryHi, on the execution depends Status new value of ERET DEPC, MFC0CACHEMFC0 LLAddr PageGrain TagLo Load/store affected by new affected Load/store state TLBP, TLBR, Load/store using new TLB entry TL Interrupted InstructionInterrupted Status                lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Table 8.1Table (Continued) Hazards Execution Possible Producer MTC0 MTCO MTC0 Other Hazards LL, LLD TLBP TLBR or Related to Exceptions Interrupts Hazards MTC0 MTC0 MTC0 CACHE MTC0 TLBWI, TLBWR MTC0 EI, DI 122Vo For Programmers Architecture MIPS® CP0 Hazards CP0

, 1 PSS ASID Status Supported Supported Config Architecture WatchLo WatchHi, SRSCtl EJTAG Cache entries Cache entries Cache a hazard on a modifi- hazard on a e no hardware interlocks. e 8.3 Hazard Clearing Instructions and Events ious GPR context be established early in early be established context GPR ious ng the new value EntryHi n fetch. Rather it is Rather n fetch. eing the new instruc- new eing the instruc- new eing the struction Hazards Hazards struction Consumer On Hazard Consumer On Hazard Function are not meant to cover this case. to cover are not meant nd instruction hazards nd instruction MFC00 register CoProcessor any e executionof one instruction, and seen by the instructionanotherfetch of   Instruction fetch seei Instruction Instruction fetch seeing Instruction the new value (including a change to ERL followed by seg- useg from the fetch an instruction ment) fetch using new TLB Instruction entry entry TLB fetch se Instruction tion stream fetch se Instruction tion stream RDPGPR WRPGPR me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 123        Table 8.3Table Clearing Instructions Hazard Table 8.2Table In Possible structions and Events Table 8.1Table (Continued) Hazards Execution Possible lists the possible instruction hazards when there ar when there hazards instruction lists the possible Producer Producer cation to the previous GPR context field, followed field, followed by a previous-context reference to cation to the previous GPR context because hazard an execution than rather hazard an instruction considered It is GPRs. the prev the that require may implementation some and execution hazards pipeline, the DERET a execution both Clear Hazards Related to the TLB to the Related Hazards MTC0 MTC0 TLBWI, TLBWR Cache an Instruction or Modifying Stream the Instruction to Writing Related Hazards Entry stream Instruction writes CACHE Other Hazards MTC0 Mnemonic 1. This is not precisely a hazard on the instructio Table 8.2 MTC0 lists the instructions designed to eliminate hazards. designed to lists the instructions Table 8.3 Instruction hazards are those created by th created are those hazards Instruction instruction. 8.2.2 Possible Instruction Hazards MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 8.3 Clearing In Hazard

registers and registers Status , the JALR.HB or , the , or lity. See the JALR.HB lity. the target instruction instruction the target such, kernel software run- such, kernel software nother way, no hazards remain no hazards nother way, ErrorEPC Supported Supported ent instructions which will do this , Architecture is encoding was chosen for compat- for was chosen encoding is Release 2 Release 2 Release Release 1 Release All onwards onwards ASE MCU onwards onwards onwards Release 2 ged Resource Architecture, Rev. 6.03 ing the CACHE instruction. EPC tations, including many which pre-date ly implementations re execution of that re execution of , 2 of the 2 of the Architecture, DERET and ERET field of the JALR and JR instructions. hint DEPC and forward compatibi of the instruction and nd instructionhazards betweenthe instruction that or interrupt handler. Said a handler. or interrupt struction description for additionalinformation. Release 1 implementations. As Release 1 implementations. As the Architecture; EHB, JALR.HB, JR.HB, and SYNCI the Architecture; ng of the REGIMM opcode.ofng the REGIMM This encoding was chosen on stream write, and on and befo stream write, , but is included here included 0 hazard, but is y a coprocessor can emulate the function us instruction hazards instruction hazards instruction Function and they are the only timing-independ variant of the NOP/SSNOP encoding. Th azards between the execution atibility withimplemen existing MIPS peline flush clears hazards on most ear hazards on most flush clears peline ecture. In both Release 1 and Release ecture. In both Release 1 and Release also clears both execution a also clears both lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: t of the instruction exception cluded in existing software for backward cluded in existing software d may be still a write of the created between Synchronize caches after instruction stream write stream instruction after caches Synchronize 2 Release chaining to another interrupt. chaining to another Table 8.3Table (Continued) Instructions Clearing Hazard 1 of the architecture. EHB hazard Clear execution IRET not hazards when instruction and execution both Clear ERET hazards and instruction execution both Clear JR.HB and execution both Clear SSNOP No Operation Superscalar SYNCI JALR.HB and execution both Clear for completeness. for instruction stream. As such, it is not precisel As such, stream. instruction Mnemonic 1. SYNCI synchronizes caches after an instructi and JR.HB instructions for additional information. a new encodi using is encoded SYNCI instruction The because it causes a Reserved Instruction exception on all on exception Instruction a Reserved because it causes ning on processors that don’t implement Release 2 implement Release don’t that ning on processors The EHB is instruction a encoded using in both releases in both releases h and ERET clear DERET Even though stream, an execution hazar DERET, ERET, and SSNOP are available in Release 1 of ERET, DERET, were added 2 of the in Release Archit clear hazards both execution and instruction ibility with the Release 1 SSNOP instruction, such that existing software may be modified to be compatible with both Release 1 and Release 2 implementations. See the EHB in The JALR.HB are encodingand JR.HB usinginstructions the bit 10 of comp were chosen for encodings These a pi the MIPS64 architecture. Because JR.HB instructions can be in the DERET or ERET instruction.the DERET In addition, an exception or interrupt created the hazard and the firs hazard and the the created visibleinstructionfirst by the ofinterrupt an exception or handler. 8.3.1 MIPS64 Instruction Encoding 124Vo For Programmers Architecture MIPS® CP0 Hazards CP0

ng. See the ng. See the and EHB SSNOP 8.3 Hazard Clearing Instructions and Events variant NOP encodi of the me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 125 instruction description for additional information. The EHB and SSNOP The EHB instructions are using a encoded 8.3.2 microMIPS64 Instruction Encoding MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 126Vo For Programmers Architecture MIPS® CP0 Hazards CP0

ers) (Others) (Others) (Others) (Others) (Others) Optional Optional Required (Release 6) Required (TLB (Pre-Release 6); (Pre-Release Optional (Others) (Others) Optional Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (TLB MMU) Required (TLB MMU) MMU); Optional(Oth- e PRA. register is discussed Each 9.6 on page 9.4 on page Reference Compliance Level mber, then by select field number. then field number. by select mber, MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification Section Section Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification Section 139 MIPS®MT Module Module MIPS®MT Specification 135 MIPS®MT Module Module MIPS®MT Specification dual registers are described later in this document. If used without generat- (TLB MMU)”), it applies only (TLB MMU)”), it appliesif the qualifyingcondition true. is ead configuration infor- configuration ead ead configuration infor- configuration ead containing relatively vol- containing Function register containing global register containing global nfiguration data used in the used in field of the same name MTC0 instructions. in the MFC0 and Required ide interface the ISA and between the th numerical order, first by registernu numerical order, me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 127 ing an exception ing qualifier bits may be bits may qualifier mation mation atile thread co thread atile Index into the TLB Index into the TLB array ration information ration array ration information ration MIPS® MT configuration data configuration MT MIPS® gister Summary Table 9.1Table Order in Numerical 0 Registers Coprocessor Register Name 1 lists the CP0 registers in numerical order. The indiviThe lists the CP0 registers in numerical order. below, with the registers presented in with the registers presented below, The Sel column indicates the value to be Table 9.1 The Coprocessor 0 registers prov (CP0) “ the compliance level is qualified (e.g., 1 4 YQMaskwhich YIELD register defining Per-VPE 1 3 VPEConf1 multi-thr Per-VPE 1 2 VPEConf0 multi-thr Per-VPE 1 1 VPEControl register Per-VPE 01 3 MVPConf1 0 Randomconfigu- multi-VPE dynamic Per-processor the TLB index into Randomly generated 0 2 MVPConf0configu- multi-VPE dynamic Per-processor 0 00 Index 1 MVPControl Per-processor Number Sel Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.1 0 Re Coprocessor Coprocessor 0 Registers 0 Coprocessor Chapter 9 Chapter

ers) ers) ers) ers) (Others) (Others) (Others) (Others) (Others) Optional Optional Optional Optional Optional Optional (Release 2) uired (SmartMIPS (SmartMIPS uired Recommended Recommended Required (TLB Required (TLB Required (TLB Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Module); Optional Optional Module); Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (MIPS MT Required (Release 6) ASE); Optional (Oth- Req MMU); Optional(Oth- MMU); Optional(Oth- MMU); Optional(Oth- page 157 ged Resource Architecture, Rev. 6.03 9.7 on page 9.9 on page 9.7 on page 9.11 on page Reference Compliance Level on MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Section 141 MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification 153 Specification ification and Section ification and 9.10 MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification MIPS®MT Module Module MIPS®MT Specification Section 141 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Module MIPS®MT Specification Section Section 159 SmartMIPS ASE Spec- ASE SmartMIPS of and Status g g Halt state of TC MIPS®MT Module as cache partition- as cache partition- and read via RDHWR ocessor implements the the implements ocessor to manage scheduling to manage restart instruction address configuration Function to manage scheduling a of to manage scheduling er to provide scheduling er to provide information, including cop- information, registers. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Per-TC register to provide control register to provide control over Per-TC Per-TC register controllin register Per-TC TC back to software virtual pages odd-numbered optional features, such ing control ing system use for the associatedfor of execution thread binding feedback to software optional features, such virtual even-numbered pages of bits thread-specific of ies a VPE withina VPE a processor control ing EntryHi register 29. the If pr regis- a per-TC is MT Module, this MIPS® ter. privileged software Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 22 63 TCSchedule 7 TCScheFBack register Per-TC 03 register to provide scheduling feed- Per-TC EntryLo1 74 Low-order portion of the TLB entry for TCOpt 0 Context in memory entry table to page Pointer Section 2 5 TCContext read/write storage for operating Per-TC 4 1 ContextConfig Context register 2 4 TCHalt 2 3 TCRestart value of Per-TC 2 2 TCBind TC ID information about and VPE Per-TC 1 5 VPESchedule register Per-VPE 11 6 VPEScheFBack 72 regist Per-VPE VPEOpt 02 EntryLo0over control register to provide Per-VPE 1 Low-order portion of the TLB entry for TCStatus status Per-TC 4 2 UserLocal by be written can that information User Number Sel Register 128Vo For Programmers Architecture MIPS® Coprocessor 0 Registers

ers) ers) (Others) Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Required Reserved (Release 2) Required (TLB Required (TLB ASE); Optional Module); Optional Optional Module); Required (MIPS MT Required (Release 2) Required (SmartMIPS (SmartMIPS Required MMU); Optional(Oth- MMU); Optional(Oth- 9.25 on page 9.24 on page 9.16 on page 9.13 on page 9.14 on page 9.17 on page 9.18 on page 9.19 on page 9.20 on page 9.21 on page 9.22 on page 9.23 on page Reference Compliance Level 9.1 Coprocessor 0 Register Summary ection ection S Section Section Section 9.15Section on page Section Section 199 Section Section 197 175 163 Section 165 169 and SmartMIPS ASE Specification 175 175 Section Section 181 Section Section 181 MIPS®MT Module Module MIPS®MT Specification Module MIPS®MT Specification Module MIPS®MT Specification Module MIPS®MT Specification 193 184 Section 191 Module MIPS®MT Specification gister set configura- gister set configura- gister set configura- gister set configura- gister set gister set configura- gister set Hardware Page Walker Page Hardware Section r of fixed (“wired”) inters for Hardware Page Hardware Page inters for Address for Hardware Address for Function all page support ster configuration me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 129 address-related exception to selected hardware registers to Reserved for future extensions future Reserved for entries Page Walker Controls the numbe Walker controlling shadow re controlling shadow re controlling shadow re controlling Control Page Walker HW tion tion tion tion controlling shadow re controlling TLB entries tion controlling shadow re controlling na Enables accessvia the instruction RDHWR Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name HWRE 1 0 8 0 BadVAddrrecent most the for the address Reports 4 3 XContextConfig XContext regi 5 2 SegCtl01& Segments 0 for Control Programmable Section 7 1-7 5 3 SegCtl13& Segments 2 for Control Programmable Section 5 05 PageMask 1 size page Control for variable in TLB PageGrain Control for sm 5 4 SegCtl25& Segments 4 for Control Programmable Section 5 5 PWBase Base Page Table 5 6 PWFieldof po Bit indices 5 7 PWSizeof pointers for Size 6 36 SRSConf2 46optionally and register indicating Per-VPE SRSConf3 56optionally and register indicating Per-VPE SRSConf47 6optionally and register indicating Per-VPE PWCtl 6 2 SRSConf1optionally and register indicating Per-VPE 6 0 Wired 6 1 SRSConf0optionally and register indicating Per-VPE Number Sel Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

6) 6) ers) ers) ers) dent dent mented) (Others) (Others) (Others) (Others) Required Required Required Required (TLB Module; Optional Module; Module; Optional Module; Module; Optional Module; Optional Module; Required (Release Required 2 Required (Release 6) Required (Release 6) Required (Release 2) Required (Release 2) ASE); Optional (Oth- ASE); Optional (Oth- Required (MIPS VZE Required Required (MIPS VZE Required Required (MIPS VZE Required (MIPS VZE Required Optional (Pre-Release Optional (Pre-Release Optional (Pre-Release Optional (Pre-Release Required (MIPS MCU Required Required (MIPS MCU Required MMU); Optional(Oth- implementation-depen- implementation-depen- and shadow sets imple- and ged Resource Architecture, Rev. 6.03 9.27 on page 9.33 on page 9.34 on page 9.26 on page 9.28 on page 9.32 on page 9.31 on page 9.35 on page 9.29 on page 9.30 on page Reference Compliance Level Section Section Section Section Section Section Section 9.36Section on page MIPS® VZE Module VZE Module MIPS® MIPS® VZE Module MIPS® Section Section 203 213 225 Section Section 201 205 Section 211 211 Specification Specification MIPS® VZE Module VZE Module MIPS® 229 Section Section 205 207 Specification Specification 233 Specification Specification MIPS® MCU ASE MIPS® Set Control VZE Module MIPS® which caused the which caused and IPL fields. IPL and MCU ASE MIPS® t status and control Section ementation-dependent ementation-dependent ementation-dependent lized Guest lized status and control Section ch instruction if a delay instruction ch Function ruction GuestCtl0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Processor cycle count cycle Processor Interrupt system Interrupt Shadow register se Shadow slot causedmost therecent exception. Processor status and control Processor most recent exception. exception. most recent user Available for impl for Available user Available for impl for Available Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 9 0 Count 8 1 BadInstr the inst Reports 8 2 BadInstrP Reports the bran 9 6-7 11 6-7 1111 0 Compare 4 GuestCtl0Ext interrupt control Timer of Extension 12 1 IntCtl 12 0 Status 12 2 SRSCtl 10 0 EntryHi portion of the High-order TLB entry Section 10 410 GuestCtl1 510virtua GuestID of GuestCtl2 6Control Guest Interrupt GuestCtl3 Register Guest Shadow 12 3 SRSMap set IPL mapping Shadow 12 412 View_IPL 5 view Contiguous of IM SRSMap2mapping set IPL Shadow Number Sel Register 130Vo For Programmers Architecture MIPS® Coprocessor 0 Registers

ers) dent (Others) (Others) Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Required Required Required Required Required Module); Optional Optional Module); Module); Optional Optional Module); Required (Release 2) ASE); Optional (Oth- Required (MIPS VZE Required Required (MIPS VZE (MIPS Required Required (MIPS MCU Required implementation-depen- age p on 9.42 on page 9.38 on page 9.40 on page 9.41 on page 9.39 on page 9.48 on page 9.49 on page 9.50 on page 9.51 on page 9.52 on page 9.47 on page 9.43 on page 9.46 on page 9.56 9.37 on page 9.44 on page 9.53 on page Reference Compliance Level 9.1 Coprocessor 0 Register Summary Section Section Section Section Section Section Section Section Section Section Section Section Section Section Section Section 249 Section Section 241 Section 245 247 Specification 243 267 271 279 285 Section 293 263 Specification Section 253 259 235 Section 255 295 Specification MIPS® VZE Module 307 MIPS® VZE Module t OS and RIPL fields. and MCU ASE MIPS® zed Gues ementation-dependent cation and cation and revision Section ger Global Control ger Global Control Regis- Function ce Memory Map Base ion Support - EXL, ERL val- ion Support - Program Coun- general exception Offset me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 131 Cause of last Exception vector base register vector base Exception ues at current exception ter at current exception user register ter Base register Available for impl for Available Program counter at last exception at last counter Program Section register Configuration Processor identifi Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name 1 15 1 EBase 1314 514 NestedExc 015 EPC Nested except 2 NestedEPC 0 PRId Nested except 1616 216 Config2 316 Config3 3 register 2 Configuration 16 Config4 4 register 3 Configuration Config5 6-7 register 4 Configuration register 5 Configuration 15 2 CDMMBase Common Devi 16 1 Config1 register 1 Configuration 17 0 LLAddr Load linked address 1313 0 Cause 4 View_RIPL view Contiguous of IP 1516 3 CMGCRBase 0 Mana Coherency Config 18 0-n WatchLo address Watchpoint 12 7 GTOffset Timer Guest 12 6 GuestCtl0 Control of Virtuali Number Sel Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ers) dent mended. mended. Optional Optional Optional Optional Optional Required Reserved Pre-Release 6: Recommended Required (Cache) Required Required (Cache) Release 6: Required. at select 3 are recom- 3 are select at MMU) Optional (Oth- Required (64-bit TLB Required (64-bit TLB select 2 and KScratch2 Optional; KScratch1 at implementation-depen- Specification Optional ged Resource Architecture, Rev. 6.03 9.57 on page 9.59 on page 9.58 on page 9.63 on page 9.67 on page 9.68 on page 9.69 on page 9.70 on page 9.72 on page 9.65 on page 9.64 on page 9.66 on page ce Specification Optional ce Specification Optional Reference Compliance Level ection ection Section Section S Section Section PDtrace SpecificationPDtrace Optional PDtrace PDtrace SpecificationPDtrace Optional PDtrace SpecificationPDtrace SpecificationPDtrace Optional Optional 309 Section 315 311 EJTAG SpecificationEJTAG Optional EJTAG SpecificationEJTAG Optional EJTAG SpecificationEJTAG Optional 323 335 337 339 341 345 331 329 333 PDtra PDtra che data interface data che Section er er Kernel Mode Section ster ster ontrol and status and ontrol Section ementation-dependent ementation-dependent Function rror control and statuscontrol rror Section control register control register control register lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Low-order Low-order portion of ca Reserved for future extensions. extensions. future for Reserved High-order portion of cache tag interfaceHigh-order Section High-order portion of cache data interfaceof portion High-order Section Available for impl for Available use Program counter at last EJTAG debug debug at counter last EJTAG Program exception Scratch Registers for for Scratch Registers EJTAG Debug Debug register EJTAG Low-order portion of cache Low-order tag interface Section Parity/ECC error Parity/ECC error c Table 9.1Table (Continued) Order in Numerical 0 Registers Coprocessor Register Name TagHi TagLo DataLo DataHi 1 selects selects selects selects 19 0-n WatchHi22 control Watchpoint all 20 021 XContext all Context Page Table Addressing Extended Section 23 0 Debug 23 1 TraceControl control regi PDtrace 232323 424 5 TraceIBPC 6 TraceDBPC 0 PDtrace control regist Debug2 PDtrace control regist DEPC Debug2 register EJTAG 2425 2 TraceContol3 0-n regi control PDtrace PerfCntinterface counter Performance 29 even 3131 0 2-7 DESAVEn KScratch debug exception save register EJTAG Specification EJTAG Optional 30 0 ErrorEPCerror last at counter Program 23 2 TraceControl2 PDtrace 2728 0-3 CacheErr even Cache parity e 23 3 UserTraceData1 PDtrace 26 0 ErrCtl 28 odd 24 3 UserTraceData2 PDtrace 29 odd Number Sel Register 132Vo For Programmers Architecture MIPS® Coprocessor 0 Registers

rchitec- 9.2 Notation UNPRE- UNDEFINED this field return the this field return the field, and the reset state the field, elds that are reserved for elds Software reads of this ly, by hardware. ly, eld with zero before it as all previous software as hout affecting hardware hardware hout affecting e read from a coprocessor 0 register register 0 coprocessor from a e read the impactPro- of writes to other fields. value except after a hardware after value except Software Interpretation Software re and, potential re and, . Software updates of this field are visi- field return zero as long writes are zero. “Undefined”, field is of this State If the Reset software must writethis fi is guaranteed to read as zero. A field to which the value written by software the value written to which A field must be Software writes of non-zero val- zero. result in may field to this ues hardware. the behavior of A field to which the value written by is written software the A to which value field Software may write any by hardware. ignored field wit this value to reads of Software behavior. updated by hardware. last value “Undefined”, field is of this State If the Reset in an software reads of this field result DICTABLE specified in update under the conditions done field. the description of the the read/write properties of the read/write properties ing coprocessor 0 register fi This rule means that software can read a register, modify rule means that software can read a register, This e bits is consistent with software assumptions. tion behavior. e by and writable readable softwa not intended to act as a not intended s the term “Externally s value. This should not be formal return a predictable confused with the stream). These terms are are terms These stream). that the state is estab- assume that it can validly write the valu the appropriate state, the register withoutthe register havingconsider to me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 133 w, field descriptions include field descriptions w, Table 9.2Table Bit Field Notation Read/Write UNDEFINED teproperties thethe field, of following notationused: is Hardware Interpreta licitly noted as available for implementation-dependent use is reserved for future use by A use the by for future use is reserved implementation-dependent for available as noted licitly Hardware by software read Hardware updates visible of this field are ble by hardware read. value the initialize must hardware or software either is “Undefined”, field of this State Reset the If before first read will the of definition by hardware. If the Reset of this State field is either “0”, “Pre- initializes hardware Set”, “Externally or set”, to or zero to field this is term “Preset” The powerup. on respectively, the establishes processor the that suggest to used appropriate state, wherea is used to suggest Set” lishedviasource an external (e.g.,personality pins or initialization bit and are suggestions only, which hardware can assume a zero value. requirement on the implementation. is of this field “Undefined”, If the Reset State those under only this field hardware updates of the description conditions specified in the field. 0 field which hardware does not update, and for A R field which is either static A or is updated only R/W in which all bits ar field A Notation Read/Write Read/Write implementations and make sure that the use of thes use the make sure that and implementations cessor designers shouldtake this into consideration when us back to that register without having unintended side effects. one field,back and write the value to With certainsoftware restrictions, may With For each register described belo For each register of the field. For the read/wri ture. 1. Any select (Sel) value not exp 9.3 CPU Registers Writing 9.2 Notation MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

if a field is reserved, then a write of a if a field is reserved, ged Resource Architecture, Rev. 6.03 ssor the register between modifies the soft- NED or UNPREDICTABLE behavior. For behavior. NED or UNPREDICTABLE ting. An exception to this rule is that ed by hardware. This meansed by hardware. This that no fieldis in theCOP0modified register defined COP0 register field thatfielddefined COP0 may register have reservedwrites encodings,of unsup- lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: is ignoreditselfto by but write doesentire be dropped. the not cause es where software can cause UNDEFI can cause where software es this rule is situationa in which the proce an not event does occur. ware read and write, such as might occur if an exception or interrupt occurs between the read and write. Software read and write. the interrupt occursor between occuras might an exception such if and write, read ware that such guarantee must of cas limits the number Release 6 a for writes to 6, example, in Release ported values cause the write to be ignor for all fields meet the conditions unless wri non-zero value to the reserved field The most exception significant to 134Vo For Programmers Architecture MIPS® Coprocessor 0 Registers

Index equal to the number of Undefined Required nn-1 0 register fields. fields. register an, or equal to, the number of TLB R R/W Index (Release 6) 9.4 Index RegisterRegister(CP0 0,Select 0) (Pre-Release 6) if a value greater than or greater a value if otherwise. field describes the the describes plementation-dependent as a function of the number of Field Descriptions Field Descriptions ontains the index used to access the TLB for TLBP, TLBR, TLBP, for the TLB to access ontains the index used Index Optional UNDEFINED Table 9.3 Table Meaning ons may use P=0 to cause a cause use P=0 to ons may 0 ites this bit during execution execution during this bit ites field unchanged if a value greater th unchanged field register; indicate whether a TLB returns zero on read. 0 0 Reserved e minimum value for TLB-based MMUs is Ceiling(Log2(TLBEntries)). For Index Description Read/Write Reset State Compliance Index Figure 9.1Figure Format Register Index register. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 135 UNPREDICTABLE Register 0, Select 0) 0, Select Register contains the index of the matching matching the index of the contains entry is for TLB-based MMUs; for TLB-based register. Index ation theof processor is Table 9.3Table Register Index 1 field match occurred and the Index No 0 A match occurred, and the Index Required

Encoding TLBWR to write to a TLB entry other than that indexed that indexed than entry other a TLB to write to TLBWR this to by 0 the Index a write of field. Hardware ignores bit. of the TLBP instruction to TLBP instruction of the 6 requires that match occurred. this bit be R/W Release allowto softwareafter set to TLBPbita the has 1 to Implementati the bit. cleared shows the format of the register is a 32-bit read/write register which c 32-bit read/write register which is a register Index Fields The

For Release 6: Hardware leaves the leaves For Release 6: Hardware and TLBWI instructions.width The theindex of field im is Th implemented. are TLB entries that withentries).six bits are required for a TLB 48 example, The oper 6: For Pre-Release Compliance Level: entries is writtenentries is to the Figure 9.1 TLB entries is writtentheto 0 30. n be written as zero; Must P 31 Failure. Hardware wr Probe P Name Bits 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.4 (CP0 Register Index

ged Resource Architecture, Rev. 6.03 R/W Undefined Required of the TLBP instruction. . ferenced by the TLBR and ites this field to provide the ites this field to provide lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Read/Write Reset State Compliance TLB entry re TLB entry UNPREDICTABLE Table 9.3Table (Continued) Descriptions Field Register Index index to the If the TLBP fails to find a match, the contents of this contents the to find a match, If TLBP fails the field are TLBWI instructions. match- of the index the with field this writes Hardware execution ing TLB entry during Fields Index n-1..0 TLB wr index. Software Name Bits 136Vo For Programmers Architecture MIPS®

=1). VP DIS Config5 register fields. VPControl R 0 Required Write Reset State Compliance Read/ 9.5 VPControl0,4) Select Register (CP0 describes the describes 12 11 8 7 0 sed Multi-threading supported ( i.e., =1. er Field Descriptions andconfiguration support for Release 6 multi-threading. DIS Table 9.4 all other VPs on the 0 , this virtual processor has processor virtual this register; register; rtual processors in the physi- in the rtual processors multi-threading DVP and EVP DVP and multi-threading VPControl Description VPControl VPControl me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 137 Figure Figure 9.2 Format Register VPControl Table 9.4Table Regist VPControl . if Release 6 Virtual Processor ba . if Release 6 Virtual Required

core have been core have disabled if A DVP instruction executed on DVP instruction A disabled on fetch vi all other cal core. An EVP instruction is the only means to subse- to means only the is EVP instruction An core. cal DIS. quently clear 6 of Release See definition instructions for supporting information. for supporting instructions shows the format of the Fields CP0 Virtual ControlProcessor providesregister control CP0 Virtual Figure 9.2 Compliance Level:

031:10 0 0Reserved DIS 0 For a VP that reads Name Bits 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.5 VPControl (CP04) 0, Select Register ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 138Vo For Programmers Architecture MIPS®

register is register Wired Random register above. operating system (the con- available to be written available to be written by a register fields. nn-1 0 Index TLB Entries - 1 Required Random R Write Reset State Compliance Read/ a Reset Exception, and when the 9.6 Random RegisterRegister (CP01, 0) Select register is the first entry entry the first is register describes the ed for exclusive use ed exclusive use by the for , the mannerthe , in whichprocessor the selects values for ed to index the TLB during a TLBWR instruction. The Wired Table 9.5 register; 0 returns zero on read. 0 0 Reserved Description register to the upper bound on Register 1, Select 0) 1, Select Register Random me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 139 Figure Figure 9.3 Format Register Random Random Table 9.5Table Field Descriptions Register Random register). The entry indexed by the for TLB-based Release MMUs; in only; deprecated Optional Pre-Release6 otherwise. Required

Wired register is a read-only register whose value is us register is implementation-dependent. shows the format of the Random tents of the TLB Write Random operation. TLB Write Random Fields 6. The Compliance Level:

width of thewidth Random of fieldcalculatedin is the same manner for as that described the The valuethe registerThe of between an uppervaries and lowerfollow: bound as • A lower boundtheby is setof number TLB entries reserv written. Figure 9.3 The processor initializesThe the the • An upper bound is set by the totalof number entries TLB minus 1. andtheconstraints the required lower upper of bounds Within 0 31. nas zero; be written Must Name Bits Random n-1..0 TLB Random Index 31 9.6 (CP0 Register Random MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 140Vo For Programmers Architecture MIPS®

32 regis- PFNX / registers; register Table 9.7 Table 9.6 PFN Context ure added sup- added ure EntryHi or EntryLo1 and registers; registers; registers and reading the registers and reading in different bit locations bit in different 65 3210 BadVAddr of the architect EntryLo0 EntryLo1 EntryLo1 EntryLo1 or and and ddress error exception, and some fields error exception, and ddress otherwise. otherwise. R 0 Required Write Reset State Compliance Read / Read EntryLo0 EntryLo0 EntryLo0 holds the entries for odd pages. Optional Optional . These protection bits appear register fields. Release 3 Release fields. register shows the format of the the shows e TLB and the TLBP, TLBR, TLBWI, and TLBWR TLBR, TLBWI, the TLBP, TLB and e EntryLo1 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 Fill EntryLo1 error exception sequence. Software writes to the Figure 9-7 it update of address-relatedit updatefieldsthe in of for more information. struction pairs toprovide compatibility between the 32-bit and 64-bit and . shows the format of the shows the format of the by writing all ones to the ange as a function of the registers are not defined after an a not defined after are registers field allow software to determine the boundary between the for a TLB-based MMU; TLB-based for a MMU; TLB-based for a Registers 2 and 3, Select 0) 2 and 3, Registers PABITS PFN PABITS EntryLo0 Description register fields. fields. register of2 the architecture fields. Release support addedaddress register for physical me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 141 Figure 9-6 and EntryLo1 Required Required . See Table 9.10 . See is is and EntryLo1 EntryLo1 PA BI TS describethe and and the holds for entries and even pages EntryLo0 EntryLo1

EntryLo0 registers act as the between interface th The boundaries of this field ch value of Table 9.9 EntryLo0 EntryLo0 EntryLo0 EntryLo and fields to calculate the value of value the calculate to fields Figure Figure 9-4 Architecture of the 1 in Format Release Register EntryLo1 EntryLo0, Fill Fields ComplianceLevel: The pair of maybemodified by hardware during the address- Table 9.8 instructions. (via MTC0 or DMTC0) do not cause the implic value back. Bits read as “1” from the “1” from read as Bits back. value Software may determine the value of and port for Read-Inhibitand Execute-Inhibit page protection bits

architectures. for the DMFC0/DMTC0in and MFC0/MTC0 ters. the Architecture, Figure 9-4 of For Release 1 Compliance Level: describes the describes the For Release 2 of the Architecture, Figure 9-5 of For Release 2 36 spaces beyond bits in range and support for 1 kB pages. 3 of the Architecture, For Release The contents The contents of the Fill 63..30read. on zero on write and return ignored bits are These Fill PFN C D V G 31 30 29 63 Name Bits Table 9.6Table Architecture 1 of the in Release Descriptions Field Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.7 EntryLo0, EntryLo1 (CP0

32 MMU) CDVG 65 3210 ged Resource Architecture, Rev. 6.03 R 0 Required R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W Undefined (TLB Required Write Reset State Compliance Write Reset State Compliance Read / Read Read / Read PFNX

-1..12 Table Table . See el data struc- EntryLo0 PA BI TS is the width of the PABITS for more information. this bit is a one, accesses ange as a function of the PFN PABITS ception that results on any on ception that results becomes the G EntryLo1 becomes ng which pages have been pages have ng which to update kern to update y of the Attribute page. See are permitted. If is this bit a permitted. are use a TLB Modified exception. the G bits of both and and lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Description bits. The boundaries of this field . See Table 9.10 . See EntryLo0 reflect the state of the G of the TLB bit. state the reflect below. 55 54 PA BI TS EntryLo1 The boundaries of this field ch value of change as a function of the value of value of the change as a function more information. for 9.10 Table 9.11 is a one, stores to the page page ca zero, stores to the paging implement to bit this use may software Kernel knowi algorithms that require is initially when a page zero If this bit is always written. TLB mapped, the Modified ex used can be page store to the of the physical address, where of the physical address, in physical address tures that indicatethatwas page the actually written. tual page mapping are valid. tual If to accesses zero, is a bit this If permitted. are page the to exception. Invalid cause a TLB page the both bits from G bit is a one, If TLB entry the entry. in the TLB bit TLB matches. On during are ignored ASID comparisons entry, from a TLB a read and Fill Figure Figure 9-5 Architecture of the 2 in Format Release Register EntryLo1 EntryLo0, Fields Fields

C 5..3Coherenc Cacheability and D 2 this bit If is writable. page the that indicating bit, “Dirty” V 1G the vir- and thus entry, the TLB that indicating bit, Valid 0 Global bit. On a TLB write, the logical AND of the G Fill 63..55 read. on zero on write and return ignored bits are These PFN 29..6 bits to Corresponds Page Frame Number. PFNX 31 30 29 63 Name Bits Name Bits Table 9.6Table 1 of the Architecture Release in Field Descriptions Register EntryLo1 EntryLo0, Table 9.7Table Architecture the 2 of in Release Descriptions Field Register EntryLo1 EntryLo0, 142Vo For Programmers Architecture MIPS®

R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W 0 Optional Write Reset State Compliance Read / Read

LPA field -1..10 of -1..10 Config3 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 m Release 1. 1. m Release bits  from Release 1. 1. from Release PAB I TS = 0), these bits are = 1), the combined combined = 1), the = 1),the PFN field below. = 0), the PFN the 0), = = 0), the = 0), combined ll page frame number ll page ). for more information. for more information. ESP ESP ELPA ESP ESP ange as a function of the ange as a function of the ts as must be written field, described field, described is above address, thereby providing address, thereby the address (the physical addresses is not enabled is not enabled addresses 11 10 ion. If the processor is field to form the full page the full to form field of the address. physical See the description of the the of description the See Table 9.11 = 1), this field is concatenated d is unchanged fro tens PFNX eld is unchanged more information. more e physical addresses ( e physical PFN Description PageGrain PageGrain PageGrain ELPA PageGrain PageGrain me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 143 . See Table 9.10 . See . See Table 9.10 . See fields corresponds to 0b00 fields corresponds to 0b00 fields corresponds to bits to corresponds fields field to form fu the above. above and and above = 0 or = 0 or = 0 or = 1 and = 0 or = 0 or = 1 and SP SP SP SP SP SP LPA SP SP PFN PFN PA BI TS PA BI TS PFN ). -1..12 of the physical (the field is address   field above for field above

Table 9.6 Table 9.6 11 10 See value of corresponds to bits 35..12 corresponds The boundaries of this field ch unshifted and the upper two bi and the unshifted PA BI TS zero). The boundaries of this field ch value of See If support for large physical If support for large (Config3 If the processor is enabled to support 1 kB pages pages kB 1 enabled to support is the processor If (Config3 frame number. If the processor is not enabled to support enabled to support not is the processor If frame number. is number addresses, the entire page frame physical large this field. represented by PFNX concatenated with the bits of the physical page number to the corresponding virtual page. If the processor is enabled to support large the physical addresses, field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA ignored on write and return 0 on read, thereby providing read, thereby providing on write and return 0 on ignored of implementations with compatibility backward full Architecture. the 1 of Release to bits 33..10 of corresponds If the is not enabled processor to 1 support kB pages (Config3 with the enabled to support larg physical to the corresponding address. up to 59 bits of physical pages kB 1 enabled to support is processor the If (Config3 If the is not enabled processor to 1 support kB pages (Config3 PFNX rel- 2 bits by left is shifted address (the field physical the for to make room nition 1 defi Release the to ative PA = 1 and= 1 PageGrain PFNX Fields C 5..3 of this fi definition The D 2 of this fiel The definition PFN 29..6 least-significant contains field This Number. Frame Page PFNX 54..30Ex Page Frame Number Name Bits Table 9.7Table 2 of the Architecture Release in Field Descriptions Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

32 when when Fill field. fields are are fields MMU) mented. XI otherwise not imple- SmartMIPS SmartMIPS If not imple- If not ASE; Optional location is part is part location of the mented, this bit bit this mented, and and CDVG 65 3210 ged Resource Architecture, Rev. 6.03 R 0 Required if RI R/W UndefinedR/W Undefined Required Required (TLB R/W 0 Required by Write Reset State Compliance Write Reset State Compliance Read / Read Read / Read PFNX m Release 1. 1. m Release m Release 1. 1. m Release bit of bit bitwritable is to read data on RI RI register register is set. If for more information. ange as a function of the PFN B Invalid or a TLBRI excep- or a TLBRI Invalid B register fields.

is not set, the the is not set, PageGrain d is unchanged fro d is unchanged fro SM lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Description DMFC0 & DMTC0 Instructions DMFC0 is set to zero on any write to the the to on write to zero any is set (Valid) bit is set. The The is set. bit (Valid) . See Table 9.10 . See V Config3 PageGrain above. above. or RIE bit of the EntryLo1 55 54 Accessed with DMFC0 and DMTC0 Instructions DMTC0 Instructions DMFC0 and with Accessed PA BI TS RXI bit of bit Table 9.6 Table 9.6 RIE tion, even if the if the even tion, value of virtual page causes the a TL The boundaries of this field ch load, other than a MIPS16 PC-relative See See only if the the the / EntryLo0 written. regardless value of the register, the by denoted is existence its and is optional bit This Config3 Fill Fields Fields

V 1 of this fiel The definition G 0 of this fiel The definition RI 63 Read Inhibit. an If this attempt, bit is set in a TLB entry, Fill 61..55 read. on zero on write and return ignored bits are These PFNX 63 62 61 31 30 29 Name Bits Name Bits RI XI Table 9.7Table 2 of the Architecture Release in Field Descriptions Register EntryLo1 EntryLo0, Figure 9-6Figure with Accessed when Architecture the of 3 Release in Format Register EntryLo1 EntryLo0, Table 9.8Table of the Architecture 3 in Release Descriptions Field Register EntryLo1 EntryLo0, 144Vo For Programmers Architecture MIPS®

when when Fill field. otherwise SmartMIPS SmartMIPS If not imple- If not ASE; Optional location is part is part location of the mented, this bit bit this mented, R/W 0 Optional R/W 0 by Required Write Reset State Compliance Read / Read

LPA -1..10 of -1..10 Config3 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 bits PageGrain isnot set, the  PAB I TS = 0), these bits are = 1), the combined combined = 1), the = 0), the = 0), combined ll page frame number ll page (Valid) bit is set. The (Valid) for more information. ESP bit of the ELPA V ESP ange as a function of the PageGrain ts as must be written address, thereby providing providing address, thereby is set any write to zero on ge causes a TLB Invalid or Invalid a TLB ge causes addresses is not enabled is not enabled addresses XIE register fields.

= 1), this field is concatenated bit of tension. If the tension. processor is SM e physical addresses ( e physical Description PageGrain PageGrain XIE ELPA EntryLo1 PageGrain / me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 145 . See Table 9.10 . See Config3 fields corresponds to 0b00 fields corresponds to 0b00 fields corresponds to bits to corresponds fields field to form fu the = 0 or = 0 or = 0 or = 1 and or SP SP LPA SP SP EntryLo0 PFN PFN PA BI TS PFN RXI ). -1..12 of the physical (the field is address  

mpt to fetch an instruction or to load MIPS16 PC-rel- MIPS16 load or to instruction an fetch to mpt 11 10 bit is writable only if the is writable bit of bit Accessed withDMFC0 and DMTC0 Instructions (Continued) tte enabled to support larg unshifted and the upper two bi and the unshifted value of PA BI TS zero). The boundaries of this field ch physical If support for large (Config3 ignored on write and return 0 on read, thereby providing read, thereby providing on write and return 0 on ignored of implementations with compatibility backward full Architecture. the 1 of Release with the physical to the corresponding up to 59 bits of physical address. pages kB 1 enabled to support is the processor If (Config3 If the is not enabled processor to 1 support kB pages (Config3 is shifted left by 2 bits rel- 2 bits by left is shifted address (the field physical the for to make room nition 1 defi Release the to ative PA PFNX register is set. If the register PFNX ative data from the virtual pa virtual the from data ative exception,a TLBXI even if the XI XI and= 1 PageGrain a to the register, regardless of the value written. of the value regardless register, the to the by denoted is existence its and is optional bit This Config3 Fields XI 62 an a TLB in entry, If this bit is set Inhibit. Execute PFNX 54..30Ex Page Frame Number Name Bits Table 9.8Table of the Architecture 3 Release in Descriptions Field Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

32 when when MMU) protection bits. bits are visible at their at their are visible bits XI / XI RI 65 3210 and field (this fieldis not visible by RI ged Resource Architecture, Rev. 6.03 PFNX R/W Undefined Required R/W Undefined Required R/W UndefinedR/W Undefined Required R/W Undefined Required Required (TLB Write Reset State Compliance Read / Read field m Release 1. 1. m Release m Release 1. 1. m Release 1. m Release from Release 1. 1. from Release SignExt = 1),the PFN field below. = 0), the PFN the 0), = ). for more information. ESP ESP ange as a function of the field described above field described above is the address (the physical 11 10 field to form the full page the full to form field of the address. physical a MIPS64 Release 3 implementation, the a MIPS64 Release See the description of the the of description the See Table 9.11 d is unchanged fro d is unchanged fro d is unchanged fro PFNX eld is unchanged more information. more PFN lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description PageGrain PageGrain using MFC0 MTC0 Instructions and using MFC0 . See Table 9.10 . See machine will cause all zeros to be written to the above. above. above. above and and above = 1 and = 0 or SP SP SP PA BI TS field above for field above Table 9.6 Table 9.6 Table 9.6 Table 9.6 Accessed withDMFC0 and DMTC0 Instructions (Continued) See See See corresponds to bits 35..12 to bits 35..12 corresponds The boundaries of this field ch value of See If the processor is enabled to support 1 kB pages pages kB 1 enabled to support is processor the If (Config3 frame number. If the processor is not enabled to support support enabled to not is the processor If frame number. number is addresses, the entire page frame physical large this field. represented by PFNX field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA concatenated with the of to bits 33..10 corresponds bits of the physical page number to the corresponding virtual page. If the processor is enabled to support large the physical addresses, If the is not enabled processor to 1 support kB pages (Config3 Fields software via the MTC0/MFC0 instructions). MTC0 on a MIPS64 Release 3 MTC0 on a MIPS64 Release For the MTC0 andMFC0 instructions in MIPS32 locations.allows This for backward compatibilitywithwhen MIPS32the using C 5..3fi of this definition The D 2 of this fiel The definition VG 1 of this fiel The definition 0 of this fiel The definition Figure Figure 9-7 when Accessed Architecture 3 of the in Release Format Register EntryLo1 EntryLo0, PFN 29..6 least-significant contains field This Number. Frame Page 63 31 30 29 Name Bits RI XI PFN C D V G Table 9.8Table of the Architecture 3 Release in Descriptions Field Register EntryLo1 EntryLo0, 146Vo For Programmers Architecture MIPS®

when when Fill field. Fill field. otherwise otherwise SmartMIPS SmartMIPS SmartMIPS If not imple- If not imple- If not ASE; Optional ASE; Optional location is part is part location is part location of the of the mented, this bit bit this mented, bit this mented, R 0 Required. R/W Undefined Required R/W 0 Required by R/W 0 Required by Write Reset State Compliance Read / Read

RI field field is 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 bit of PageGrain isnot set, the bitwritable is to read data on RI PFNX RI register register is set. If = 1),the PFN field = 0), the PFN the 0), = (Valid) bit is set. The (Valid) ). ESP bit of the bit of the for more information. more for V ESP ange as a function of the PageGrain field, described field, described above is the address (the physical ge causes a TLB Invalid or Invalid a TLB ge causes XIE 11 10 B Invalid or a TLBRI excep- or a TLBRI Invalid B register fields. register register fields. field to form the full page the full to form field

of the address. physical is not set, the the is not set, PageGrain See the description of the the of description the See bit of SM SM PFNX more information. more PFN Description Table 9.10 Table is set to zero on any write to the the to on write to zero any is set PageGrain XIE is set to zero on any write on EntryLo1 write set to zero is any PageGrain / me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 147 (Valid) bit is set. The The is set. bit (Valid) . See V Config3 Config3 PageGrain are ignored on write. The = 1 and = 0 or or or RIE bit of the EntryLo1 Accessed using MFC0 and MTC0 Instructions MFC0 and MTC0 using Accessed SP SP SP EntryLo0 PA BI TS RXI RXI bit of bit field above for field above RIE bit is writable only if the only if the is bit writable of bit If the processor is enabled to support 1 kB pages pages kB 1 enabled to support is the processor If (Config3 frame number. If the processor is not enabled to support enabled to support not is the processor If frame number. number is addresses, the entire page frame physical large this field. represented by PFNX concatenated with the bits of the physical page number to the corresponding virtual page. If the processor is enabled to support large the physical addresses, corresponds to bits 35..12 corresponds The boundaries of this field ch value of written with zeros. zeros. with written On a read, the GPR bits are extended the signed from bit. other than a MIPS16 PC-relative load, other than a MIPS16 PC-relative if the even tion, the virtual page causes a the TL field isshifted leftrelative by 2 bits theto Releasedef- 1 inition to make room for PA corresponds to bits 33..10 of corresponds register is set. If the register a TLBXI exception,a TLBXI even if the XI XI written. of the value regardless register, the to the by denoted is existence its and optional is bit This Config3 attempt to fetch an instruction or to load MIPS16 PC-rel- load or to instruction an fetch to attempt pa virtual the from data ative If the is not enabled processor to 1 support kB pages (Config3 only if the the the / EntryLo0 written. regardless value of the register, the by denoted is existence its and optional is bit This Config3 Fields

RI 31 Read Inhibit. an If this attempt, bit is set in a TLB entry, XI 30 an in a TLB entry, If this bit is set Inhibit. Execute PFN 29..6 least-significant contains field This Number. Frame Page Name Bits SignExt 63..32 The GPR bits Table 9.9Table of the Architecture 3 Release in Descriptions Field Register EntryLo1 EntryLo0, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For when when MMU) ged Resource Architecture, Rev. 6.03 can never be larger than and there 36 bits be larger can never R/W Undefined Required R/W UndefinedR/W Undefined Required R/W Undefined Required Required (TLB Write Reset State Compliance Read / Read PABITS fields as a function of 1 kB page support enabled, and the m Release 1. 1. m Release m Release 1. 1. m Release 1. m Release PFN from Release 1. 1. from Release below. , and PFNX ons of the Architecture, , Table 9.11 d is unchanged fro d is unchanged fro d is unchanged fro Fill eld is unchanged lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description above. above. above. above and and above Table 9.6 Table 9.6 Table 9.6 Table 9.6 Accessed using MFC0 and MTC0 Instructions (Continued) MTC0 Instructions MFC0 and using Accessed See See See See .Note that.Note in implementati shows the movement of the Fields Table 9.10 value of PABITS is no supportfor 1 kB pages, soonlysecond the rowof applies the table inRelease 1. C 5..3 of this fi definition The D 2 of this fiel The definition VG 1 of this fiel The definition 0 of this fiel The definition Name Bits Table 9.9Table of the Architecture 3 Release in Descriptions Field Register EntryLo1 EntryLo0, 148Vo For Programmers Architecture MIPS®

reg- fields of fields Release Release 2 Release 5 Release 1 Release 5 Config Required PFN and if software if uses a 33 10 35 12 35 12 33 10 ))..6 ))..6 = 34 = 36 = 11 = 13 field of the of the field PFNX = PA = PA = PA = PA K0 ed with a C field encoding 29..6 29..6 PABITS PABITS 29 6 29 6 29 6 29 6 Example: Example: UNDEFINED 6..6 if PAB I TS 6..6 if PA if 6..6 BI TS PAB(29-(34- I TS PAB(29-(36- I TS 29..6 if 29..6 if EntryLo EntryLo EntryLo EntryLo if this sequence is not done. is mandatory. Instead,software mustinvali- mandatory. is registers and the and registers 59 34 59 36 = 35 = 59 = 37 = 59 ))..30 ))..30E EHINV = PA = PA =1. lease prior to Release 6), the prior to Release lease EntryLo1 PA BI TS Field UNDEFINED Field PABITS 54 30 52 30 re instruction) that was creat xample: Example: EntryHI and EHINV 9.7 EntryLo0, EntryLo1(CP0 Registers 3,and 0) Select 2 Displaced by the Fill Fill by the Displaced Displaced by the Fill Fill by the Displaced 54..30if 54..30if PA(54-(59- BI T S 31..30 if PAB31..30 I TS 30..30 if PAB30..30 I TS 52..30 if PAB52..30 I TS (52-(59- EntryLo EntryLo EntryHI EntryLo0 )) )) )) )) = 35 = 36 = 59 = 34 = 37 = 59 register is changed. register is Thisoperation mustbewhilecarried out running in = 11 = 13 tions, the operation of the processor is processor the tions, the operation of Corresponding EntryLo Field Bit Ranges on. In Release 6, hardware must ignore writes of unsupported values of the PA BI TS PA BI TS PA BI TS PA BI TS PAB I TS PAB I TS PAB I TS PAB I TS PAB I TS PAB I TS PA BI TS PA BI T S field of the field of ration of the processor is ration C Example: Example: Example: Example: Fill FieldFill Field PFNX Field PFN PageGrain me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 149 registers must be written with flushed zero, and the TLB must be before each 2 of there (and any Architecture 63..7 if 63..7 if 63..7 if 63..31 if 63..30 if 63..55 if 63..30 if 63..31 if 63..53 if EntryLo1 > 12 63..(30-(36- > 34 63..(55-(59- > 10 63..(30-(34- > 36 63..(53-(59- and Value Table 9.10Table PABITS of a Function as Widths Field EntryLo PAB I TS PAB I TS PAB I TS PAB I TS

    lists the encoding of the the lists PABITS EntryLo0 36 36 34 For Release 6, this is not a requirement because support for instance in which the value of the Table 9.11 ister. An implementation may choose to implement a subset of the cache coherency attributes shown, but must imple- but shown, attributes the cache coherency implement a subset of choose to An implementation may ister. mentencodings encodingsalways at least cantheseon depend appropriately. workingsoftware 2 and 3 such that In other cases of Pre-Release 6 implementa C field for the implementation. C field for TLB mappingfor an instructiona load/sto (either for fetch or for the implementati RESERVED which is an unmapped address space. The ope address space. an unmapped Programming Note: Programming In implementations of Release . date the TLB entries explicitlyTLB entriesdate the using TLBWI with both the No 59 Yes 59 Support Support Enabled? 1 kB Page MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 r the cacheability and coherency attributes. tion-dependent usetion-dependent usetion-dependent usetion-dependent use Optional tion-dependent use Optional tion-dependent use Optional Optional Optional Optional With Historical With Usage Compliance lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Cacheability and Coherency Attributes Table 9.11Table Attributes and Coherency Cacheability 012 • for implementa Available 3 • for implementa Available 4 • Uncached5 • Cacheable6 • for implementa Available 7 • for implementa Available • for implementa Available • for implementa Available Required Required lists the required and optionalrequired and lists the encodings fo C(5:3) Value Table 9.11 150Vo For Programmers Architecture MIPS®

0 Optional register fields. fields. register VPId 0 Reserved nally set ware or exter- ware Global Number 8 7 location of software threads from vir- from threads software location of R hard- by Preset describes the describes 12 11 the maximum virtual processor count in any core in ASE) in a clusterin from can be derived a the contentsASE) of Table 9.12 Table 9.8NumberRegister3, Register 1) Select Global (COP0 optionally can Themethod must be uniformly applied to all virtual proces- gister Field Descriptions gister 6 core implements multi-threading. 6 core implements register; mberingvirtual of processorsa cluster. in n be or preset, eld are not writeable; reads not writeable; eld are ClusterNum Reserved CoreNum ally programmable. This allows for real This programmable. ally COP0 Register 3, Select 1) 3, Select COP0 Register eassigning the VPNum to thevirtual processor. Description Read/Write Reset State Compliance 20 19 16 15 Global Number me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 151 ber asssigned to a cluster sys- ber asssigned to a cluster of cores in the Figure Figure 9.8 Format Register Number Global Table 9.12Table Re Global Number Optional Release6

register is required if a Release tem. Reserved if clustering is not implemented. is not clustering if Reserved tem. Unimplemented bits in the fi 0. return but ca read-only, field is This be programmed by a register external to COP0 to COP0 through a be programmed by a register external memory mapped register. for examples. Reserved shows the format of the Global Number a cluster. This results in non-contiguous nua cluster. with heterogenous thread counts). multi-threading (cores with different Table 9.13 Fields The unique name of a virtual processor (VPNum;see COP0 EB twotheby methods one of this register described below. The naming convention is hierarchical.unique Thein virtualis the systemClusterNum.VPNum. name of processor a extern be can indicated where The fields sors in the system. sors in the • VPNum = CoreNumThis methodVPId. allows + for contiguous numberingofprocessors a cluster in virtual • VPNum = CoreNumX Max-VP or VPId, where Max-VP is See tual processor to virtual processor by r ClusterNum is optionalandrequired only thata system in supports clusters of cores. Figure 9.8 Compliance Level: The 0 15:12 0 Reserved. 0 31:20 0 Reserved. 0 Reserved 31 Name Bits ClusterNum 19:16 A unique num 9.8( Register Number Global MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Required nally set nally set ware or exter- ware ware or exter- ware ged Resource Architecture, Rev. 6.03 R hard- by Preset R hard- by Preset 0, 1, 2, 314, 15 13, 12, . 3 0, 1, 2, 33 2, 1, 0, . is dependent is dependent optionally can optionally can Field Descriptions (Continued) Field Descriptions icalcore in a cluster. lemented bits bits lemented contiguous numbering is contiguous numbering a virtual processor in a core. a virtual a phys n be or preset, n be or preset, eld are not writeable; reads writeable; not eld are eld are not writeable; reads writeable; not eld are en VPId en VPId size equals VPId VPNum VPId VPNum Description Read/Write Reset State Compliance Contiguous NumberingContiguous Numbering Non-Contiguous lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: (total VP count in cluster) ) (total VP Table 9.13Table VPNum Unique Deriving 2 45, 6, 7 4, 10 9, 7, 8, supported. If contiguous, If contiguous, supported. th on whether contiguous or non- or on whether contiguous If non-contiguous, then VPId size equals equals VPId size then If non-contiguous, ceiling (log any core) log2 (maximum VP cont of This field is read-only, but ca read-only, field is This be programmed by a register external to COP0 to COP0 through a be programmed by a register external memory mapped register. return 0. The number of unimp of number The 0. return Unimplemented bits in the Unimplemented bits in fi Unimplemented bits in the Unimplemented bits in fi 0. return but ca read-only, field is This through a to COP0 external be programmed by a register memory mapped register. Table 9.12Table Register Number Global 0121 43 4 6 2 0 8 1, 2, 3 0, 3, 41, 2, 0, 4, 5 0, 1 4,5 CoreNum of VPs # Fields VPId 7:0 number assigned Ato unique Name Bits CoreNum 11:8 number assigned A unique to 152Vo For Programmers Architecture MIPS®

describes describes 0 =0 SM register. The register. register. register. =0 Table 9.14 a TLB miss, the operat- a TLBmiss, the SM =0; Context SM BadVAddr register is primarily intended a way that the operating system register can pointregister can to any power-of- =0 and =0 and Config3 Config3 e page table entry (PTE) array. This e page table entry (PTE) array. Context field of the riate shifting and masking. =0 and Config3 =0 R Undefined Required CTXTC Context error exception and this field may be modi- BadVPN2 R/W Undefined Required Write Reset State Compliance =0 and Read / Read BadVPN2 CTXTC 9.9 Context RegisterRegister (CP04, 0) Select CTXTC otherwise. the PTE array. The array. the PTE =0. Config3 SM the information provided in the 23 22 4 3 0 register is organized in such in is organized register Optional r implementedthe by refillafter approp handler Config3 Register as a pointer pointer a as Register Context containing a in pointer to an entry th returns zero on read. on returns zero 0 0 Reserved Register when of the virtual address that Context =0 and e in memorye in thatmapping. describesthe For PTE structuressizes, other of by hardware on a TLB exception. TLB exception. on a hardware by Description 31 13 e by the operating system and is =0 then a TLB exception =0 thenRefill,a TLB (TLB XTLB Refill, TLB Invalid, or TLB Modi- Context =0 then the Register 4, Select 0) 4, Select Register register is not defined after an address me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 153 CTXTC =1 then the pointe SM SM SM for TLB-based MMUs; for TLB-based data structurethat stores virtual-to-physical translations. During address error exception sequence. error address register duplicates some of of some register duplicates Context Config3 Config3 of thevirtual address tobewritten into the Config3 Config3 PTEBase normally written with a value that allows the operat- the allows that value a with written normally to use the system ing in memory. array PTE the current into VA It contains bits exception. the caused Required Context

31..13 =0 and =1 or =0 and =0 and field of the register is a read/write register a register is register fields CTXTC shows the format of the CTXTC CTXTC fieldis written and used by the operating system. Figure 9.9Figure Config3 when Format Register Context Context BadVPN2 Context Fields Config3 Config3 Config3 Table 9.14Table Config3 when Field Descriptions Register Context The ing system loads the TLB withfrom the missing translation array is an operating system If

Figure 9.9 fied byfied hardware duringthe can directly reference a 16-byte structur reference can directly TLB by the this register can be used the content of If The If fied) causes bits VA bits fied) causes two-sized PTE structure within memory. This allows This TLB refill theusepointertheto handler without additional withintwo-sized structure PTE memory. PTEBase Compliance Level: for use with the TLB Refill handler, but is also butloaded is hardware by Refill and on an XTLB software be used by may withforTLB Refillthe use handler, The in that handler. the 0 3..0 zero; as be written Must Name Bits 63 PTEBase 63..23us for field is This BadVPN2 22..4 This field is written MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.9 (CP0 Register Context

, the 31:31-((X- describes 0 =1 SM ContextConfig =1 Table 9.15 ). Although the fields ). Although the fields SM =1; 31:13 State Compliance Reset SM y in a two-levely in lookup scheme. of the contents of the contents of the =1 or Config3 ftware, and are unaffected by the unaffected are ftware, and Config3 ged Resource Architecture, Rev. 6.03 R Undefined Required R/W Undefined Required Write =1Config3 or Read / CTXTC BadVPN2 =1 or register, it may point topair 8-byte an of 32- register, Invalid, or Modified) causes bits VA causes bits Modified) or Invalid, CTXTC of register, where this range corresponds to the corresponds to range where this register, CTXTC . Context 64 nomenclature is retained. Bits 63:X are referred to as Config3 ContextConfig =1. following a modification 31:31-((X-Y)-1) first level page directory entr XX-1 YY-1 0 SM If = X 23 and Y = i.e. bits4, 22:4 are set in register (bits 22:4 are filled with VA register (bits 22:4 are BadVPN2 system to use the the use to system by the operating system ontaining the virtual register. Bits 63:X are R/W to so Bits 63:X are R/W to register. n n by hardware on a TLB Config3 Description Context Register when =1 or Register as a pointer to an array of to an array a pointer as Register lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Context ContextConfig CTXTC =1 then the a TLB exception (Refill, then the a TLB exception =1 Y are referred to as exception. It contains bits VA It contains bits exception. This field is for use for This field is and with a is normally written value that allows the operating Context to corresponding data structures in memory address region c the address which caused the exception. writte is field This the virtual address that caused the exception. address that caused the virtual the SM Config3 register is UNPREDICTABLE Config3 PTEBase Context =1 or register. field, and bits X-1: bits and field, =1 then Bits Y-1:0 will always as 0. read Y-1:0 Bits =1 then shows the format of the the shows register fields CTXTC SM Figure Figure 9.10 Config3 when Format Register Context where X in {32..1} and Y in {31..0}. be null. May X in {31..0}. be null. May Fields to be written to a variable range of bitsto of the “(X-1):Y” be writtenrange of a variable to Context PTEBase Table 9.15Table when Config3 Field Descriptions Register Context Config3 Config3 contiguousbitsof set range in the The value of the bit PTEs withinbit PTEs a single-level pagetable scheme, or to a If If behavior is identicalbehavior to the standard MIPS64 exception. Bits Y-1:0 are unaffected by the exception. unaffected are Y-1:0 Bits exception. ContextConfig shifting and maskingDepending steps. onvalue the in the Y)-1)

Figure 9.10 Figure the have been made variable in size and interpretation, the MIPS the Name Bits 63 PTEBase where 63:X Variable, BadVPN2 (X-1):Y Variable, 154Vo For Programmers Architecture MIPS®

Reserved =1 (Continued) or or SM State Compliance Reset 0 (if R) 0 (if R/W) Undefined =1) or or for for only R/W (R/W Write Read / allowed allowed Config3 CTXT =1 or Config3 CTXTC 9.9 Context RegisterRegister (CP04, 0) Select Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 155 eld Descriptions when when Config3 eld Descriptions Must be written as zero; returns Must be written as zero; zero on read. R be null. where Y in {31:1}. May Fields 0 (Y-1):0 Variable, Name Bits Table 9.15Table Fi Register Context MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 156Vo For Programmers Architecture MIPS®

reg- Context ContextConfig register fields. register fields.

SM e bit cause the corre- the bit cause e field.Bitsthe below P0 Register 4, Select 1) Config3 then the least significant significant then the least ess will be ess will be extracted. Bits or ContextConfig e lefte of the most- significant of the smallest of the implemented en the settingen not is imple- PTEBase field cannot contain address bits register configuration. CTXTC tting is implementedby writing that BadVPN2 Context Config3 e least-significant on describes the BadVPN2 ware and unaffected by TLB exceptions. ware and unaffected bits of that addr virtual page pairs used by the JTLB entries. This limitsThis thethe by JTLB entries. used page pairs register may be programmed.of set bits The register are R/W for software and unaffected by TLB software and unaffected R/W for are register register, in which some number of bits are read-only register, and 9.10 ContextConfig Register (C register. The register. register into which the bits starting from 31 of the virtual c what value is read back wh value is c what Context e least significant one bit causes the corresponding original written value. All implementations of the Config Register; Table 9.16 to the bits that represents Context ContextConfig by TLB exceptions. Any zero bits to th to zero bits Any by TLB exceptions. ContextConfig registerto bitssoft to be R/W (CP0 Register 4, Select 1) 4, Select (CP0 Register register are R/W to and serve as software the implemented page size is 4 kB, virtual address bit 13 is the least significant bit

ContextConfig ware can determine whether a specific se ware can determine whether a specific field.bits Any zeroright to the of th ContextConfig field within the me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 157 would correspond to virtual address bit 11. wouldcorrespond tovirtual address bit 11. Context Context register will be unaffected by TLB exceptions. TLB by unaffected will be register BadVPN2 VirtualIndex Optional. Context

ContextConfig register is optional and its existence is denoted by the register defines the bits of the register bits to be unaffected bits to be unaffected register field. Another field. example:theif smalle 1 kB was implemented page size st define the register’s register’s is set, then zero bits any to the right of th

shows the formats of the of the the formats shows SM Context BadVPN2 ContextConfig ContextConfig Config3 selected field of the selected field of exceptions. The If address causing a TLB exceptionaddress causing a will be written,many how and one bit causethecorresponding above the selected field of the field of the selected the above registerthe must emulationfor allow MIPS64/microMIPS64 of the fixed writable bit within ContextConfig ContextConfig Compliance Level: The Figure 9.11 Figure The field tofield contain The the virtualindex address defined is singlecontiguous block a by of non-zero bits withinthe page size. For example, if the smallest if the smallest page size. For example, of the sponding This paragraphdescribes restrictionsthe on how the register value. If the read value matches the original written value exactly, the original written value exactly, the register value. If value into the register and reading back the read value matches then the setting is supported. It is implementation specifi set to one or zero as appropriate. Soft appropriate. as zero set to one or ister bitsto be read as zero. ister It permissible is to implement a subset of the which to index are used memory a locationwithin the even-odd least significant writablebit within A valueof all zeroes meansthat the full 64bits of the mented except that the read value does not match the MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.10 Register ContextConfig

0 State Compliance Reset ged Resource Architecture, Rev. 6.03 R/W 0x007ffff0 Required Write Read / gister Field Descriptions Descriptions Field gister register to be writ- register values. VirtualIndex

Context if non-con- UNDEFINED if m 31 of the virtual address into the register field. the into tiguous causes tiguous 1 bits in this field Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ContextConfig Figure 9.11Figure Format Register ContextConfig Page Table Page Table Organization Size Page PTE Size Compliance Table 9.17 Table Values ContextConfig Recommended the corresponding bits of the bits of the corresponding the fro the bits starting with ten causing a TLB exception. a TLB causing Behavior of the processor is written 1 bits are tiguous Table 9.16Table Re ContextConfig Value describes some describes useful 0x007ffff00x007ffff8 Level Single Single Level 4K 2Kbits/page 64 bits/page 32 REQUIRED RECOMMENDED Fields Table 9.17 Name Bits 31 VirtualIndex 31:0 0 mask of A to 32 con 158Vo For Programmers Architecture MIPS®

0 to unprivileged software register fields. d conditionally readable d conditionally readable via register contains register contains a pointer to a register must be set to a 1 to enable UserLocal R/W Undefined Required Write Reset State Compliance Read/ UserLocal HWREna describes the describes ation and make it accessible it and make ation 9.11 UserLocal RegisterRegister (CP04,2) Select rpretedby the hardware an register field is field is set. register register is instantiatedper TC.

must be 1. ULRI Table 9.18 ULRI . Config3 UserLocal UserInformation register; Config3 information that is not inter- information

Description ster with arbitrary inform some operating environments, the UserLocal Recommended me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 159 Required Figure 9.12Figure Format Register UserLocal Table 9.18Table UserLocalRegister Field Descriptions ster is mandatory, and ster is mandatory, Release 6: Release 6: preted by the hardware. the preted by Pre-Release 6: Pre-Release register is a read-write register thata read-write is not interegister register is shows the format of the the shows 63..0software This field contains UserLocal Fields the RDHWR instruction. theimplemented, Module MIPS®If is MT the Figure 9.12 Figure Priorthis to Release 6, register only exists if the thread-specific storage block that is obtained via the RDHWR register. obtained is storage block that thread-specific For Release 6, this regi For Release 6, this via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the via register 29 (ULR) of the RDHWR instruction. To Programming Notes Programming Privileged software may write this regi

unprivileged access to the register. In unprivileged access to the register. The Compliance Level: Name Bits mation 63 UserInfor- MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.11 4, Select 2) Register Register (CP0 UserLocal ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 160Vo For Programmers Architecture MIPS®

0 register registers MIPS specific be present if be present DRSEG Debug ContextID ContextID Debug rporated into t switch, but may be any be any sup- may but t switch, int. The value programmed int. The value ent the register =0. R/W Undefined Required Write Reset State Compliance Read/ DM describes the Debug 9.12 Debug4, ContextID 4) Select Register (CP0 Table 9.19 ocess specific tag to be inco specific tag to ocess register do not have any side-effects on processor oper- processor on register have do not any side-effects gister Field Descriptions gister restored on a process contex a process restored on register; Release 6. Release trace, PC-sample and breakpo ID =1. However, it is not a requirem However, =1. kernel-mode when kernel-mode EP g specifically for use in hard- g specifically EJTAG Specification i.e., it is not part of the set of part of the set i.e., it is not Specification EJTAG Optional Description Register 4, Select 4) 4, Select Register Config1 Debug ContextID ContextID Debug me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 161 Pre-Release 6; Pre-Release Figure 9.13Figure Format Register ContextID Debug =1. It is accessible in It is accessible =1. at can assist debug. at DM Table 9.19Table Re ContextID Debug ware debug mechanisms. ware software May be used by kernel for debug pur- to inject any supplemental information poses. Debug =1. EP Fields Other thanbeing factoredintodebug hardware, writes to this plemental information th ation. Nor is this register to be used to observeof processor operation. side-effects ofThis register the as part defined is also not Compliance Level: Reserved Debug ContextIDDebugis programmedprovidekernel to by the a pr examples being debug related mechanisms, hardware wouldsaved/ typicallysuchuniqueprocess and as be to a Config1

fields. Figure 9.13 shows the format of the This register maybepresent only if accessible when accessible ID 31:0 Provides a process specific ta Name Bits 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.12 (CP0 ContextID Debug ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 162Vo For Programmers Architecture MIPS®

register PTEBase register register fields. Context register configu- SM Config3 XContext ficant address bit within the d separately, not sharing any d separately, XContextConfig and R fields. The or CTXTC implemented page size implemented page size then the least and hold different address and pointer val- hold different PTEBase ich are not accessible (accesses to such ecific settingecificis implemented by writing describes the Config3 value matchesthe original written value the least significant one bit cause the corre- one bit the least significant register bits to be R/W to software and unaf- R/W to software and be to bits register o bits to the left of the most significant one bit below the field of the selected Select 3) Select or smaller. or smaller. register may be programmed. Theregister may be programmed. set bitsof by TLB register are R/W for software and unaffected register. The BadVPN2 field cannot contain address register. register, in which some number of bits register, are read-only XContext SEGBITS is usedwithinSEGBITS is thisdocument to denote the register into register which the high(starting order bitsSEG- at For that reason, the For that reason, the most signi registers must be implemente register serve as the

SEGBITS-1 9.13 XContextConfig RegisterRegister (CP04,Select 3) to the bits that represents BadVPN2 of the smallest XContext XConfig Register; Table 9.20 register is meant to be a pointer to a page table data-structure. data-structure. table a page to a pointer meant to be is register XContext XContextConfig XContext would be the bit correspondingtobitaddress virtual 11. onds toVA P0 Register 4, P0 Register XContextConfig register can be of different width can be of different register ContextConfig ContextConfig XConfig XContextConfig implement virtual address segments segments address implement virtual implementations are allowed to ectures, e valuee of SEGBITS-1. This restricts the most significant writeablewithin bit and back the register value. If the read back the register value. nother example: if 1KB was the smallest field. Any zero bits to the right of of right the to bits zero Any field. a TLB exception willand be written, howmany thatbits virtual of will address d have regions in the memory map wh the have regions in d XContextConfig at corresp XContext e. Software can determine whether a sp Software e. R field is written by hardware. Bits me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 163 ple, if the smallest implemented size is page 4KB,address virtual bit 13 is the least the full 64 bits of the and XContextConfig

e selected field of the e VirtualIndex XContextConfig Context Context Optional. register defines the bits of the register is and its existence optional is denoted by the

register bits to be unaffected by hardware. zer Any to be unaffected register bits tolocation the bit th definethe BadVPN2 field within the register mustallowemulation for the MIPS64/microMIPS64of the fixed register’s register’s shows the formats of the of the the formats shows XContext XContextConfig XContextConfig exactly, then the setting is supported.isimplementation It specificwhatisback value read setting when the is not exactly, implemented except that the read value does not match the original written value. All implementations of the field is R/W to the software while ration. This paragraphdescribes restrictionsthe on how and set to one or zero as appropriat as zero or and set to one that value into the register and reading register and value into the that The PTEBase fields of sponding exceptions. The bitswhichmemory are used to index a location withineven-oddthe theusedby limits JTLB entries. This pairs page the least significant writeablebit within fected by TLB exceptions. by TLB fected isIt permissible to implementthe a subset of fields. storage. 9.14 Figure A value of all zeroes means that means value of all zeroes A XContextConfig XContextConfig XContextConfig XContextConfig Compliance Level: The will be unaffected by TLB exceptions.TLB by will be unaffected tofield contain The the virtualindex address defined is singlecontiguous blocka by of non-zero bits withinthe BITS-1) of theaddressBITS-1) virtual causing of th be extracted. Bits above implemented page size. For exam significant bit of the BadVPN2 field. A significant writeablebit within BadVPN2 than th field can not be larger That page table must reside in memory which is accessible. reside in memory which is accessible. table must That page In the MIPS64 and archit microMIPS64 an than the full 64-bits which are less regionsexceptions). would cause Address Error symbolThe size of the accessible address segments.The accessible address of the size designate the location of the R field and cause the remaining the and cause of the R field designate the location ues. For this reason, the MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.13 (C Register XContextConfig

0 Required Required ) SEG- are set VA BITS-1:13 bits corre- bits sponding to sponding BITS-13+3:4 BITS-13+3:4 ( thesethe are ged Resource Architecture, Rev. 6.03 R/W bits SEG- Write Reset State Compliance Read / register to be register VirtualIndex XContext if non-con- UNDEFINED if tiguous causes tiguous 1 bits in this field causing a TLB exception. a TLB causing Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Figure Figure 9.14 Format Register XContextConfig Table 9.20Table Descriptions Field Register XContextConfig the corresponding bits of the the bits of corresponding the written with the high-order bits starting at SEGBITS-1 at SEGBITS-1 bits starting the high-order with written of the address virtual Behavior of the processor is tiguous 1 bits are written into the register field. into written 1 bits are tiguous Fields 63 Name Bits VirtualIndex 63:0 mask of 0 A to 64 con 164Vo For Programmers Architecture MIPS®

0 32 Required Required shows the format of the 0 0 =1 =0 to the TLB. It holds a comparison the TLB. It holds a to Figure 9.15 Figure . BPG BPG R/W Undefined Write Reset State Compliance Read / Read MaskX MaskX otherwise. 9.14 PageMask RegisterRegister (CP05,Select 0) 13 12 11 10 0 13 12 11 10 . Mask introduces optionalsupport for small whereas pagesizes, Mask register fields. ster Field Descriptions Field Descriptions ster Optional PageMask used for reading from and writing reading from and used for [14:13] is read-only PageMask l 1s to determine the the determine 1s to l example, if 4 kB pages at are read-only read-only 0, at are and in the implementation in the implementation Description PageMask me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 165 ze for each TLB entry, as shown in Table 9.22 ze for each TLB entry, Mask ported pages must be continuous. describes the describes for TLB-based MMUs; for TLB-based Mask Table 9.21Table Regi PageMask Figure 9.15Figure if Config Format Register PageMask Figure 9.16Figure if Config Format Register PageMask are disallowed, sup- of the range can determine 1s. Software al writing pages by ported The Mask field is a bit mask in which a “1” bit which a “1” in is a bit mask Mask field The the virtual bit of corresponding that the indicates match. TLB not in the address should participate small for the support optional 6 makes Release page sizes 4 Corresponding from kB onwards. disabled pages bits for For 1. must be read-only most-significant bits th writing all 0s to determine least-significant bits least-significant 0s all determine to writing read-only are 1s within that Required Table 9.21

=0 =1 register is a read/write register read/write register is a BPG BPG if register; 28..13 59..13 60 59 Config Config PageMask Fields 0 The mask that sets the variable page si page variable the mask that sets

prior to Release 6, all page sizes from 4 kBmuston6, all pagesizes from be supportedto Release implementa-prior themaximum the up to for size page sup range of the tion; however, Release 6 removes supportremovesRelease for Release 6 6 also 1 kB pages. PageMask Compliance Level: 0 63 31 31 29 28 Mask if Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.14 5, Select 0) Register Register (CP0 PageMask

2) Reserved (Release 6) Required (Release Required (Release

1 0 0 field ged Resource Architecture, Rev. 6.03 (See Description) Values for MaskX for Values R R/W Write Reset State Compliance 0x00x00x3 0x0 0x3 0x3 0xF 0x3 Read / Read 0x3F 0x3 0xFF 0x3 Fields of the PageMask Register Register PageMask the of Fields = 0 or 1 ) SP SP = 1 and 13 SP SP Config3 Config3 at of the Mask field, pages. pages. This field is kB pages with definition with definition pages kB PageMask Release 6 onwards. Release 6 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description = 0), these bits are not writable, = 1), these bits are writable and and writable these bits are 1), = (lsb of value is located at value is located (lsb of ESP ESP leases), the MaskX field is an extension to the to the is an extension field the MaskX leases), re Mask field to support 1 to support Mask field and action analogous to th and action analogous defined above. If 1 kB pages are enabled ( return zero on read, and the effect on the TLB return zero on and the effect read, with written as if they were is on a write entry value 0b11. the must bits these Architecture, 1 of the In Release read, and have on zero be written as zero, return on the translation. address virtual no effect kB 1 6 disallows Release 0 read-only from readable, and their values are copied to and from to and from copied are values and their readable, respec- or read, on a TLB write TLB entry the tively. ( enabled are not If 1 kB pages PageGrain PageGrain Ignored on write; returns zero on read. on write; Ignored R 0 Required Table 9.21Table PageMask Register (Continued) Descriptions Field =1 =0 1 kB 4 kB 4 1 MB 16 kB 64 kB 256 kB 256

BPG BPG f Page Size for Mask field Values if 10..0 63..60, 31..29, Table 9.22Table and MaskX the Mask for Values Config Config Fields 0i Name Bits MaskX 12..11the subsequent Architecture (and Release 2 of In 166Vo For Programmers Architecture MIPS®

. A Table 9.22 Table

1 register, then reading register, 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 = 0 or SP are implemented. All processors PageMask field Config3 by software. Release 6 requires that by software. Release 6 requires fferent value on read. Hardware may read. Hardware on value fferent Mask field as defined in size encoding is not implemented by a Values for MaskX for Values of Release 2 of the architec- of 2 of Release ements that page size. that page ements if software writes the Mask field with a value 0x3FF 0x3 0xFFF 0x3 0x3FFF 0x3 0xFFFF 0x3 9.14 PageMask RegisterRegister (CP05,Select 0) g bits read-only 1s up to the minimum supported page 0x3FFFF 0xFFFFF 0x3FFFFF 0xFFFFFF =1 0x3FFFFFF 0xFFFFFFF 0x3FFFFFFF 0xFFFFFFFF BPG 0x3FFFFFFFF 0xFFFFFFFFF ) 13 =1. The =1. left-most bits of the Mask field neces- Fields of the PageMask Register (Continued) Register PageMask the Fields of 1 BPG value 0b11 if 1K pages are not enabled ( if 1K pages are value 0b11 ones, the processor impl processor the ones, , even if the, evenif hardware returns a di g a value different than that written value different g a illegal or unsupported values to the to Release 6). If a particular page exists only exists only on implementations PageMask MaskX register must return zeros in all bits that correspond to encodings that are not size exist only if Config3 (lsb of value is located at value is located (lsb of me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 167 Table 9.22 Table = 0). In Release 6, these bits are reserved. are bits these 6, In Release 0). = PageMask = PageMask ESP 2 2 12 11 2 2 2 2 2 2 2 2 4 MB 1 TB 4 TB 1 GB 4 GB 64GB 16 MB 16 MB 64 64 TB 16 TB 16 GB 256 MB 256 TB 256 GB Page Size for Mask field Values sary to represent this page this to represent sary ture and are treated as if they had the the had if they as are treated and ture PageGrain 2. only if Config3 .This page size is available 1. PageMask Table 9.22Table MaskX and Mask the for Values write of all 1s remains consistent with Pre-Release 6 behavior. It is implementation-dependent how many of theencodings described in Table 9.22 processor, a read of the a read processor, the value back. If a pair of bits reads back as back of bits reads pair If a back. the value For Pre-Release 6: The For Pre-Release 6: The operation of the processor is UNDEFINED otherofone thanin those listed depend requirement on this in implementingstructures hardware For Release 6: Hardware ignores writes of unsupported pagesfromkB 4 onwards have their correspondin implemented, thereby potentially returnin size. Software maydetermine whichpagesizes are supported bywriting all ones to the must implement the 4 kB page size (prior MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

field of MaskX ged Resource Architecture, Rev. 6.03 of the Architecture, the of the Architecture, is mandatory. Instead, software must invali- must software Instead, mandatory. is EHINV =1. EntryHi EHINV EntryHi if thisnot sequence if done.UNDEFINED is lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: register is changed. This operation must be carried out while running in an unmapped address must be flushed before each instance in which before each TLB must be flushed and the the 0b11 be written with register must PageGrain Programming Note: Programming SP SP PageMask value of the space. The operation of the processor is processor of the space. The operation because support for not a requirement is For Release 6, this Config3 the In implementations(and subsequent of Release 2 6) to Release releases prior date the TLB entries explicitlyTLB entriesdate the using TLBWI with 168Vo For Programmers Architecture MIPS®

0 ASE; optional optional =1); Required otherwise, (Release 6) SmartMIPS SmartMIPS Required by Required by (Pre-Release 6) (Pre-Release LPA register fields. Config3 E definitions take prece- 0 1 PageGrain (Release6) (Pre-Release 6) 8 7 5 4 for XPA ( for XPA ssing, and for large physical address ssing, and for large R relevant to Release 2 of the relevant to Release Architecture. describes the Write Reset State Compliance equent releases) of the Architecture that the Architecture of equent releases) Read / R/W or R R/W or (Release 6) (Release (Pre-Release 6) 13 12 1 kB page support, the XI/RI TLB protection bits, Table 9.23 e SmartMIPS™ ASE, the AS 9.15 PageGrain RegisterRegister (CP05, 1) Select EntryLo1 EntryLo1 register; registers is not and and and not writeable and not for SmartMIPS™ASE; Required 0 ASE 0 MCCause Meaning EntryLo* PageGrain Required . If this bit is not bit in Config3 this If bits . exception, and Extended Physical Addre Extended Physical exception, and Description bit in the bit of the EntryLo0 the bit of EntryLo0 the bit of me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 169 RI or RXI RI by software. RI registers is disabled registers is enabled.registers is Figure 9-17Figure Format Register PageGrain for implementationsRelease 2 (and of subs the description below only describes the fields SM 0 1 register is present in both and in Release 2 (and the SmartMIPS™ ASE releases) subsequent Table 9.23Table Descriptions Field Register PageGrain S32 Required

Encoding shows the format of shows the format of the implemented. This bit is optional. The existence of this bit is denoted the by either the then settable, register is a read/write register used for enabling a read/write is register PageGrain otherwise. PageGrain Fields include TLB-based MMUs and support 1 kB pages, the XI/RI TLB protection bits, multiple types of Machine Check addresses; physical exceptions, or large reporting the type of Machine Check support. The Optional The Compliance Level:

of the Architecture. As such, In implementations of both In implementations th of the Architecture and Release 2 dence. Figure 9-17 RIE 31 Enable. Read Inhibit Name Bits 31 30 29 28 27 26 25 RIE XIE ELPA ESP IEC 9.15 PageGrain Register (CP0 Select 1) Register 5, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Required Required (Release 2) (Release 6) SmartMIPS SmartMIPS ASE; other- Required by Required by wise, optional (Pre-Release 6) (Pre-Release 0 1 0 (Release 6) (Pre-Release 6) ged Resource Architecture, Rev. 6.03 0 R R/W 0 Required Write Reset State Compliance Read / R/W or R R/W or (Release 6) (Release (Pre-Release 6)

regis- field to registers register. If If register. EntryLo1 EntryLo1 PFN EntryLo1 EntryLo* and not writeable and not and Config3 Meaning Meaning and EntryLo0 and EntryLo0 and ementations of Release 2 of of Release ementations bit in the the in bit EntryLo0 XI bits in the in the bits rge physical addresses. physical rge lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description RXI bit of the bit of the bit or XI disabled registers is by software. XI enabled.registers is enabled enabled = 0, large physical addresses are not are physical addresses = 0, large field of the field SM LPA 0 1 01 is not physical address support Large is support address physical Large PFNX Encoding Encoding form the number. page frame full ters is writable and concatenated with the the with concatenated and writable is ters Config3 his bit is optional. The existence of this bit is denoted T is not implemented. by eitherthe this bit is not settable, the the settable, is not this bit implemented, and this bit is ignored on write and returns on write and returns and this bit is ignored implemented, read. zero on For implementationsReleaseof the 1 of Architecture, read. zero on bit returns this If ASE and are not used in impl in not used ASE and are the Architectureunless suchan implementation also ASE. SmartMIPS™ the implements to Copro- occur the following changes 1, a is bit If this cessor 0 registers: • The Table 9.23Table (Continued) Field Descriptions Register PageGrain Fields XIE 30 Execute Inhibit Enable. ASE 12..8 SmartMIPS™ the of features control are fields These ELPA 29la for Enables support Name Bits 170Vo For Programmers Architecture MIPS®

Required Required 0 1 (Release6) (Pre-Release 6) R/W 0 Required R/W Write Reset State Compliance Read / (Pre-Release 6) 9.15 PageGrain RegisterRegister (CP05, 1) Select and Mask field register is writ- is register EntryLo0 ical address down to register is writable is writable register Meaning Meaning bit exceptions can bit exceptions only llow the SmartMIPS ASE, ASE, SmartMIPS the llow tion algorithm is modified algorithm is tion EntryHi PageMask turns zero on zero read.turns 0 0 Reserved d left by 2 bits from the from bits by 2 left d codes for the Read-Inhibit and codes for fields of the Description the virtual address. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 171 PFNX exceptions both use the TLBL excep- TLBL exceptions both use the tion code. code. exception TLBRI use the Execute-Inhibit exceptions TLBXI exception code field of the = 0, 1 kB pages are not implemented, and = 0, not implemented, 1 kB pages are registers hold the phys SP 0 and Execute-Inhibit Read-Inhibit 1 the exceptions use Read-Inhibit 01 is not enabled page support kB 1 is enabled page support kB 1 MaskX field of the VPN2X PFN and bit is a 1, the following changes occur to copro- occur the following changes 1, a is bit Encoding Encoding bit 10 (the field is shifte definition). Release 1 able and is concatenated to the right of the page size. the smaller to reflect EntryLo1 care” mask for the TLB entry. to form the “don’t of and bits 12..11 Config3 If this • The If • The • The virtual address transla cessor 0 registers: • The this bit on is ignored write and zero on returns read. For For implementations which fo this bit by is ignored the hardware, meaning the Read-Inhibit and Execute-Inhi use the TLBL exception code. Execute-Inhibit exceptions. Execute-Inhibit Must be written as zero; re as zero; written be Must Table 9.23Table (Continued) Field Descriptions Register PageGrain 7..5 Fields 0 25..13, IEC 27 exception Enables unique ESP 28 Enables support for 1 kB pages. Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

needed. needed. wise not of Machine multiple types ported.; Other- Check are sup- are Check itecture, be the following fields must . ged Resource Architecture, Rev. 6.03 R 0 if Optional EHINV Write Reset State Compliance Read / is mandatory. Instead, software must inval- is mandatory. 0 0 EHINV EntryHi out while running in an unmapped address space. The EntryHi flushed before each instance in which the value of the properties of =0 is written into into is written =0 =0 is written into into is written =0 PFN PFNX Meaning if this sequence if is not done. EHINV EHINV release prior to Release 6) of the Arch of the 6) Release prior to release , EntryLo1 , EntryLo1 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Field Value Required PFN ing TLBWI and the PFNX FTLB but the VPN2 field is con- not by set selected the TLB with sistent register. the Index Dual of Mode Page Directory Level mem- from accessed PTE - PTEs first ory has PTEVld bit set but second does not memory from PTE accessed set. bit PTEVld have power-of-4 size is Huge Page derived but Dual not implemented. Page mode FTLB and PageMask is not set to a that is pagesize supported by the FTLB. EntryHi with tive accesses. The value in EPC might might EPC in value The accesses. tive not point to the faulting instruction. EntryHi with UNDEFINED requirement because support for EntryLo0 EntryLo0 5 and Walker Table Hardware Page For 6 and Walker Table Hardware Page For 4page and FTLB. A VTLB Dual For 01 No Machine Check Reported 2 Hit in TLB(s). Multiple specula- for Hits in TLB(s) Multiple 3page and FTLB. A VTLB Dual For 24-31 specific Implementation Others Reserved Encoding Check Exception. Table 9.23Table (Continued) Field Descriptions Register PageGrain register is register is changed. This operation must be carried Fields For Release 6: This is not a operation of the processor is operationis processor of the written with the specified values, and the TLB must be Programming Note: Programming In implementations of Release 2 (and any PageGrain idate the TLB entries explicitly us idate Name Bits MCCause 4..0 Machine after a . Only valid Cause Machine Check 172Vo For Programmers Architecture MIPS®

and a PageGrain 0 0b11 between the instruction that writes writes that between the instruction 9.15 PageGrain RegisterRegister (CP05, 1) Select must be cleared using the EHB instruction. EHB the using must be cleared MaskX VPN2X Field Value Required me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 173 EntryHi PageMask is changed, a hazard may be created PageGrain subsequent CACHE instruction. This hazard instruction. subsequent CACHE Note also that if MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 174Vo For Programmers Architecture MIPS®

), Table 9.29 register. register. ocessor is operatingis ocessor with Config3 MUSK, MUSUK or UUSK). MUSUK or MUSK, um privilege level ( privilege level um e access control mode from the mode control e access otherwise. 9.16 SegCtl0Register (CP05, Select 2) Optional entation system. If implemented, the Seg- implemented, If entation system. field. e behavior of each region is controlled by a AM . CFG s an associated minim fined by thePrivileged Resourcetobe Architecturemodi- E in an MT Module processor. processor. Module E in an MT = MSK) or USER (AM = RNEL are allowed when the pr RNEL are allowed when the are used together are used with th rrespond to the 32-bit Compatibility Address Space. Address Space. 32-bit Compatibility rrespond to the set with the set with the Status bit is set. bit Register. SX, registers is denoted by the SC field withinregistersfield is denoted by the SC the Status bit is set. SegCtl0 control mode is Segment Configuration ha KX me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 175 for programmable ; Section 4.13 “Segmentation Control” Status registers are instantiated per-VP registers allow configuringthe memory segm bit is set. bit Address Address Space is split into six segments. Th UX Segmentation ControlSegmentation Required Required

Status EHINV TLB invalidate feature is required by Segmentation Control. The legacy software method of rep- shows the format of the shows Segmentation Control Segmentation Control EntryHi Each Access Mode Each Access Mode allowed by the Segment Configuration. The access Segment Configuration. See and The highest lowest 2GB of the address space co Segmentation Controlbehaviorsallows address-specific de or disabled. fied The The existence of the mentation Configurations are always active. are always mentation Configurations The 32-bit Compatibility Figure 9.18 Figure Access to segments with a minimum privilege level of USER allowed are when the processor is operating with USER privilege and the resentingan invalidunmappedTLB entry by using value an address is not guaranteed to work. For MIPS64 segments,inbitsKX,SX and UX the ComplianceLevel: The Access to are allowed segments with when a theminimum processor is operating privilege level of SUPERVISOR privilege and the with SUPERVISOR KERNEL (AM = UK, MK or XKP), SUPERVISOR (AM orMK XKP), SUPERVISOR = UK, (AM KERNEL segmentsto with Access a minimumprivilege level of KE the and privilege KERNEL The MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.18 4) (CP0 Register 5, Select SegCtl2 9.17 5, Select 3) Register SegCtl1 (CP0 9.16 5, Select 2) Register SegCtl0 (CP0

0 0 32 32 0 0 0 dent dent tion Depen- tion Depen- R/W Undefined R/WR/W Implementa- R/WR/W Implementa- Write Reset State Write Reset State Read / Read / CFG 2 CFG 0 CFG ged Resource Architecture, Rev. 6.03 0 Table 9.29 Table 9.28 Table 9.28 Table 9.28 Table 9.28 0 as zero; returns zero on read. R0 as zero; returns zero on read. R0 as zero; returns zero on read. R0 16 15 16 15 Description Description Register. Register. access mode, access mode, see lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: SegCtl2 SegCtl1 Table 9.25Table Descriptions Field Register SegCtl1 Table 9.24Table Descriptions Field Register SegCtl0 CFG 1 CFG 3 Figure 9.19Figure 3) Select 5, Register (CP0 Format Register SegCtl1 Figure 9.18Figure 2) Select 5, Register (CP0 Format Register SegCtl0 shows the format of the shows shows the format of the the shows Fields Fields 0 58..32 Reserved. Must be written 0 63..62 Reserved. Must be written 0 63..32 Reserved. Must be written XAM 61..59 region xkphys CFG 2 15..0 2, see Segment Configuration CFG 3 31..16 3, see Configuration Segment CFG 0 15..0 0, see Segment Configuration CFG 1 31..16 1, see Configuration Segment Name Bits Name Bits Figure 9.20 Figure Figure 9.19 Figure 0 XAM 31 63 63 62 61 59 58 31 176Vo For Programmers Architecture MIPS®

field. field. 0 32 regions within

SegCtl2XR dent byte tion Depen- PABITS R/WR/W Implementa- R/W 0 =1 uses the access mode speci- Write Reset State Read / CFG 4 CFG 9.18 SegCtl2Register (CP05, Select 4) SegCtl2XR[n] 0 through through through fieldto is setbehavior zero. This is designed to be Virtual AddressVirtual range Table 9.28 Table 9.28 0xA800 0000 000 0000 0000 000 0xA800 0xB000 0000 000 0000 0000 000 0xB000 0xB800 0000 000 0000 0000 000 0xB800 0xAFFF FFFF FFFF FFFF FFFF FFFF 0xAFFF 0xB7FF FFFF FFFF FFFF FFFF FFFF 0xB7FF 0xBFFF FFFF FFFF FFFF FFFF FFFF 0xBFFF for the corresponding region region for the corresponding SegCtl2XR with associated bit with associated 16 15 n Description ss mode enable. Each bit of XR[0..7] of XR[0..7] ss mode enable. Each bit 63..56 1 2 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 177 SegCtl2 tion of the default kernel-unmapped access kernel-unmapped access default redefinition of the allow region selectable fields defines access mode enable access mode defines of the xkphys segment. legacy microMIPS64 systems. Table 9.26Table Descriptions Field Register SegCtl2 56 66 763 field isundefined and the XR SegCtl2XR 56 55 CFG 5 . Thereby mapped. xkphys CCA informationuse regions from the TLB. For regions where Table 9.27Table regions address xkphys of MIPS64 XR indexing and Figure 9.20Figure 4) Select 5, Register (CP0 Format Register SegCtl2 field defines an enable bit2 8xkphys for each(xkphysregion of consists =0, default xkphys behaviorisoperational. SegCtl1XAM describes the XR indexingthe XR of describes the microMIPS64 xkphys address space. Fields XR SegCtl1XAM byte xkphys segment).The xkphys regions are indexed 0..7 in ascending address order in the XR 63..56acce region xkphys 62 CFG 4 15..0 4, see Segment Configuration CFG 5 31..16 5, see Configuration Segment Name Bits SegCtl1XAM SegCtl2XR fied by The SegCtl2XR[n] the 2 The On reset, the backward compatible with Table 9.27 mode used by xkphysAn regions. xkphys region 31 63 9.18.1 xkphys override access mode MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

R/W Required R/W Required R/W Required Write Compliance Read / ged Resource Architecture, Rev. 6.03

. finedin all CFGfieldsof the Segmentation Control UNDEFINED through through through through through ntation Control” . R/W Required hys address regions (Continued) regions address hys =1. =1. Virtual AddressVirtual range 0x8800 0000 000 0000 0000 000 0x8800 0x9000 0000 000 0000 0000 000 0x9000 0x9800 0000 000 0000 0000 000 0x9800 0xA000 0000 000 0000 0000 000 0xA000 0x87FF FFFF FFFF FFFF FFFF FFFF 0x87FF 0000 0000 0000 0x8000 FFFF FFFF FFFF 0x8FFF FFFF FFFF FFFF 0x97FF FFFF FFFF FFFF 0x9FFF 0xA7FF FFFF FFFF FFFF FFFF FFFF 0xA7FF ERL for use when unmapped. As when unmapped. for use Table 9.29 Table Segment becomes unmapped Description for Segment, for use when Segment, for for Status Section 4.13 “Segme 63..56 6 7 8 9 0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: SegCtl2 and uncached when and uncached when unmapped. See unmapped. This field is provisioned to mapping of up support to a physical address. 36-bit Table 9.11 on page See Table 9.11 on by base architecture. defined 150 for the encoding of this field. For Release 6, writes of of 6, writes Release For field. of this encoding the for whereas the field unmodified, leave values unsupported in Release 5, such a writeresult may in behavior. 05 15 25 35 46 XR Table 9.28Table CFG (Segment Confi Field Description guration) Table 9.27Table xkp MIPS64 XR of indexing describes the CFG (Segment Configuration) fields de Fields 0 8..7 Reserved. R0 Required C 2..0 attribute, coherency Cache PA 15..9bits Physical address EU 3 behavior. condition Error AM 6..4 mode. Access control See Name Bits registers. Table 9.28 178Vo For Programmers Architecture MIPS®

0 0 0 0 1 1 EU el mapped region el mapped name(s) modes, with unmapped Description 2 3 C Equivalent Segment Undefined Undefined Undefined Undefined 9.18 SegCtl2Register (CP05, Select 4) kseg3 sseg, ksseg upervisor and kern field. rvisor and kernel mapped mapped rvisor and kernel region AM sed to implement a fully-mapped flat address space address flat a fully-mapped sed to implement upervisor unmapped upervisor region and kernel e.g. sseg in a fixed mapping TLB. e.g. kseg0, kseg1 e.g. kseg0, e.g. kseg3 sseg e.g. ksseg, kuseg, suseg e.g. useg, in user and in user and supervisor appear in regions which kernel mode. CFG dregion unmapped Unrestricted PA 0x000 0x000 0x002 0x000 apped unmapped region Kernel-only Undefined Undefined mode Kernel through through Virtual AddressVirtual range 0xFFFF FFFF FFFF FFFF FFFF FFFF 0xFFFF 0000 FFFF E000 0xFFFF FFFF FFFF DFFF 0xFFFF 0000 FFFF C000 0xFFFF the microMIPS64 address space. Mode mode UK UK AM MK MSK Supervisor Supervisor MUSK MUSK me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 179 31..29 VA User mode Action when referenced from Operating Operating from referenced when Action Table 9.29Table Modes Control Access Configuration Segment 63..61 VA describes the partitioning of describes describes a configuration of Segmentation Control equivalent to legacy fixed partitioning. This is a rec- describes the access control modes specifiable in the in modes specifiable control the access describes 1 111 110 0111111 Table 9.30Table state reset legacy Region) Compatibility (32-bit Configuration Segment CFG Mode 0 kseg3 1 ksseg, sseg 23 kseg1 4 kseg0 useg kuseg, suseg, 5useg kuseg, suseg, Table 9.31 Table 9.30 ommended reset configuration for conformancewith legacy segmentation.fixed Table 9.29 Table 9.31Table space of MIPS64 address partitioning Configuration Segment Compatibility 32-bit UK 000 Error Address Error Address Unm CFG Segment MK 001 Error Address Error Address Mapped mapped region Kernel-only USK 101 Address Error Unmapped Unmapped S MSK 010 Address Error Mapped Mapped Supe UUSK 111 Unmapped Unmapped Unmappe MUSK 011 Mapped Mapped Mapped s User, MUSUK 100 Mapped Mapped Unmapped U MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

name(s) ged Resource Architecture, Rev. 6.03 Equivalent Segment kseg1 kseg0 useg, kuseg, suseg on partitioning of MIPS64 address space (Continued) space address MIPS64 of partitioning on through through through through FFFF BFFF FFFF FFFF BFFF Virtual AddressVirtual range 0xFFFF 0xFFFF FFFF A000 0000 FFFF A000 0xFFFF FFFF FFFF 9FFF 0xFFFF 0000 FFFF 8000 0xFFFF FFFF 0000 7FFF 0x0000 0000 0000 4000 0x0000 FFFF 0000 3FFF 0x0000 0000 0000 0000 0x0000 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 31..29 VA 63..61 VA 2111101 3111100 4 0005 000 011 001..000 CFG Table 9.31Table Configurati Segment Compatibility 32-bit 180Vo For Programmers Architecture MIPS®

0 register con- register . PWBase register specifies the specifies register State Compliance Reset n of the indexn fields in the table system contains only a register fields. ich are Page Table Entries. ich are Page Table PWSize PWBase Write tries (PTEs). This array is knownistries (PTEs). This arrayas a Read / describes the the describes 9.19 PWBase RegisterRegister(CP0 5, 5) Select registers. r TLB refills. It is used in combinationTLB refills. It r the with ories. Adirectoryan array of pointers.ories. Each consists of tables - up to four- tables directory levelsplus one page table register specifies the locatio register address. A single-level address. page lowest (leaf) of elements wh =1. PWSize er Field Descriptions er Field Descriptions Table 9.32 PW and Section 4.15Page Table Walker” “Hardware PWField PWBase bits extracted from faulting the The address. se virtual address, used as the starting point for hardware page table y or to a Page Table. Table. a Page to or y Config3 register; PWField Description VPE in an MT ModuleVPE in processor. e system is an array of Page Table En Page Table an array of is e system Register 5, Select 5) 5, Select Register =1. Register 5, Select 6) address pointeraddress R/W 0 Required PWBase PW me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 181 Figure 9.21 PWBase Register Format for the page walker feature. hardware for the walker feature. hardware page Config3 Table 9.32Table Regist PWBase either to another director registers. Required Required Required Required

register contains the Page Table Ba Table the Page contains register register configurespageregister hardware table walkingfo PWSize register is instantiated per-VPE in an MT Moduleprocessor. in an MT register is instantiated per-VPE register is instantiated per- instantiated is register shows the format of the shows and PWField PWField PWBase PWBase PWBase Fields The Page Table and the Directories are indexed by indexed are and the Directories Page Table The Levels above the lowest Page Table level are known as Direct level are known as Table Page above the lowest Levels pointer in a directory is The operation of page table walking is described in faulting address. This register only exists if The existence of thisexistence register of is denotedThe when walking.is incombination It used with the The PWBase Compliance Level: The Compliance Level: The The or Page Table which will be accessed. The tainsbase theofPage Table address the first Directory or number of index bits to be used for each level. The be used of index bits to number single Page Table. A multi-levelthe - tree structure page table system forms a Page Table (PT) and is indexed using bits from the faultingPage Table The hardwareThe page walker feature supportsmulti-level page level.level The lowestpagetabl of any Figure 9.21 Figure Name Bits PWBase 63..0 Base Page Table 63 9.20 (CP0 PWField Register 9.19Register (CP0 PWBase MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

register fields. PWField ware page-tableware walking, auto- the ged Resource Architecture, Rev. 6.03 describes the describes Table 9.33 Register; tected on a read during operation hard PWField lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: shows the formats of the the formats shows XTLB Refill exception is taken. taken. is mated Refill exception XTLB process or aborted and a TLB is 9.22 Figure If a synchronousIf exception condition is de 182Vo For Programmers Architecture MIPS®

GDW UDW 0 MDW Required PWSize PWSize PWSize Required when Required when Required when Required is implemented is implemented is implemented BDI PTEI 0 Optional 12 12 12 12 6 5 38 37 32 (Release 6) (Release 6) (Release 6) (Release 6) (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) PTI or R0 R/W 0 R/W 0 R/W 0 R/W R/W 0 Write ResetState Compliance Read / Read 12 11 9.20 PWField RegisterRegister (CP05, Select 6) =0 t of the index the t of MDI PWDirExt t of the index field the t of s, which is used to index is used to index s, which PWCtl r of index bits is specified bits is of index r y. The number of index bits y. y. The number of index bits y. The number of index bits is number of The y. The number The of index bits y. . . . t significant bit of the index index the of bit significant t ast significant bit of the index 18 17 ast significant bi . ast significant bit of the index returns zero on read.zero on returns R0 0 Optional returns zero on read.zero on returns R0 0 Required UDW MDW GDW Description BDW Reserved UDI . x. Least significant bi me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 183 PWSize PWSize PWSize Figure Figure 9.22 Format PWField Register PWSize PTW Table 9.33Table PWField Register Field Descriptions 24 23 PWSize field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted the Base Directory. into index specified by specified is specified by field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted index into the Upper Director field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted index into the Middle Director is specified by Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: Entire write is dropped if the write value to this field is less than 12. the pagesize is downgraded If PTI is not a power of four, four. nearest power of to the Release 6: Entire Release 6: Entire write is dropped if the write value to this field is less than 12. Release 6: BDI is 0 read-only if by into the Page Table. The numbe into the Table. Page extracted from the faulting addres field extracted from the faulting address, which is used to to which is used address, faulting from the field extracted index into the Global Director is specified by GDI Fields 0 0 63..38 zero; as be written Must 0 31..30 zero; as be written Must PTI 11..6 inde Table Page BDI 37..32 Le index. Directory Base UDI 23..18 Leas index. Directory Upper GDI 29..24 Directory index. Le Global MDI 17..12 Directory index. Le Middle 31 30 29 63 Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 C, V, G TLB fields are overwritten G TLB fields are overwritten C, V, R/W 2 Required Write ResetState Compliance Read / Read

er to includeer support for an additional 4th directory -2 bits ltiple tables. For example, user and kernel page tables PTEI eld Descriptions (Continued) eld Descriptions for these cases. ailable values by writing ailable values by writing this A value of 4 means logical 4 A value of the shifted value are rotated rotated are value the shifted unsupported value leaves the value leaves unsupported e RI/XI positions RI/XI positions for the e TLB t value is not available, PTEI programmed so that the entire PFN, PFN, entire the that so programmed Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ). With this additional level,). With the length of the page table walk increases to 5 levels for the hardware page walk feature. page for the hardware UNPREDICTABLE UNPREDICTABLE BDI field is used by Software to determine the presence of this feature. of this to determine the presence by Software used field is Required Required

PWField will remain unchanged. field. If the requested shif register unmodified. Values of 0,1 are unsupported, 2 is register unmodified. Values implemen- and are optional values and all other required, tation-specific. the Software can discover av into position for RI and XI the bit locations protection the entry. TLB within A value of 2 means rotate the right-most two bits into the entry. TLB the for positions bit RI/XI entire bit the by one A value of 3 means logical shift right RI/XI into the twobits the right-most then rotate PTE and positions for the TLB entry. For Release 6, a write of an first. The purpose of this shift is to remove the SW-only shift is to remove the first. The purpose of this SW-only the Then entry. the TLB into be written what will bits from two least-significant bits of the rotate then and PTE by two bits the entire right shift two into th bits right-most entry. 0 are 1 and RESERVED of values 6, the Pre-Release For operation not be used; HW Page and should the of the Walker is Specifies the logical right shift and rotation which will will be which and rotation shift right the logical Specifies Entry values loaded by hardware applied to Page Table page table walking. The entire PTE is logically by shifted right PWDirExt Table 9.33Table Fi PWField Register field can be incorrectly field can be PTEI register may be optionally extendedto a 64 bit regist PWCtl PWField Fields level priorlevel to PGD ( with zeros by the logical right shift operation. The intention of this facility is to only remove the SW-only bitswithlogical zeros by the of the right shift operation. The intentionfacility this of is to only removeSW-only the valuePTE from the whichbelater will writtenthe into TLB. Compliance Level: The The purposeThe of thisadditional level is to supportwalking mu can be maintained separately. can be maintained separately. that the Note from 4. The PTEI 5..0 Entry shift. Table Page Name Bits 184Vo For Programmers Architecture MIPS® 9.21 PWSize Register (CP0 Register 5, Select 7)

PS PWBase register PWSize ltiplier (left . The PWSize . e locationof the index BadVAddr register fields. table system contains only a table system contains =1, the nativesize is pointer ich are Page Table Entries. ich are Page Table An additional mu PS allocated in the Page Table struc- Table Page in the allocated PWSize PWSize ze for the refill. For 32-bit addressing, directory levels plus onedirectory levels plus page table tries (PTEs). This array is knownistries (PTEs). This arrayas a register specifies th ft shift),hardware and walking page table is describes the describes 9.21 Register PWSize Register (CP05,7) Select PWField ories. A directory consists of an array of pointers.Adirectory Eachories. consists of by the native pointer size. by the native pointer address. A single-level page address. lowest (leaf) of elements wh Table 9.34 Table g is appliedonlyg is when exception an XTLB Refill would be Section 4.15Page Table Walker” “Hardware field. This allows space to be to allows space This field. y or to a Page Table. Table. a Page to or y For 64-bit addressing,For 64-bitthe nativesize is set by the pointer PTEW d by bits extractedfrom the faulting address Register; E in an MT Module processor. processor. Module E in an MT multi-levelpage tables - upto four are multiplied by the native pointer si native the multiplied by are e system is an array of Page Table En Page Table an array of is e system PWSize =1. PWSize PWSize PW to be used for each level. The to be used for each me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 185 Config3 either to another director =0, the nativesize pointerle(2 bit is 32 bits registers. PS . -managed fields. PWField register configures pagehardware table walking for TLB refills. It is used in combination with the register is instantiated per-VP PWSize shows the formats of the formats the shows BadVAddr and PWSize PWSize applied onlyTLB or XTLB Refillthe when exception wouldbe taken.When The Page Table and the Directories are indexe The Page Table register contains the base address of the first Directory or Page Table which will be accessed. The accessed. be which will Table or Page the first Directory of register contains the base address the native pointer32 size is bits(2 bitshift). left Figure 9.23 Figure Index values used to access Directories Directories access used to Index values The The PWBase field. When This register only if exists ture for software specifies the number of index bits taken. is multiplied Page Table the value used to access index The 64 bits (3 bit left(3 bitwalkin table64 bitshardware page shift), and Levels above the lowest Page Table level are known as Direct level are known as Table Page above the lowest Levels The operation of page table walking is described in pointer in a directory is pointer in a directory is fields in shift value) be specified using the can single Page Table. A multi-level the - tree structure page table system forms a Page Table (PT) and is indexed using bits from the faultingPage Table The hardwareThe feature supports page walk level.levellowest The pagetabl of any MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

0 BDW PTEW 0 Optional 6 5 38 37 32 ged Resource Architecture, Rev. 6.03 or R0 PTW R/W Write ResetState Compliance Read / 12 11 =0 PWDirExt MDW e Walking is acti- is Walking e acti- is Walking e PWCtl rmed using Base Meaning Meaning . to create an index into the the into index an to create BDI turns zero on turns read. 0 0 Required 18 17 returns zero on returns read. 0 0 Optional Description Reserved read-only 0 read-only if lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Directory index. BadVAddr Base Directory. The least significantBase Directory. by is specified bit of the field PWField Directoriesare loaded as 32-bit addresses. Page Tabl Hardware vated only for 32-bit address regions, when the TLB Refill vector would be used. Directoriesare loaded as 64-bit addresses. Page Tabl Hardware vated only for 64-bit address regions, vector Refill TLB/XTLB the when be used. would UDW Figure 9.23 Figure Format Register PWSize ory index width. 0 No read is perfo 0Pointers within 32-bit pointer size. 1Pointers within 64-bit pointer size. Table 9.34Table Descriptions Field Register PWSize Value Value Non-zero Number of bits to be extracted from 24 23 Release 6: BDW is Fields 0 63..38 Must be written as zero; 0 31 Must be written as zero; re PS 30 Size. Pointer R/W 0 Required BDW 37..32 Direct Base 0 PS GDW Name Bits 31 30 29 63 186Vo For Programmers Architecture MIPS®

Required 1 (Release 6) (Pre-Release 6) R/W 0 Recommended R/W 0 Recommended R/W 0 Recommended R/W 0 Write ResetState Compliance Read / . PTI 9.21 Register PWSize Register (CP05,7) Select PWField e least significant 0 is ignored; entire Meaning Meaning Meaning Meaning . . . to create an index into the the into index an to create the into index an to create to create an index into the the into index an to create the into index an to create UDI MDI GDI Description ndex width. ndex width. Middle Directory. The least signifi- least The Middle Directory. by is specified of the field bit cant PWField bit of significant least The Table. Page by is specified the field Directory index. BadVAddr of Release 6: Write dropped. write is BadVAddr Directory index. BadVAddr Directory index. BadVAddr Global Directory. Th Global Directory. by is specified bit of the field PWField significant The least Directory. Upper by is specified bit of the field PWField me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 187 0 No read is performed using Middle 0 Pre-Release 6: UNPREDICTABLE 0 No read is using Global performed 0 No read is performed using Upper ble index width. Value Value Value Value Non-zero Number of bits to be extracted from Non-zero Number of bits to be extracted from Non-zero Number be of bits to extracted from Non-zero Number of bits to be extracted from Value 0 meaning has changed for Release 6. for meaning has changed 0 Value Table 9.34 Table (Continued) Descriptions Field Register PWSize Fields PTW 11..6 Ta Page GDW 29..24i Global Directory UDW 23..18 index Directory width. Upper MDW 17..12i Middle Directory Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

PTE PWSize

patibility PA>32bits PA>32bits 64-bit with 32-bit with Use Case & & extended & extended Huge Pages Huge Huge Pages Huge Pages Huge Huge Pages Huge Suggested & PA>32 bits & PA>32 Compatibility Compatibility Compatibility extended PTE =1 PS

. . Size 64 bits PTEW 128 bits 128 PWSize Leaf PTE PWSize ged Resource Architecture, Rev. 6.03 R/W 0 Required Write ResetState Compliance Read / 64 bits 128 bits 128 PTE Size Non-Leaf Non-Leaf the page table walk the page tablelevels 5 increases to 1 1 settings. Whether the case settings. Whether 64 bits 128 bits 128 Directory Pointer SIze Pointer HugePg is writeable, or read-only read-only or writeable, is PWCtl account for the native data account for the ilable values by writing this writing ilable values by = 1, then it is implementation- is it then 1, = 64 bits 32 bits is implementation-dependent. is implementation-dependent. shift of one must be imple- shift of Pointer Pointer and PS PS Addressing Description Table 9.35Table PS/PTEW Usage lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: PS/PTEW

PWSize PTEW ). With this additional level, the length of With ). 1 1 BDW PWSize field is used by Software to determine the presence of this feature. of this to determine the presence by Software used field is PWSize addition to the shift required to shift required to the addition sizethe of machine. The set of availableshifts ava Software the can discover PTEW not available, shift value is the requested field. If A zero. as written be will mented. if 6, In Release dependent as to whether PTEW as to whether dependent 0. PTE sizes of 128-bits are not recommended. 128-bits sizes of PTE 0. PWSize Table 9.34 Table (Continued) Descriptions Field Register PWSize PWDirExt HugePg 1 1 PWCtl register maybe optionally extended64an additionaltoinclude to a bit registersupportfor 4thdirectory describes valid describes is supported is implementation-dependentis as specified in description for PWCtl =1 PWSize Fields PS level priorlevel ( to PGD PTEW The Table 9.35 from 4. The 1 0 111 0 0 1 0 1 0 64 bits 64 bits 64 bits 64 bits 64 bits N/A 64 bits N/A 64 bits 64 bits 128 bits Base 64-bit 64 bits 64-bit with 64 bit with 00 00 0 0 1 1 32 bits 0 32 bits 32 bits 32 bits 32 bits N/A N/A 32 bits 32 bits Com- 32-bit 32 bits 64 bits 32-bit with 32 bits 32-bit with PTEW 5..0 in index, Table Page the to applied shift the left Specifies Name Bits PWSize 188Vo For Programmers Architecture MIPS®

Use Case Suggested Not supported the directory lev- Size Leaf PTE fields and reading, unsupported val- for each pointer in each pointer for PTEW PTE Size Non-Leaf Non-Leaf 9.21 Register PWSize Register (CP05,7) Select and PWSize PS Directory Pointer SIze Pointer PWSize

Pointer Pointer Addressing tes how many bytes of memory is used used of memory is many bytes tes how and/or 64-bitand/or compatibility/extendedis modes implementation-dependent. Soft- self, the pointer uses the least significant bytes. uses the pointer self, me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 189 PTEW >1 Table 9.35Table PS/PTEWUsage (Continued) PWSize HugePg N/A PWCtl PS ues will be written as zero. 64-bit architectural64-bit support 32-bit of ware can determine supportedmodes bywriting to N/A els. If this size is larger than the pointerthe than it If this size is larger els. PWSize 1. Pointer Size” The “Directory deno column MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 190Vo For Programmers Architecture MIPS®

0 Required (Release 6) Wired ware n n-1 ged Resource Architecture, Rev. 6.03 00Reserved 00Reserved Rby hard- Preset Write Reset State Compliance Read/ 0 Limit. Wired. and to is equal and 16 15 =1 or 4. A fixed-size TLB A fixed-size 4. =1 or Meaning able to a variable-sized an implementation-depen- MT =4 does not have wired entries. does not have =4 Limit Description MT lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Config d is determined by determined by d is d is determined by determined by d is Figure 9.25 WiredRegister Format The maximum number of maximum number of The wired of entries may be equal to the number TLB entries minus one. fieldTheis reserved i.e., writesare return 0s. ignored, reads the less than be must which entries, number of TLB entries one. minus number of The wired entries is imple- mentation-dependent Limit. Config Table 9.36Table Wired Register Field Descriptions m m-1 0 6 compatibility. Release Pre > 0 The maximum number of wired Encoding TLB, such asTLB, when such The size of this fiel this of size The are only applic entries Wired The size of this fiel this of size The in the case of of case the in programmed but only Limit may alternatively be programmed but only as specified by the contents of architecturally is not capability this i.e., register dent visible. Attempting to writevaluea greater than Limitinto the be dropped. the write to field causes Wired 0 Fields 0 31. m Must be written as zero; returns zero on read. 0 15..n Must be written as zero; returns zero on read.

Limit m-1..16 below. - table see wired limit TLB Wired n-1..0 wired TLB boundary R/W 0 Required Name Bits 31 192Vo For Programmers Architecture MIPS®

PWBase register . The PWSize e locationof the index BadVAddr table system contains only a table system contains ich are Page Table Entries. ich are Page Table register fields. register PWCtl tries (PTEs). This array is knownistries (PTEs). This arrayas a register specifies th 9.23Register PWCtl Register (CP06, 6) Select describes the the describes PWField TLB refills. It is used in combination with the ories. Adirectoryan array of pointers. Eachories. of consists tables - up to four- tables directory levelsplus one page table address. A single-level page address. lowest (leaf) of elements wh =0. =1. PW Table 9.37 PWEn y or to a Page Table. Table. a Page to or y PWCtl Config3 d by bits extractedfrom the faulting address Register; VPE in an MT Modulean VPE in processor. e system is an array of Page Table En Page Table an array of is e system PWCtl to be used for each level. The to be used for each me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 193 registers. for the walker feature. hardware page either to another director PWSize Required Required

and . register is instantiated per- instantiated is register shows the formats of the formats the shows register configures hardwarewalking table page for BadVAddr PWField PWCtl The Page Table and the Directories are indexe The Page Table Levels above the lowest Page Table level are known as Direct as level are known Table Page lowest above the Levels pointer in a directory is Figure 9.26 Figure The Page Table (PT) and is indexed using bits from the faultingPage Table single Page Table. A multi-levelthe - tree structure page table system forms a Hardware pagetable walking is disabled when The hardwareThe page walker feature supportsmulti-level page level.levellowest The pagetabl of any register contains the base address of the first Directory or Page Table which will be accessed. The accessed. be which will Table or Page the first Directory of register contains the base address The existence of thisexistence register of The is denoted when PWBase, PWField Compliance Level: The specifies the number of index bits fields in 9.23Select 6) Register 6, (CP0 PWCtl Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

5..0 0 Required State Compliance Reset DPH HugePg Psn ged Resource Architecture, Rev. 6.03 or or R0 8 7 6 R/W 0 Required R/W 0 Required R/W 0 Required R/W 0 Required R/WR/W 0 Required Write Read / R or R/W 0 Required R or R/W 0 Required .e., directory .e., directory is bit is only is bit Field Descriptions Field Descriptions Reserved - extended for 4th - extended read-only 0. If read-only read-only 0. If read-only a TLB miss exception. a TLB miss exception. miss a TLB a TLB miss exception. e valuein3-bits of the the MTC0 write data is reserved, then the -of-4 in size. For this case, Page PTE can represent a Directory levels. If this bit is PTE is used for even TLB TLB even for used is PTE will synthesize will synthesize the physical zero; returns zero; read.zero on R0 0 Required uge Page PTE can only repre- Page PTE uge non-leaf table (i non-leaf table PWSize Page support. Th Page support. in Huge Page PTE. Only used and Description =1. =1. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: field is set. PTEvld PWField Figure 9.26Figure Format Register PWCtl HugePg Table 9.37Table PWCtl Register HugePg =0, xuseg misses generate =1, walker handles xuseg. bit is set, then a Huge DPH is then bit set, XU XU bit is clear, then a H a then is clear, DPH bit XS=0, xsseg misses generate =1, walker handles xsseg. xsseg. XS=1, walker handles XK=0, xkseg misses generate =1, walker handles xkseg. xkseg. XK=1, walker handles used when used If If is not initiated. walk page hardware The power-of-4 memory region or a 2x power-of-4 memory memory 2x power-of-4 region or a power-of-4 region. For the case, one first when page and the adjacent PTE used for the is odd PTE PTE. For adjacent the and page latter the case, the Hardware power 2 x that is sent a region for the physical addresses Hardware will the synthesize both the even and odd TLB pages from single the PTE entry. level) is supported. addresses for both the even and odd TLB pages from the single PTE entry. If set, then Huge Page PTE in The hardware page walk is not initiated. walk page hardware The If The hardware page walk is not initiated. walk page hardware The If If this bit is enabled.is set, then the Hardware Page Table directory level - the level. Base may be In Release 6, PWDirExt supported. is not Base Directory 0, then are considered a single field - if th - field are considered a single

30 29 28 27 26 25 XKXSXU Fields 31 - 29, 25..8 as Reserved, Must written be PWCtl entire write is dropped.entire write is XS 27 If XU 26 If XK 28 If PSn 5:0 of position Bit PWEn PWDirExt 0 XK XS XU DPH 7 Dual Page format of Huge PWEn 31 walker enable HardwareTable Page Name Bits HugePg 6 in Page PTE supported Huge PWDirExt 30 PW Indices - 194Vo For Programmers Architecture MIPS®

is , if a then read- HugePg =1. Software PWFieldGDI PWCtl HugePg PWCtlPsn PWCtlPWDirExt=1) PWCtl up to bit An PTE. the 64 in PTEvld X Huge-Page Support No Must be 0 Support Huge-Page leaf entry Comment xuseg reserved reserved reserved capability Rsvd Field in Non- in Field Rsvd xuseg and xuseg and xsseg xuseg and xkseg xuseg 9.23Register PWCtl Register (CP06, 6) Select xuseg, xsseg, xkseg xuseg, xsseg, Hardware walker ster Field configurations Field configurations ster Huge Page configurations configurations Page Huge not used not used directory level feature (determinable by PTEVld PTEVld = 0. An implementationAn= 0. that doesHugesupport not Pages is required Always PTE Always PTE register field configurations. PTE PTE XU Directory Index / HugePg Prepended to Global to Global Prepended XS / field is used to denote whether HugePages are supportedor not. XK register control visibilityvirtual of 63..62 address bits specifiedin

fields functionperformanceas a primarily optimization,allowing segment based PWCtl me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 195 Type of Entry HugePg PWCtl PWCtl rtual address bitsaddress 63..62 are used in Base Directory lookup.rtual to 0. Software can determine the supported range by writing ones to Fields Address Bits Virtual = 0 read-only. Software can determine Huge Page support by writing1to 0 read-only. = Psn not used XK, XS, XU 110- 00 0010- 0 00 None 1100- 1 None 1 1 0 62 1 1 1 63 1 disabled 63..62 XK XS XU Table 9.39Table Field HugePg and =0 means Pointer Pointer =0 means Table 9.38Table PWCtl XK/XS/XU Regi The =1 means Huge Page HugetPg Non-Leaf Leaf PTEVld PWCtl fields of the of the fields fields are ignored if the optional 4th field is provisioned field is bits,allowing at 6 a starting bit positionfor PTEVld PTE PTEVld PWCtl describes allowed describes describes how describes the PTE XK, XS, XU XK, XS, XK, XS, XU XK, XS, PWCtlPsn PWSizeGDW. PWSizeGDW. HugePg can disable Huge Pages bycan disable setting HugePages exclusionaddress translations of pagefrom the hardware table. The and If the implementationIf supportsHuge Pages,Huge Software enables then Pagessetting by followingread returnsthen support HugePage 0, is not implemented. The The ing. Table 9.38 implementation may choose to support a more limited range by hardwiring an implementation defined number of the high order bits of to hardwire Table 9.39 implemented, in this case, vi this case, implemented, in 1PTE 0 Pointer Always PWCTL MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Comment power-of-4) power-of-4) any power-of- 2 power-of- any Huge-Page region can region Huge-Page only be 2x power-of-4 2x power-of-4 only be (either power (either power of 4 or 2x Huge-Page region can Huge-Page be ged Resource Architecture, Rev. 6.03 Allowed Allowed non-Power of 4 of non-Power Even TLB page and Odd TLB page and TLB Even from derived page entries both single PTE Even TLB page and Odd TLB page and TLB Even from derived page entries both single PTE esented in the Directory Levels. esented in Size of Huge Page Huge Size of lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Allowed Allowed Power of 4 Power Not Allowed Not exception is taken. aborts and TLB/XTLB Refill TLB/XTLB Refill and aborts Table 9.40Table Levels in Directory representation Huge Page If encountered, HW Page Walker If encountered,Walker Page HW Two PTEs are read from mem- Two to HW Page Walker ory by the used for and Odd be the Even entries. page TLB DPH 0 1 describes how describes repr HugePages are PWCTL Table 9.40 196Vo For Programmers Architecture MIPS®

43 0 for Implementations for register fields. register State Compliance Reset HWREna R/W 0 Reserved - Optional R/W 0 Required Write Read / Read cessor 0 is not enabled. 0 is cessor describes the the describes 9.24 HWREna RegisterRegister (CP07, 0) Select Table 9.41 Mask . XNP sters, and register sters, and register in this field is a 1 and and a 1 in this field is a mode in a mode whichcopro implemented, bit ‘n’ of Register; plemented, access to the the to access plemented, gisters via the registers are accessible RDHWR which hardware determines at hardware register register (which hardware ented, the corresponding bit ented, the corresponding Config5 ignored on write. ignored on Description HWREna access to the to the implementation- access me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 197 Figure 9.27Figure Format Register HWREna PerfCnt and (Release 2). (Release lists the RDHWR regi RDHWR the lists Table 9.41Table HWREna Register Field Descriptions Required

instruction to a particular to a particular instruction may not be an register). may not be an actual ‘n’ is not If RDHWR register a write. is ignored on and zero a field returns this If RDHWR register ‘n’ is im register is enabled if bit in this field is a ‘n’ 1 and dis- 0. a of this field is ‘n’ abled if bit See for the RDHWR instruction a list of valid hard- ware registers. Table 9.42 disabled if bit is a 0. the corresponding dependent hardware registers 31 and 30. hardware registers 31 dependent If a register is not implem returns a zero and is is register to that access implemented, is If a register enabled if the corresponding bit to bit number ‘n’ corresponds ‘n’ in this field. register contains a bit mask th register contains shows the format of the shows HWREna Fields Release 6 adds access to CP0 adds Release 6 instruction when that instructionis executed in Figure 9.27 Figure Compliance Level: The Impl Mask 29..0 by the RDHWR access enables in this field bit Each 31..30 Impl These bits enable 31 30 29 Name Bits 9.24 7, Select 0) Register Register (CP0 HWREna MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

register mented Optional Required Required Required Required Required Reserved (Release 6) (Release 6) ister is imple- is ister Required if the is implemented is Required if any if Required UserLocal reg- PerfCnt turn value can be vir-

register, then reading register, sel ers are accessible via the a Reserved a Reserved Instruction Excep- is notprovide desirable to is HWREna ged Resource Architecture, Rev. 6.03 ndent use. If they ndent use. If they ould be the smallest the ould be field. register, while odd while odd register, at hardware register. at hardware SCX family of instruc- cess to the coprocessor 0 coprocessor cess to the dually disabled and the re . CPUNum Control XNP h of the hardware regist of the hardware h pecific storage block. In Release 6, is currently This register running. Meaning instructions is not present, other- not present, is instructions EBase er provides read access to the copro- access to the read provides er In some operating environments, the the In some operating environments, software may emulate the instruction’s software may emulate the instruction’s the return value sh value return the the system which must be synchronize must be synchronize the system which zed at the cost of handling zed at the cost of r implementation-depe r for future architecture use. Access architecture future for zed value. For example, if it etc. In absence of hardware support for In absence of hardware support in a Reserved Instruction Exception. in a Reserved Instruction selects the the selects Config5 value denotes the value denotes number of cycles synchronize. sel register provides read ac lease 6 Double-Width LLX/ 6 Double-Width lease e processor implements th be used with the SYNCI instruction. See that instruction’s instruction’s that See instruction. SYNCI with the be used register in the in the pair. register Register. register is required. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 123register CC incrementscycle every CPU CPU cycle register increments every second CC register CC incrementsCPU cycle every third register, if it is implemented. is implemented. if it register, a thread-s to a pointer is register Counter Count Table 9.42Table Numbers Register RDHWR CCRes Value UserLocal register, access to that register may be indivi register, selects the implementation. in the wise present atomics, user or extended double-width behavior through means. other See tions. If set to 1, then LLX/SCX family of family LLX/SCX to 1, then If set tions. between update of the register. For example: between update of the register. description for the use of this value. In the typical implementation, this value value this implementation, In the typical for the value. use of this description caches in are no should be zero if there tracks cache the instruction or because no caches, are there because (either cases, other In cache). data the to writes that must be caches of the size line cessor 0 results in a Reserved Instruction Exception. Instruction in a Reserved results These registers numbers are reserved provides read access to the coprocessor 0 the coprocessor to access read provides UserLocal UserLocal These register numbers are reserved fo are not implemented, access results the the register, privileged software may select whic privileged software may select register, Count CC This regist cycle counter. High-resolution XNP Indicates support for Re ULR This Local User Register. CCResThis CC register. the of Resolution PerfCnt Even Counter Pair. Performance CPUNum of the Number CPU on which the program SYNCI_Step Address step sizeto HWREna 5 3 4 1 0 2 29 6-28 Using the tualized by the operating system. tualized by the Software maydetermine which registers are implementedby writing all ones to the the value back. If a bit back as reads a one, th RDHWRa registerinstruction.In doing may so, be virtuali tion, interpreting the instruction, and returning the virtuali direct access to the direct access 30-31 Number Mnemonic Description Compliance Register 198Vo For Programmers Architecture MIPS®

0 register fields. fields. register ndefined Required address that caused one of the fol- one of the caused that address rs, or for Watch exceptions, since or for Watch rs, BadVAddr Write Reset State Compliance Read/ describes the 9.25 BadVAddr RegisterRegister (CP08, Select 0) er Field Descriptions er Field Descriptions Table 9.43 BadVAddr register; register; ss information for cache or bus erro ss information for cache Register 8, Select 0) 8, Select Register Description BadVAddr me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 199 Figure 9.28Figure Format Register BadVAddr . rtual address R U Table 9.43Table Regist BadVAddr Required

register does not capture addre capture register does not register is a read-only register that captures the most recent virtual that captures the most recent register read-only register is a shows the format of the the shows BadVAddr BadVAddr Fields

Compliance Level: The lowing exceptions: • Addresserror (AdELAdES) or • Modified Refill TLB/XTLB • TLBS) Invalid (TLBL, TLB •TLB The an addressing error. is none 9.28 Figure 63 Name Bits BadVAddr 63..0 Bad vi MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.25 (CP0 Register BadVAddr ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 200Vo For Programmers Architecture MIPS®

0 Required Required (Release 6) (Pre-Release 6) (Pre-Release register fields. Register 8, Select 1) register is onlyby set State Compliance Reset BadInstr register is instantiatedper- BadInstr R Undefined Optional BadInstr Write Read / describes the on emulation. The registerMachineInterrupts,set by is not NMI, 9.26 BadInstr Register (CP0 Table 9.44 Table . bit must bit always to 1. be set bit set to 1. Thebit 1. set to BI Read Inhibit, TLB Execute Inhibit, TLB Modified BI register is not set by Watch or EJTAG exceptions. or EJTAG register is not set by Watch BadInstr register; Config3 Config3 int, Floating-Point, exception2 Coprocessor BadInstr BadInstr 32 bits are placed in bits bits are 32 capture the most recent instruction which caused the following one of BadInstr UNPREDICTABLE Description is Register 8, Select 1) 8, Select Register 16 containing zero. 16 containing Optional me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 201 Required Figure 9.29Figure Format Register BadInstr BadInstr instruction word. cessor. For Release For Release 6, the cessor. Table 9.44Table Descriptions Field Register BadInstr e Error exceptions. The e Error exceptions. register is indicated by the is register Instruction words words Instruction smaller than bits 31: with 15:0, Release 6 -

BadInstr register is provided to allow acceleration of provided to is instructi register register is a read-only register that is a read-only register register shows the proposedtheformat of BadInstr Address Error, TLB or XTLB Refill, TLB Invalid, TLB Invalid, TLB XTLB Refill, TLB or Error, Address Coprocessor Unusable, Coprocessor Unusable, Reserved Instruction System Call, Breakpo Trap, Integer Overflow, BadInstr Fields Presence of the exceptions whichto are synchronous an instruction. The Figure 9.29 VPE in an MT ModuleanVPE in pro The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release check, Bus Error or Cach Error check, Bus When a synchronous exception occurs for whichWhen a synchronous exception occurs there is no valid instruction wo rd (for example TLB Refill - Instruc- tion Fetch),stored the value in The • Addressing exceptions: • validity Instruction • Execution Exception Name Bits BadInstr 31:0 Faulting 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.26Register (CP0 BadInstr ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 202Vo For Programmers Architecture MIPS®

0 Required Required (Release 6) (Pre-Release 6) (Pre-Release register fields. register register is only set by register is instantiated register is per- BadInstrP State Compliance Reset register contains the prior BadInstrP P BadInstrP R Undefined Optional Write Read / BadInstr describes the registerMachine is not set by Interrupts, NMI, Table 9.45 9.27 BadInstrP Register (CP0 Register 8, Select 2) register. The register. bit set to 1. The bit mustset to1. be BP BP Read Inhibit, TLB Execute Inhibit, TLB Modified register is not set by Watch or EJTAG exceptions. or EJTAG register is not set by Watch BadInstrP register; ster Field Descriptions Field Descriptions ster BadInstr BadInstr Config3 Config3 int, Floating-Point,2 exception Coprocessor ation of instruction emulation. The emulation. instruction ation of BadInstrP BadInstr 32 bits are placed in bits bits are 32 BadInstrP Description Register 8, Select 2) 8, Select Register 16 containing zero. 16 containing . Optional me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 203 for these exceptions: for these exceptions: Required Figure Figure 9.30 Format Register BadInstrP cessor. For Release For Release 6, the cessor. register is indicated by the e Error exceptions. The e Error exceptions. Table 9.45Table Regi BadInstrP Instruction words words Instruction smaller than 15:0, with bits 31: with 15:0, Release 6 - BadInstrP UNPREDICTABLE register is used in conjunctionwith the register is updated register is provided to allow acceler P P is shows the proposedtheformat of BadInstr BadInstr Coprocessor Unusable, Coprocessor Unusable, Reserved Instruction System Call, Breakpo Trap, Integer Overflow, TLB Invalid, TLB XTLB Refill, TLB or Error, Address BadInstrP Fields BadInstrP Figure 9.30 check, Bus Error or Cach Error check, Bus branch instruction, when the faulting instruction is in a branch delay slot. The The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release Presence of the When a synchronousWhenand exception faulting the occurs instructionthenslot,a branch delayin is not the value stored in The • validity Instruction • Execution Exception • Addressing exceptions whichto are synchronous an instruction. The MT ModuleanVPE in pro Name Bits 31 BadInstrP 31:0 instruction. branch Prior 9.27 Register (CP0 BadInstrP MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 204Vo For Programmers Architecture MIPS®

0 tion is executed, retired, register fields. Selects 6 and 7) Selects e width of the processor. processor. the of e width and are not defined by and are not defined the architecture. Count Write Reset State Compliance Read/ 9.28 CountRegister Register (CP09, 0) Select , whetheroran instruc not rposes,synchronize includingto proces- reset or at describes the P0 Register 9, the processor, not the issu the processor, Table 9.46 Count . register; Description served for implementation-dependent use Count me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 205 Figure9.31 Count Register Format . Table 9.46Table Count RegisterField Descriptions Implementation-dependent Required

shows the format of the shows register acts as a timer, incrementing at a constant rate constant at a incrementing a timer, register acts as functionalor diagnostic registerpufor can be written Count Count Fields sors. CountThe registerread via RDHWR can also be register 2. 9.31 Figure Compliance Level: CP0 register 9, Selects 6 and 7 are re Compliance Level: The

or any forward progress is made through the pipeline. The rate at which the counter increments is implementation- functionof the pipelinedependent,clock and is a of The Count 31..0 Interval counter R/W Undefined Required 31 Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.29 (C Reserved for Implementations 9.28Select 0) Register 9, (CP0 Count Register ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 206Vo For Programmers Architecture MIPS®

reg-

, or field is ASID fields to field is the the is field EntryHi Fill Context ASID , VPN2 and ASID VPN2 register. A TLBR TLBR A register. Register 10, Select 0) VPN2 BadVAddr ite, access operations. and its of thevirtual address EntryHi e EHINV field around the use register fields. register 40 39 32 is set to a value of 2 or 3. is set to a valueof This field 2 or register and reading the value back. IE address error exception and these EntryHi ASIDX ry between ry between the field of the EntryHi EH INV Config4 VPN2X register. An implementation of Release 2 of the register. 9.30 EntryHiRegister (CP0 ds from the selected TLB entry. The ds from the selected TLB entry. ftware mustsave andrestore thevalue of VPN2X describes the otherwise. ation used for TLB read, wr ation used EntryHi 13 12 11 10 8 7 0 TLB Modified) causes the b the TLB Modified) causes into the the into and restore the and restore value of th value and is used value and is during to the TLB comparison process rmine the bounda Select 0) Select TLB Invalidand TLB Modified and exceptions, in other 12..11 Optional Table 9.47 Table ess ess error sequence. Software writes exception of the ant for the subsequent usage of TLBWI instructions. ant of TLBWI instructions. for the subsequent usage memory accesses. One method of invalidating the memory accesses. by writing all ones to the register are not defined after an defined after not are register register; Fill field of the TLB entry can be optionally invalidated. When this is done, the EntryHi EntryHi Register 10, Register VPN2 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 207 fields tobe written into the Figure 9.32Figure Format Register EntryHi . field allow software to dete for TLB-based MMU; for TLB-based register with the corresponding fiel register with the corresponding VPN2 fields of the fields VPN2 R VPN2, cont. and SEGBITS EntryHi R Required Required

, and , and field is overwrittenTLBR instruction,by so a fieldinstruction.field withThisTLBWI exists the if VPN2 ASID , register contains the virtual register contains the address match inform shows the format of the the shows EHINV registers. VPNX2 EntryHi Architecturewhich supports pages also writes VA 1 kB software. the architecture, Release 3 of the In around use of the TLBR. This is especially important in

use of the instruction writes the is overwritten by a TLBR instruction, so software must save of the TLBR instruction. This is especially import Software may determine the value of SEGBITS Bits read as “1” from the as “1” from the read Bits A TLB exception(TLBRefill,TLB Invalid, XTLB Refill, or corresponding to the ister (via MTC0 or DMTC0) or (via MTC0 theister not do implicit cause write of address-related fields in the XContext Compliance Level: The calculate the value of fields may be modifiedhardwareby duringthe addr Figure 9.32 Figure invalidated entry is ignored on address match for determine TLB match. TLB determine Because the written with the current by software address space identifier The R 31 63 62 61 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.30 (CP0 EntryHi Register

port) and and 1 kB Page Sup- State Compliance Reset ged Resource Architecture, Rev. 6.03 R 0 Required R/W 0 (Release Required 2 R/W Undefined Required R/W Undefined Required Write Read / . field to sup- field to 63 62 er Field Descriptions er Field Descriptions quent releases), this default, the the default, this bits. bits. le by either hard- either by le field must be is written with = 1 (access to 32- only supply the VPN2 R Fill AT not implemented, = 1 and and = 1 address region. If address VPN2 SP SP irtual page number / 2). / page number irtual Meaning EntryHi Config software before a TLB write. software before a software before a TLB write. before a TLB write. software take up the unimplemented the unimplemented take up ros on read, ignored on write. on read, ignored ros on 40 bits. If the processor If bits. 40 if if ocessor will cture (and cture (and subse rcumstance, the rcumstance, operation of the Config3 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description ual address bits than e bits are not writab expansion of the virtual address the of expansion gion, corresponding to VA to corresponding gion, Supervisor Mode is Supervisor this encoding is reserved = 1. If enabled for write, this field con- of the virtual address and is written by hard- of the virtual address and is written UNDEFINED ESP field is an extension to the Table 9.47Table Regist EntryHi 12 11 of the virtual address (v 0b11 xkseg: address region kernel 0b10 Reserved 0b000b01region address xuseg: user xsseg: supervisor bits. If the processor virtual implements more VPN2X Encoding 39 13 field must be extended to be extended must field space. See below. Returns ze Returns See below. space. ware on a TLB exception or on a TLB read, and is by write. before a TLB software not enabled, and in If writes are implementations of must be written field this of the 1 Architecture, Release on read. with zero and returns zeros any other value, any other and the pr legal values on an exception. bit compatibility segments only), only the 0b00 and 0b11 bit only), only the segments compatibility 0b00 and 0b11 values are legal. In this ci is processor PageGrain tains VA tains This field is written by hardware on a TLB exception or on on a TLB exception or on is written by hardware This field by and is written read, a TLB implementing processors For This field is written by hardware on a TLB exception or on on a TLB exception or on is written by hardware This field by written is and read, a TLB of size the limits implicitly field this of width default The each virtual address space to extended to take up some or all of the implements fewer virt fewer implements port 1 kB pages. Thes port 1 ware or software unless the the VPN2 the bits this default, address than Fill Fields

R 63..62 memory re Virtual Fill 61..40 Fill bits reserved for VPN2 39..13 VA Name Bits VPN2X 12..11the Archite 2 of In Release 208Vo For Programmers Architecture MIPS®

field =2 or 3. or =2 VPN2X IE MMU) Required support, or if Config4 hardware invalidate hardware invalidate Required (Release 6) Required for TLBWI Register 10, Select 0) in an unmapped address in an unmapped = AE If then then

else 0 State Compliance 1 Reset Undefined Config4 of the Architecture, the Architecture, of the A before each instance in which the value then

If is mandatory. Instead, software must invali- must software Instead, mandatory. is R/W Undefined Required (TLB R/W 0 Optional (Release 3). R/W else 0 Write = 1 Read / E Config4 EHINV 9.30 EntryHiRegister (CP0 carried out while running carried out while =1. EntryHi EHINV eld Descriptions (Continued) eld Descriptions EntryHi on will update this field on will update this field if thisnot sequence if done.UNDEFINED is n with zero and the TLB must be flushed Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 209 then these bits extend the ASID field. the ASID field. these bits extend then

= 1 returns zero; as be written = 0 Must then > 1, and this bit is set, the TLBWI instruc- TLBWI the this bit is set, > 1, and > 1, a TLBR instructi > 1, a TLBR IE AE AE IE Table 9.47Table Fi Register EntryHi Config4 Config4 Config4 Config4 register is changed. This operation must be If If zero on read. zero on on a TLB read and the by software to establish current ASID value for TLB write and against which TLB refer- TLB ASID field. ences match each entry’s tion will invalidate the VPN2 field of the selected TLB entry. If withe the VPN2 invalid bit of the read TLB entry. TLB entry. read of the bit VPN2 invalid withe the register must be writte PageGrain EntryHi Fields Programming Note: Programming implementationsIn 6) of Releaseprior to Release 2 (and any subsequentreleases of the date the TLB entries explicitly entriesTLB date the using TLBWI with of the space. The operation of the processor is processor space. The operation of the for not a requirement because support is For Release 6, this ASID 7..0 by hardware is written field This identifier. Address space Name Bits ASIDX 9..8 If EHINV 10 TLB HW Invalidate MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 210Vo For Programmers Architecture MIPS®

0 IPTI register is shows the IntCtl . Compare ecture, the presence ecture, the presence Figure 9.33 Figure Register 11, Select 0) State Compliance Reset ementation-dependent way with a ementation-dependent Selects 6 and 7) Selects Write Read / register, an interrupt request is made. In register, er. In normal use however, the In normal use however, er. register fields. the Interrupt System” on pagethe Interrupt 96 -dependent use -dependent use and are not defined by the architec- 9.31 Compare Register (CP0 Compare Compare registerimplement to anda timer timer interruptfunction. P0 Register 11, P0 Register 11, t Mode, the interruptisat thelevel by the specified bit and is combined in an impl bit and is

Count TI Compare . e does not and own. change on its Cause register, as a side effect, clears the timer interrupt. the clears a side effect, as register, describes the the describes B instruction can be used to makein visible when the terrupt state changes Description , Select 0) , Select 11 Register served for implementation served register is a read/write regist are value R/W Undefined Required register. In Release 2 (and subsequent releases) of the Archit In Release 2 (and subsequent register. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 211 Compare Table 9.48 njunction with the Figure 9.33Register Format Compare Cause . register equals the value of the the value of register equals Compare Table 9.48Table Register Compare Field Descriptions register; Count Implementation-dependent Required (7) in the

IP register acts in co acts in register maintains registerstable valu a Compare register is written.register is See 6.1.2.1and “Software Hazards Compare Compare Fields The Release 1 of this request the architecture, combinedis in an implementation-dependent way with hardware interrupt 5 to set interrupt bit When the value of the ture. Compare Compare Compliance Level: CP0 register 11, Selects re 6 and 7 are registerCP0 11, Compliance Level: The field. Fordiagnostic purposes, the Programming Note: Programming Release2 of the Architecture, the EH In

write-only. Writing a value to the Writing write-only. hardware or software interrupt. For Vectored Interrup hardware or software interrupt. For Vectored of the interruptof is visible to software via the format of the Name Bits Compare 31..0 comp count Interval 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.32 (C Reserved for Implementations 9.31 (CP0 Register Compare ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 212Vo For Programmers Architecture MIPS®

reg- Status “MIPS64 and Register12, 0) Select “Interrupts” onpage 85 for a shows the format of the terrupt enabling, and thediagnostic 109 8765432 10 10 9 8 7 6 5 4 3 2 1 0 Figure 9.35 9.33 StatusRegister (CP and the associated pseudocode for reference, in and the associated pseudocode rating modes for the processor. See processor. rating modes for the IPL KSU IPL KSU Table 9.50 Table . See register fields. for a discussion forofmodes, operating a and Status register for Pre-Release 6; register for Pre-Release that contains the operating mode, in operating the contains that KX/SX/UX Status me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 213 this register combine to create ope combine to create this register describes the the describes . P Register 12, Select 0) 12, Select P Register . Figure 9.35Figure 6 Release for Format Register Status Figure 9.34Figure 6 Pre-Release for Format Register Status Required

Table 9.49 KX/SX/UX shows the format of the Status register is a read/write register register register is a read/write Status states of the processor. Fields of states of the processor. microMIPS64 Operating Modes” on page 23 discussion of interruptmodes. 9.35 Figure Status of behavior the modifies Release 6 Compliance Level: The addition to ister for Release 6; ister for Release RW 0 FR 0 MX PX BEV 0 SR NMI ASE Impl IM7..IM2 IM1..IM0 KX SX UX UM R0 ERL EXL IE CU1 CU3.. CU3..CU0 RP FR RE MX PX BEV TS SR NMI ASE Impl IM7..IM2 IM1..IM0 KX SX UX UM R0 ERL EXL IE 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.33 (C Register Status

Required Register12, 0) Select 1/0 State Compliance Reset Undefined R R/W Write Read / (Release 6) (Pre-Release 6) (Pre-Release 9.33 StatusRegister (CP “64- er model continues behavior. See behavior. UNPREDICTABLE. e of this bit, the contents Meaning bit and other state or oper- other state or and bit ng-point unit. In Release 2 Release In unit. ng-point = 1 is required. I.e. the 64- on of a 32-bit FPU with sin- a 32-bit on of lease 2 of the Architecture 2 of the Architecture lease a 64-bit FPU; i.e., FR is FR i.e., FPU; 64-bit a of the Architecture (and sub- this case, FR=0, although although this case, FR=0, equent releases), both 32-bit releases), both 32-bit equent in which a 64-bit floating- ure, only MIPS64 processors processors ure, MIPS64 only 64-bit floating-point unit is 64-bit floating-point for a discussion of these com- a discussion of for FR implement a 64-bit floating- implement a 64-bit t isimplemented Description lease 5 of the Architecture, if floating- if Architecture, the 5 of lease bi-modal support for both 32-bit and both 32-bit bi-modal support for me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 215 w for more details. nt registers are = 1 64-bit FPU register model, is register model, FPU FR1 64-bit = t implemented = 0 32-bit FPU regist 32-bit FPU = 0 64-bit datatypes 64-bit datatype. 32-bit any pairs of regis- are stored in even-odd ters. datatype any UNPREDICTABLE =0. FR D/L floating-point units: floating-point 0 contain registers can Floating-point 1 contain registers can Floating-point FIR Table 9.49Table (Continued) Descriptions Field Register Status Encoding point unit is no point unit tecture (and subsequent releases) for 64-bit floati could implement a 64-bit can and 64-bit processors Re point unit. As of implemented then point is In Release 1 of the Architect In Release of the Architecture (and subs Certain combinations of the FR Certain combinations of binations. valu the changes software When floating-poi of the ations can cause ations can bit FPR Enable” on page 25 bit FPU, with the the bit FPU, with The required. to be required. disallows Release 6 64-bit FPU register models in read-only. See belo See read-only. This bit must be ignored on write and read as zero under zero under as read and write ignored on bit must be This conditions: the following •uni floating-point No • Archi- the of 1 of Release implementation In a MIPS32 • In implementation of an Re an 1 for as read and write ignored on bit must be This of Release implementation 6 a which in releases) sequent implemented. Release 6 allows implementati In gle only. precision support this does not imply even-odd pairing of 32-bit registers because Fields FR 26 mode This bit is used to register the floating-point control Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Optional (Release6) (Pre-Release 6) 0 Reserved State Compliance Reset 0 if the pro- the if 0 cessor imple- ments the neither MDMX nor the MIPS DSP Mod- ules; other- wise Undefined ged Resource Architecture, Rev. 6.03 0 R/W Undefined Required R/W 1 Required R/W Undefined Optional Write Read / R if the proces- the if R sor imple- neither ments the MDMX nor theMIPS DSP Modules; R/W otherwise

for details. e enabled in User User in enabled e versed endianness versed of these ASEs. If neither Meaning Meaning Meaning Meaning memory references while memory el Mode nor Supervisor Supervisor el Mode nor ations in User mode, without ations PX can only enable/disable write and read as zero. ndian Locations” on page 98 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description User Mode Mode 01 64-bit operations are not enabled in 64-bit operations ar 01 Normal Bootstrap 01 not allowed Access allowed Access 01 mode endianness User uses configured mode User uses re “Exception Vector Table 9.49Table (Continued) Descriptions Field Register Status Encoding Encoding Encoding Encoding See See enabling 64-bit addressing. on processors implementing one on implementing processors is implemented, DSP Module the MIPS the MDMX nor bit must be ignored on this user mode64-bit operations if StatusUX=0. the processor is in user mode: running Kern Mode nor Debug Neither bit. of this state the by affected are references Mode on write be it must ignored If bit is not implemented, this and read as zero. Fields 0 25 This returns bit as zero; zero on read. must written be RE 25reverse-e enable to Used PX 23 oper access to 64-bit Enables MX 24 Enables access to MDMX™ and MIPS® DSP resources BEV 22 of exception vectors: location the Controls Name Bits 216Vo For Programmers Architecture MIPS®

Required if Soft Required imple- is Reset mented (Release6) processor detects processor and reports a match on multi- entries TLB ple 6) (Pre-Release Register12, 0) Select 0 if the Required 0 Reserved State Compliance erwise Reset 1 for Soft 1 for Reset; 0 oth- Reset; 0 0 R/W R/W Write Read / 9.33 StatusRegister (CP whether UNPRE- for a discussion of gnores or accepts the this bit when its value is a its value is when this bit When such a detection detection a such When Meaning sition. If such a transition is hould not write a 1 to this bit causing a 0-to-1 causing a 0-to-1 transition. If t should be cleared by soft- t should be cleared by d, it d, on write must be ignored detected a match on multiple on multiple a match detected rough the reset exception vector UNPREDICTABLE ignores a write of 1. tion-dependent whether this whether tion-dependent ndent whether whether plementation-dependent ed by software, it ed by software, is Description essor initialization. essor ion” on pageion” on 43 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 217 whether hardware i resuming normal operation. normal resuming In 2 of the Architecture (and Release sub- 01 Soft Reset Not (NMI or Reset) Reset Soft “TLB Initializat “TLB Table 9.49Table (Continued) Descriptions Field Register Status Encoding entries. It is implementa is It entries. or an access TLB, to the on a write all, at occurs detection to the TLB. sequent releases), multiple TLBmatchesonly may a TLB write. bereported on occurs, the processor initiates a machine check exception exception check a machine initiates the processor occurs, It is bit. and sets this im condi- If the software. be corrected by can condition this bi this tion can be corrected, ware before See check a machine avoid to used initialization TLB software exception during proc on write it must be ignored If bit is not implemented, this and read as zero. to 1 a should not write Software causing a 0-to-1 tran thereby 0, was due to a Soft Reset: this bit is implemente If not and read as zero. For Pre-Release 6, software s a 0, thereby is value its when such a transition is caus write. For Release 6, hardware caused by software, it is side no with write the accepts write, the ignores hardware check machine a initiates and write the accepts or effects, exception. DICTABLE 21TLB has Indicates that the Fields 1 0 21 returns This bit as zero; zero on read. must written be SR 20th entry Indicates that the TS Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required for Required for wise Reserved 2 and EIC inter- EIC and 2 mode rupt only) Required if NMI Required is implemented MCU ASE; other- MCU State Compliance Reset otherwise 0 if MCU Undefined Optional ASE is not 1 for NMI; 0 1 for implemented ged Resource Architecture, Rev. 6.03 R/W Undefined (Release Optional R/W R/W Undefined Required Write mented Read / is not imple- is not 0 if MCU ASE = 1), 1), = = 0), for a for VEIC VEIC UNPRE- exception vector Config3 Config3 gnores or accepts the Meaning Meaning . An interrupt will sig- will be . An interrupt they are not implemented, implemented, not are they e 2 of the Architecture (and Architecture e 2 the of hould not write a 1 to this bit causing a 0-to-1 If causing a 0-to-1 transition. quest disabled d, it d, must be ignored on write t meaning and are interpreted t meaning and are interpreted IPL ich EIC interrupt mode is rough the reset “Interrupts” on page on “Interrupts” 85 the enabling of each of the hard- ignores a write of 1. ed by software, it ed by software, is = 1), this field is the encoded encoded the is field this 1), = lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description entation-dependent and entation-dependent and are not VEIC whether hardware i field, below. described Config3 01 Interrupt re Interrupt request enabled 01NMI NMI (Soft Reset or Reset) Not IPL Table 9.49Table (Continued) Descriptions Field Register Status Encoding Encoding these bits take on a differen as the IM7..IM2 bits, described above. ware interrupts. Refer to Refer ware interrupts. interrupts. enabled discussion of complete in Architecture the 2 of Release of In implementations ( is enabled mode interrupt EIC which was due to an NMI exception: to an NMI exception: due was this bit is implemente If not and read as zero. For Pre-Release 6, software s a 0, thereby is value its when such a transition is caus write. For Release 6, hardware be this bit must then If not MCU ASE implemented, is as zero; returns written zero on read. DICTABLE defined by the architecture. If they must ignored on be write and read as zero. (0..63) value of the current naled only if the IPL is requested higher than this value. If EIC interrupt mode is not enabled ( these bits take on a differen the as In implementations of Releas In implementations of subsequentreleases) in wh enabled ( Fields IPL 15..10Level. Interrupt Priority ASE 18 This bit is reserved for the MCU ASE. Impl 17..16are implem These bits NMI 19th entry Indicates that the Name Bits IM7..IM2 15..10 Interrupt Mask: Controls 218Vo For Programmers Architecture MIPS®

bit Addressing bit Register12, 0) Select State Compliance Reset R/W Undefined Required R/W Undefined for 64- Required Write Read /

9.33 StatusRegister (CP = 1), 1), = for a for Table 9.50 VEIC Enhanced Vir- and Config3 Meaning Meaning or references to Kernel or for emented, this bit emented, must be to 64-bit Kernel Segments ase 6 onwards, access to 64- 6 onwards, ase ve no effect on the interrupt the on effect ve no quest disabled enabling of each of soft- of each the enabling ddress are also sign-extended ecute 64-bit instructions, lease 5 without evented by explicitly sign- explicitly evented by “Interrupts” on page on “Interrupts” 85 the Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 219 ments; TLB Refill Vector is used for ments; TLB Refill Vector Segments. Kernel to references is used for Vector Refill XTLB ments; Segments. Kernel to references “32-bit Compatibility Addressing for Compatibility Addressing for “32-bit e stateKX. of 0 Seg- Kernel 64-bit to access Disables 1Seg- Kernel 64-bit Enables access to 01 Interrupt re Interrupt request enabled Table 9.49Table (Continued) Descriptions Field Register Status Encoding Encoding Segments. complete discussion of enabled interrupts. interrupts. enabled discussion of complete in Architecture the 2 of Release of In implementations ( is enabled mode interrupt EIC which ware interrupts. Refer to Refer ware interrupts. for further detail. Kernel mode can always ex regardless of th If 64-bit addressing is not impl tual Addressing (EVA), access (EVA), Addressing tual In Error. by causing an Address is disabled, when KX=0, and Rele ReleasewithEVA, 5 is pr Segments bit Kernel extending bit 31 when KX=0, the address from providing the inputs that generate the a from bit See 31. Release 5 EVA, andon page Release 6” 39 ignored on write and read as zero. Prior to Release 5, or in Re Release 5, or to Prior these bits are writable, but ha system. • Access to 64-bit Kernel Segments. • Vect Refill Use of the XTLB Fields KX 7behavior: following Enables the Name Bits IM1..IM0 9..8 Controls Interrupt Mask: MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Supervisor Mode and 64-bit addressing are implemented 6) (Pre-Release if 64-bit Required addressing is implemented (Release 6) State Compliance Reset ged Resource Architecture, Rev. 6.03 R/W Undefined if both Required Write Read / SX “32-bit “32-bit Enhanced Vir- 6, if Supervisor 6, if Supervisor pervisor Segments. pervisor Meaning 64-bit instructions, regard- instructions, 64-bit or for references to Super- ss to ss to what would normally emented, this bit emented, must be ented, enables the follow- to 64-bit Supervisor Seg- t whether access to what Release 5 EVA, and Release for further detail. isor Mode is not implemented, isor Mode is not implemented, em e address from bit 31 when from e address lease 5 without upervisor address space is Segment is prevented by by Segment is prevented lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Table 9.50 5 with EVA, and and Release 6 onwards, 5 with EVA, Segments; TLB Refill Vector is used Vector Refill Segments; TLB to Su for references Segments; XTLB Refill Vector is used Segments; XTLB Refill Vector for references to Supervisor Segments. SX or KX bit. In Release and 0 access Disables to 64-bit Supervisor 1Supervisor 64-bit Enables access to Table 9.49Table (Continued) Descriptions Field Register Status Encoding visor Segments 6” on page 39 tual Addressing (EVA), access (EVA), Addressing tual an Address causing by is disabled, when SX=0, ment In Release Error. access to 64-bit Supervisor th explicitly sign-extending the KX=0 or that generate SX=0, providing the inputs also sign-extended from address are bit 31.See Addressing for Compatibility and Release 6 onwards, if KX is In Release 5 with EVA, as 0, then as SX is 0. also written written always execute can Supervisor ignored on write and read as zero. ing behavior: • Segments Access to 64-bit Supervisor • Vect Refill XTLB Use of the in Re Release 5, or to Prior of SX. state of the less ReleasePriorto 6, if Superv is not implemented, acce Mode bit. If 64-bit addressing is not impl it is implementation-dependen s normally be 64-bit would with the enabled the enabled with space is address 64-bit supervisor be Fields SX 6is impl Mode Supervisor If Name Bits 220Vo For Programmers Architecture MIPS®

bit Addressing bit Register12, 0) Select State Compliance Reset R/W Undefined for 64- Required Write Read /

9.33 StatusRegister (CP Sta- Enhanced Vir- ents; Execution of ents; Execution of while the processor processor the while ich perform 64-bit Meaning “32-bit Compatibility or for references to User or for references to User and Release 6” on page 39 emented, this bit emented, must be to 64-bit User Segment is ase 6 onwards, access to 64- 6 onwards, ase d by explicitly sign-extending sign-extending d by explicitly which perform 64-bit opera- 64-bit which perform lease 5 without Description =1. PX me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 221 enabled; XTLB Refill Vector is used for is used enabled; XTLB Refill Vector Segments; Execution references to User wh instructions of is allowed while operations the proces- sor is Mode. in User running instructions which perform 64-bit oper- 64-bit which perform instructions ations is disallowed is running in User Mode unless abled; TLB Refill Vector is used for ref- abled; TLB Refill Vector Segm to User erences tus for further detail. 1 Segments is 64-bit User to Access 0dis- Segments is 64-bit User to Access Table 9.50 Table 9.49Table (Continued) Descriptions Field Register Status Encoding Access to 64-bit User Segments. Segments. in User Mode. is the processor operating while tions • tual Addressing (EVA), access (EVA), Addressing tual In disabled, when UX=0, by causing an Address Error. and Rele ReleasewithEVA, 5 is prevente Segment User bit the address bit from or SX=0 31 when KX=0 or UX=0, also are address the that generate the inputs providing from sign-extended 31. See bit Prior to Release 5, or in Re Release 5, or to Prior for Release 5 Addressing EVA, and • Vect Refill XTLB Use of the • Execution of instructions In Release 5 with EVA, and Release 6 onwards, if KX or In Release 5 with EVA, 0. as written also UX is then as 0, written are SX If 64-bit addressing is not impl ignored on write and read as zero. Fields UX 5behavior: following Enables the Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

d e v r e s e Supervisor Mode is implemented; Optional other- wise State Compliance Reset ged Resource Architecture, Rev. 6.03 R0R R/W Undefined Required R/W Undefined if Required Write Read / for a full for “MIPS64 UNDE- fields, described fields, described R0 and and of this value. field, described field, described above. field, described above. Meaning Meaning The encoding of this bit is: 64 Operating Modes” on 64 Operating UM ting mode of the processor. ting mode of the processor. ignored on write and read as implemented, this bit implemented, denotes implemented, this bit this bit is implemented, hown below. The meaning of hown below. if this value is written to the the to is written value this if lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: field. For Release 6, hardware 6, hardware For Release field. Description opera ation of the processor is FINED KSU ignores a write 01 Base mode is Kernel Mode Base mode is User Mode for a of operating full discussion modes. The 0b11oper- 6, the Pre-Release For Reserved. 0b000b01 Base is Kernel Mode mode 0b10 Base is Supervisor Mode mode Base mode is User Mode “MIPS64 and microMIPS Table 9.49Table (Continued) Descriptions Field Register Status Encoding Encoding field denotes the base field denotes the base See See Note: This field overlaps the the overlaps field This Note: page 23 is s encoding of this field has for Release changed 6. encoding 0b11 zero. KSU the bit overlaps This Note: Note: This bit overlaps the KSU the bit overlaps This Note: reserved. This bit must be the base operating mode of the processor. See the base operating mode of the processor. and microMIPS64 Operating Modes” on page 23 discussion of operating modes. below. Fields R0 3 If Supervisor Mode is not UM 4 If Supervisor Mode is not KSU 4..3 this of encoding If Supervisor Mode is implemented, the Name Bits 222Vo For Programmers Architecture MIPS®

LB

Register12, 0) Select 1 Required State Compliance Reset e TLB structure, so the TS bit e TLB structure, matches and shutdown the T the shutdown and matches R/W Undefined Required R/W Undefined Required R/W Write Read / 9.33 StatusRegister (CP if the if the cause physical damage to th physical damage cause uits detected multiple TLB Cache Error excep- Error Cache . This allows main main allows This . UNDEFINED use the general exception Meaning Meaning Meaning e the return address held in essor is executing instruc- essor e (and e (and subsequent releases), ) will not be updated if will not be updated ) processor when any exception processor when any exception as an unmapped and uncached and uncached as an unmapped e mastersoftware enablefor parately via the DI and EI B/XTLB Refill vectors. B/XTLB r exception are taken. EPC Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 223 Soft Reset, NMI or Soft Reset, NMI and SRSCtl (implementations of Release SRSCtl (implementations of and hutdown” condition in which circ BD “Address Translation “Address Translation for the kuseg Segment instead of instead or Cache Erro is set: is set: 01 Interrupts are disabled Interrupts are enabled 01 level Normal level Exception 01 level Normal level Error bit is set while the the proc set while bit is EXL ERL Table 9.49Table (Continued) Descriptions Field Register Status Encoding Encoding Encoding 2 of the Architecture only Architecture the 2 of is taken another exception ErrorEPC region. See page = 1” on StatusERL when 37 memory to be accessed in the presence of cache errors. The operation of the is processor vector instead of the TL ERL from tions kuseg. Reset, NMI When When • The is in kernel processor running mode • Hardware and software interrupts are disabled •will us The ERET instruction and hardware and hardware interrupts: Architectur the 2 of In Release this bit may be modified se instructions. • is treated kuseg Segment • Mode The is in Kernel processor running • Hardware and software interrupts are disabled. • exceptions Refill TLB/XTLB other than Reset, other than • EPC, Cause tion are taken. taken. are tion When Fields IE 0 Interrupt Enable: Acts as th ERL 2 Error Set Level; by the when a Reset, processor Soft EXL 1 Exception Level; Set by the Name Bits s, multiple TLB matches do not s, multiple TLB matches do design In newer damage. physical to prevent and detected were matches TLB multiple that handler exception check machine the to indicator an but is simply name, its retains the processor. by reported 1.S “TLB a indicated The TS bit originally MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

4,5 address User Mode e Interrupt System” e Interrupt on Unmodified 64-bit Unmodified 64-bit anonical sign-extend = 01). Canonical sign-extend KSU = 02). = 00)). 3 KSU in User Mode with StatusUX = 0” KSU Status xtend Canonical sign-extend ged Resource Architecture, Rev. 6.03 Status s visible changes visible terrupt state , when the IM Status = 0 and address address ERL = 1 or = 1 = 0 and = Unmodified 64-bit Unmodified 64-bit “Software Hazards and th “Software Supervisor Mode Supervisor Canonical sign-extend C in Release 5 and its effect on effective gen- address on effective in Release 5 and its effect ERL ERL Status 2 = 0 and = 0 Status KX/SX/UX KX/SX/UX = 1 or EXL sign-extend Canonical sign-e = 0 and Status EXL address address address EXL Status Status Kernel Mode Kernel Unmodified 64-bit Unmodified 64-bit Unmodified Unmodified 64-bit Unmodified “Special Behavior for Data References Data “Special Behavior for Status register are written. See register are Status B instruction can be used to make in = 0 and = 0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 1 Status DM = 0 and ( and = 0 AddressingSupervisorSegments in(K) / (S) / User Kernel (U) = 1. = 0 and DM ion operates as if in user mode. user in operates as if ion DM DM address address address Debug Table 9.50Table Generation Address 5 Effective Release Debug Debug Mode Debug Debug fields the fields of IE , or provides further detail. indicates the relationship between between indicates the relationship EXL , . ERL , CP0 Status eration for instruction and data addressing. Programming Note: Programming the EH of the Architecture, 2 Release In IPL page 96 Table 9.50 on page 38 0 – – Canonical sign-extend Canonical 11 0 1 – Unmodified 64-bit 0 Unmodified 64-bit 1 1 1 Unmodified 64-bit KX SX UX 3. Processor mode is in supervisor if (Debug 4. Processor if ( is in user mode 1.debug mode if in Processor is 2. Processor is in kernel mode if ( 5. memory access instruct A kernel EVA 224Vo For Programmers Architecture MIPS®

0 Required 0 e, including vec- Register 12, Select 1) 5 4 State Compliance Reset hardware or Externally Set VS register fields. register of the Architectur RPreset by by RPreset Write Read / IntCtl 10 9 9.34 IntCtl Register (CP0 0000 if External if External 1 2 3 4 5 describes the W W W W W ller. Thisregister exist does not in implementations of ller. Hardware 14 13 Interrupt Source Table 9.51 for a potential interrupt. interrupt. potential a for TI is both implemented and both implemented is y and Vectored Interrupt modes, modes, Interrupt y and Vectored UNPREDICTABLE terrupt capability added in Release 2 Release in terrupt capability added register; Description Cause ed, and allows software to determine to determine allows ed, software and MCU ASE IntCtl me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 225 Figure 9.36Figure Format Register IntCtl 22 HW0 33 H 44 H 55 H 66 H 77 H (Release 2). (Release Table 9.51Table Field Descriptions Register IntCtl Encoding IP bit this field specifies the IP number to which the Timer Inter- Timer the which to IP number the specifies field this merg rupt request is whether to consider The value of this field is enabled. The external interrupt controller is expected to is expected controller interrupt external The enabled. mode. interrupt that information for this provide Interrupt Controller Interrupt Mode Required

shows the format of the shows register controls the expanded in register controls IntCtl Fields tored interruptsexternalan and support for interrupt contro Release 1 of the Architecture. Release 1 9.36 Figure Compliance Level: The

. IPTI IPPCI IPFDC IPTI 31..29 Compatibilit For Interrupt 31 29 28 26 25 23 22 Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.34 Select 1) 12, (CP0 Register IntCtl Register

Optional Fast (EJTAG Chan- Debug nel Imple- mented) Optional (Per- formance Counters Implemented) State Compliance Reset hardware or Externally Set hardware or Externally Set ged Resource Architecture, Rev. 6.03 00Reserved RPreset by by RPreset RPreset by by RPreset Write Read /

PC for a PCI if External if External if External if External Config1 for a poten- 1 2 3 4 5 1 2 3 4 5 W W W W W W W W W W Cause FDCI Hardware Hardware Interrupt Source Interrupt Source Cause ectored Interrupt modes, modes, Interrupt ectored st is merged, and st is merged, allows is both implemented and both implemented is is both implemented and both implemented is UNPREDICTABLE UNPREDICTABLE ity and Vectored Interrupt modes, modes, Interrupt ity and Vectored ity and V Description ed for the MicroController ASE. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: turns zero on read. 22 HW0 33 H 44 H 55 H 66 H 77 H 22 HW0 33 H 44 H 55 H 66 H 77 H Encoding IP bit Encoding IP bit enabled. The external interrupt controller is expected to is expected controller interrupt external The enabled. mode. interrupt that information for this provide this field returns d, zero FDC is not implemente If EJTAG on read. Interrupt Controller Interrupt Mode The value of this field is zero; as written be must implemented, not is ASE that If read. zero on returns tial interrupt. interrupt. tial = re this field = 0), The value of this field is field specifies the IP number to which the Fast Debug this software allows and is merged, request Interrupt Channel to consider whether determine to potential interrupt. to is expected controller interrupt external The enabled. mode. that interrupt information for this provide counters are not implemented ( performance If Interrupt Controller Interrupt Mode this field specifies the IP number to which the Perfor- the which to IP number the specifies field this reque mance Counter Interrupt to consider whether to determine software Table 9.51Table (Continued) Descriptions Field Register IntCtl Fields IPPCI 28..26 Compatibil Interrupt For Name Bits IPFDC 25..23 Compatibil Interrupt For MCU ASE 22..14reserv Thesebits are 226Vo For Programmers Architecture MIPS®

Register 12, Select 1) State Compliance Reset 0 0 Reserved R/W 0 Optional Write Read / 9.34 IntCtl Register (CP0 32 64 128 256 512 = 0), this field ), this field speci- VInt if a reserved value reserved if a VEIC o on read. o on Config3 nor VI mode are imple- VI mode are nor Config3 (hex) (decimal) returns zero on read. on returns zero 0 0 Reserved returns zer UNDEFINED or n vectored interrupts. interrupts. n vectored = 0 and Description Spacing Between Vectors Between Vectors Spacing VInt VEIC me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 227 Config3 0x000x01 0x000 0x020 0 0x020x040x08 0x040 0x10 0x080 0x100 0x200 Encoding is ignored on is ignored write and as zero. reads denoted by denoted by All other values are reserved. For Pre-Release 6, the oper- processor is of the ation fies the spacing betwee spacing the fies is written to this field. For Release 6, hardware ignores writes of reserved values. If neither EIC interrupt mode mented (Config3 Table 9.51Table (Continued) Descriptions Field Register IntCtl Fields 0 4..0 zero; as be written Must 0 22..10 zero; as written be Must VS 9..5 interrupts implemented (as are Spacing. If vectored Vector Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 228Vo For Programmers Architecture MIPS®

only) CSS Required interrupt mode interrupt Register 12, Select 2) 0 00 State Compliance Reset hardware register fields. register PSS R Preset by R Undefined (EIC Required SRSCtl Write Read / 0 00 reg- for a for is 0, is 9.35 Register SRSCtl (CP0 is 1 (EIC describes the CSS fields VEIC SRSMap ESS VEIC , and UNDEFINED if a PSS , Config3 ster Field Descriptions ster Table 9.52 Table Config3 0 register to select the cur- to select register 00 zero value in this field zero shadow sets are numbered EICSS is field is written to any of is written to any field is is field is loaded from the the is from is field loaded , roller Mode” on page 92 zero, and returns zero on read. GPR shadow sets in the processor. This register does not exist in imple- GPR shadow the sets in processor. register; returns zero on read. 0ESS 0 Reserved returns zero on read. 0 0 Reserved returns zero on read. 0 0 Reserved is field contains the highest contains is field SRSMap Description EICSS SRSCtl Register 12, Select 2) 12, Select Register me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 229 Figure 9.37Figure Format Register SRSCtl (Release 2). (Release Table 9.52Table SRSCtl Regi 0 “External Interrupt Cont 00 00 00 0. n, where n is the value of the field. value highest the represents also field in this value The the to written be can that shadow set number that is implemented by this processor. by this processor. shadow set is implemented number that normal the only that indicates field in this of zero A value GPRs A non- are implemented. implemented the that indicates of this register, or to any of the fields of the of this register, interrupt mode is enabled), th interrupt ister. The operation of the is processor ister. request and for each interrupt external controller interrupt is used in place of the value thanthe larger one in th these other values. these this field must be written as be written must field this rent shadow set for the rent shadow interrupt. See EIC interrupt mode. If discussion of Required

register controls the operation of register controls the shows the format of the shows HSS SRSCtl Fields

mentations of the architecture prior to Release 2. architecture mentations of the 9.37 Figure Compliance Level: The 0 31..30 zeros; as written be Must 0 17..16 zeros; as be written Must 0 25..22 zeros; as be written Must 0 00 HSS 29..26 Highest Shadow Set. Th Name Bits EICSS 21..18 interrupt EIC mode shadow set. If 10922 211111 210 6543 1211109 0 2625 2221 18171615 313029 9.35 (CP0 SRSCtl Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

State Compliance Reset Comment ged Resource Architecture, Rev. 6.03 Treat as as exception Treat 0 0 Reserved R 0 Required R/W 0 Required R/W 0 Required Write Read /

= BEV Source if soft- if if soft- if = 0. Table 9.53 CSS field is CSS Status BEV onException an or Interrupt = 1. = 1. Neither is it = 1. Neither ESS ESS BEV CSS BEV = 1 or = 1 SRSCtl eld Descriptions (Continued) eld Descriptions Status rectly by software ERL UNDEFINED UNDEFINED ception or interrupt that or interrupt that ception ception or interrupt that or interrupt that ception e next paragraph, this field Status Status An ERET instruction copies An ERET instruction er of the current GPR set. current the er of field specifies the shadow set set shadow the specifies field ons in the next noted para-

ode caused by any exception caused by ode any exception which sets which any exception any exception which sets which any exception Status returns zero on read. 0 0 Reserved returns zero on read. GPR shadow registers are imple- are registers GPR shadow field and executing an an ERET field and executing GPR shadow registers are imple- = 1, or = 1, = 1, or = 1,

Description PSS EXL EXL lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: = 0 SRSCtl IV can be changed di be changed CSS can to 1 (i.e., NMI or cache error), an entry into to 1 (i.e., NMI or cache error), an entry into Condition Cause ERL ERL mented, and with the exclusi mented, and with when an field CSS from the copied is field this graph, occurs. interrupt exception or if CSS field the into back value this other than a vectored interrupt. than a vectored other of The operation processor the is the is than that greater this field into a value writes ware valuefield.HSS in the to use on entry to Kernel M entry on use to Status an ERET with updated on 1. The value of instruction. This field is not updated on This field is the writing only by The operation of The operation the processor is ware writes a value into this field that is greater than the the is than that greater this field into a value writes ware valuefield.HSS in the is updated with a new value on any interrupt or exception, ERET. an on the PSS field and restored from Status mented, this field isthe numb in th noted exclusions the With describes the various sources from which the interrupt. an exception or updated on not updated on This field is EJTAG Debug mode, or any ex any mode, or Debug EJTAG occurs with Status EJTAG Debug mode, or any ex any mode, or Debug EJTAG occurs with Status occurs Table 9.52Table Fi SRSCtl Register Table 9.53Table SRSCtl for new Sources rupt Exception All SRSCtl Fields Exception Type Exception Non-Vectored Inter- Non-Vectored 0 11..10 be written as zeros; Must 0 5..4 zeros; as be written Must PSS 9..6If Shadow Set. Previous ESS 15..12 Shadow Set. This Exception CSS 3..0 Current Set. If Shadow Name Bits 230Vo For Programmers Architecture MIPS®

register and the use Register 12, Select 2) al map register al map SRSCtl Comment Source is Source intern is external interrupt Source controller. . A hardware change . A hardware change to PSS the field as the result Source 9.35 Register SRSCtl (CP0 CSS be cleared with a JR.HBinstruction as or JALR.HB azard between the write of the azard between the write VectNum EICSS SRSCtl on an Exception or Interrupt (Continued) or Interrupt on an Exception 4 4+3..VectNum SRSMap SRSCtl  CSS and Events” on page on and Events” 123 = 1 = 1 = = 0 and VInt = 1 and = 1 and VEIC me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 231 IV IV VEIC field creates an instruction h field creates an instruction Condition Config3 Cause Config3 Config3 “Hazard Clearing Instructions rupt Table 9.53Table Sources fornew SRSCtl Vectored InterruptVectored Cause Exception Type Exception Vectored EIC Inter- EIC Vectored Programming Note: Programming to the PSS A software change of interrupt or exception entry automaticallyis cleared the for executionof the first instruction in the interrupt or exception handler. of a RDPGPR or WRPGPR instruction. This hazard must described in MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 232Vo For Programmers Architecture MIPS®

0 . 4 3 ditional Shadow Sets Register 12, Select 3) register fields. State Compliance r a non-interrupt exception, r Reset 8 7 SRSMap UNPREDICTABLE R/W 0 Required R/WR/W 0R/W 0R/W Required 0 Required 0 Required Required R/W 0 Required Write Read / if the Architecture Ad , the shadow, the set number comesfrom SRSCt- 12 11 describes the describes register are not used fo used are not register 9.36 SRSMap Register (CP0 s for vectornumberss for 7..0. The same shadowset num- mapping from an vector number to the shadow set num- Table 9.54 creatingmany-to-one a mapping a vector from toa single = 0). In such cases 16 15 VS read or write of this register are read or write of for Vector Number 4 Number Vector for 3 Number Vector for 1 Number Vector for 0 Number Vector for for Vector Number 7Number Vector for 6Number Vector for 5 Number Vector for R/W R/W 0 0 Required Required register; Description rrupt. The valuesrrupt.this The from Register 12, Select 3) 12, Select Register 20 19 = 0 or IntCtl 0 or = SRSMap IV me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 233 if a valueUNDEFINED is written to any field in this register that is greater than the Figure Figure 9.38 Format Register SRSMap in Release 2 (and subsequent releases) of subsequent 2 (and in Release Table 9.54Table Descriptions Field Register SRSMap Mode are Implemented 24 23 Required

. HSS register containsnumber the shadowregister set register containsregister 8 4-bit fieldsthe that provide the results is zero, of a software shows the format of the the shows HSS 28 27 SRSMap SRSMap . Fields SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSV0 ESS The operation of the processor is value of SRSCtl Compliance Level: and Vectored Interrupt and Vectored The The l shadow register set number. 9.38 Figure ber to use when servicing such an inte when servicing use to ber or a non-vectored interrupt (Cause can be established forber multiple interrupt vectors, If SRSCtl

SSV3SSV2SSV1 15..12SSV0 11..8register set number Shadow 7..42 Number Vector for register set number Shadow 3..0register set number Shadow register set number Shadow SSV4 19..16register set number Shadow SSV7 31..28register set number Shadow SSV6SSV5 27..24 23..20register set number Shadow register set number Shadow 31 Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.36Register (CP0 SRSMap ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 234Vo For Programmers Architecture MIPS®

, DC , 1..0 2) 2 1 0 IP Register13, 0) Select exception of the exception State Compliance Reset register fields. R Undefined Required R Undefined (Release Required R Undefined Required Cause Write Read / are interpreted as the Requested Interrupt 10 9 8 7 6 atched. With the atched. With 7..2 for IP 9.37 Cause Register (CP0 describes the describes was zero Field Descriptions Field Descriptions EXL interrupts are disp Table 9.55 Table Status is field is loaded by hard- is loaded by field is UNPREDICTABLE Meaning Meaning e 1 of the Architecture, this this Architecture, the 1 of e ASEASE IP9..IP2 RIPL IP1..IP0 0 Exc Code 0 se of the most recent exception. In addition, fields also control soft- fields also control addition, of the most recent exception. In se bits for other interrupt IP only if and returns zero on read. exception taken occurred in a in occurred taken exception register; BD register are read-only. Release 2 of theadded Architecture optional support register are read-only. Description 000 Cause me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 235 Cause Figure 9.39Figure Format Register Cause . 01 in delay slot Not In delay slot 01pending interrupt is timer No pending is interrupt Timer Table 9.55Table Register Cause Encoding Encoding Required ).

all exceptions except Unusable. all exceptions for Coprocessor branch delay slot: branch The processor updates Unusable exception is taken. exception Th Unusable on ware every exception, but is bit must be written as zero as must be written bit types): types): Releas an implementation of In when the exception occurred. Architecture, this bit denotes whether a timer interrupt is interrupt a timer whether this bit denotes Architecture, (analogous to the pending RIPL shows the format of the shows register primarily describes the cau describes primarily register fields, all fields in the WP Cause Fields , and IV Compliance Level: The for External an Interrupt Controller (EIC) interruptin mode, which Figure 9.39 Figure Priority Level( ware interrupt requests and the vector through which

TI 30 of Release Interrupt. In an implementation 2 of the Timer CE 29..28 unit when a Coprocessor Coprocessor number referenced BD 31 whether the Indicates last Name Bits 31 30 29 28 27 26 25 24 23 22 21 20 17 15 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.37 Select 0) Register 13, (CP0 Cause Register BD TI CE DC PCI ASE IV WP FDCI

2) Required for 2 and perfor- implemented) mance counters erwise Reserved erwise MCU ASE; Oth- State Compliance Reset ged Resource Architecture, Rev. 6.03 R Undefined (Release Required R/W 0 Required (Release R/W Undefined Required Write Read /

is PC BEV Config1 Status register register d Descriptions (Continued) d Descriptions on uses the general Count er-sensitive applica- er-sensitive Count is 1 and IV these bits return zero on zero return bits these Meaning for other interrupt types): Meaning Meaning rmance counter interrupt is rmance counter interrupt e 1 of the Architecture, this this Architecture, the of 1 e e 2 of the architecture (and representsthebase of the (and subsequent releases), power dissipation. This bit This bit power dissipation. , and returns zero on read. zero , and returns ecial interrupt vector: vector: interrupt ecial Description itten with zeros. zeros. with itten ), if the Cause the if ), lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: an interrupt excepti interrupt an register to be stopped in such situations. register to be (0x180) (0x200) pending ing register is not used but may still be the be still may is not used but register register. In some pow register. nt Count Count 01 Use the general exception vector vector interrupt special the Use 01of Enable counting of counting Disable 01is interrupt counter performance No pend- counter interrupt is Performance Cou Encoding Encoding Encoding subsequent releases In implementations of Releas In implementations exception vector or a sp exception vector or tions, the the tions, Releas implementation of an In zero as must be written bit pending (analogous to the IP bits or Architecture, 1 the of of Release In an implementation are not implemented ( counters performance if If MCU ASE is not implemented, source of some noticeable the allows bit denotes whether a perfo this reads and must be wr Release 2 of the Architecture the 2 of Release = 0), this bit must be written as zero and returns zero on zero returns and zero as written be must bit this 0), = read. 0, the special interrupt vector 0, the table. vectored interrupt Table 9.55Table Fiel Register Cause Fields IV 23 Indicates whether DC 27 Disable PCI 26 an implementation of In Interrupt. Counter Performance ASE 17:16 25:24, These bits are reserved for the MCU ASE. Name Bits 236Vo For Programmers Architecture MIPS®

registers are are registers implemented Register13, 0) Select State Compliance Reset R Undefined Required R Undefined Required R/W Undefined if watch Required Write Read /

ERL 9.37 Cause Register (CP0 field, Status RIPL UNPRE- are both zero. are and ERL d Descriptions (Continued) d Descriptions Meaning deferred because deferred EXL ld not write a 1 to this bit ld not write a 1 to this Status Meaning = 1), these bits take on a Status bit both indicates that the that indicates bit both e 2 of the Architecture (and h EIC is h EIC interrupt mode not interrupt. If EIC interrupt If EIC interrupt. and upt. This bit denotes whether a VEIC werea one at the timewatch the ception was EXL = 0), timer and performance coun- performance and timer = 0), Description ERL VEIC Config3 rdware ignores a write of 1. a write of ignores rdware Status me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 237 Status whether hardware ignores the write, accepts the ignores whether hardware or an interrupt is pending: interrupt an 01pending interrupt is FDC No is pending interrupt FDC 11 IP3 Hardware interrupt 1 1514 IP713 IP612 Hardware interrupt 5 IP5 Hardware interrupt 4 IP410 Hardware interrupt 3 Hardware interrupt 2 IP2 Hardware interrupt 0 EXL Bit Name Encoding

ter interrupts are combined in implementation-depen- an in combined are interrupts ter dent way with any hardware is enabled ( mode exception was detected. This Status to exception the and causes deferred, was exception watch once initiated be FDC interrupt is pending: As such, software must clear this bit as part of the watch as part of the watch this bit clear must As software such, exception loop. handler to prevent a watch exception For Pre-Release 6, software shou are both zero. For Release 6, ha bit must be this implemented, are not registers If watch as on write and read ignored zero. subsequent releases) in whic when its value is a 0, thereby causing a 0-to-1 transition. If transition. 0-to-1 a causing thereby 0, is a value its when is software, it is caused by a transition such timer 1 of the Architecture, of Release In implementations in an and interrupts are combined performance-counter way with hardware implementation-dependent interrupt 5. of Releas In implementations enabled (Config3 DICTABLE ini- and the write or accepts no effects, with side write the once exception watch a tiates different meaning and are as the interpreted different below. described Table 9.55Table Fiel Register Cause Fields WP 22 ex a watch that Indicates FDCI 21 Channel Interr Debug Fast Name Bits IP7..IP2 15..10 Indicates MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

field to rupt mode only) 2 and EIC inter- 2 and EIC DExcCode State Compliance Reset ged Resource Architecture, Rev. 6.03 e processor is running in EJTAG running in EJTAG processor is e 0 0 Reserved R Undefined (Release Optional R Undefined Required R/W Undefined Required AG is implemented and an SDBBP implemented and an AG is Write Read / a reference: load or store) load a reference: on (load or instruction fetch) instruction or on (load = 0), 0), = ruction exception VEIC d Descriptions (Continued) d Descriptions Config3 Meaning denote an SDBBP in Debug Mode. denote an SDBBP in Debug instruction is instruction executed while th to the Debug is written value this Debug Mode, external interrupt controller interrupt external e 2 of the (and Architecture e 2 of the Architecture (and ich EIC interrupt mode is mode ich EIC interrupt = is 1), this field the encoded Description Int Interrupt Bp If exception. EJT Breakpoint Sys exception Syscall IBE Bus error exception (instruction fetch) Mod modification exception TLB DBE Bus error exception (dat AdES exception (store) error Address TLBS TLB exception (store) AdEL Address error excepti TLBL TLB exception (load or instruction fetch) ) which also implements EIC interrupt EIC interrupt also implements ) which lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: st for software interrupts: VEIC ts, described ts, described above. Mnemonic Description Table 9.56Table Field ExcCode Register Cause 98 IP1 IP0 1 interrupt software Request 0 interrupt software Request Bit Name 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 these bits take on a different and are interpreted meaning bits take on a different these bi as the IP7..IP2 Must be written as zero; returns zero read. on (0..63) value of the requested interrupt. A value of zero of value A interrupt. requested the value of (0..63) is requested. interrupt no that indicates mode is If EIC interrupt not enabled ( In implementations of Releas In implementations wh subsequent releases) in enabled (Config3 An implementation of Releas An implementation subsequent releases for prioritization sources. with other interrupt mode exports these bits to the exports these bits to mode Table 9.55Table Fiel Register Cause 1..0 20..16, 7, 20..16, 1 0 2 5 6 3 4 7 8 9 10 0x0a RI Reserved inst Fields Exception Code Value Code Exception Decimal Hexadecimal

0 25:24, RIPL 15..10 Requested Interrupt Priority Level. Name Bits IP1..IP0 9..8 Controls the reque ExcCode 6..2 Exception code - see Table 9.56 238Vo For Programmers Architecture MIPS®

that re-entry to Register13, 0) Select ception has a dedi- ception duling Exceptions duling (MIPS® to indicate field rs while in Debug Mode, this Mode, Debug in rs while er is not updated. If EJTAG is er is not updated. If EJTAG “Software Hazards and the Interrupt Hazards “Software DExcCode le Exception (MDMX ASE). MDMX ode, a cache error ex ed by a cache error. ed by a cache e Coprocessor 2 exceptions 2 e Coprocessor 9.37 Cause Register (CP0 plementation-dependent use plementation-dependent on, Deallocation, or Sche erflow exception the EHBtheinstruction used can be to makeinterrupt state on-Inhibit exception on-Inhibit , register is written. See cated vector and the regist Cause implemented and a cache error occu code is written to the Debug to the is written code deprecated with Revision 5. (MIPS® DSP Module) Debug Mode was caus Mode was Debug MT Module) Cause - Reserved - Reserved - im for Available Tr exception Trap Ov Arithmetic Ov GE Guest Exception Virtualized FPE exception Floating-Point C2E precis for Reserved CpU Unusable exception Coprocessor Thread Thread Allocati TLBRI TLBRI Read-Inhibit exception TLB TLBXI TLB Executi TLB TLBXI DSPDis exception Disabled Module State DSP MDMX Previously MDMX Unusab WATCH address Reference to WatchHi/WatchLo MCheck Machine check MSADis exception Disabled MSA CacheErr m In normal Cache error. MSAFPE exception MSA Floating-Point Mnemonic Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 239 field of the e (and the subsequent releases) 1..0 Table 9.56Table Field (Continued) ExcCode Register Cause 0x1f 0x0f 0x1e 0x0c 0x0e 0x1a 0x17 0x1b 0x0b 0x0d 0x18 0x19 0x13 0x14 0x15 0x16 0x12 . 11 30 23 24 27 31 12 13 14 25 26 22 15 18 19 20 21 28-290x1d 0x1c - 16-17 0x10-0x11 Exception Code Value Code Exception Decimal Hexadecimal System” on page on System” 96 Programming Note: Programming 2 of the Architectur Release In changes visible when the IP visible changes MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 240Vo For Programmers Architecture MIPS®

ERL Status and ERL EXL 0 32 1 0 EXL register fields. Status State Compliance Reset termined by reading termined by reading the NestedExc R Undefined Required R Undefined Required Write Read /

9.38 NestedExc (CP0 Register 13, Select 5) - EXL describes the describes er containing of values the Status ErrorEPC the register can be de be can register the er Field Descriptions Descriptions Field er Table 9.57 terrupt, Address Error, Error, terrupt, Address scall, FPU, etc.). theseFor register; 0 field is updated regardless of field is updated regardless . Description prior to acceptance of current excep- prior to acceptance of current excep- EXL NestedExc ) register is a read-only regist ) register me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 241 Fault feature, existence of feature, existence Fault ERL EXL gister 13, Select 5) gister . Not updated by Debug exceptions. . Not updated by Debug exceptions. Figure Figure 9.40 Format Register NestedExc Status is not set (MCheck, In

ERL Status Status EXL Table 9.57Table Regist NestedExc NestedExc ( the current exception. Status Optional.

tion. set either would that by all exceptions Updated types which update updated by exception Not tion. by Updated exceptions which would update EPC if Status or all TLB exceptions, Bus Error, CopUnusable, Reserved Reserved CopUnusable, Error, Bus exceptions, all TLB Sy Trap, Overflow, Instruction, this exception types, register the value of (Reset, Soft Reset, NMI, Cache Error). Not updated by Not updated Cache Error). Reset, NMI, Soft (Reset, Debug exceptions. bit. shows the format of the shows NFExists Nested Exception Fields Figure 9.40 Figure Config5 Compliance Level: The prior to acceptance of to acceptance prior This registerof is part the Nested

0 31..30. as read Reserved, R0 0 Required 0 00. as read Reserved, R0 0 Required ERL 2 of Value EXL 1 of Value Name Bits 31 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.38 (CP0 Re NestedExc ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 242Vo For Programmers Architecture MIPS®

0 register to determine register requires special register requires EPC at which processing at which processing resumes EPC State Compliance Reset register when an exception register is set. register fields. EPC t and mustt and be writable. ruction, when the exception causing the exception causing ruction, when Cause EPC R/W Undefined Required ich processing resumes with the value of Write Read / 14, Select 0) 14, Select exception, or of the bit in the that contains the that contains the address describes the PS64 base architecture, the PS64 base in Processors that Implement MIPS16e register are significan register are Field Descriptions Field Descriptions ecution of the ERET instruction. the processor writes the writes the processor Branch Delay 9.39 Exception Program Counter(CP0 Register 14, Select 0) EPC contains contains the address of the ructioninst at which to resume execu- Table 9.58 Table was was the direct cause contains either: (CP0 Register (CP0 Register EPC EPC ately preceding branch or jump inst ately preceding branch register; ) read/write register is a Description EPC register, it combines the address at wh address the it combines register, Figure 9.41Figure Format EPC Register me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 243 EPC ( register is already a 1, EPC . register as the result of ex result of the register as register to change resume the processor address and read the t the MIPS16e ASE or microMI Table 9.58Table EPC Register Base Architecture Status EPC EPC Required

ssor writes the the writes ssor bit in the the in bit register: shows the format of the the shows EXL instruction is in a branch delay slot, and the instruction is in a branch delay slot, and tion. • virtual the instructionthe of address that •immedi the of virtual address the Exception Program Counter ISA Mode Fields The processor reads reads The processor the

handling. When the proce the In processors that implemen Compliance Level: The occurs. • synchronous For (precise) exceptions, after an exception has been serviced. All bits of the EPC All bits of has been serviced. after an exception Unless the at what address the processor will resume. will the processor address at what 9.41 Figure • asynchronous For (imprecise) exceptions, Software may write the EPC 63..0 Exception Program Counter Name Bits 63 ASE or microMIPS64 9.39.1 Handling of the EPC Register Special MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.39 Program Counter Exception

registers: ged Resource Architecture, Rev. 6.03 ISAMode and PC valuewritten with no interpretation. Software reted by the processor as described above. described as processor by the reted 0 ocessing resumes, as described above. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: register, it distributesthe the bitsto register, EPC  ISAMode register simplyregister return the last a GPR to 63..1 0 EPC  0 registera newvalueis which interp store 63..1 EPC  EPC EPC  resumePC EPC PC  EPC ISAMode writes to the When the processor reads reads processor the When the Software readsthe of “resumePC” is at which the address pr 244Vo For Programmers Architecture MIPS®

. reg- 0 EPC NestedEPC register fields. register State Compliance the occurrence of any excep- Reset NestedEPC termined by reading termined by reading the ith thesame behavior as the R/W Undefined Required Write Read / - instructions. Software is requiredto copy the describes the ErrorEPC the register can be de be can register the and is therefore updatedon and is therefore Table 9.59 EXL ter (CP0 Register 14, Select 2) Register ter (CP0 ) is a w read/write register Status terrupt, Address Error, Error, terrupt, Address NestedEPC register if it is desired to return to the address stored intoregister the address desired to return is if it register; register; scall, FPU, etc.). theseFor field is updated regardless of field is updated regardless 9.40 Nested Exception Program Counter (CP0 Register 14, Select 2) EPC NestedEPC . ( Description EXL NestedEPC me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 245 Fault feature, existence of feature, existence Fault Status Figure 9.42Figure Format Register NestedEPC is not set (MCheck, In

register to the register EXL Table 9.59Table Field Descriptions Register NestedEPC register ignoresof the value registerthebyused is not ERET/DERET/IRET Optional.

Not updated by exception types which update types which update updated by exception Not Updated by Updated exceptions which would update EPC if Status all TLB exceptions, Bus Error, CopUnusable, Reserved Reserved CopUnusable, Error, Bus exceptions, all TLB Sy Trap, Overflow, Instruction, this exception types, register the value of (Reset, Soft Reset, NMI, Cache Error). by Debug exceptions. Not updated NestedEPC bit. shows the format of the the shows NestedEPC NestedEPC NFExists tion, including nested tion, including nested exceptions. value of the Nested Exception Program Counter Fields •The

Figure 9.42 Figure This registerof is part the Nested Config5 Compliance Level: The ister except that: •The Name Bits 63 NestedEPC 63..0Counter Nested Exception Program MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.40 Coun Program Exception Nested ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 246Vo For Programmers Architecture MIPS®

0 shows Optional Optional Required Required Revision P0 Register 15, Select 0) State Compliance Reset hardware hardware hardware hardware 8 7 R Preset by R Presetby R Preset by R Preset by Write Read / thatcontains information identifying the Processor ID register fields. register 9.41 Processor Identification (C PRId d allows software d allows r implementations 16 15 this field for zero. If it is it If zero. for this field The value in this field is in this field The value . If this field is not imple- not field is this . If Meaning ds creates a unique number ds ish between one revision and ber of the processor. This field ber of the processor. describes the describes or manufacturer of the processor processor the of manufacturer or that designed or manufactured or that designed manufactured the Description processor. This processor. fiel d above. The combination of the Com- een various processo een various ) register is a 32 bit read-only register bit read-only 32 is a ) register the list of Company ID assignments ID of Company the list MIPS64/microMIPS64 processor Figure 9.43Figure Format Register PRId me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 247 Company ID Table 9.60 Table . PRId ( options, processor identification and revision level of the processor. Figure 9.43 options, processor identification andrevision level of the processor. Table 9.60Table PRIdRegister Field Descriptions 01 a MIPS32/microMIPS32 Not or Inc. Technologies, MIPS 2-255for Inc. Contact MIPS Technologies, register; register; Encoding 24 23 Required

for company-dependent options. not by the specified architecture mented,must itread as zero. processor. a MIPS32/microMIPS32 or Software can distinguish one implementing processor from MIPS64/microMIPS64 an earlier MIPS ISA by checking non-zero the processor implements the MIPS32/ processor implements the non-zero Architecture. or MIPS64/microMIPS64 microMIPS32 when a by MIPS Technologies IDs are assigned Company or license MIPS32/microMIPS32 MIPS64/microMIPS64 is acquired. in this field are: The encodings to distinguish betw distinguish to within a single company, and is qualified by the Compa- by and is qualified company, single a within nyID field, describe panyID fiel and ProcessorID implementation. processor to each assigned allows software to distingu to software allows another of the same type. this field is not If processor implemented,it must read zero. as PRId 31..24 the designer to Available Processor Identification Processor Fields Company Options the format of the the format of manufacturer, manufacturer manufacturer,

Compliance Level: The Name Bits Options Revision 7..0 Specifies the revision num 31 Company Company Company IDCompany 23..16 Identifiesthe company Processor ID 15..8 type of Identifies the MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.41 0) 15, Select (CP0 Register Identification Processor

register value, register value, PRId ged Resource Architecture, Rev. 6.03 r configuration information about the processor. Rather, the Rather, configurationr information about processor. the ient, requiring them to revert to check on the on revert to check to them requiring ient, lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: [email protected] case. the , reporting ilities of the processor. Programmers who identify cases cases who identify Programmers configurationregisters should be used to determine processor. the capabilities of the in whichnot the configurationsuffic are registers Software shouldthisuse not thefields register of toinfe should send email to 248Vo For Programmers Architecture MIPS®

BEV is 0. Status BEV describes the 6.2.2 “Exception Status 0b10,and the addi- be in the kseg0 or kseg1thebe in kseg0 or equal 1. The operation of CPUNum thina multi-processor sys- For the write-gate case, the For the write-gate case, BEV Status lly in systems composed of heteroge- lly in systems composed erent value when when erent value detect the existence of the write-gate by detect the existence the exception vectors used when the exception vectors 0 0 0 address space. To ensure backward compati- space. To address w the bitsupper of the Exception Base field to 12 11 10 9 0 9.42 EBase Register (CP0 Register 15, Select 1) it 29is forced toa 1 in theultimate exceptionbase are fixed with the value register itten with a diff , providing0xFFFF.FFFF.8000.0000 backward ed by software to distinguish different processors in a to distinguishsoftware ed by different tify the specific processor wi tify the specific processor e upper bits can be changed. ces the final exception address to EBase is 1, or for any EJTAG Debugbits exception. 31..12 of The reset state any EJTAG for 1, or is e kseg1 unmapped, uncached virtual address segment. error exceptions, b BEV Table 9.61 ; Table implemented. if the write-gate is not register to form the base of the exception with zeros to form the base are concatenated register each processor to be different, especia different, each processor to be exception offset is performed inhibitingexceptionoffset a carry between29 bitsof and 30 the er containing the base address of ception base registerception base to Status if multithreading is implemented. EBase EBase Register 15, Select 1) 15, Select Register mpute location. Software can the vector me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 249 Figure 9.44 EBaseRegister Format ) when (Release 2). (Release Exception Base register can be optionally extended to allo ception vectors to be placed anywhere in the in to be placed anywhere ception vectors The is 0. exception vector base address comes from the fixed defaults (see EBase Required BEV

if the Exception Base field is wr Exception UNDEFINED if the Status register initialize the ex shows the format of the shows register provides theability for software to iden register is a read/write regist register is a read/write register fields. EBase EBase EBase full set of bits 63..12 are used to co writingthat one toposition bit the and checking was set. bit if and the the base address of The addition final exception address. is to beIf the value of the exception base register changed, this must be done with of the the processor is be written. This allows ex be written. This allows bilitywith MIPS64, the write-gate bit before th be set must Vector Locations” on page 98 EBase Compliance Level: The equals 0, and a read-only CPUread-only number 0, and a equals value that may be us multi-processor system. The compatibility with Release 1 implementations. compatibility with Release 1 If the write-gate bit is not implemented, bits 31..30 of the neous processors. Bits 31..12 of theneous Bits 31..12 of processors. tem, and allows the exception vectors for vectors exception tem, and allows the Release 6 reuses the field CPUNum reuses Release 6 9.44 Figure vectors when tion of the base address and the exception offset is done inhibiting is done carry betweentionexcep-finalthebitand of the base address and the exception a bit 29 offset 30 of tion address. Thecombination these of two restrictions for segments. For cache address virtual unmapped runs in th always this exception so that address The operation of the

1 0 31 30 29 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.42 (CP0 EBase Register

EBase Required Required describes the CPUNum State Compliance State Compliance Reset Reset nally Set nally or Exter- FF80000 hardware Table 9.62 ged Resource Architecture, Rev. 6.03 0 0 Reserved R Preset by R/W 0xFFFFFF R/W 0 Required R/W 0 Required Write Write Read / Read Read / Read 0 WG is zero. 12 11 10 9 0 for usage. -gate is implemented. implemented. -gate is BEV register 0. register Status RDHWR hers. The value in this field field in this value The hers. this field specifies the base base the specifies field this by software to distinguish a to distinguish by software Section 9.8, "Global "Global Section 9.8, r hardware when the proces- em environment. In a single by VPNum to indicate by the gister 3, Select 1)," address address of the exception vec- ading, CPUNum can be used CPUNum can ading, registerwrite if the Description Description is zero. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: BEV EBase Figure 9.45 EBaseRegister Format Table 9.61Table EBase Register Field Descriptions Table 9.62Table EBase Register Field Descriptions Exception Base Exception address of the exception vectors when when vectors exception of the address Bits 63..30 can be written only when WG is set. When When set. is WG when only written be can 63..30 Bits write. on unchanged bits are zero, these WG is when WG=0 in the value being written. The WG bit must WG bit must The being written. value in the when WG=0 of the values bits to change value in the written be set true 63..30. tors when Status cessor system and can be used particular processor from the ot the from particular processor is set by inputs to the processo in the syst sor is implemented system, this value should be processor set to zero. This field can also be read through Number Register (COP0 Re In Release 6 of the architecture, with multi-threading sup- with multi-threading architecture, 6 the of Release In CPUNum ported, is replaced See virtual processor number. of multi-thre absence the In as defined. shows the format of the 29..12 31..30, conjunction with bits In 63..12 field specifies the This base Fields Fields Figure 9.45

register fields. 10 31 30 bit is ignored This on write and returns one on read. bit is ignored This on write and returns zero on read. R R 1 0 Required Required 0 11..10 read. zero on returns zero; as be written Must WG 11 gate. Bits 63..30 are on writes to EBase unchanged Write Base Base 63 Name Bits Name Bits CPUNum 9..0 CPU in a multi-pro- of the the number specifies field This Exception Exception Exception Exception 250Vo For Programmers Architecture MIPS®

bits EBase Required Set 63 State Compliance   Reset      Externally Externally VN VN VN VN VN ) if this condition is not met. Table 1 VS Ror Preset R0 0 Reserved represents the interrupt vector number the interrupt represents Write Read / Read VN       VN VN VN VN UNDEFINED 9.42 EBase Register (CP0 Register 15, Select 1) for usage.     VN VN eld Descriptions (Continued) eld Descriptions bit must bitzero. to be set hers. The value in this field field in this value The hers. by software to distinguish a to distinguish by software Section 9.8, "Global "Global Section 9.8, r hardware when the proces- em environment. In a single   by VPNum to indicate by the gister 3, Select 1)," ading, CPUNum can be used CPUNum can ading, turns zero on read. zero on turns EBase vector offset greater than 0xFFF is generated when anvector interrupt offset occurs with Description Interrupt Vector Spacing in Bytes (IntCtl Spacing Interrupt Vector me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 251 to zero in allpositions bit less than or equal to the most-significantbit in off- the vector and thetoandmust bit zero if any be set relationships of thein are true. the row No 15..12 In the absence of multi-thre absence the In as defined. Number Register (COP0 Re virtual processor number. See virtual processor number. particular processor from the ot the from particular processor is set by inputs to the processo in the syst sor is implemented should be system, this value processor set to zero. This field can also be read via RDHWR register 0. sup- with multi-threading architecture, 6 the of Release In CPUNum ported, is replaced cessor system and can be used Table 9.62Table Fi Register EBase Table 9.51 on page 225 12 VN 1513 None None None None None VN VN 14 None None VN Table 9.63Table Be Zero Must EBase15..12 Which Under Conditions Table 6.4 EBase bit 32 64 128 256 512 1. See 10 re zero; as be written Must interrupt modeThe operation enabled. of the processor is EIC Fields or as described in in as described mustbeset tozero if theinterrupt vector spacing is 32 (or zero) bytes. Programming Note: Programming Software must set EBase set. This situation can only occur when a VI shows the conditions under which each the conditions under which 9.63 shows 0 Name Bits CPUNum 9..0a multi-pro- CPU in of the the number specifies field This MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 252Vo For Programmers Architecture MIPS®

0 register field. register field. If

MVP CDMMSize State Compliance Reset VPEConf0 R Preset Optional R/W 0 Required R/W Undefined Required EN CI Write Read / 11 10 9 8 describes the register fields. the register describes a write tothis register is ignored. ster ster is controlled by the 9.43 CDMMBase Register (CP0 Register 15, Select 2) Table 9.64 byte Device Reg- “Physical Memory” Memory” “Physical address bits - writes Meaning on behavior not IO on behavior and are mory. If this bit is set, mory. physical address bits is physical register, and register, ical address of the memory that the first 64- ; returns zero on read on returns zero ; 0 0 Reserved Description P0 Register 15, Select 2) 15, Select P0 Register Figure 9.46Figure Register CDMMBase me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 253 CDMMBase CDMM_UPPER_ADDR this register returns this zeros all and ltiple VPEs, access to this regi to this access ltiple VPEs, is set toone. is 01 is Region CDMM disabled. CDMM Region is enabled. CDMM Encoding Table 9.64Table Descriptions Field Register CDMMBase reserved for additional regis- for additional ister Block of the CDMM is reserved manage CDMM regi ters which device registers. If this bit is cleared, memory requests to this address to this address requests memory bit cleared, If this is system region go to regular me the CDMM logic to go region this to memory requests are ignored, returns zero on zero on are ignored, returns read. implementation specific, see Section Section see specific, implementation on page 27. For the unimplemented mapped registers. mapped registers. of The number implemented Optional.

Config3 9 indicates this 1, to set If the format of has the 59:11base phys the of Bits 63:15 bit is cleared, a read to bit is cleared, a 60 59 MVP Fields 0 For devices that implement mu that implement For devices Compliance Level: The 64-bit physical base address for the This Commonregis- Device Memory Map facility is defined by this register. ter only exists if the Figure 9.46 Figure 0 63:60 as zero Must be written CI EN 10CDMM region. Enables the Name Bits CDMM_UP PER_ADDR 63 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.43(C Register CDMMBase

State Compliance Reset ged Resource Architecture, Rev. 6.03 R Preset Required Write Read / eld Descriptions (Continued) eld Descriptions Meaning number of 64-byte Device Regis- number of 64-byte Device Description the lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 01 DRB DRBs 01 DRBs 12 23 ...... 511 512 DRBs Encoding ter Blocks are instantiated in the core. in the core. instantiated Blocks are ter Table 9.64Table Fi Register CDMMBase Fields Name Bits CDMMSize 8:0 represents field This 254Vo For Programmers Architecture MIPS®

0 Required 0 Register 15, Select 3) State Compliance Reset hardware (IP Configu- ration Value) 0 0 Reserved R Presetby Write Read / describes the register fields. 11 10 is set to one. to set is instantiated once per processor. once per instantiated CMGCR 9.44 CMGCRBase Register (CP0 Coherency Manager Global Configuration Register space Coherency Manager ster Field Descriptions Field ster “Physical Memory” Memory” “Physical Config3 address bits - writes physical address bits is physical register, and Table 9.65 register, ical address of the memory- ger GCR registers. registers. ger GCR Description ro; returns zero on read on returns zero ro; PS MT Module, this register is register Module, this PS MT me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 255 Figure 9.47Figure Register CMGCRBase CMGCRBase CMGCR_BASE_ADDR is register only exists if if exists only register is Table 9.65Table CMGCRBase Regi This register field reflects This the value of the register field reflects GCR_BASE field withinManager the memory-mapped Coherency GCR Base Register. of The number implemented Section see specific, implementation on page 27. For the unimplemented mapped Coherency Mana mapped Coherency zero on are ignored, returns read. Optional.

the format of has the 59:11base phys the of Bits 63:15 60 59 Fields 0 Figure 9.47 Figure is reflected by this register. Th register. is reflected by this Compliance Level: for the memory-mapped base address physical The 64-bit On devices that implement the MI that implement the On devices 0 63:60, 10:0 be written as ze Must Name Bits CMGCR_B ASE_ADDR 63 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.443) 15, Select Register (CP0 Register CMGCRBase ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 256Vo For Programmers Architecture MIPS®

0 , Select 4) , Select =1). Required Required EVA Mask Register 15 Register Config5 erlaya configurable is vir- hardware or Preset by or Preset 8 7 to specify the Boot to specify Exception Vec- R Externally set Write Reset State Compliance 0 Read/ 12 9.45(CP0 Register BEVVA register fields. the describes BEVVA in order toa configurable map tophysicaladdress. in order erlaps with BEV. The BEV Ov The BEV erlaps with BEV. if the implementation supports 32-bit backward compati- er Field Descriptions lity into BEV since the address is pin configurable i.e., not Table 9.66 at the virtual captures used address Description quires a means to read BEV. the programmable to support Release 5 Enhanced Virtual Addressing (EVA). In addition, can it Addressing (EVA). to support Release 5 Enhanced Virtual implementation must guarantee BEVVA correspondssingle to the overlay that implementation must guarantee BEVVA 20 19 register; BEVVA Register 15, Select 4) 15, Select Register me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 257 =1. BEV in this case is sign-extended from its 32-bit value, locating it in one of two Figure 9.48Figure Format Register BEVVA Base e core, otherwisepins the may be hardwireda non-legacy to value. . if Release 5 Enhanced Virtual Addressing is supported ( i.e., if Release 5 Enhanced Virtual . EVA Table 9.66Table Regist BEVVA Required

The BEV address is the aligned on a 4KB within boundary maximum and 1MB minimum of is a BEV overlay which of 256MB in size. Config5 register is a read-only register th a is register shows the format of the the shows 27 Fields BEVVA The BEVVA compatibility regions. 9.48 Figure Compliance Level: tor when it is programmable as required programmable is tor when it which ov BEV Overlay the size of the be used to determine

tual addresstualthat range overlays kernel unmappedsegment(s) i.e., bility for EVA The purpose of this register is tovisibipurpose provideregister is software of thisThe throughsettable COP0. is It optional implementation for an toallow programmability ofthrough the pins a memory- to th mapped register external requiredmaps,it address tosupport is twoconfigu- For32-bita implementation that supportsboth legacyand EVA one For an unmapped cached and uncached addresses. overlays, for implementation only EVA, rable that supports to mapoverlay a virtualis sufficient address within therange of the overlay to an implementation-dependent physical supported, the Where two are address. re software as mode, in EVA is in effect Forimplementations, 64-bit this register supported is only 011:80 0 0Reserved Base 31..12 Address (BEV) Virtual Boot Exception Vector 31 Name Bits 9.45 (CP0 Register BEVVA MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required hardware or Preset by or Preset ged Resource Architecture, Rev. 6.03 R Externally set Write Reset State Compliance Read/ er Field Descriptions define size of overlay: define size of , that is, , that shown above is not supported not supported shown above is Base Description of lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Table 9.66Table Regist BEVVA is encoded as follows to encoded is Applies to bits 27:20 BEV_Overlay[31:20] = BEVVA[31:20] & (0xf || ~Mask) = BEVVA[31:20] BEV_Overlay[31:20] Mask 8’b00000000 - 1 MB - 1 8’b00000000 MB - 2 8’b00000001 - 4 MB 8’b00000011 - 8 MB 8’b00000111 MB 16 - 8’b00001111 - 32 MB 8’b00011111 - 64 MB 8’b00111111 - 128 MB 8’b01111111 8’b11111111 - 256MB that other than An encoding and causes UNDEFINED results. Fields Mask 7:0 size to define the of the Mask overlay. Name Bits 258Vo For Programmers Architecture MIPS®

, K0 reg- , and Config KU Optional Optional Required , K23 P0 Register 16, Select 0) 1 wise wise Undefined Optional register fields. Fixed Mapping Mapping Fixed Fixed Mapping Mapping Fixed MMU; 0 other- MMU; 0 other- processors with a processors with a Config on. Most of the fields in the in fields on. Most of the R e constant. Three fields, e constant. R/W for Undefined R/W for Undefined Write Reset State Compliance Read / Read describes the describes 9.46 (C Register Configuration BE AT AR MT 0 VI K0 cheability and Table 9.67 Table 16 15 14 13 12 10 9 7 6 4 3 2 0 Exception process, or ar process, Exception eld readseldand as zero is s as zero and is ignored on register; igurationcapabilities and informati e format and definition of definition e format and nizations” on pagenizations” on 347 for a nizations” on pagenizations” on 347 for a essors that do not implement cacheability and coherency and cacheability for the encoding of this field. of encoding for the for the encoding of this field. of encoding for the 2 and kseg3 ca 2 and kseg3 at do not implement a Fixed do not at Config Impl Description for implementations. Refer to the Refer implementations. for me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 259 implement implement a Fixed Mapping MMU, implement implement a Fixed Mapping MMU, Figure 9.49Figure Format Register Config es of unsupported values are ignored. es of unsupported values are ignored. register is implemented at at a is Config1implemented register . Table 9.67Table ConfigRegister Field Descriptions Required

“Alternative MMU Orga MMU “Alternative Table 9.11 on page 150 “Alternative MMU Orga MMU “Alternative Table 9.11 on page 150 processor specification for th processor specification this field this field specifies the kuseg the specifies field this attribute. For th processors read MMU, this field Mapping write. See of the description Fixed Mapping MMU organization. See For Release 6, writ ignored on write. on ignored See a Fixed Mapping MMU, this fi of the description Mapping Fixed MMU organization. See For Release 6, writ select field value of 1. For proc coherency attribute. this field specifies the kseg the specifies field this shows the format of the shows register specifies various conf specifies register Config Fields ister are initialized by hardware during the Reset must be initialized by software in the reset exception handler. 9.49 Figure Compliance Level: The

M 31 Denotes that the KU 27:25 that For processors 31 30 28 27 25 24 M K23 KU K23 30:28 that For processors Impl 24:16reserved This field is Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.46 0) 16, Select (CP0 Register Register Configuration

Required Required Required nally Set nally hardware hardware ware or Exter- ged Resource Architecture, Rev. 6.03 Rby hard- Preset R Preset by R Preset by Write Reset State Compliance Read / Read eld Descriptions (Continued) eld Descriptions PS64 with access access with PS64 the processor is run- the processor the ISA register field of register is not is not Config3 register Meaning Meaning Meaning of 0-2, denotes address of 0-2, denotes address If If Config3 or other register is one, then MIPS64 is not is not MIPS64 then is one, in which on sets (MIPS32/64 and/or lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description field is not used. field is not Config3. Config3 only to 32-bit compatibility segments compatibility 32-bit to only to all address segments All features introduced in Release 3 detect- and are optional 5 and Release able through fields. field of 23 access with microMIPS64 MIPS64or Reserved 1Big endian 01Big endian Little 01 or microMIPS32 MIPS32 or microMI MIPS64 01 Release 1 Release 2 or Release 3 or Release 5 2 Release 6 3-7 Reserved ISA Table 9.67Table Fi Config Register Encoding Encoding Encoding the ning: For Release 3, encoding values Config3. and register width (32-bit or 64-bit). and width (32-bit register instructi implemented The microMIPS32/64) denoted by are implemented then microMIPS is not implemented. microMIPS implemented then If vision level is denoted by revision level Architecture microMIPS64 the MMAR field of implemented and this implemented and Encoding 2 is new for Release 6. Fields AT 14:13 implemented by the processor. Architecture Type BE 15 Indicates the endian mode AR 12:10level. Architecture revision MIPS64 Name Bits 260Vo For Programmers Architecture MIPS®

Required Required Reserved P0 Register 16, Select 0) 0 Preset by hardware hardware 0 R R Preset by R/W Undefined Required Write Reset State Compliance Read / Read Table 9.46 (C Register Configuration “Dual “Dual ) eld Descriptions (Continued) eld Descriptions ) “Fixed Mapping “Fixed Mapping ) “TLB “TLB and Fixed-Page- is not virtual e is virtual Meaning Meaning “Block Address Translation” Translation” Address “Block (using both virtual and indexing coherency attribute. See coherency Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 261 es of unsupported values are ignored. Standard TLB (See Standard Organization” on pageOrganization” 42 BAT (See BAT on page) 351 (See Fixed Mapping MMU” on pageMMU” on 347 Variable-Page-Size Dual VTLB and FTLB (See page on Size TLBs” 353 for the of encoding this field. 01 None 01 Instruction Cache Instruction Cach 2 3 4 Table 9.67Table Fi Config Register Encoding Encoding virtual tags): virtual tags): 9.11 on page 150 For Release 6, writ Fields 0 6:4 on read. returns zero zero; as Must be written VI 3 instructioncache Virtual K0 2:0 and cacheability Kseg0 MT 9:7 MMU Type: Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 262Vo For Programmers Architecture MIPS®

Required Required Required ts per way, the line size, the ts per way, (CP0 Register 16, Select 1) register fields. hardware hardware hardware Config1 R Preset by R Preset by R Preset by Write Reset State Compliance Read/ codings for the number of se for the codings having MT register is 9.47 Configuration Register 1 er Field Descriptions er Field Descriptions Table 9.68the describes Config2 register Config Config2 register and encodes additional capabilitiesinformation. All fields in Meaning register; register is not implemented, Config Description Config1 Config2 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 263 Figure 9.50Figure Format Register Config1 Table 9.68Table Regist Config1 064 1128 2256 3512 45 1024 6 2048 732 4096 ere is no cache implemented. Encoding

Required.

implemented, this bit should read as a 1. read as this bit should implemented, this bit should read as a 0. If the the If 0. a as read should bit this is present. If the If the is present.

a value of ‘none’. a value of through 63 through in this field correspond to 1 to 64 TLB value zero is entries. The implied by 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0 register is an adjunct to the shows the format of the shows register are read-only. register are 30..25 values 0 one. The minus in the TLB entries Number of Config1 Cache Size = Associativity * Line Size * Sets Per Way Sets * Line Size * = Associativity Size Cache Config1 Fields M 31 a that to indicate is This bit reserved IS 24:22 I=cache sets per way: MMMU Size - 1 - IS IL IA DS DL DAC2MDPCWRCAEPFP Size MMMU 31 30 the The I-Cache and D-Cache configuration parameters include en and the associativity. The total cache size for a cache is therefore: cache size for total The associativity. and the If the line size is zero, th is zero, size the line If Figure 9.50 Compliance Level: The MMU Name Bits Size - 1

9.47 1) 16, Select (CP0 Register 1 Register Configuration MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Required Required hardware hardware hardware ged Resource Architecture, Rev. 6.03 R Preset by R Preset by R Preset by Write Reset State Compliance Read/ Meaning Meaning Meaning Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 012-way Direct mapped 23-way 34-way 45-way 56-way 67-way 78-way 064 1128 2256 3512 45 1024 6 2048 732 4096 14 bytes 0 bytes 14 I-Cache No present 28 34 bytes 16 5 bytes 32 6 bytes 64 7 bytes 128 Reserved Encoding Encoding Encoding

Table 9.68Table (Continued) Descriptions Field Register Config1 Fields IL 21:19 I-cache line size: IA 18:16associativity: I-cache DS 15:13 D-cache sets per way: Name Bits 264Vo For Programmers Architecture MIPS®

Required Required Required Required (CP0 Register 16, Select 1) hardware hardware hardware hardware R Preset by R Preset by R Preset by R Preset by Write Reset State Compliance Read/ 9.47 Configuration Register 1 Module is implemented. at the processor contains at the contains processor at the contains processor Meaning Meaning Meaning Meaning Release Release 5 and cannot be Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 265 01MDMX No ASE implemented MDMX ASE implemented 012-way Direct mapped 23-way 34-way 45-way 56-way 67-way 78-way 01coprocessor No 2 implemented Coprocessor 2 implements 14 bytes 0 bytes 14 D-Cache No present 28 34 bytes 16 5 bytes 32 6 bytes 64 7 bytes 128 Reserved Encoding Encoding Encoding Encoding

This bit indicates not only th This bit indicates not only th a coprocessor such but that 2, support for Coprocessor is attached. support for MDMX, but that such a processing ele- attached. is ment MDMX is deprecated in implemented when the MSA

Table 9.68Table (Continued) Descriptions Field Register Config1 Fields C2 6 2 implemented: Coprocessor DL 12:10 size: line D-cache DA 9:7 associativity: D-cache MD 5 ASE implemented: MDMX Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Required Required Required Required hardware hardware hardware hardware hardware ged Resource Architecture, Rev. 6.03 R Preset by R Preset by R Preset by R Preset by R Preset by Write Reset State Compliance Read/ CP1 FIR at the processor contains at the contains processor Meaning Meaning Meaning Meaning Meaning Description registers registers implemented lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: No performanceNo counter registers implemented Watch registers implemented: 01 implemented watch registers No 01implemented not MIPS16e implemented MIPS16e 01 implemented EJTAG No implemented EJTAG 01 FPU No implemented FPU implemented 0 1 Performance counter registers implemented Encoding Encoding Encoding Encoding Encoding

This bit indicates not only th unit is but that such a support for a floating-point unit, attached. of the FPU capabilities the FPU is implemented, If an bits in the capability from the be read can

Watch register. Table 9.68Table (Continued) Descriptions Field Register Config1 Fields FP 0 FPU implemented: EP 1 implemented: EJTAG PC 4 implemented: registers Counter Performance CA 2 Code compression (MIPS16e) implemented: WR 3 Name Bits 266Vo For Programmers Architecture MIPS®

0 Optional Required Required 4 3 register is required; (CP0 Register 16, Select 2) State Compliance Reset register fields. hardware hardware hardware Config3

. 8 7 L2C Config2 R Presetby R Preset by R/W Preset by Write Read / Config5 12 11 describes the describes is implemented, or if the or is implemented, 9.48 Configuration Register 2 er Field Descriptions er Field Descriptions 4 is dependent on Table 9.69 implemented, this 128 256 512 register is imple- Config3 register is 1024 2048 4096 8192 16 15 Reserved Config2 Config3 iary cache control or status or status control cache iary register; emented it should read as zero Description 20 19 Config2 06 1 2 3 4 5 6 7 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 267 8-15 ts per way: Figure 9.51Figure Format Register Config2 Config3is not register Encoding Per Way Sets if a level 2 or level 3 cache or level 2 a level if Table 9.69Table Regist Config2 24 23 Required

mented, this bit should read as a 1. should mented, this bit bit should read as a 0. If the the read as a 0. If should bit present. If the bits. If this field is not impl write. ignored on and be register encodes level 2 and level 3 cache configurations. level 3 cache and 2 register encodes level shows the format of the shows otherwise. In Release 6, presence of presence 6, Release In otherwise. Config2 Fields M 31 a that to indicate is This bit reserved The Compliance Level: Optional Figure 9.51 Figure

TS 27:24 cache se Tertiary TU 30:28 tert Implementation-specific Name Bits 31 30 28 27 MTU TS TL TA SU SS SL SA 9.48 2) 16, Select (CP0 Register 2 Register Configuration MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Optional Required Required Required State Compliance Reset Preset by hardware hardware hardware hardware ged Resource Architecture, Rev. 6.03 R R Preset by R Preset by R/W Preset by Write Read / 6 2 4 128 128 256 Reserved emented it should read as zero Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: ts per way: way: per ts 064 1 012 23 34 Mapped Direct 45 56 67 78 23456 256 7 512 1024 2048 4096 8192 014 28 No cachepresent 31 43 56 6 7 8-15 Reserved 8-15 Reserved 8-15 Encoding Per Way Sets Encoding Associativity Encoding Size Line Table 9.69Table (Continued) Descriptions Field Register Config2 bits. If this field is not impl write. ignored on and be Fields SS 11:8se Secondary cache TL 23:20 size: cache line Tertiary TA 19:16cache associativity: Tertiary SU 15:12 or status cache control secondary Implementation-specific Name Bits 268Vo For Programmers Architecture MIPS®

Required Required by (CP0 Register 16, Select 2) State Compliance Reset Preset by hardware hardware R Write Read / 9.48 Configuration Register 2 6 2 4 128 256 Reserved Description ciativity: R Preset 012 23 34 Mapped Direct 45 56 67 78 014 28 No cachepresent 31 43 56 6 7 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 269 8-15 Reserved 8-15 Encoding Associativity Encoding Size Line Table 9.69Table (Continued) Descriptions Field Register Config2 Fields SL 7:4 Secondary cache line size: SA 3:0asso cache Secondary Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 270Vo For Programmers Architecture MIPS®

MT SM TL Required Required M M CD SP t I n V I E C V ware ware (CP0 Register 16, Select 3) P L A register fields. register I T L T T C C X Config3 register are read-only. S P P D Rhard- by Preset Rhard- by Preset 2 S P P D Config3 I R X describes the I L R U otherwise. 9.49 Configuration Register 3 ISA Table 9.70 Table Optional On Exc ISA implemented, this Config4is register o n u C M register; Meaning Config4 register is imple- Config3 MMAR me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 271 Description Read/Write Reset State Compliance Figure9-52 Config3 Register Format if any optional feature described by this register is implemented: 2Release of the PageMask register is 32bits wide. is 64bits wide. Mask register Register is 64-bits wide. wide. is 64-bits Register IPLW PS™ ASE, or trace logic; logic; or trace PS™ ASE, register is not is not Config4 register Z V Table 9.70Table Descriptions Field Config3 Register Required

01 implemented and not Big Pages are implemented and Page- Big Pages are PW S C Encoding TLB pages larger than 256 MB are supported, and that MB are 256 than larger pages TLB C0_PageMask bit shouldbit read as a 0. If the as a 1. read should mented, this bit present. If the If the present. register encodes additional capabilities.fieldsthe in All I shows the of format the B P B Config3 S P A M Figure 9-52 Compliance Level: the SmartMI Architecture, The

C R G CM Fields M 31 a that to indicate bit is reserved This P B G BPG 30 that indicates bit This is implemented. Big Pages feature Name Bits 313029282726252423222120191817161514131211109876543210 M 9.49 3) 16, Select (CP0 Register 3 Register Configuration MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

tiple -Core Required Required Required Required Manager. implementa- Required for for Required tions that use the Coherency the Coherency Coherent Mul- Coherent 1 1 ware ware ware ware ware (Release 6) (Release (Release 6) (Release (Pre-Release 6) (Pre-Release 6) ged Resource Architecture, Rev. 6.03 Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset , SegCtl0 is implemented. This bit indicates indicates bit This implemented Meaning Meaning Meaning Meaning Meaning ted. This bit indicates indicates bit This ted. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: register not implemented register implemented is always imple- always BadInstrP is are present. present. are Description Read/Write Reset State Compliance is always implemented. BadInstr BadInstr register not implemented register not BadInstrP BadInstrP register implemented SegCtl2 register implemented. BadInstr register implemented. This bit indicates indicates bit This implemented. register and 1 0 01 not implemented Control Segment implemented is Control Segment 01 MSA Module not implemented is Module MSA 0 1 01 CM GCR space is not implemented implemented is GCR space CM Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding ion RegisterSpaceion is implemented. Encoding whether the Segment Control registers Segment Control whether the BadInstrP regis- instruction word branch prior faulting whether the 6: Release is present. ter mented. BadInstr present. is register word instruction faulting whether the 6: Release rat SegCtl1 Fields BI 26 SC 25 Segment Control implemen BP 27 MSAP 28 MIPS SIMD Architecture (MSA) Name Bits CMGCR 29 Configu- memory-mapped Global Manager Coherency 272Vo For Programmers Architecture MIPS®

Required Required Required if Required if implemented implemented MCU ASE is microMIPS is ware ware ware ware (CP0 Register 16, Select 3) Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset 9.49 Configuration Register 3 This bit indi- fields: are present. RIPL gnificant bit and second Meaning fields are 6-bits in fields are 8-bits in Meaning Meaning Module not imple- Module Meaning ented. This bit indicates ented. This bit level is denoted by the is denoted by level dth, bits 18 and 16 of 16 and bits 18 dth, implemented. is zero, microMIPS64 is not is microMIPS64 is zero, Module is implemented. RIPL RIPL PWSize Cause me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 273 Description Read/Write Reset State Compliance and and and and

and and itecture revision level. itecture revision . t, respectively, of that field. field. that of respectively, t, t, respectively, of that field. field. that of respectively, t, Config3 IPL width. IPL width. IPL mented Config field is 8-bits in width, bits 17 and 16 of PWField field of field is 8-bits in wi field is , Status are and second used bit as the most-significant 0 Release3 01 not implemented Walking Table Page is implemented Walking Table Page 0 1 1 implemented is Module Virtualization 0 Virtualization are used as the most-si as are used

1-7 Reserved IPL RIPL ISA Others Reserved. field of Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding most-significant bi If the the If Status most-significant bi the If Table Walking registers Walking cates whetherPage the Table PWBase Cause MIPS64 Architecture revision AR the If implemented and this field is not used. whether the Virtualization Virtualization whether the Fields VZ 23 Module implem Virtualization PW 24 Walk Page Table HardWare IPLW 22:21 of Width Name Bits MMAR 20:18 microMIPS64 Arch MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Required if Required if implemented implemented implemented MCU ASE is microMIPS is microMIPS is 1 ware ware ware Undefined Required if (Release 6) (Release Preset by hard- by Preset (Pre-Release 6) ged Resource Architecture, Rev. 6.03 R Rhard- by Preset mented. mented. are imple- RW if both if RW if only micro- mented; Preset instruction sets sets instruction MIPS is imple- MIPS is is always is ion Set is imple- ion Set is implemented. Coprocessor 0 reg- UserLocal Meaning Meaning Meaning Meaning register is not imple- is not register is implemented register cts all exceptions whose off- exceptions cts all lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: . UserLocal t Availability. R Preset by hard- Description Read/Write Reset State Compliance UserLocal mented UserLocal exception vector. exception vector. exception vector. mented. are implemented. MIPS64 ISA used of reset. when coming out are implemented. microMIPS64 ISA of reset. used when coming out register UserLocal register implemented. This 0 1 01 ASE MCU not implemented. is ASE is implemented MCU 01 MIPS64 is used on entrance to an entranceis used on to an microMIPS 0 MIPS64 Instruct Only 1 microMIPS64 Only 2 ISAs and microMIPS64 Both MIPS64 3 ISAs and microMIPS64 Both MIPS64 Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding implemented. bit indicates whether the the whether indicates bit ister is implemented. Release 6: toring to an Affe toring to an exception. setsrelative are to EBase 16 vec- after used Architecture Set the Instruction Reflects Fields ISA 15:14Se Instruction Indicates MCU 17ASEimplemented. is MCU MIPS® ULRI 13 Pre-Release 6: Name Bits ISAOnExc 274Vo For Programmers Architecture MIPS®

Required Required Required Required 1 ware ware ware ware (CP0 Register 16, Select 3) (Release 6) (Release (Pre-Release 6) Rhard- by Preset Rhard- by Preset Rhard- by Preset Rhard- by Preset

RIE bits 9.49 Configuration Register 3 regis- regis- XIE registers are

RIE and XContextConfig register depends on XContextConfig PageGrain PageGrain fields. register and register

bits are not imple- bits are imple- and and and and Meaning Meaning Meaning Meaning XIE XIE ented. This bit indicates ented. on 2 implemented. This bit 2 implemented. This bit on register. Release 6: The 6: The Release register. 2 of the MIPS DSP Module dule is implemented. implemented. is dule XConfig BadVPN2 BadVPN2 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 275 Description Read/Write Reset State Compliance RIE and RIE and XContextConfig

ContextConfig register respectively. respectively. register ContextConfig the for implemented and is used are Config are not implemented. ContextConfig mented within the mented within the is not implemented is implemented ter. ter. ter. XConfig ndicates whether the and PageGrain I bits are always implemented 1 0 0 The 1 The 01 Revision 2 of the MIPS DSP Module Revision 2 of the MIPS DSP Module 01 MIPS DSP is implemented Module not MIPS DSP Module is implemented XIE Config register and the Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding the contents of the contents the XContextConfig . ContextConfig the BadVPN2 field within BadVPN2 field implemented and the width of the the whether the MIPS DSP Mo exist within the the within exist and indicates whether Revision is implemented. Fields RXI 12 6: Pre-Release DSPP 10implem DSP Module MIPS® Name Bits DSP2P 11Revisi DSP Module MIPS® CTXTC 9 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Only) Only) Required Required Required Required (Release 2 (Release 2) (Release 2.1 (Release ware ware ware ged Resource Architecture, Rev. 6.03 Rhard- by Preset Rhard- by Preset Rhard- by Preset to support to support ted, and the ted, and the EntryLo1 Meaning Meaning Meaning fieldsand associated con- ase 1 of the Architecture, 1 of the Architecture, ase ase 1 of the Architecture, 1 of the Architecture, ase port is implemen lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: terrupt controller is imple- terrupt controller is Description Read/Write Reset State Compliance mechanism implemented. This bit bit This implemented. mechanism EntryLo0 and ™ implemented implemented implemented implemented register exists. register MVH lowtrace 01 is not EIC interrupt mode for Support is EIC interrupt mode for Support 01implemented not is IFlowTrace MIPS implemented is IFlowTrace MIPS 01 physical is not address support Large is support physical address Large Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding physical addresses larger than 36 bits. addresses physical larger • • PageGrain • Config5 The following Coprocessor 0 aretrol present if this bit1: is a • to Modifications PageGrain For implementations of For implementations Rele read. on returns zero this bit contains processor This bit indicates not only that the such that but controller, an external interrupt for support attached. is controller a For implementations of For implementations Rele read. on returns zero this bit mented. MIPS® IF indicates whether is implemented. the MIPS IFlowTrace Fields ITL 8 LPA 7sup Physical Address Large VEIC 6in an external for Support Name Bits 276Vo For Programmers Architecture MIPS®

Only) Only) Required Required Required Required Required Required Required Reserved (Release 2 (Release 2 (Release 6) (Pre-Release 6) (Pre-Release 0 ware ware ware ware ware (CP0 Register 16, Select 3) (Release 6) (Release (Pre-Release 6) Rhard- by Preset Rhard- by Preset Rhard- by Preset R Rhard- by Preset Rhard- by Preset 9.49 Configuration Register 3 t indicates t indicates t is implemented Meaning ted. This bit ted. indicates Meaning Meaning Meaning Meaning ted. This bi This ted. ase 1 of the Architecture, 1 of the Architecture, ase ase 1 of the Architecture, 1 of the Architecture, ase t is implemented, and the is t this bit must be 0. be this bit must me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 277 upts are implemented. r Description Read/Write Reset State Compliance mented register exists register 01 not implemented are interrupts Vector implemented are interrupts Vectored 01 Small page support is not imple- suppor page Small 01implemented is not ASE SmartMIPS is implemented ASE SmartMIPS 01not implemented CDMM is CDMM isimplemented 01implemented is not MT Module MIPS is implemented MT Module MIPS Encoding Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding Encoding Encoding Encoding whether the SmartMIPS ASE is implemented. For Release 6 and after, ReleaseFor 6 and after, whether the MIPS MT Module is implemented. indicates whether the CDMM is implemented. CDMM is implemented. whether the indicates PageGrain of For implementations Rele read. on returns zero this bit whether vectored inter For implementations of Rele For implementations read. on returns zero this bit Fields SP 4 suppor Small (1 kB) page SM 1ASE not implemented. SmartMIPS™ SM 1 ASE SmartMIPS™ implemen MT 2implemen Module MT MIPS® VInt 5implemented. interrupts This bit indicates Vectored Name Bits CDMM 3 bit This implemented. Map Memory Device Common MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required ware ged Resource Architecture, Rev. 6.03 Rhard- by Preset Meaning lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description Read/Write Reset State Compliance implemented. 01 is not implemented logic Trace implemented is logic Trace Table 9.70Table (Continued) Descriptions Field Register Config3 Encoding data trace is trace data or Fields TL 0 Logic implemented. This bit indicates whether PC Trace Name Bits 278Vo For Programmers Architecture MIPS®

and Required VTLBSizeExt (CP0 Register 16, Select 4) register fields. Config4 FTLBWays FTLBSets FTLBWays FTLBSets FTLBWays FTLBSets State Compliance Reset hardware Config4 FTLB PageSize R by Preset FTLB FTLB Definition Depends on MMUExtDef Depends on Definition PageSize PageSize Write Read / describes the describes 9.50 Configuration Register 4 er Field Descriptions er Field Descriptions register is ExtDef Table 9.71 161514131211109876543210 161514131211109876543210 register is imple- register Config5 register; in the VTLB is defined by concatenating VTLB is defined by concatenating in the FTLB = decode(FTLBSets) * decode(FTLBWays). = FTLB decode(FTLBSets) Config5 Config4 Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 279 if any optional feature described by this register is implemented: 2Release of the register is not implemented, this Config5 register is not implemented, this Table 9.71Table Regist Config4 Figure 9.54Figure 6) (Release Format Register Config4 Figure 9.53Figure 6) (Pre-Release Format Register Config4 otherwise. Required If MMUExtDef=3 0 If MMUExtDef=2 000 If MMUExtDef=1If MMUExtDef=0 000000 00000000000000 MMUSizeExt

. Modifying. can be used to allow VTLB size softwareinindex high to reserve the VTLB. slots present. If the bit should read as a 0. If the 0. If a as bit should read mented, this bit should read as a 1. a as read should bit this mented, Optional register encodes additional capabilities. shows the format of the shows MMUSize AE VTLBSizeExt KScrExist Reserved AE VTLBSizeExt KScrExist MMU Config4 Figure 9.54 Figure Config1 Compliance Level: Architecture; The number of page-pair entries within the page-pair entries within number of The The number of page-pair entries accessible page-pair entries accessible number of The

The Fields 109872423 3130292827 109872423 3130292827 MIE MIE M 31a that is reserved to indicate bit This Name Bits 9.50 4) 16, Select (CP0 Register 4 Register Configuration MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

=3 =1 or MT =1 or 4 MT Config MMUExtDef Required EHINV (Release 6) (Release Required if Required if Required if (Pre-Release 6) Config Config4 These features must be must features These implemented if Segmenta- tion Control is imple- mented. recom- are features These FTLB/VTLB mended for MMUs. Always Required for implementations with i.e., TLBs; Required for TLBINV, Required for TLBINV, TLBINVF, EntryHi 4. (Release 6) 4. (Release State Compliance Reset hardware hardware hardware ged Resource Architecture, Rev. 6.03 R by Preset R by Preset Write Read /

. EHINV MMUSize = 3, this field is con- = 3, this field is extended to 10 bits. 10 to is extended R by Preset supported. Refer to Refer to Vol- supported. supported. Refer to Refer to Vol- supported. Meaning concatenatedtheto left of Config1 ASID support/configuration. MMUExtDef MT = 1 or 4; otherwise, EHINV EHINV lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description ction EntryHI field to indicate the size of the VTLB. the of size the to indicate field

not supported supported by hardware. In Release not TLBINV i.e., is this field reserved; 6, and TLBINVF must be supported in implementations. Release 6 EntryHi ume II for the of full description these instructions. on instructions operate TLBINV* entire MMU. ume II for the of full description these instructions. on one instructions operate TLBINV* TLB entry. EntryHi Config4 MMUSize 11 TLBINVF supported. TLBINV, 00 EntryHi TLBINVF, TLBINV, 0110 Reserved. TLBINVF supported. TLBINV, Table 9.71Table (Continued) Descriptions Field Register Config4 Encoding catenated to the left of the most-significant bit of the of the bit most-significant the of to the left catenated Config1 Release 6: This field is always of the bit most-significant the

reserved. If 6: Pre-Release 27:24Config Applicable only if Fields IE 30:29 TLB invalidate instru AE 28 If this bit is set, then Name Bits VTLB- SizeExt 280Vo For Programmers Architecture MIPS®

Required Reserved (Release 6) (Release (Pre-Release 6) Registers are are available Registers Required if Kernel Scratch if Required (CP0 Register 16, Select 4) State Compliance Reset hardware hardware hardware R by Preset R Preset by R by Preset Write Read / -6

9.50 Configuration Register 4 DESAVE KScratch1 Meaning her purposes are not repre- her purposes for Coproecessor0 Register for Coproecessor0 Register 31. Bit 23 represents Select 7. 7. Select represents 23 Bit r kernel-mode software. r kernel-mode in COP0 Register 31. 17 is preset to zero. is preset 17 Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 281 scratch registers are availabletoker- Config4[12:0] - Must be written as - Must Config4[12:0] read. zeros on returns zeros, used as FTLBWays. Config4[7:4] used as FTLBPageSize. Config4[10:8] used as FTLBSets. Config4[3:0] used as FTLBWays. Config4[7:4] used as FTLBPageSize. Config4[12:8] as VTLBSizeExt. used Config4[27:24] [13:0] is to be interpreted. is to be interpreted. Config4[13:0] 0 Reserved. 12 used as MMUSizeExt. Config4[7:0] used as FTLBSets. Config4[3:0] 3 and VTLB FTLB supported. Table 9.71Table (Continued) Descriptions Field Register Config4 Encoding nel-mode software with nel-mode software select a represents bit Each 0, represents Select Bit 16 is imple- register scratch is the If the associated bit set, fo mented and available For Release 6, bits 2-7 are 1 because always must be implemented. must ot for Scratch registers meant imple- is if EJTAG example, For field. in this sented though zero even to preset is mented, Bit 16 register is implemented at Select 0. Select 1 is reserved for for is reserved 1 Select 0. Select at implemented is register not be used as a kernel future debug purposes and should bit so scratch register, Defines how 23:16 Indicates how many 15:14 Release In these 6, bitsreserved. are 15:14 MMU Extension Definition. Fields st Ext Ext Def Def KScr Exi MMU MMU Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Def=2 (Pre-Release 6) Required if MMUExt- cific State Compliance Reset Preset by by Preset hardware, tation spe- ged Resource Architecture, Rev. 6.03 chosen value is implemen- one page- RW if FTLB FTLB FTLB FTLB Write imple- mented Read / mented. mented. multiple multiple sizes are is imple- R if only page size B B B B B k G G k k 6 5 64 kB 16 kB Reserved implement implement any subset of ted, the register field value ze is implemented by writing implemented by ze is only one pagesize. Software only one updated to the desired encod- lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Description 14 2 3 42 51 64 7 01 Encoding Size Page UNDEFINED if therevalid areFTLB entries Table 9.71Table (Continued) Descriptions Field Register Config4 Implementations are allowed to thesesizes, even a subset of can detect si if a FTLB page imple- is size the If field. this register into desired size the mented, register field is the is not implemen size If ing. the is not changed. of any valid entries this The FTLB must be flushed before The FTLB software. by changed register field value is behavior is page programmed using a common not all which were size. 10:8 Entries. Array FTLB Indicates the of the Page Size Fields Size FTLB Name Bits Page 282Vo For Programmers Architecture MIPS®

= 4 MT Config Def=3 (Release 6) (Release (Pre-Release 6) Required if MMUExt- Required if Required (CP0 Register 16, Select 4) cific State Compliance Reset Preset by by Preset hardware, tation spe- chosen value is implemen- one page- FTLB FTLB FTLB FTLB Write imple- R/W if R/W if mented Read / mented. mented. multiple multiple sizes are is imple- R if only page size 9.50 Configuration Register 4 size. Software B B B B B B B k M M k k 6 M M 6 4 1 TB 4 TB 1 GB 4 GB 5 64 kB 16 TB 16 TB 64 16 GB 64 GB 16 kB 256 TB 256 GB 256 256 MB implement implement any subset of ted, the register field value only one page only one updated to the desired encod- Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 283 14 2 3 42 51 86 9 01 64 71 11 10 12 13 14 15 16 17 18 19 Encoding Size Page UNDEFINED if therevalid areFTLB entries Table 9.71Table (Continued) Descriptions Field Register Config4 can detect if an size is FTLB page by writing implemented imple- is size the If field. this register into desired size the mented, register field is the is not implemen size If ing. the is not changed. of any valid entries The FTLB must be flushed this before The FTLB software. by changed register field value is behavior is page programmed using a common not all which were size. Implementations are allowed to thesesizes, even a subset of 12:8 Entries. Array FTLB Indicates the of the Page Size Fields Size FTLB Name Bits Page MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

=2 =4 =4 MT MT ExtDef Config Config MMU Def=2 Def=1 (Release 6) (Release (Release 6) (Release (Pre-Release 6) (Pre-Release 6) (Pre-Release 6) Required if MMUExt- Required if MMUExt- Required if Required if if Required Required if Required if State Compliance Reset hardware hardware hardware ged Resource Architecture, Rev. 6.03 R by Preset R by Preset R by Preset Write Read / field to indicate the size of the field to indicate the size of the lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: = 1 then this field is an extension of extension is an this field = 1 then Description field. field. 02 13 24 35 46 57 68 7-15 Reserved MMUSize-1 01 12 24 38 416 532 664 7128 8256 9512 Encoding Associativity 11 2048 1012131415 1024 4096 8192 16384 32768 MMUExtDef MMUSize-1 Encoding per Way Sets Table 9.71Table (Continued) Descriptions Field Register Config4 Config4 This field is concatenated to the left of the most-signifi- the of left the to concatenated is field This cant bit to the Config1 Array. Array. TLB-1. 7:0 If 7:4 Array. FTLB the of Associativity Set the Indicates 3:0 within the FTLB the Indicates of Sets per number Way Fields ys Sets Wa FTLB FTLB Name Bits MMU- SizeExt 284Vo For Programmers Architecture MIPS®

(CP0 Register 16, Select 5) register fields. ). ). Config5 ). ). XNP). L2C UFR UFE LLB / ). ). ). FRE VP describes the describes SBRI ). DEC). NestedEPC , MHV 9.51 Configuration Register 5 ). Table 9.72 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XNP 0 DEC L2C UFE FRE VP SBRI MVH LLB MRP UFR 0 NFExists MRP NestedExc ( register; cache configurations) in COP0 ( configurations) cache MAARI ns ns (for example, LBE). Config5 and 0 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 285 Figure 9.55Figure Format Register Config5 vector control. vector if any optional feature described by this register is implemented: 3Release of the MAAR s additional capabilities: s additional capabilities: otherwise. Required

Optional shows the format of the the shows • Existence of Config2 (L2 and L3 • Existence of COP0 • control Kernel over non-kernelexecution ( of SDBBP • Support for additional LL/SCinstruction handling capabilities ( • 6 LLX/SCX familyofRelease instructions presence of Determine ( •( feature of the Nested Fault Existence • Support for COP0 capabilitiesmulti-threadingtorelated ( • Support for trap and emulatefloating-point capabilityfor ( • Existenceof MTHC0 and MFHC0 instructions ( • Support for software reset-based Endian switching ( • Cache Error exception •legacy compatibility. Control Segmentation • instructio of EVA Existence • Existenceof the User ModeFP Register mode-changing facility( Figure 9.55 Figure Compliance Level: Architecture;

The Config5 register encode M K CV EVA MSAEn 31 30 29 28 27 26 9.51 5) 16, Select (CP0 Register 5 Register Configuration MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

) ) 4.1.5 4.1.5 mented. Control. Control. Optional is imple- Required on page 28 on page 28 Segmentation Segmentation Segmentation Segmentation MSA Module (Refer to (Refer to State Compliance Reset hardware hardware ged Resource Architecture, Rev. 6.03 R by Preset R/W 0 Required for R/W 0 Required for Write Read / dis- Cache K23 K23 K23 K23 K23 K23 er Field Descriptions er Field Descriptions value for bits Config Config yet undefined yet undefined con- Config forced to place place to forced Ku , Ku Ku , and registers are and registers are EBase Ku , Meaning Meaning Meaning control. Disables forc- logic t. With the current architec- the current With t. if is Control Segmentation =0. , Config cate that as , Config K0 should always read a 0. should always as read BEV K0 Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Config abled. enabled. Configk0, Config address bits 63..29 bits 63..29 address vector in kseg1. uses address full 63..29. disabled. Executing a MSA instruc- disabled. Executing tion causes a MSA Disabled excep- tion. enabled. Config 1 Table 9.72Table Regist Config5 0 1 0vector exception, Cache Error On 1vector exception, Cache Error On 1 instructions MSA 0 instructions MSA Encoding Encoding Encoding Coherency Attribute control control Coherency Attribute implemented. ing use of kseg1 region in the event of a Cache Error exception when Status figuration registers are figuration presen tural definition, this bit definition, this bit tural Fields 0 26:13 Returns on read.zeros R0 0 Reserved K 30 Enable/disable M 31indi reserved to bit is This CV 29 Vector Exception Error Cache EVA 28 implemented Addressing instructions Enhanced Virtual R Preset by Name Bits MSAEn 27 (MSA) Enable. Architecture SIMD MIPS R/W 0 if Required 286Vo For Programmers Architecture MIPS®

Required Required Required Required Required (Release 6) (Release 6) (Release 6) 0 Reserved State Compliance (CP0 Register 16, Select 5) Reset hardware hardware hardware R by Preset R by Preset R by Preset R0 Write Read / . BE 9.51 Configuration Register 5 Config mode supported. mode supported. Big-Endian modes support. This support is support. an mode by setting a bit in bit a setting by mode an bility of legacy LL/SC LL/SC of legacy bility Meaning Meaning Meaning ructions is required for ructions is required for on subsequent reset. For cur- bility of processor. bility of processor. Description me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 287 software should read Config2 to determine L2/L3 cache configuration. software that register mapped memory can read instead. supported. Any implementation must support Lit- Any implementation tle-endian mode. ported ported 0 can Software Config2 present. read 1 Config2 not present. Replaced by 1 Both Little and 0sup- family instruction LLX/SCX 0 Little-Endian Only 1sup- not family instruction LLX/SCX ended LL/SC family of instructions Not Present. of instructions LL/SC family ended Encoding Encoding Encoding Table 9.72Table (Continued) Descriptions Field Register Config5 Ext state, endian rent instructions. instructions. The endian mode register. external a memory-mapped change will only take effect The LLX/SCX family of inst family of The LLX/SCX atomic Double-Width Release 6 provided by extending the capa capa endian Determines If both modes are supported, then the will processor ini- soft- Thereafter, always. mode in little-endian boot tially wareforce can a change in endi Fields 0 12read. on zero Returns L2C 10 Indicates presence of COP0 Config2. XNP 13 DEC 11 Endian Capability Dual Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

(Release 5) (Release 5) State Compliance Reset ged Resource Architecture, Rev. 6.03 R/W 0 Optional R/W 0 Optional Write Read /

=0. =0. FP FP FRE FRE =0. If Statu- . User mode . User FR =0 handling on =0 handling FRE FR using CTC1 and using CTC1 and using CFC1. using is 0 or Config1 is 0

ion FP arithmetic is 0, or Config1 dditional exception FRE =1 when the MSA Module MSA Module =1 when the Meaning Meaning FREP are removed in Release 6. FREP using CTC1 and CFC1 (only) FR causes a Reserved Reserved a causes E always equals 0. E FRE FRE FRE Description onfig5 using MTC0/MFC0. to 1. User mode hardwired can con- lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: FR tions. tions. instructions. - All SWC1/SWXC1/MFC1 instruc- - All SWC1/SWXC1/MFC1 - All LWC1/LWXC1/MTC1 instruc- - All LWC1/LWXC1/MTC1 do not generate do not generate a conditions. exception: Reserved Instruction - All single-precis Instruction exception. Instruction read and CTC1, (only) using Config5 Config5 applies also to kernel use of CFC1/CTC1. use applies also to kernel is reserved if: FIR . is reserved if FIR FRE FRE UFE UFE 1 following instructions The cause a 1 to write Config5 is User allowed 0by Config5 impacted Instructions 0attempt An by user to read/write =0, then effective FR Encoding Encoding Table 9.72Table (Continued) Descriptions Field Register Config5 UFE s A kernelaccess can C Config5 CFC1 instructions. CFC1 instructions. instructions. Release 5 requires that Status ReleaseCOP1 branches by are 5 and 6 not affected Config5 instructions LWXC1/SWXC1 Config5 an FPU with Status ditionally access Config5 Config5 is enabled. Release 6 eliminates the Status can conditionally access Config5 can conditionally Fields FRE 8 Enableemulateto for user mode Status UFE 9Config5 to access user mode Enable for Name Bits 288Vo For Programmers Architecture MIPS®

XPA Optional (Release 5) (Release 6) (Release 6) Required for for Required State Compliance (CP0 Register 16, Select 5) Reset hardware hardware R by Preset R by Preset R/W 0 Required Write Read / 9.51 Configuration Register 5 r pre-Release 6. r pre-Release ode. User (or super- User (or ode. Meaning on. It prevents user (and It prevents user on. Meaning Meaning is bit determines is bit determines if multi- to restrict availability of to restrict Release 6 implementation. is reserved fo tering Debug mode using tering ons are only required for only required ons are Description must must be 0 for Release 6 and after. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 289 MT ported. COP0 extensions do exist. not to 32-bit COP0 registers Extensions exist. visor, if supported) if supported) execution of visor, SDBBP will cause a Reserved Instruc- tion exception. defined to Release prior 6 m kernel in cuted only one virtual core/physical core. core/physical only one virtual There are no or ISA extensions COP0 for multi-threading. This includes CP0 Global Number register = 3, sel (reg = 1), instructions changes to EBASE to sup- DVP/EVP, core numbering. port virtual Config3 01 and MFHC0 are not sup- MTHC0 and MFHC0 are supported. MTHC0 01 as executes instruction SDBBP instruction can be exe- SDBBP only 0 multi-threading support. There is No 1 features supported. Multi-threading Encoding Encoding Encoding Table 9.72Table (Continued) Descriptions Field Register Config5 tions are implemented. are tions instructi these Currently Extended Physical (XPA). Addressing supervisor) code from en supervisor) code from The of purpose this field is operati mode to kernel SDBBP SDBBP. The new Release 6 multi-threading features replace the the replace features multi-threading 6 Release new The Module. existing Multi-threading Note that The value of this bit must be the same for all virtual pro- virtual all for same the be must bit of this value The cessors in a physical core. Th threading is supported in a Fields VP 7 bit This Processor. Virtual SBRI 6 Instruction control. Reserved instruction SDBBP MVH 5 High COP0 (MTHC0/MFHC0) instruc- Move To/From Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Required Reserved Reserved MAAR(I) MAAR(I) LLAddr is (Release 5) (Release 6) if Required (Release 5) Required if Required Optional in Optional (Release 5) (Release 6) Nested Fault implemented implemented implemented implemented feature exists. feature is set. Otherwise Otherwise is set. UFRP 1 0 0 State Compliance Reset FIR Preset by by Preset hardware hardware =1 2 ged Resource Architecture, Rev. 6.03 accessed unmapped. R by Preset R R R R Preset Required if the UFRP Write else 0 else R/W if Read / FIR eld determines the CCA of a segment when

. r using MAAR FR when the region is LLAdd =1. VZ Status present. not present. below shows which fi below

is mandatory. =1 are recommended if =1 are recommended LLB

Config3 Meaning Meaning Meaning MAARI MAARI LLB [0]. Table 9.72 llows recognition of faulting recognition of faulting llows is read-only 1. is read-only is software accessible through accessible through is software LLAddr and and Description LLB lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Config5 LLbit LLAddr fied. Software Software may program these registers to fetch/ attributes additional to apply to memory/IO access load/store address ranges. MAAR MAAR pre-Release 5 LL/SC compatible. • added. ERETNC instruction •CP0 • •modi- behavior is instruction SC Config5 , are , are present. 1 0 01 No new added. Hardware is support exists: support Additional 01 allowed. not FR instructions User-mode FR instructions allowed. User-mode MAARI Encoding Encoding =1, with/without a TLB, on implementations Encoding Table 9.72Table (Continued) Descriptions Field Register Config5 K and and Virtualization is supported, i.e., supported, is Virtualization CTC1 and CFC1 instructions. instructions. and CFC1 CTC1 Features enabled by 6, In Release The Nested Fault feature a within an exception behavior handler. , Segment CCA determination: K Config5 0 Indicates that the Nested Fault feature exists. is0. is R/W if an FPU is present, and if the User-mode FR changing feature is present, if i.e. present, is feature FR changing User-mode the and if is if an FPU present, R/W is =0 or Config5 UFR UFR K Fields NF LLB 4COP0 in is present (LLB) Bit Load-Linked UFR 2 to access user-mode allows feature This MRP 3Accessibility COP0 MemoryRegisters, Attribute Exists Name Bits Config5 Config5 Config5 1. Note on 2. 290Vo For Programmers Architecture MIPS®

(CP0 Register 16, Select 5) =1 C0 C1 C2 C3 C4 C5 K

SegCtl0 SegCtl1 SegCtl1 SegCtl2 SegCtl2 SegCtl0 1 1 1 1 =0 Config5 C2 ementations containing a ementations containing K K0 Config SegCtl1 Undefined Undefined Undefined Undefined 9.51 Configuration Register 5 Segment CCA Determination Segment =1 if it is programming any of these segments to =1 if it is programming any of these segments K K plementation containing a TLB. containing plementation =0 Config5 C2 K K0 KU KU K23 K23 ese regions is mapped on impl No TLB With TLB Config Config Config Config Config SegCtl1 Config5 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 291 Table 9.73Table SegCtl0 1 2 3 4 5 0 Segment TLB. Software must set Config5 TLB. Software be used as unmapped on an im 1. of th state Reset Note: MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 292Vo For Programmers Architecture MIPS®

defined by the architecture. defined registers are not needed for the registers are not Config3 plement CP0 register 16,plement CP0 register Selects 2 through 5 and Config2 tion-dependent use and is not P0 Register 16, Selects 6 and 7) 16, Selects P0 Register . bits for presence detection of Selects 1 to 5. 1 to of Selects presence detection bits for 9.52 ReservedImplementations for Register (CP0 16, 6 and Selects 7) sters. That is, if the sters. That is, me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 293 16, Selects 6 and 7, it is not necessary to im Implementation Dependent Implementation

bit in each of these regi these bit in each of M Compliance Level: CP0 register 16, Selects 6 and 7 are reserved for implementareserved Selects 6 and 7 are register 16, CP0 implementation, theyneed not be implemented just to provide bits. the M the use defines of the MThe architecture only only to set the In order to use CP0 register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.52 (C for Implementations Reserved ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 294Vo For Programmers Architecture MIPS®

0 LLB . 10 LLB in Release 6. nked instruction. nked instruction. Config5 Required register fields for register State Compliance Reset register fields. =1. LLAddr LLB LLAddr which is set when an LL instructionan LL set when is is which R Undefined Optional (pre Release 5) Config5 Write Read / describes the describes the the describes 9.53 Load Linked Address (CP0 Register 17, Select 0) in Release 5 if in Release is required. Table 9.74 stic purposes only, and serves no function duringnormal stic purposes only, Table 9.75 an implementation an implementation PAddr LLAddr Required PAddr The format of this regis- bits or format the address bits or register and register; of physical address read the by the most Li recent Load in Release 5 can be detected by software throughbedetectedsoftware by in Release 5 can e ability to read and clear the LLbit, the clear to read and e ability Description LLAddr LLAddr LLAddr me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 295 finds convenient. tion-dependent, and is read-only 1, and CP0and is read-only 1, Figure 9-56Figure 5) Release (pre Format Register LLAddr LLB prior to Release 5. OptionalRelease prior to

Figure 9-57Figure after) 5 and (Release Format LLAddr Register recent Load Linked instruction. is ter implementa may implement as many of the way that it any in Table 9.74Table Field Descriptions LLAddr Register Config5 contains relevant bits register shows the of format the shows the of format the LLAddr Fields 63 63 The Figure 9-56

Compliance Level: In Release In Release 6, pre-Release 5 implementations. Figure 9-57 This register is implementation-dependent,diagno is for operation. provides software with th also Release 5 of LLB in executed. The presence PAddr 63..0 most This encodes the address read by the field physical Name Bits 9.53 0) 17, Select (CP0 Register Address Load Linked MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

=1 LLB Required Required (Release 5) (Release 6) (Release 5) (Release 6) Config5 State Compliance Reset ged Resource Architecture, Rev. 6.03 R Undefined Optional R/W 0 if Required Write Read / . an implementation an implementation The format of this regis- bits or format the address bits or s bits is implementation- re cannot be set. but to be software accessible. accessible. to be software rdware events may clear LLB Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: finds convenient. tion-dependent, and is always 32-byte aligned. [1] is always aligned to PA[5], which implies implies which to PA[5], aligned is always [1] can be cleared by softwa is set when the LLD instruction is executed. The SC The executed. is instruction the LLD when is set PAddr specific. For the unimplemented address bits, writes are are writes bits, address unimplemented the For specific. zero. return and reads ignored The number of addres The number physical may implement as many of the may implement as many any way that it in LLAddr that recent Load Linked instruction. is ter implementa LLB This field allows the LLbit LLbit the allows field This LLB and other ha instructions Table 9.75 Table 5 and after) (Release Descriptions Field Register LLAddr Fields LLB 0 LLbit. PAddr 63..1 most This encodes the address read by the field physical Name Bits 296Vo For Programmers Architecture MIPS®

9.53 Load Linked Address (CP0 Register 17, Select 0) me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 297 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

MAAR =1, other- must be ini- be must ELPA result. Similarly, Similarly, result. MAARI and subsequent exe- and subsequent show the format of ease 5 feature. In a ease MAAR PageGrain urce Architecture, Revision urce MAARI feature to allow architectural may be composed of up to composed of up be may required. The presence and use use and presence required. The Figure 9-60 to1, thenthe access should not MAAR MAAR. and te, along with MAAR. An access with with An access te, along with MAAR. e for any region of the address space, the address e for any region of VH is effective if VH is effective . CP0 Register2). 17, Sel (XPA), a MIPS32 Rel (XPA), , is accessed with a COP0 move-to or with a COP0 move-to is accessed MRP the MMU yields a cacheable CCA, but a cacheable yields MMU the Figure 9-59 Index

de any equivalentde any attribute determined through other MAAR . speculate as determined by the as determined speculate itecture include the ftware. As described, software must set the logical valid Config5 placed between the write to cacheable CCA on the other hand is not allowed to spec- allowed the other hand is not on cacheable CCA register; MAAR MVH registers be paired, i.e., one specifiesi.e., registers be paired, an upper bounds of use MTHC0 to writeuse MTHC0 tothis bit. software 64-bit mustuse ( must be extended by additional physical address bits. To where the valid of each register two valid bits, VL and VH are . a attribute set yields speculate register fields. register fields. MAAR MAAR MAAR Config5 MAAR MAARI =1. In this circumstance, =1. In this defines whether a fetch MAAR instruction data load or can specula- MAAR MAAR, MAAR, MAAR cluded in Release 5 of the architecture that defines the accessibility attri- the accessibility defines that the architecture of cluded in Release 5 and MAAR MAAR MVH entations of the arch implementation todetermine speculation.stronglyIt is recommended that . An access with un ELPA may be used to specify an attribut may be used to Register 17, Select 1) 17, Select Register Register (CP0 ttribute lume III: MIPS64® / microMIPS64™ Privileged/ lume III: MIPS64® Reso requires that register number before the Config5 now defines whether the access can specula the access whether defines now MAAR ervative outcome. For example, if ervative outcome. For instruction is required to be instruction MAAR to 0, then the access should not the access to 0, then describes the PageGrain MAAR show the format of the format of the show or write that specifies is impacted by Extended Physical Addressing is impacted by Extended Physical Addressing

can be detectedsoftware through can be by Optional

Table 9.76 MAAR MAAR Figure 9-59 functiona valid yieldsit attribute, will overri only register is a read/write register in register read/write a is register

and register; register; must be implementedin conjunction with

MAAR MAAR MAAR butes of physical address regions. In particular, butesaddressIn particular, of physical regions. address bounds tively specifiedthe physical such a region within access by the If the of both bits is conditional on move-from instruction. An EHB a cacheable CCA is allowed to speculate cacheable CCA a the address range, andthe address the other the lower bound. wise it is reserved. When effective, 32-bit software must 32-bit Whenwise it is reserved. effective, DMTC0, though 32-bit software runningimplementation on a 64-bit use willMTHC0. that Release 5 It is recommended implem instead of implementation-dependent definition of speculation. The Release 5 specification of The presence of MAAR Both VL and VH will be present if means, means, if it provides a more Compliance Level: The Operation: pseudo-codeThe showsMAAR a 3-pair implementations follow this description to enable portable so a MAARpair, in the pair to enable register each to 1 of whether memory (DRAM)or memory-mapped I/O. The definition of the Figure 9.58 Figure maintain atomicitythe write of to an extended 32-bit implementation, if XPA is supported, then 32-bit implementation, if XPA yields a speculate attribute set yields a MMU CCA, but an uncacheable the yields if tialized with the appropriate cution of the COP0 read the COP0 cution of (UCA) is used. The final speculative attribute is a combination of the CCA attribute is and the uncacheable CCA=7 (UCA) is used. The final speculative ulate unless MAARas described above. The address range specified by a speculate. 5, the CCA of an access Release In 298Vo Architecture For MIPS® Programmers 6.03 9.54 A Accessibility Memory

) MVH region. For ) MVH MAAR MAAR ture, Revision 6.03 0 .  region must be must region MAAR Config5 or not MAAR address. A fetch or load is address. A fetch retire. For implementations Table 9.78 ELPA ster (CP0 Register 17, Select 1) or not Config5 range is valid,range hardware factors in . Software may . Software clear the logical region with speculationMAAR ELPA ant speculate attribute of each region ant speculate attribute d Resource Architec is a requirement. is a

S Table 9.77 Table index,shown in as MAAR issuing to IO addresses, with the tradeoff possiblyaddresses, issuing with to IO the tradeoff or not PageGrain or and MAARmatch g the oldest to instruction VH MAAR region to overlap a speculative CCA or not PageGrain [i] and MAAR or fetch access to memory and IO or fetch

VH MAAR eculation is allowed. (The state of MAAR is set to disallow specula- register with even register with (MAAR[i+1] ) // valids of both registers must be set to 1 be set must registers of both // valids ) V pports such overlays, then the result initializationpointanyatto occur of time withoutof the risk execution and 9.54 Memory Accessibility AttributeRegi VL and speculate and ate the whole MAAR pair. Once the address address the Once MAAR pair. ate the whole [i] and (MAAR MAAR  speculate me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me MAAR  1 tion,support and initialization of VL physical address of the access matches against a of the access physical address MAAR CCA [i+1] and MAAR V [i+1][35:12] <= PA_Align))// lower bound ; 40-bit PA. ; 40-bit bound lower PA_Align))// <= [i+1][35:12] (MAAR is to control speculation on load to control is = MAAR[i+1] V  1 speculate 0 0 // default is not to speculate is not to default  0 // = MAAR[i] = V MAARmatch  1 MAARmatch speculate speculate CCA MAAR instances are then no sp instances invalid, MAAR endif [i][35:12] >= PA_Align) && // upper bound ; 40-bit PA. bound ; // upper && >= PA_Align) if ((MAAR[i][35:12] overlap is allowed : This allows non-speculative region MAAR enables speculation, then accesses to addressesphysical outside this endif if (MAAR[i] [i+1] MAAR // Factor in valid(s) Factor in // [i] MAAR as defined has the following as defined properties: e.g., with this property, a non-speculative region can be overlayed on e.g., witha speculative thisDRAM property, region with the use of su If hardware two MAAR pairs. just and’ed. must be logically overlaps that non-speculative, unless the non-speculative, unless speculative (mispredictedfetches from loads branch or path) being lower performance. endfor speculate then occurs, MAAR match or no is valid, if no MAAR // speculate enabled. This access can then speculate. can then access This enabled. MAAR tion on reset.) This allowsThis tion the on reset.) speculate  speculate // Modify speculate attribute as per CCA of memory access (Release 5) (Release memory access of CCA as per attribute Modify speculate // UCA speculates CCA and 5: cached Release // == “uncached-accelerated(UCA)”)) or (CCA “cached”) ((CCA == if endif in MAAR Now factor //  MAARmatch speculate implementation-dependent. size is PA aligned; PA is 64KB of 40-bit Example //  PA[39:16] PA_Align 3 pairs // assume i=i+2) (i=0; i<6; for •If any any •If Programming Notes : Notes Programming The purpose of • two valids, a high and low. The logical valid two valids,is determined a highas given and in low. validofonepair of any the to invalid the speculateattribute of only the upper MAAR •If all MAAR bein its memory prior to if it accesses considered speculative all MAAR •If that support load or fetch specula MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 299

32 =1. 2 1 0 2 1 0 2 1 0 MVH is a 64-bit is register is a 64-bit is a register =0 =1 Config5 pair. , if MVH MVH MAAR urce Architecture, Revision urce MAAR VH 0SVL 0SVL 0SVL MAAR =0 =1 i.e., =1 i.e., 32

=0 i.e., ELPA MVH MVH is limited register. a 32-bit to =1 and Config5 =1 and Config5 R Config5 Config5 D MAAR D ELPA ELPA 12 12 12 ADDR regionMAAR become non-speculative. =1. This =1. This includes MAAR the attribute state of a state of the attribute compatibility, and thus thus and MFHC0, for 32-bit backward compatibility, =1 and =1 and =0 i.e., =0 i.e., ELPA ELPA ELPA ELPA 16 15 16 15 16 15 the upper valid bit is not present.bit the upper valid is not . Accesses to the to . Accesses PageGrain reprogramming VL PageGrain PageGrain PageGrain . 32-bitMAAR softwareMTC0, uses which initializeshalf thelower of MAAR when when when lume III: MIPS64® / microMIPS64™ Privileged/ lume III: MIPS64® Reso MAAR MAAR MAAR as needed. ADDR ADDR ADDR 55 55 ELPA Figure 9.58Figure if PageGrain Format Register MAAR along with other fields inalongfields with other

pair by clearing clearing by pair MAAR VL [63:32],MAAR whichis present if PageGrain shows the of format shows the of format 0 shows the format of . 64-bit. softwareinitialize uses DMTC0 to the entire MAAR. Figure 9-60Figure PageGrain if Format MAAR Register Figure 9-59Figure PageGrain if Format MAAR Register 0A MAAR MAAR • the Disable • Program the upper validis bit present. accessible not only by DMTC0 and DMFC0, but MTHC0 and but MTHC0 DMTC0 and DMFC0, only by not accessible •Set •Set Figure 9-59 Software must follow the described method for Figure 9.58 Figure Figure 9-60 accessible only by DMTC0 and DMFC0,accessible only by DMTC0 and and thus • Initialize 31 63 31 63 31 VH 300Vo Architecture For MIPS® Programmers 6.03

Reserved ture, Revision 6.03 0 or Required ster (CP0 Register 17, Select 1) te Reset State Compliance d Resource Architec R0 R/W, Read/Wri =1 MVH ) =1 then MVH MVH =0, then this VL Config5 or not or struction fetch or struction fetch or ELPA , software must also , software must also VH This is considered a This is considered Meaning set or clear VH. An MTC0 set or clear VH. An MTC0 ELPA d that only VL be cleared d that only VL be cleared Config5 implementations that do not implementations that do not ir to invalidate the MAAR ir to invalidate hus will not modify behavior = MAAR truly considered 1 truly considered if VH is . VH only factors into any any into factors VH only =1. MAAR register is valid : MAAR register V =0. MVH MVH 9.54 Memory Accessibility AttributeRegi Description =0, software must always clear VH PageGrain MAAR =0 when and (MAAR invalid result. invalid or not Config5 or not . VL this MAAR should not mod- register any instruction of behavior ify the data load. fetch or the may modify MAAR register behavior of any in data load. ELPA VH PageGrain me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me ELPA =0 or , then both VL and VH must be factored be VL and VH must then both =1, =1. Otherwise, write to VH is ignored, VH is ignored, VH to write Otherwise, =1. Config5 , the Otherwise if supported. upper half of ELPA ELPA Config5 VH MVH MVH MAAR MVH 0 and thus not valid is MAAR[63:32] 1 is valid and thus this MAAR[63:32] Table 9.76Table MAAR Register Field Descriptions = MAAR V MAAR PageGrain Encoding Config PageGrain Config If to : equation reduces logic if it is R/W. R/W. is it if logic If is R0 and is factored not into logic. clearing to Prior VH is R/W if by writing If both valids are present, and if either valid bit (as calcu- bit (as valid either if and are present, valids If both of the MAAR register is set to 0, then the reg- lated above) t and invalid is assumed ister support VH. MTC0 writes also clear VH. clear also writes MTC0 may An MTHC0, if supported, where case the VH. For clears always PageGrain in valid one clear thus may Software access. of a memory pa MAAR of the one register recommende comparison. It is for software consistency with VH is R0 if DMTC0 will is 1, providing set VH if VL in write-data Config5 but MAAR into determining whether a a whether determining into See definition of VL also. VL of See definition If VH is present, then VL is also 1. If clear match, MAAR a determining in effective still MAAR is an may yield which error. programming : . as follows is then it interpreted If VH R/W, is Fields VH 63 High 32-bits Valid, Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 301

0 Required urce Architecture, Revision urce R te Reset State Compliance R/W Undefined Required R/W Undefined Required Read/Wri pair speculation attri- 17, Select 2) for method 2) for Select 17, d, and thus least sig- the allowed to specula- allowed ess bits. Unused leading Meaning pping regions is determined regions is pping read as 0. 0 and MFHC0 in MIPS32, and MFHC0 in MIPS32, 0 on-speculative, it must be old- be on-speculative, it must be allowed to speculate. reserved. For this purpose, the never may Description gnored, is equal to PA[16]. is than or equal to ADDR. than or = 1, then ADDR may be extended to lume III: MIPS64® / microMIPS64™ Privileged/ lume III: MIPS64® Reso matches MAAR register pair address range tively access address range. address access tively matches MAAR register pair address range is ELPA 1 Instruction fetch or data load that 0 Instruction fetch or data load that Table 9.76Table MAAR Register Field Descriptions Encoding PageGrain ADDR must always specify a physical address.a always specify ADDR must are 64KB aligne MAAR regions nificant bit of ADDR If the the upper specifies any sourced bound then register address must be less If the the lower specifies any sourced bound then register address must be greater than or equal to ADDR. See MAAR Index (CP0 Register pair. a in or lower register is upper which determine to This allows a 32-bit MAAR to MAAR[12] = PA[16]. PA[35]. = where MAAR[31] PA, 36-bits of specify If MAAR regions are allowed to overlap. The MAAR are cumulative regions allowed to overlap. for overla attribute speculative If an access is qualified as as n qualified is access If an est in machineallowed before being to accessor memory memory-mapped regions. valid by ANDing individual MAAR butes. a maximum of 59 physical addr bits must be treated as PA to an additional by up extended be must MAAR register MTHC accessible by 32-bits, which are Release defined in MIPS32 or 5, MIPS64 DMTC0 and DMFC0. Fields 0 15:2 are ignored, read as 0. Reserved. Writes R 0 Required 0 62:56 are i Reserved. Writes S 1 Speculate. Name Bits ADDR 55:12 Address bounds. 302Vo Architecture For MIPS® Programmers 6.03

regis- MAAR ture, Revision 6.03 ster (CP0 Register 17, Select 1) te Reset State Compliance d Resource Architec R/W 0 Required Read/Wri y never speculate y never Result Result is valid is Result Result is invalid Result is invalid Resultant Valid Resultant modify modify may may pair is determined pair is by the cumulative individualspeculate of any of any instruction pair is determinedthe from cumulative individual struction fetch or struction fetch or MAAR V S Meaning s to determine an effective effective an to determine s MAAR truly considered 1 truly considered if VH is 1 0 1 9.54 Memory Accessibility AttributeRegi Description MAAR[i+1] MAAR[i+1] not modify behavior not modify data load. fetch or behavior of any in data load that falls within the range of range the within falls that load data by the MAAR addresses specified register pair. te attribute for a te me III: MIPS64® / microMIPS64™ Privilege / microMIPS64™ III: MIPS64® me S V 0 valid and should is not MAAR[31:0] 1 is valid and MAAR[31:0] Table 9.76Table MAAR Register Field Descriptions 10 0/1 0/1 speculate may access Valid ma access Valid 00 1 1 0 Result is invalid Table 9.77Table Determination for MAAR Pair Valid Encoding MAAR[i] MAAR[i] Table 9.78Table for MAAR Pair Determination Speculate If VH is present, then VL is valid for a MAAR register. also 1. See description of VH mean for where i iseven where i iseven 0 32-bits Low Valid, shows howa the validfor attribute shows how the specula Fields attributes. Table 9.77 Table 9.78 ter valids. VL Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 303 urce Architecture, Revision urce lume III: MIPS64® / microMIPS64™ Privileged/ lume III: MIPS64® Reso 304Vo Architecture For MIPS® Programmers 6.03

registers are INDEX MAAR register fields. register number that may register number that 65 210 MAAR MAAR Index registers (CP0 Register 17, Select er Index (CP0 Register 17, Select 2) CP0 Register 17, Select 2) 17, Select CP0 Register R/W Undefined Required MAAR . MRP describes the the describes to theto appropriate value.

register. is used to specify a is used to specify INDEX Config5 INDEX MAAR Table 9.79 is unchanged is MAARI to determine the the determine to register pair. register pair. register MAAR Index INDEX register; Meaning INDEX gister gister range is always con- MAAR MAAR 0

(CP0 Register because 17, Select 1) is supported. This is nored, read as 0.nored, R 0 Required ttribute Register Index ( Register Index ttribute registers included is implementa- registers is greater than 1. than is greater registers Description Read/Write Reset State Compliance register to access. MAAR Index me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 305 MAAR 9.55 Memory Accessibility Attribute Regist bound of the of bound the of bound MAAR MAAR MTC0 or MFC0 instruction. MTC0 or MFC0 (Release 5) MAAR there is always more than there is always more one Figure 9.61 MAARI Index Register Format MFC0, software must set MFC0, software must 01 This register specifies the address upper This register specifies the lower address is encoded as follows to indicate which register of indicate follows to is encoded as can be detectedby software through

Table 9.79Table Descriptions Field MAARI Register Index Encoding Optional

registers may be implemented - may registers maximum value supported. Other than the all ones, if the if the ones, the all Other than supported. value maximum then supported, is not written value from its previous value. The re and starts tiguous at value 0. The number of The number must be an even numberbut tion-dependent in Release 5. to ones all write may Software specifies the the specifies of bit least-significant The are paired. MAAR registers INDEX the pair is being accessed. The number of The number MAARI is usedinis conjunction with an implementation thatsupports

is always required if MAAR shows the format of the shows Fields Prior to access by MTC0 or by Prior to access The The presence of MAAR Index MAAR Index Compliance Level: 1). Multiple be accessed by software with an Figure 9.61 Figure paired in Release 5, and thus and paired in Release 5, 0 31:6 ig are Writes Reserved. 63 Name Bits INDEX 5:0 MAAR Index MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.55 A Accessibility Memory ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 306Vo For Programmers Architecture MIPS®

Watch and bit in the the in bit WatchLo M IRW bits are zero in the 3210 ERL h conditions.For micro- register fields. and econd half-word overlaps a econd half-word overlaps State Compliance Reset supported by a particular registers may be dedicated registers to a EXL WatchLo Watch registers, referencing them via the select them via the select registers, referencing R/W 0 Optional R/W Undefined Required Write 9.56 18) Register (CP0 Register WatchLo Read / register address matc register address see which ones were actually set. actually were which ones see a watchpoint debugwhich facility initiatesa WatchHi describes the register, and the watch exception is deferred until register, Watch register. See the discussion of the of See the discussion register. ype of reference (instruction fetch, load, store) to r a match occurs if the s theoccursr a match if and Cause Config1 triggered by a prefetch, CACHE, or SYNCI (Release 2 and 2 (Release or SYNCI triggered by a prefetch, CACHE, determine which enables are Table 9.80 Table WatchLo ). Software mayif at least one pair of determineSoftware ). bit of bit the VAddr ess and are actually issued issued actually and are ess register; writes to writes to it must be ignored, instructions never cause s not overlap with the watched address. bitin is set the FC0 instructions, and each pair of each pair FC0 instructions, and ptions are enabled for instruc- WR WP Description WatchLo les bits and reading them back to and reading them bits les me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 307 Figure9.62 Register Format WatchLo (CP0 Register 18) (CP0 Register register only supportsthetypes, a subset of the reference unimplemented enablesmust be registers together provideto interface the registers together Table 9.80Table Register WatchLo Field Descriptions are zero. bits Watch Optional.

WatchHi ERL Watch exceptions). Watch If this bit is not implemented, zero. must return and reads tion fetches that match the addr by the (speculative processor this is a doubleword address, since bits [2:0] are used to used since [2:0] are this is a doubleword address, bits match. type of control the register virtual specifies the base address and the t and and shows the format of the EXL registers are implemented via the registers are implemented register description below. register. If either bit is a one, the one, bit is a If either register. WatchLo WatchLo Fields 63 Figure 9.62 It isIt implementation-dependent whetherdata a watch is subsequent releases only)instruction addresswhosethe matches ignoredon write and return zero on read. Software may field of the MTC0/MFC0 and DMTC0/DM the field of register pair by setting all three enab WatchHi WatchHi Status Compliance Level: The

both the watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate As such, specified in the registers. address instruction or data access matches the watch exception if an exceptions are takenonly if the debug solution. Watch some functions of theEJTAG

MIPS implementations, it is implementation-dependent whethe watched address and the first half-word doe An implementation may provide zeroor more pairs of The particularinstructionof type (e.g., reference or data match. If a particularIf match. I 2 If this bit is one, watch exce VAddr 63..3 Note that to match. address the virtual specifies This field Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.56 Register WatchLo

State Compliance Reset ged Resource Architecture, Rev. 6.03 R/W 0 Optional R/W 0 Optional Write Read / eld Descriptions (Continued) eld Descriptions enabled for loads writes to writes to it must be ignored, writes to writes to it must be ignored, ptions are enabled for stores ptions are Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Table 9.80Table Fi Register WatchLo that match the address. the match that If this bit is not implemented, and reads must return zero. must return and reads and reads must return zero. return must and reads that match the address. the match that instruc- load PC-relative the MIPS16e of the purposes For data, a be to considered is reference PC-relative the tions, watch- is, the That reference. instruction an than rather 1. is a only if this bit is triggered point If this bit is not implemented, Fields R 1 If this bit is one, watch exce W 0 If this bit is one, watch exce Name Bits 308Vo For Programmers Architecture MIPS®

and ’. register n+1 register: an WatchLo WatchHi bits are zero in the 3 2 1 0 ERL WatchLo clear”, such that such that clear”, software and register fields. State Compliance Reset tion. The optionalThe tion. mask field registers may be dedicated registers to a EXL bit is one in the in is one the bit M WatchHi is to write the value is to write the read from the Watch ion matched. When set proces- the set by When matched. ion t when the register was read are cleared the register t when registers, referencing them via the select them via the select registers, referencing R Preset Required at matches the address will cause the specified matches at Write 9.57 WatchHi Register(CP0 Register 19) ) that denote the condition that caused the caused condition that that denote the ) Read / W . a watchpoint debugwhich facility initiatesa WatchHi , and register, and the watch exception is deferred until register, describes the describes register. If the If register. regis- R , and I pair is implementedof withfield ‘ a select WatchLo Cause All three bits are “write one to bits are All three Config1 register cause a watch excep a watch cause register WatchLo / Table 9.81 WatchLo WatchLo / ). Software mayif at least one pair of determineSoftware ). lifies the virtual address specified in the lifies the virtual EntryHi 16 15 12 11 bit of bit the WatchHi register; bitin is set the FC0 instructions, and each pair of each pair FC0 instructions, and WatchHi WR WP one is implemented) and which condit clear its value. The The clear its value. typical way to do this Description WatchHi ASID 0 Mask I R W me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 309 . Indoing so, only those bits whichse were ’, another bit is one, any virtual address reference th Figure 9.63Figure Format Register WatchHi n G bit is a zero, only those virtual address references for which the ASID value in the a zero, onlyASIDis whichaddressin value bit those virtualthe references for registers together provideto interface the registers together n+1’ Table 9.81Table Field Descriptions Register WatchHi G WatchHi are zero. bits Optional.

EAS WatchHi ERL ters is implemented at an MTC0 or MFC0 select field ‘ value of bits are set by the processor when the corresponding bitsthe are set by the processor when watchregister condition satisfiedindicate and is 0 and W and register contains information that qua shows the format of the the shows (lobal) bit, an optionalbitsaddress ( mask, and three EXL register back to register matches the ASID value in the the in value ASID the matches register registers are implemented via the registers are implemented G , and R register. If either bit is a one, the one, bit is a If either register. , a , WatchHi WatchLo I Fields 31 30 29 28 27 26 25 24 23 MGWM provides address maskingprovidesaddress to qualifythe address specified in The watch register to match. If the field of the MTC0/MFC0 and DMTC0/DM the field of WatchHi ASID WatchHi WatchHi Status Compliance Level: The when the register when the register is written back. 9.63 Figure both the watch exception if an instruction or data access matches the address specified in the registers. As such, they duplicate As such, specified in the registers. address instruction or data access matches the watch exception if an exceptions are takenonly if the debug solution. Watch some functions of theEJTAG must write a one to the bit in order to to order in the a bit to one write must which watch registerpair (if more than sor, each of these bits remain set until cleared by software. by bits remain set until cleared these each of sor,

The An implementation may provide zeroor more pairs of reference with of a select field ‘ particularinstructionof type (e.g., reference or data a watch exception. If the If watch exception. a M 31of is one, another pair this bit If Name Bits 9.57 Register 19) (CP0 Register WatchHi MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

2) 2) 2) Required = AE AE If then then

else 0 else State Compliance 1 Reset Undefined Config4 A ged Resource Architecture, Rev. 6.03 then then

0 0 Reserved If R/W Undefined Optional R/W R/W Undefined Required R/W Undefined Required W1C Undefined Required (Release W1C Undefined Required (Release W1C Undefined Required (Release else 0 0 else Write = 1 Read / E Config4

EntryHi ASID field of register. registermust register to cause a cause to register WatchHi WatchHi implemented, any bit in is field and then reading hat matches that specified in t EntryHi cleared by software, cleared by software, which is when a store condition matches matches condition a store when bits the corresponding address the corresponding bits Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: required to match that in the required to match that in the field of the lization Module. lization Module. then these bits extend the the extend these bits then

field of the bit is zero in the ASID = 1 returns zero; as = 0 then Must be written G

register will cause a watch exception. If this register will cause a watch exception. AE AE ASID register. If this field is If register. WatchLo Config4 Config4 Table 9.81Table (Continued) Descriptions Field Register WatchHi this register. register. this If zero on read. accomplished by writing a 1 to the bit. register if the When pair. register watch this in values the matches dition set, the bit remains set until WatchLo inhi one a field that is this match. address the in from participating bit be it to must writes is not implemented, field If this and reads must return ignored, zero. Software may determine how many mask bits are imple- th ones the by writing mented back the the result. back the values in thisWhen watch set, theregister bit pair. accom- is which software, by cleared until set remains plished by writing a 1 to the bit. the values in thisWhen watch set, theregister bit pair. accom- is which software, by cleared until set remains plished by writing a 1 to the bit. Must be written as zero; returns zero on read. 0 0 Reserved match the the match the the the is zero, bit watch exception. watch 15..12 Fields I 2 con- fetch an instruction when is This bit set hardware by 0 27..26, R 1 matches condition load a when by hardware is set bit This G 30one, any address If this bit is W 0 This bit is set by hardware WM 29:28 Virtua Reserved for EAS 25:24 If Mask 11..3 the in address the qualifies that mask bit Optional ASID 23..16 ASID value which is Name Bits 310Vo For Programmers Architecture MIPS®

to nce XContext Complia State Reset describes the the describes SEGBITS-1:SEGBITS-(X-Y) y power-of-two-sized PTE PTE y power-of-two-sized corresponds to the contigu- =0 R Undefined Required R Undefined Required Table 9.83 Write Read / ged Resource Architecture, Rev. 6.03 CTXTC =1; , the behavior is identical to the standard the exception. Bits Y-1:0 are unaffected are unaffected the exception. Bits Y-1:0 of a two-level lookupa two-level scheme. CTXTC register can point to an register can point to . = 1 (access = 1 to -1SEGBITS 13 register, where this range register, Config3 AT when SEGBITS equalsAlthough 40). thehave fields XContextConfig address region. address If XContext BadVPN2 register, it maypoint to an 8-byte pairwithin of 32-bit register, PTEs 63..62 of the virtual the 63..62 of 39:13 39:13 Meaning XContext Fields when Config3 when Fields Invalid,Modified)bits or VA causes ents only), only the 0b00 only the ents only), l page directory entry in contains bits VA contains Description Register when Register Supervisor Mode is not imple- Mode is Supervisor not is reserved mented, this encoding register. The exceptionbits The 63..62 causes virtual of the bewrit- address to register. XContextConfig field contains field contains bits followingmodification a of the contentsthe of UNPREDICTABLE lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: R/W to software, and are unaffected by R/W to software, and are unaffected 1:Y are referred to as to as 1:Y are referred 0b11 xkseg 0b000b01 xuseg xsseg: supervisor 0b10 Reserved Region field is written by written is Page Number/2 field Bad Virtual Encoding =1. of bits “(X-1):Y” of thebits of “(X-1):Y” of The implementing Config For processors address. the virtual address the that missed. The hardware on a miss. It 32-bit compatibility 32-bit segm and 0b11 values are supplied by the on an processor and 0b11 exception. XContextConfig register is CTXTC Table 9.82Table Register XContext register (bits 30:4 register are filledwith VA -13+4 is 40) is 40) XContext =1 thentheimplemented pointer by the =1 then the a TLB exception (Refill, then the =1 -13+5 .. register. -13+3 .. 4 Config3 shows shows the format of the XContext CTXTC CTXTC XContext andfields, R X- and bits SEGBITS SEGBITS SEGBITS (30..4 assuming (32..31 assuming (32..31 SEGBITS SEGBITS Field Config3 Config3 by the exception. If X = 31 and Y = 4, i.e. bits 30:4 are set in structure within memory. This allows the TLB refillThisallows handler the TLB touse thepointer without additional shiftingstructurewithinandmask- memory. ing steps. Depending on the value in the MIPS III III MIPS been made variablethe been made 63:X are referred to as in size and interpretation,is retained. Bits the MIPS64 nomenclature PTEBase The value of the ten into the R field. Bits 63:X+2 are Figure 9.65 a single-level page table scheme, or to a first leve If be writtento a variablerange XContextConfig If ous range oftheous range set bits in register fields 0 3..0 on read.zero returns zero; as be written Must 0 0 Reserved R Name Bits BadVPN2 312Vo For Programmers Architecture MIPS®

ce Reserved 0 Complian YY-1 0 or Register 20, Select 0) =1 State Reset 0 (if 0 (if R) (if R/W) Undefined Undefined =1 CTXTC / R Undefined Required R R Undefined Required or R/W Undefined Required R/W Read Write CTXTC of the of = 1 (access to to (access 1 = 9.58 XContext Register (CP0 BadVPN2 AT address region. address If Register as a pointer to Meaning ts only), only the 0b00 only ts only), rdware on a TLB exception. rdware on e operating system and is e operating Context Description caused the exception. SEGBITS-1:SEGBITS-(X-Y) Supervisor Mode is imple- Supervisor not is reserved mented, this encoding field contains bits 63..62 of the virtual the of bits 63..62 contains field 0b11 xkseg 0b000b01 xuseg xsseg: supervisor 0b10 Reserved me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 313 Region R Encoding This field by th is for use operat- the allows that value a with written normally the to use system ing an array of data structures in memory corresponding memory corresponding structures in data an array of address the to region containing virtual the address which caused the exception. The Config implementing For processors virtual address that address. Must be written as zero; returns zero on read. 32-bit compatibility compatibility segmen 32-bit an on processor the by are supplied values and 0b11 exception. It contains bits VA This field is written by ha by This field is written X+2 X+1 X X-1 Figure Figure 9.65 Config3 when Format Register XContext Bits Table 9.83Table Config3 when Descriptions Field Register XContext May be null. PTEBase Fields where X in {63..0}. May be null. where X in {63..0}. where where Y in {63:1}. May be null. where where and X in {64..1} Y in {63..0}. May be null.

0 (Y-1):0 Variable, RX+1:X 63 Name PTEBase 63:X+2 Variable, BadVPN2 (X-1):Y Variable, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 314Vo For Programmers Architecture MIPS®

l Select values) l Select P0 Register values) 22, all Select Register 22, al Register ndent use and is not defined by the architecture. defined ndent use and is not . 9.59 Reserved Implementations for (C me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 315 Implementation Dependent Implementation

Compliance Level: CP0 registerCP0 implementation-depe 22 is reserved for MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.59 (CP0 for Implementations Reserved ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 316Vo For Programmers Architecture MIPS®

on for the format and description of 9.60 Debug Register(CP0 Register 23, Select 0) ecification. Refer to that specificati me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 317 Optional.

register is part of the EJTAG sp partregister is of the EJTAG Debug this register. Compliance Level: The MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.60 Select 0) Register 23, (CP0 Debug Register ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 318Vo For Programmers Architecture MIPS®

Register 23, Select 6) 9.61 Debug2 Register (CP0 me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 319 ter (CP0 Register 23, Select 6) 23, Select Register ter (CP0 Optional.

register is part of the EJTAG specification.to that specification Refer for the format description and of registerof is part the EJTAG Debug2 Compliance Level: The this register. 9.61 Regis Debug2 MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 320Vo For Programmers Architecture MIPS®

register to deter- to register register requires requires register format and descrip- DEPC DEPC registers: ISA Mode ocessing resumes after excep- a debug n, when the exception causing instruc- causing n, when the exception 9.62 Register DEPC Register (CP0 24) and ich processing resumes with the value of PC register is set. set. is register value writtenvalue with no interpretation. Software Cause of the exception, or exception, of the and must be writable. registerwith, ssor resume address and read the DEPC ecution of the DERET instruction. the DERET ecution of bit inthe ster in Processors the That Implement E or the microMIPS64 base architecture, the base or the microMIPS64 E was was the direct cause 0 that contains the address at which pr at address that contains the Branch Delay y preceding branch or jump instructio branch y preceding register are significant ocessing resumes, as described above. register, it combines the address at wh it combines register, ferred there for the there ferred is re reader and the specification e EJTAG register, it distributesto the bits the register, me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 321 DEPC S64 Base Architecture , the processor writes , processor writes the the  ISAMode DEPC register as the result of ex register to change the proce DEPC register simply returnto a GPR the last 63..1 DEPC 0 DEPC e processor will resume. e processor  0 DEPC Optional.

rpreted by the processor as describedinterpretedabove. by the processor as is value which new register store a 63..1 register: DEPC register register is a read-write  DEPC ISAMode  DEPC ISAMode tion is in a branchtionindelay a is slot, and the PC DEPC  resumePC DEPC DEPC ISA Mode When a debug exception occurs When The processor reads reads The processor the • virtual the instructionthe address of that • of the immediatel address virtual the writes to the tion serviced. It has been is part of th the All bits of tionof theregister. special handling. When the processor writes the Software may write the Software readsthe of “resumePC” is the address at which pr reads When the processor the In processorsIn that implement MIPS16e AS the Compliance Level: The mine at what address th mine at what address the MIPS16e ASE or microMIP 9.62.1 Handling of Regi the DEPC Special 9.62 24) (CP0 Register DEPC Register MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 322Vo For Programmers Architecture MIPS®

register, and and register, ter overflows), the ter overflows), Cause bit is one bit in the Perfor- is es under a specified set of of a specified set under es M the Architecture, this the Architecture, this inter- the performance counter. the performance counter. bit in the describes the Performance ted, each performance counter lease 2 of the Architecture, 2 of lease 5 4 3 2 1 0 PCI is a one (the coun a one (the is register: Even selects access the con- Even selects register: Table 9.85 register. If the register. PerfCnt nce counter. The counter register increments counter register The nce counter. n+3’. Config1 ontrol Register 0 ontrol ontrol Register 1 ontrol showstwo an examplecounters performance of ounter Register 0 ounter Register 1 ontrols the behavior of behavior the ontrols C C C C n’, another pair of Performance Counter Control and PerfCnt Register Usage lementationsRelease 1 of of e, extending the select field in the obvious way to obtain determineleast if atoneof Performance pair Counter 9.63 Performance Counter Register (CP0 Register 25) hardware interrupt5. InRe values of the bit in the n+2’ and ‘ Table 9.84 register. register. PC EventExt Event IE U S K EXL and a 32-bit or 64-bit counter register. To provide additional provide To and32-bit a 64-bit or counter register. rformance counters are implemen rformance TD PerfCnt 16 15 14 11 10 -significant bit of the counter register of the counter bit -significant gister (CP0 Register 25) (CP0 Register gister to even-odd select each performance counter c each performance 0PC renced via a select field of ‘ field of select a renced via . me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 323 Select Value to the interrupt mode of the processor. Counting continuesregister aftercounter a over- theto interrupt processor. the mode of PerfCnt, Select 1 PerfCnt, Select 3 PerfCnt Register s access the counter register. register. the counter s access ined by the control register for the performa EC Recommended

performance counters may be implemented. be may performance counters Figure 9.66Figure Format Register Control Counter Performance 0 PerfCnt, Select 0 1 PerfCnt, Select 2 Counter shows the formatControlPerformance Counter of the Register; Performance Table 9.84 Table Register CP0 PerfCnt the of Usage Counter Performance Example pendinginterruptsfrom performance all counters are ORed together to become the and how they mapthe intoth values of e select are prioritized as appropriate as are prioritized flownot whether or an interruptis requestedtaken. or Each performance counter is mapped in performancecounter optionally requests an interrupt. In imp rupt is combineda implementation-dependentin way with once for each enabled event. When the most event. When the once for each enabled Compliance Level: The Control Register associated with 9.66 Figure Counter registers is implemented at the select values of ‘ values of the select implemented at is registers Counter trol register and odd select trol register and Control and Counter is implemented registers via the More or less than two performance counters are also possibl ofthe desired number performance counters. Software may consists of a pair of registers: a 32-bita pair of registers: controlregister of consists multiple capability, events or cycl to count can Performance counters implementation-dependent be configured conditionsdeterm that are The ArchitectureThe supports implementation-dependentperformance countersprovide that capability the to count performance analysis. If pe events or cycles for use in Counter Control Register fields. Control Register Counter mance Counter Control register refe 31 30 29 25 24 23 22 MW Impl 9.63 Re Counter Performance MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

2) Optional Required implemented. mance Counter PDTrace Perfor- PDTrace Tracing feature is Tracing Required (Release State Compliance Reset hardware hardware mentation Undefined 0 if not used 0 if not by the imple- the by ged Resource Architecture, Rev. 6.03 R Preset by R Preset by RW 0 Required if RW Undefined Optional Write Read / n+3’. Meaning Meaning +2’ and ‘ n+2’ and is implemented at an MTC0 at an MTC0 implemented is ace event is triggered. ace event is triggered. lementation-dependent. Any Any lementation-dependent. on has the 6.00 and higher) corresponding Counter register, Counter register, corresponding more which support than the 64 tion-dependent and is not speci- and is tion-dependent not ; returns zero on read on returns zero ; 0 0 Reserved Description lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: lization Module. lization Module. 0 0 Reserved register register is 32 bits register is 64 bits EventExt|Event. 01 counter. this for is enabled Tracing is for this counter. disabled Tracing 01 of the Counter corresponding Width of the Counter corresponding Width Encoding Encoding The PDTrace facility (revisi facility PDTrace The This bit Counter in its output. ability to trace Performance from counter performance the specified is used to disable being traced when performance counter trace is enabled counter tr and a performance Control and Counter registers registers and Counter Control of or MFC0 select field value ‘ encodings possible in the Event field, 6-bit the EventExt In such field. Event to the an extension as acts field instances the event selection is the concatenation of the two fields, i.e., is imp width field actual The as zero and are ignored not implemented read bits that are on write. as follows: fied by the architecture. by the architecture. fied zero; as written be must implementation, used by the If not read. zero on returns Table 9.85Table Descriptions Field Register Control Counter Performance Fields

0 22..16 be written as zero Must M 31 this bit If is a one, another pair of Performance Counter W 30 the Specifies width of the EC 24..23 Virtua Reserved for Impl 29:25implementa This field is PCTD 15 Disable. Counter Trace Performance Name Bits EventExt 14..11 some In implementations 324Vo For Programmers Architecture MIPS®

State Compliance Reset R/W Undefined Required R/W Undefined Required R/W Undefined Required R/W 0 Required Write Read / 9.63 Performance Counter Register (CP0 Register 25) gister Field Descriptions (Continued) Descriptions Field gister for the conditions the corresponding corresponding the (the most-significant bit (the most-significant nt Supervisor Mode, this nt Supervisor Mode, Meaning Meaning Meaning include cycles, instructions, for the conditions under er Mode. er Mode. Refer to Section t multiple performance coun- performance t multiple in Supervisor operating e interrupt request when the e interrupt request when register. register. Description be counted by Status me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 325 Mode Mode 01 in Supervisor counting event Disable Enable event counting in Supervisor 01disabled interrupt counter Performance counter interrupt enabled Performance 01 Mode in User counting event Disable Enable event counting in User Mode 3.3on page “Supervisor Mode” 24 Encoding Encoding Encoding cessors that implement Supervisor to Sec- Mode). Refer cessors implement Supervisor that tion processor is the under which on write bit must be ignored and zero on read. return ters allow ratios of events, e.g., cache miss ratios if cache if cache miss ratios cache e.g., of events, ratios ters allow in events the as selected are references memory and miss two counters which the processor is operating in User Mode. mode. If the does not impleme processor Counter Register. The list is list of events implementation- The Register. Counter but typical events dependent, cache instructions, instructions, branch memory reference and TLB misses, etc. suppor Implementations that counter overflows corresponding 3.4 “User Mode” on page 24 of the counter counter is one. of the This is bit 31 for a 32-bit wide coun- by the denoted W bit ter or bit 63 of a 64-bit wide counter, this register). in The request. interrupt the enables bit simply this that Note masks interrupt normal the by gated is still interrupt actual in the and enable Table 9.85Table Control Re Counter Performance Fields S 2 those pro- Mode (for counting in Supervisor Enables event U 3 Enables event counting in Us IE 4 th Enables Enable. Interrupt Event 10..5 Selects the event to Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

Figure 9.67 0 State Compliance Reset ged Resource Architecture, Rev. 6.03 R/W Undefined Required R/W Undefined Required describes the Performance Counter Coun- Write Read / ents once for each enabled event.

= 1, = 1, Table 9.86 Status Status Status EXL EXL register is gister Field Descriptions (Continued) Descriptions Field gister bit in the bits in the bit in the Status ERL ERL EXL Event Count Meaning Meaning , this bit enables event rnel Mode. Unlike the usual Mode. Unlike the rnel and register is one. is Debug register bit in the in the bit as described in Section described as EXL ERL Description = 0 = 0 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: bit in the in the bit ERL ERL Mode DM 1 counting while Enable event 0 event counting while Disable 01 Kernel in counting event Disable Enable event counting in Kernel Mode Encoding Encoding Figure 9.67Figure Format Register Counter Counter Performance register is one and the register is one and Counting is Counting never the enabled when the register or zero. register are zero. definition definition of Kernel Mode 3.2 “Kernel on pageMode” 23 counting only when the counting when only Table 9.85Table Control Re Counter Performance Fields or 31 63 The Counter Register associated with performance counter increm The Counter each shows the format of the Performance Counter Counter Register; ter Register fields. K 1 Enables event counting in Ke EXL 0 Enables event counting when the Name Bits 326Vo For Programmers Architecture MIPS®

s visible when the IE visible s interrupt state change R/W Undefined Required Write Reset State Compliance Read/ . 9.63 Performance Counter Register (CP0 Register 25) er Register Field Descriptions Field Descriptions er Register . When the most-signifi- bit in the corresponding in the corresponding bit W counters and indicated by by counters and indicated rrupt request is ORed with is rrupt request Description e Event Count Field of the Counter register are written. See e See sECTION Event Count Field of the Counter register are written. Cause register. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 327 the Interrupt System” on pageSystem” the Interrupt 96 e, the EHB instruction can be used to make Increments once for each event that is enabled by the is enabled that event for each once Increments Control Register corresponding inte cant bit is one, a pending Register. Control Counter Performance those from other performance other from those the in bit PCI the The width of the or counter is 32 bits either 64 bits of the on the value depending Table 9.86 Table Count Counter Performance or 31..0 63..0 Fields Programming Note: Programming In Release 2 of the Architectur field of the Control register or th 6.1.2.1 “Software Hazards and

Event Event Count Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 328Vo For Programmers Architecture MIPS®

register is imple- tionthe formatfor of this ErrCtl in conjunction with specific encodings of of with specific encodings in conjunction 9.64 ErrCtl Register (CP0 Register 26, Select 0) evious implementationsread and write parity to or od. The exact format of the The exact format of od. fer to the processor specifica to the processor fer ster has pr ster has been used in me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 329 r implementation-dependentmeth Optional.

register provides an implementation-dependent diagnostic interface with the error detection mechanisms the error detection interface with implementation-dependent diagnostic an register provides ErrCtl implemented by the processor. This regi This by the processor. implemented ECC information to and from the primary or secondary cache data arrays cache data secondary or the primary information to and from ECC othe or the Cache instruction Compliance Level: The mentation-dependent and not specified by the architecture. Re fields. the a description of register and MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.64 Select 0) 26, (CP0 Register ErrCtl Register ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 330Vo For Programmers Architecture MIPS®

at may be implemented by a pro- by a may be implemented at 9.65 CacheErr Register (CP0 Register 27, Select 0) dependent and not Referspecified to by the architecture. the cache error detection logic th error detection the cache me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 331 register is implementation- e format of thisregister and a descriptionof the fields. CacheErr Optional.

register provides an interface with an register provides CacheErr cessor. the The exact format of the processor specification for th the processor specification Compliance Level: The 9.65 27, Select 0) Register Register (CP0 CacheErr MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 332Vo For Programmers Architecture MIPS®

occupy the even select val- even select the occupy interface to all caches, or a to all caches, or interface registers as the source or sink source the as registers must accept a write of zero to must accept a write of zero all implementations. software ndefined Optional e tags at powerup. e cache tag array. The Index Store Index Store The cache tag array. e TagHi ndex Store Tag operation to cache Tag ndex Store . Refer to the processor core specifi- core processor . Refer to the PState L Impl 0 P d select 2 addressing the data cache. 876 5 4 3 2 10 and R/W Undefined Optional R/W Undefined Optional R/W Undefined Optional R/W Undefined Optional Write Reset State Compliance Read/ TagLo otherwise. 9.66 TagLo RegisterSelect (CP0 Register0, 28, 2) initializing the cach initializing the register that acts as the that acts register e register fields. However, in However, e register fields. registers are registers implemented, they Optional TagLo not for each cache, processors s that act as the interface to th as act that s registers, and then use the I the use and then registers, TagLo TagHi scription for the detailed the scription for ion for the detailed defini- ion for the detailed defini- ion for the detailed defini- ss bits of the cache tag. Refer of the cache tag. Refer ss bits and r implementations. U registers is implementation-dependent gister 28, Select 0, 2) 28, Select 0, gister Description lect 0 addressing the instruction cache an the instruction lect 0 addressing TagLo PTagLo TagHi me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 333 and if a cache is implemented; implemented; is a cache if as part of the software process of software process the part of as Figure 9-68Figure Format Register TagLo Example registers are implemented or registers are implemented TagLo TagLo registers are read/write registers are read/write register Required

TagLo definition. definition. to the processor-specific de processor-specific the to tion. processor-specific descript processor-specific tion. processor-specific descript processor-specific processor-specific descript processor-specific tion. Table 9.87 Table Descriptions Field Register TagLo Example register for each cache. If for each cache. multiple register TagHi and TagLo TagLo Fields 0 2:1 on read. returns zero zero; as Must be written 0 0 Reserved P 0 the to Refer tag. cache the for bit parity the Specifies L 5 to the Refer tag. bit for the cache the lock Specifies initialize the cache tags to valid state at a power-up. isIt implementation-dependent whetherisa single there Tag and Index Load Tag operations of the CACHE instruction and use the Index Load Tag Tag of tag information, respectively. The exact format of the dedicated select 0 and select 2 of Compliance Level: The ues for this register encoding, with se this register ues for Whether individual cation for the format of this register and a descriptionandthecation of th format a ofregister for this must beablemust into to write zeros the 63 Impl 4:3 fo reserved field is This PState 7:6 Specifies the state bits for the cache tag. Refer to the Name Bits PTagLo 63..8 upper addre Specifies the MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.66Re (CP0 Register TagLo ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 334Vo For Programmers Architecture MIPS®

the corresponding data val- they occupy the odd select and select 3 addressing the data cache. and select ace to the cache data array and are intended for register that acts as the interface to all caches, or a caches, or to all as the interface register that acts 9.67 DataLo RegisterSelect Register (CP0 1, 3) 28, registers are implemented, registers are implemented, the CACHE instruction reads instruction reads the CACHE registers is implementation-dependent. Refer to the proces-

DataLo DataLo DataHi and gister a description and of the fields. DataLo select 1 addressing the instruction cache the instruction select 1 addressing me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 335 registers. DataHi registers are registers that act as the interf act as that registers are registers Optional.

d operation of the and register for each cache. If multiple DataHi DataLo and DataLo DataLo values with encoding, values this register for diagnostic operation only. The Index Load Tag operation of The Index Load Tag diagnostic operation only. ues into theues into Compliance Level: The sor specification for the formatthis of re isIt implementation-dependent whetherisa single there The exact format an dedicated MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.67 1, 3) 28, Select (CP0 Register Register DataLo ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 336Vo For Programmers Architecture MIPS®

t a write of zero to occupy the even val- select registers as the source or sink source the as registers interface to all caches, or a e cache tag array. The Index Store Index Store The cache tag array. e TagHi . Refer to the processor specification processor . Refer to the d select 2 addressing the data cache. and ware must be able to write zeros into the to write zeros into able be ware must e, processors must accep processors e, TagLo e tags to a valid state to cache tags initialize the ation to otherwise. 9.68 TagHi RegisterSelect Register (CP0 0, 2) 29, initializing the cache tags at powerup. register that acts as the acts register that are implemented, registers they Optional TagHi s that act as the interface to th as act that s TagHi registers is implementation-dependent

lect 0 addressing the instruction cache an the instruction lect 0 addressing TagHi me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 337 and if a cache is implemented; implemented; is a cache if as part of the software process of process software part of the as and a description of the fields. However, soft However, fields. the of description a and registers are implemented or not for each cach or not registers are implemented TagLo TagHi registers are read/write registers are read/write register Required

TagHi registers and the use the Index Store Tag oper cache Tag registers and Store the use the Index

register for cache. If multiple each TagHi

TagHi and TagHi and

TagLo dedicated select 0 and select 2 of Tag and Index Load Tag operations of the CACHE instruction and use the Index Load Tag Tag of tag information, respectively. The exact format of the TagLo Compliance Level: The It isIt implementation-dependent whetherisa single there at powerup. for format the register of this ues for this register encoding, with se this register ues for Whether individual 9.68 0, 2) 29, Select (CP0 Register Register TagHi MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 338Vo For Programmers Architecture MIPS®

the corresponding data val- ace to the cache data array and are intended for 9.69 Register DataHi Select Register (CP0 1, 3) 29, the CACHE instruction reads instruction reads the CACHE registers is implementation-dependent. Refer to the proces- DataHi and gister a description and of the fields. DataLo Register 29, Select 1, 3) 29, Select Register me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 339 registers. DataHi registers are registers that act as the interf act as that registers are registers Optional.

d operation of the and DataHi DataLo and DataLo diagnostic operation only. The Index Load Tag operation of The Index Load Tag diagnostic operation only. ues into theues into Compliance Level: The sor specification for the formatthis of re The exact format an MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.69 Register (CP0 DataHi ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 340Vo For Programmers Architecture MIPS®

0 register to register requires register. All bits of register. ErrorEPC register fields. State Compliance Reset ErrorEPC ErrorEPC y referred to as error exceptions). referred to as error exceptions). y ErrorEPC when the error causing instruction is when the error causing essors That Implement the Write which processing resumes with the value value the with resumes processing which Read / 9.70 ErrorEPC(CP0 Register 30, Select 0) se architecture, the se register with: describes the the describes of the exception, or exception, of the register, at which processing resumes after a Reset, after at which processing resumes register, ssor resume address and read the and address ssor resume EPC ErrorEPC Table 9.88 ErrorEPC 0 register; was was the direct cause ASE or microMIPS64 ba or microMIPS64 ASE ) or Cache Error exceptions (collectivel ) register, it combines the address at it combines the address register, Description am Counter R/W Undefined Required ErrorEPC Register in Proc ocessing resumes, as described above. register, similar to the the to similar register, ErrorEPC and must be writable. and must be  ISAMode me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 341 register as theexecution result instruction. of ERET of the register to change the proce to register S64 Base Architecture Figure Figure 9.69 Format Register ErrorEPC ErrorEPC 63..1 rs, the processor writes the rs, the processor writes the processor will resume the processor Table 9.88Table Field Descriptions Register ErrorEPC ErrorEPC ErrorEPC register: register, thereno is correspondingbranch delay slot indication register, for the register is a read-write register are significant register shows the format of the the shows EPC ISA Mode ErrorEPC  resumePC ErrorEPC ErrorEPC in a branch slot. delay ErrorEPC Fields of the the When an error exception When an error exception occu Soft Reset, Nonmaskable Interrupt (NMI Unlike the “resumePC” is the address at which pr In processorsIn that implement the MIPS16e Compliance Level: Required. Compliance The • virtual the instructionthe address of that • preceding branch or jump instruction of the immediately virtual address the The processor reads reads The processor the special handling. When the processor writes the Figure 9.69 Figure determine at what address

Software may write the 63 Name Bits ErrorEPC 63..0 Progr Error Exception 9.70.1 Handling of the Special MIPS16e ASE or microMIP 9.70 ErrorEPC (CP0 Select 0) Register 30, MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

registers: ISAMode ged Resource Architecture, Rev. 6.03 and PC reted by the processor as described above. as processor the by reted tes the bits to thetes the bits to register, it distribu register, lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: register simply return to a GPR the last value written with no interpretation. Software ErrorEPC 0  0

registerwhicha new valueis interp store 63..1 ErrorEPC ErrorEPC  ErrorEPC ISAMode  ErrorEPC ISAMode PC writes to the Softwarethe reads of When the processor reads reads processor the When the 342Vo For Programmers Architecture MIPS®

n for the format and description of software can use those registers. those registers. can use software 9.71 Register DESAVE Register (CP0 31) Mode. If kernel mode software uses this register, it it register, this uses software mode kernel If Mode. reason, it is strongly recommended that kernel mode registers are implemented, are implemented, kernel registers ecification. Refer to that specificatio ecification. Refer to KScratch* me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 343 registers are mandatory.) are registers Optional.

registerto is meant be used solely whileDebug in register is part of the EJTAG sp EJTAG register is part of the DESAVE DESAVE (For Release 6, the KScratch* Release (For this register. The Compliance Level: The would conflict with debugging kernel mode software. For that If the softwarethis not register. use MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.71 31) (CP0 Register Register DESAVE ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 344Vo For Programmers Architecture MIPS®

0 register. If register. Required (Release 6) (Pre-Release 6) DESAVE State Compliance Reset register. register. Undefined Optional

kernelsoftware. mode These reg- Config4 R/W Write Read / register. Select 1 is being reserved for future debug register. field within the the within field Register Format KScratch n 9.72 KScratchn Registers (CP0 Register 7) 2 to 31, Selects populated with a kernel scratch register. populated with a kernel scratchregister. Data KScrExist RegisterField Descriptions available for scratch pad storage by storage pad for scratch available n Register 31, Selects 2 to 7) 31, Selects Register register. register. Description Optional, KScratch1 and KScratch2 at selects 2, 3 are recommended. recommended. Optional, KScratch1KScratch2 and selects at 2, 3 are me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 345 KScratch Required. Figure 9.70Figure KScratch Table 9.89Table KScratch Release 6 - Registers (CP0 Registers registers are read/write registers are read/write registers registers n field specifies which of the selects are selects which of the specifies field KScrExist KScratchn KScratchn Fields EJTAG is implemented, select 0 should not be used for a EJTAG use and shouldbe used for a not

The Compliance Level: Pre-Release 6 - Compliance Level: Pre-Release Debug Mode software should not use these registers, instead debug software should use the isters are 32bits32-bitwidth infor isters are processors and 64bits forprocessors. 64-bit The existence is indicated by of these registers the The 63 Data 63:0 software. data saved by kernel Scratch pad Name Bits MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For 9.72 KScratch ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 346Vo For Programmers Architecture MIPS®

rs that implement bit is zero in the the in zero is bit ERL in an address error = 1 ERL through at MIPS64 processo 0x0000 0000 0x0000 FFFF 0x7FFF bit is one in the Status register. inisone bit the Status ERL through te that address error checking is stillte that done before 0x0000 0000 0x0000 FFFF 0x1FFF = 0 Status l mannerl MMU: to the TLB-based both they to map the ERL Generates PhysicalAddress through 64/microMIPS64supports Architecture a lightweight mem- Status 0x4000 0000 0x4000 FFFF 0xBFFF mapped using an identity mapping. ing an identitymapping when the TLB-based MMU. It is th TLB-based MMU. It is not anticipated through through me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 347 0x0000 0000 0x0000 FFFF 0x7FFF 0000 0x8000 FFFF 0x9FFF useg Table A.1Table Addresses Virtual from Generation Address Physical suseg kuseg kseg0 Segment Name Address Virtual lists all mappings from virtual to physicalNo addresses. Status register, and are mapped us register, Status low 512MB of physical memory. Address translation using the Fixed Mapping MMU is done as follows: done MMU is Mapping Fixed the using translation Address • in an identica translated are addresses Kseg1 and Kseg0 • Useg/Suseg/Kuseg addresses are mapped byadding 1GBvirtual to the address whenthe As an alternative to the full TLB-based MMU, the MIPS to alternative As an The main body of this specification describes the TLB-based MMU organization. Thismain appendixbodyThe TLB-based MMU organization. of this specificationother the describes describes potential MMU organizations. ory managementmechanism with fixed virtual-to-physicaltranslation, address memory and no protectionbeyond iswhat providedaddress by the error of checks required all MMUs. may This be useful for those applications which the capabilitiesrequiredo not full of a a fixed-mapping MMU will require a 64-bit address capability. As a result,As the description a is below given assuming a fixed-mappinga 64-bitrequire MMU will a address capability. 32-bit address. • addresses are Sseg/Ksseg/Kseg2/Kseg3 Supervisor Mode is not supported witha Fixed Mapping MMU. Table A.1 the translation process. Therefore, an attemptUsreference kseg0 from to er Mode still results MMU. TLB-based exception, just as it does with a A.1.1 Fixed Address Translation MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For A.1 Fixed Mapping MMU Alternative MMU Organizations MMU Alternative Appendix A Appendix

shows the memory are FFFF 0xBFFF = 1 Figure A.2 ERL ged Resource Architecture, Rev. 6.03 are inaccessible inaccessible 0x3FFF FFFF are through register is zero; through through through through 0000 0x8000 0x0000 0000 0x0000 0000 0xC000 FFFF 0xDFFF 0000 0xE000 FFFF 0xFFFF 0x0x1FFF FFFF 0x0x1FFF = 0 Status Status ERL Generates PhysicalAddress 0x2000 0000 bit in the Status ERL register. Status lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: register, and physical addresses register, through through through 0xA000 0000 0xA000 FFFF 0xBFFF 0000 0xC000 FFFF 0xDFFF 0xE000 0000 0xE000 FFFF 0xFFFF Status s that physical addresses addresses that physical s bit is on bit in the is bit is one. ERL ERL sseg ksseg kseg1 kseg2 kseg3 bit is off in thebit is off shows the memory mapping when the Segment NameSegment Address Virtual ERL Table A.1 Table (Continued) Addresses Virtual from Generation Address Physical inaccessible when the Figure A.1 Note that this mapping mean mapping this that Note mapping when the when the 348Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

. For register fields. Config reuses much of the hard- UNDEFINED cause a Reserved Instruc- a Reserved cause anism. This mechanism has eg1 are always uncached. always are eg1 registers registers are no longer required A.2 Block Address Translation s are necessary to the CP0 register necessary are s EntryHi describes the describes new R/W Undefined Required R/W Undefined Required Write Reset State Compliance manner as for a TLB-based MMU: the the MMU: a TLB-based for manner as Read/ , and to these to these registers are Table A.2 Wired , and references to ks to , and references , cation for instruction referencesdatareferences. and cation for instructioncation for references and data references, Config virtual addresses. It contains pairs of instruction/data rtual page number, a base page frame number (whose rtual page number, rtual address translation mech rtual translation (BAT) mechanism that translation (BAT) register; Field Descriptions Field Descriptions locationkseg2and of kseg3 virtual address regions. PageMask , BE AT AR MT 0 VI K0 Config s of a read or write of a s field of K0 16 15 14 13 12 10 9 7 6 4 3 2 0 Context , gisters were Reserved for Architecture. Reserved were if the registers reads return 0 as ignored, e for the Table 9.11 on page 150 for for the encoding of this field. this of encoding the for Description nd in the kseg1 are provided same nd coherency attribute nd coherency when 0 EntryLo1 , me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 351 cheability and coherency attribute. cheability and See Figure A.3Figure Additions Register Config the additionsthe to 0 Register Interface is zero. See See is zero. Table A.2Table Register Config ERL EntryLo0 , Status Table 9.11 on page 150 encoding of this field. encoding Random , shows the format of Index Release 6, writes to these registers ar registers Release 6, writes to these tion Exception. and may be removed. Pre-Release 6, the effect Pre-Release 6, removed. and may be Fields Figure A.3

entries which provideentries which the base-and-bounds checking and relo Each entry contains a page-aligned bounds vi respectively. The BAT is an indexed structure which is used to translate indexed structure is an BAT The This section describes the architecture for a block the architecture address This section describes interface: • The Relative to the TLB-based address translation mechanism, the address following change TLB-based Relative to the cacheability attribute for kseg0 comes from the The cacheability attributes for kseg0 a attributes cacheability The • and TLBRinstructionsno longerare required and must The TLBWR, TLBWI, TLBP, ware and software interface that exists for a TLB-Based vi for exists software interface that and ware the following features: •software. and both in hardware of the TLB-Based interface, e much as possibl as preserves It •provides It independent base-and-bounds checking and relo •provides It optionalsupport for base-and-bounds re KU 27:25 a cacheability Kuseg M K23 KU 31 30 28 27 25 24 K23 30:28 Kseg2/Kseg3 ca Name Bits A.2.1 Organization BAT A.1.3 to the CP Changes MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For A.2 Block Translation Address

V D . Figure A.4 C Table A.3 lid bit is off in the entry, a inlid the bit entry, is off can as follows: be described the selected entry, shifted to align selectedthe entry, ged Resource Architecture, Rev. 6.03 te to the reference type and address and type the reference te to t implemented, it is implementation- y (D) bit, and a valid (V) bit. (V) and a valid y (D) bit, (or kseg2 and kseg3) ed bounds address, or if the va sical address. The BAT process address. The BAT sical ional andional may be implemented addressas necessary to the ated. One alternative is to combine the mapping for kseg2 and ated. One alternative is to combine the mapping ftware may determine how many BAT entries are implementedare entries ftwaredetermine may howBAT many register. Type Region Address Reference Reference 12 itiated. Otherwise, base PFN from the Config1 BasePFN If entries for kseg2 and kseg3 are no are kseg3 and If entries for kseg2 a cache coherence field (C), a dirt field (C), a a cache coherence lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: || 1 || BoundsVPN Table A.3Table Entry Assignments BAT ) Figure A.4Figure Entry of a BAT Contents 01Data 23Data Instruction45Data Instruction useg/kuseg Instruction kseg2 kseg3 12 Entry Index BoundsVPN BoundsVPN ement of a BAT entry. ement of a BAT BasePFN C D V BAT[i] BAT[i] BAT[i] SelectIndex (reftype, va) (reftype, SelectIndex InitiateTLBInvalidException(reftype) InitiateTLBModifiedException() va + (pfn || 0  va + (pfn bounds  BAT[i] bounds c  d  v  then = 0) (v or (va > bounds) if endif then = store) and (reftype (d = 0) if endif pa i   BAT[i] pfn with bit 12, is added to the virtual address to form the phy is added to the virtual address to formbitwith 12, quested, the BAT entry that is appropria entry requested,BAT theaddress translation is a virtual When region is read. If the virtual address is greater than the select in off is and the D bit a store TLB Invalidthereference is exception appropriate referenceinitiated. typethe of is If in exception is TLB Modified a the entry, kseg3 into a singleinstruction/datapair of entries. So by lookingoffield the at the MMU Size dependent how, if at all, these address regions are transl if at all, these address dependent how, width is implementation-dependent), width is implementation-dependent), The BAT is indexedtyperegion reference by the as shown and the address to be checked in BAT The shows the logicalarrang required.2, 3, 4 andare and0 Entries 5 are opt 1 Entries needs of the particular implementation. A.2.2 Translation Address 352Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

UNDE- WI and TLBR instructions. WI and e registers are ignored, reads are ignored, reads e registers well as allows for a TLB that can that for a TLB allows well as sses. In small and low-cost systems, and low-cost systems, In small sses. s are necessary to the CP0 register to necessary are s ly, such fully-associative structures can fully-associative such ly, emented is not large. emented is not large. registers are eliminated. Pre-Release 6 the effects of a 6 the effects Pre-Release registers are eliminated. read or written by the TLB read or written by the a minimum. a This section an optional describes alternative A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual clearing the valid bit in the BAT entry. Settingthe bounds entry. clearing the validin bit the BAT to implement and can dissipate a lot of power. The number The number a lot of power. dissipate can and to implement Wired ssary. The TLBWI and TLBR instructions reference the BAT TLBWI The reference the BAT and TLBRinstructions ssary. , and register. The effects of executing a TLBP or TLBWR are The effects register. FTLB use a shared, common page size. size. a shared, common page use FTLB can be practically impl Index implementation costs of implementation costs a small TLB as ble to minimizeble tothe frequencymi of TLB . For Release . For Release 6, UNDEFINED writes to thes and Fixed-Page-Size TLBs PageMask so implementation specific. so implementation , me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 353 t a fully associativea fully t Joint TLB. Unfortunate tion uses twotion TLB structures. uses were Reserved for Architecture. were Reserved Context , CP0 Register Interface CP0 Register EntryLo1 register is the interface to the BasePFN and C, D, and V fields of the BAT entry. The register has has The register entry. BAT D,of the and V fields and C, the BasePFN to is the interface register , register is the interface to the BoundsVPN field in the BAT entry. entry. register is the interface to the BoundsVPN field in the BAT register is used to index the BAT entry tobe register is used to index the BAT , but processors, should signalInstructiona Reserved Exception. EntryLo0 Random Index EntryHi read or write to these registers are or write to read •isnot The FTLB fully-associative, but rather set associative. • Theways numberperimplementation of set is specific. • Thesets number is implementation of specific. • The commonpagesize is al • the within entries all time, one any At the same format as for a TLB-based MMU. for a TLB-based the same format as FINED entry whose index is containedthe in return 0 as if the registers • The • The 1.Fixed-Page-Sizethe This first TLB is calledor the FTLB. TLB This alternative MMUThis alternative configura be slow, can require a large amountlogic components of can require a large be slow, of entries for fully a array that associative Most MIPS CPU cores implemen CPU cores Most MIPS slation mechanism, the translation mechanism, following change address TLB-based Relative to the interface: • The Inhighperformance systems, it is desira Making out-of-bounds all addresses onlycanby be done value tovalue first zero leaves the virtual page mapped. • The •and TLBWRinstructions are unnece The TLBP map number a very large of pages to be reasonably implemented. it is desirable to keep the implementation costs of a TLB to a TLB of the implementation costs keep it is desirable to MMU configuration which decreases the A.3.1 Organization MMU A.2.3Changes to the A.3 Dual Variable-Page-Size MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. bits of the specified virtual the specified bits of ing systems, on-demand pag- systems, on-demand ing and a FTLB with a larger FTLB with a larger and a e FTLB. are Implementations eam and the data stream. For data stream. the eam and register. The size of the VTLB register. ged Resource Architecture, Rev. 6.03 Config4 array size. The methodThe of choosing array size. - in FTLB page that case, the is fixed size by hard- configuration by software can only be done after a after done be only can software by configuration nd fixed-sized pages as wellsmall as for number a of the FTLB. In most operat In most the FTLB. use a page size that is dif- is a page size that use VTLB entry can That is, one ies is not guaranteed to work where the implementation dual FTLB and VTLB is denoted by the value of 0x4 in any valid entries within th nfigurable.thechoice The common of is done page size purpose. Someof the address a smallerof entries number TLB with many entries can be much less than that of than less much entries can be with many TLB register is used to program the page size used for a partic- between the instructionstr “ChangesRegisters”the to COP0 page on 357 LB entries is implementation specific. C0_PageMask presented to presented both the FTLB and VTLB in parallel. Entries in both structures ed in the FTLB fields within the new llowable at a specific TLB index. llowable at a specific able-Page-Size TLB or the VTLB. able-Page-Size TLB lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: LB as appropriate for FTLB the chosen field. The presence of the field. The ch for the physical address. lly-associative TLB. lly-associative MMUSize-1 Config1 register field. are describedThese registers in once for the entire FTLB, not on a per-entry basis. This basis. once for the entirea per-entry on not FTLB, full flush/initializationthe before there FTLB, are of also allowedFTLB the to support one only for page size ware and not software configurable. configurable. software not and ware invalid TLB to represent reserved address values entr can limit what addresses are a what addresses can limit ferent from the size used by another VTLB entry. entry. VTLB by another used the size ferent from MT • The commonpageallowed size is software co to be • The required EHINVis FTLB implementation. for TLB invalidatefeature legacy The method of using implementing a large fu implementing a large • The VTLB is fully-associative. • Theisentries implementation number of specific. • TheofVT set allowable sizes for page • basis. Thepage choiceper-entry onis done of size a without consuming a large numberwithoutin of entries the FTLB. consuminga large ular VTLB entry. ular VTLB entry. The configuration of the FTLB is reflect ing only uses one page size so the FTLB is sufficient for this ing for only uses one pagesize so the FTLB is sufficient indexaddress are used to into FT the which FTLB way to modify is implementation specific. The VTLB is very similar to the The JTLB. is reflected in the is Config large address blockslarge toMMU. the be simultaneously mapped by Most implementationswouldchoose to build a VTLB with combinationThis ofnumber entries. allows for many on-dema 2.Vari the TLB is called The second •sections of physical memory pages to mapthe large The capabilitya VTLB retains existence of oflarge using in MMU mainly the happens in of pages Random replacement The use of two TLB structures has these benefits: • The implementationbuilding costs of a set-associative address translation, the virtual address is translation, the virtual address address parallel to sear in are accessed Just as for the JTLB, both the FTLB and VTLB are shared JTLB, both for the Just as 354Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

regis- regis- 1 / C0_Random C0_EntryLo0 and x bits needed to select the needed to x bits plementation specific whether a plementation specific C0_EntryHi acy method of representing an invalid acy method ed FTLB way and set, and incremented and ed FTLB way Inanyindexing scheme, the least signifi- and TLBWRinstructions. tries. This register to choose is also used which BWR instruction modifies entries within the FTLB ll be modified for thiscase. struction, it is possible for software to choose an inap-software struction,for it is possible (VIndex) leastsignificant(VIndex) bits of the 2 FTLB. Since it is implementationas to whether defined a A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual anteed to work. anteed to (FPageSize)+1. The number of inde number of (FPageSize)+1. The 2 array are accessed through the through array are accessed accessed with the TLBWI accessed ndex to VIndex + (FSetSize * FWays)-1. (FSetSize * FWays)-1. + to VIndex ndex lue is the concatenation of the select for a specific virtual address, the leg specific virtual address, for a (FSetSize). which canbeusedby the TLBWI instruction without modification by soft- 2 ss value is not guar notis ss value e FTLB as well as the VTLB use one tag (VPN2) to map two physical pages tag (VPN2) to map one use as the VTLB as well FTLB e ted for the TLBWI instruction. ple, {selected FTLB Way, selected FTLB Set} selected + VIndex. ple, {selected FTLB Way, me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 355 s in one way of the FTLB. of s in one way ructions; the VTLB occupies indices 0 to ructions; the VTLB occupies indices 0 to and inst TLBR TLBWI the TLBP, registers, on specific whether the VTLB wi array is indexed is array is indexed is implementation specific. used by the FTLB entries LB. The entries in either in entries LB. The C0_Wired , the isnotto set the page size used by the FTLB, the TLBWR instructionwithin modifies entries the is set to the page size used by the FTLB, the TL page size used by the FTLB, to the is set register is used to set the page size for the VTLB en the page size for the VTLB register is used to set C0_Index PageMask C0_PageMask C0_PageMask The VTLB. The VTLB entry to be written is specified by the log How the FTLB set-associative by the size of the VTLB. For exam size of by the If VTLB. It is implementati the or log can be used for indexing is that bit cant address VIndex-1. The FTLB occupiesVIndex-1. VI indices The TLBP instruction produces a value referringware. When to the FTLB, the va Since the FTLB array canbemodified throughthe TLBWI in propriate FTLB indexim value forit is the specified virtualcase, In this address. Machine Check exception is genera Machine required for a is feature invalidate TLB entry EHINV The particular FTLB index value can be used (PFN), just as in the JT (PFN), just as The software The software programming interface used for the JTLB is fully-associative maintained as much as to possible amountdecrease the of software porting. th each entry in Also for that purpose, correct set withinFTLB thearray is log ter value. ters. Entries in either array (FTLB or VTLB) can be array (FTLB or VTLB) to write for the TLBWR instruction. the TLBWR for to write VTLB) or (FTLB array used:Forare followingofthe this section, the rest parameters 3.size FPageSize - the page 4.of entrie FSetSize - Number 5.FTLB. Numberthe - of ways within a set of FWays 6.Number VIndex - of entriesVTLB. in the For the The method of choosing which FTLB way to modify is implementation specific. If TLB entryusing by a predefined addre A.3.2Interface Programming MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

. (FTLB and VTLB) arrays and VTLB) arrays (FTLB C0_Index (a value within VIndex to VIn- ged Resource Architecture, Rev. 6.03 using virtual19:13.address bits The eck exception is generated for these is exception these cases. generated for eck for way selection within the FTLB. the within selection way for e specified virtual e specified address. . de the selected FTLB set as opposed to which bits are tation specific whether both tation values VIndex to VIndex+(FSetSize * FWays)-1 access VIndex to VIndex+(FSetSize * FWays)-1 values on specific, but must match what is expected by the specific, but must match what is expected on reflects the page used by the size FTLB. C0_EntryHi iswide 3 bitsentry to select the within the VTLB. specifiestheentry within the VTLB (a value withinto VIndex-1). 0 specifies the entry within the FTLB specifies the entry within the read depending on the specified index in read depending C0_PageMask ich starts at virtual12. address bit FTLB set- is indexed array is FTLB set-associative lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: C0_Index C0_Index are probed in parallel for th for are probed in parallel C0_Random ructions; the VTLB occupies indices 0 to ructions; the VTLB occupies indices 0 to and inst TLBR TLBWI the TLBP, registers, implementation chooses these values: these values: implementation chooses gn uses a cycle counter of 2 bits of 2 bits counter a cycle gn uses e address bits held in overlapping entries and overlapping whether Ch a Machine index bits are needed. index C0_Wired , the register field within C0_Index Random If the address hits in the the in FTLB, hits the address If Index values of 0 to VIndex-1 access the VTLB. Index the VTLB. to VIndex-1 access 0 of Index values the FTLB. Both the the the VTLB and FTLB Both FTLB entry is a VTLB entry or Either a If the address hits in the VTLB, the in VTLB, hits the address If ping (512 entries x 2 pages/entry x 4 kB/page) 4MB of address space simultaneously. space 4MBof address x 4 kB/page) pages/entry 2 x ping (512 entries dex+(FSetSize * FWays)-1). Which bits are used to enco dex+(FSetSize * FWays)-1). used to encode the selected FTLB way is implementati the selected used to encode TLBWI instructionimplementation. TLBWR instruction uses thes 7. The FTLB occupies indices7. 519. 8 to The FTLB entries have a VPN2 field wh index the FTLB significantbitvirtualleastbe used for FTLB indexingcan address that virtual13.The is To address 7 set-associative array, thisIn simple the example,uses design contiguous address virtual bits directly for indexingthe (it FTLB cre- does not ate for the FTLB indexing). a hash The TLBWI TLBP TLBR As an example, let’s assume an assume As example, an let’s 1.FTLBentries - 4 kB used by the FPageSize 2.thein FTLB. - 128 FSetSize of one way 3.4 ways within FTLB. (TheFTLB the - ways/set)4 of a set xhas (128 512 sets entries, capableof map- FWays 4.VTLB.8 entries in the - VIndex For the are checked for duplicate or duplicate for are checked For both the TLBWR and TLBWI instruction, it is implemen In this simple example, the desi The A.3.2.1sizes VTLB and FTLB chosen with Example A.3.3 to the TLB Instructions Changes 356Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

is not for more for field is not field is Config4 fields reflect the . VPN2 . d to reflect only the size FTLBSets for is appropriate the specified and register field mustbeset to a register. C0_Index C0_Random e TLBWR instruction modifies modifies a e TLBWR instruction Config4 C0_EntryHi MMUExtDef FTLBWays , tion is implemented. If either registerredefine field is TLBWR modifies either a FTLB entry or a VLTB or a VLTB entry FTLB TLBWR modifies either a Config4 field of values VIndex to VIndex+(FSetSize * FWays)-1 access VIndex to VIndex+(FSetSize* FWays)-1 values VPN2 fied. The FTLB set-associative array is indexed in an indexed array is fied. The FTLB set-associative A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual FTLBPageSize MMUSize-1 nding on the specified page size in C0_PageMask. C0_PageMask. size in page nding on the specified generate a machine-check exception if the a machine-check exception generate than that used by the FTLB, th the FTLB, used by than that bythe Random register within field s a Machine Check exception for these cases. for these Machine Check exception s a s a Machine Check exception for these cases. for these exception Machine Check s a field is not fixed to 2 or 3, the Dualfieldtheor VTLB/FTLB configuration2 is not fixed to 3, is not “Configuration Register 4 (CP0 Register 16, Select 4)” on page 279 is reserved; for the see the description e hardware checks(FTLB and VTLB) for valid both duplicateor over- arrays

flect the FTLB configuration. me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 357 the Dual VTLB and FTLBconfigura the Dual VTLB and if the hardware the if the hardware checks MMUExtDef specific which array is modi array is specific which MMUExtDef is fixedofa value to 2 or 3, the is fixed to a value of 2 or 3, the 3, is2 or fixed to a valueof

Config4 is set to any page size other is set to the page size used by the FTLB, the to the page is set Config4 is fixed to a value of 4, the implemented MMU Type is the dual FTLB and VTLB configuration.FTLB is the dual value4, the implementedis fixedto of a MMU Type

MMUExtDef MMUExtDef MT Config Config4 C0_PageMask C0_PageMask Config4 detail on thisregister. For Release 6, value ofvaluethatreflect 2 or 3 to set within the FTLB. The implementationset within FTLB. The the may implemented or the If implemented. If Index values of 0 to VIndex-1 access the VTLB. Index the VTLB. access to VIndex-1 0 of Index values the FTLB. It is implementation specific Either the VTLB or FTLB entry is writtenorEitherFTLB entry is depending the VTLB the specified index on in appropriate for the specified set. specified appropriate for the It is implementation-specifithe hardwarec if and VTLB) for(FTLB checks both valid arrays over- duplicate or lappingentriesif the hardware signal and A new register introducedre to of the VTLB. If FTLB configuration. Please refer to VTLB entry. The VTLB entry is specified VTLB entry. implementation-specific manner. implementation-specific manner. selectingThe methodwhich of modify FTLB way to is implementation specific. It is implementation specific if th lappingentriesif the hardware signal and entry. It is implementation entry. If Either the VTLB or FTLB entry is writtenorEither FTLB entry is depe the VTLB If C0_Config4 (CP0Register 16, Select 4) C0_Config (CP0 Register 16, Select 0) C0_Config1 (CP0Register 16, Select 1) TLBWR A.3.4Registers to the COP0 Changes MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

C0_Index C0_RANDOM odified by a TLBWR ld a value of VIndex-1orld a value of zes are available in the VTLB. register field. field. register select the VTLB entry which is mod- ged Resource Architecture, Rev. 6.03 or the FTLB is m is FTLB the or the FTLB, and a TLBWR instruction is exe- TLBWR instruction is FTLB, and a the FPageSize e FTLB, and a TLBWR instruction is exe- FTLB, and a TLBWRinstruction is e MMU are the values reported in the the TLBWI instructionimplementation. ementation specific the whether Config4 register field can only ho entry in the FTLB or the VTLB. Index values of 0 to FTLBor the VTLB. Index values entry in the VIndex+(FSetSize * FWays)-1 access the FTLB. access the * FWays)-1 VIndex+(FSetSize fields reflect what page si this alternative MMU configuration, the value reflects both Wired MaskX and Random register field is used to sizes which are available in the FTLB. Mask register field value is VIndex. register field value is entry is modified. It is impl ispage-size set to theth used by is not set to the page-size used by lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: set when a FTLB entry is specified. set when a FTLB entry is anges introduced by this alternative alternative introduced by this anges but mustbut match what is expected by Random field values determine whether the VTLB field values determine whether the entries.TLB address matchFTLB operationthe The for affect fields do not register ster 5, Select 0) is fixedofa value to 2 or 3, the is fixedofa value to 2 or 3, the register is redefinedin this way: is fixedofa valueregister 2 or 3, the toin is redefined way: this is fixedofa value or 3, the register to 2 is redefinedin this way: MaskX MaskX C0_PageMask C0_PageMask and and MMUExtDef MMUExtDef MMUExtDef MMUExtDef Mask Mask

The VIndex-1 access the VTLB. Index values VIndex to values VIndex Index VTLB. the VIndex-1 access Which bits in the register field which encode the FTLB set as opposed to which bits encode the wayFTLB is implementation specific, The value held in the Index field can refer to either an in the Index field can The value held If the value in The software writeable bits in the cuted, a FTLB entry or a VTLB or a entry cuted, a FTLB cuted, a VTLB entry is modified. The is entry VTLB cuted, a ified. the value in If register is used to select the FTLB entry. FTLBentry. register is used to select the boundThe upper of the These fields do not reflect the page not reflect the do fields These page size used by the FTLB entries are specified by the entries are specified by the page size used by the FTLB instruction. The Config4 Config4 Config4 Config4 For Release 6, this register has beenthis register deprecated. has For Release 6, If If less. That is, only VTLB entries can be wired down. If If C0_Random (CP0 Register 1, Select1, 0) C0_Random(CP0 Register C0_PageMask (CP0 Regi (CP0 C0_PageMask a selected way as well as a selected well as selected way as a register. Previously, it was just a simple linear index. For Previously, register. One of the main software visible ch C0_Index (CP0 Register 0, Select 0) Select Register 0, (CP0 C0_Index C0_Wired (CP0 Register 6, Select 0) C0_Wired A.3.5 Compatibility Software 358Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

registerfields must VPN2 bits to VPN2 bits index FTLBSets EntryHi register. register. Config4 acy method of representing an invalid of representing acy method and C0_Index FTLBWays ction. Software then justissuesinstruc- TLBWI the ed for wired-down pages, so this restriction should not Config4 , FTLB. Since it is implementation-definedto whether as a A.3 TLBs Fixed-Page-Size and Variable-Page-Size Dual anteed to work. work. anteed to , that page, thatbe programmed must into the the VTLB using field no longer field no longer initial- size. For TLB reports the entire MMU MMUSize-1 appropriately modified. appropriately MMUSize-1 Config1 for a specific virtual address, the leg address, specific virtual for a of TLB entries that must be initialized. TLB initialization and flushing are ss value is not guar notis ss value me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 359 registers have been have registers * C0_EnLo registerupon instru a TLBP by hardware is generated Another software visible change is that the change is that the software visible Another ization flushing, and TLB contentsthe of tion once the Only the VTLB entriesOnlymay the VTLB be wired down. This limitation toisduesome using of the Fortunately, this Indexfrequently valueisn’t generated by software norFortunately, byread software. Instead, the contents of the C0_Index all be number read to the entire calculate the onlysoftware times to generate an Index needs write to value into the TLBWI instruction, as the TLBWR would instruction only access the situation and could not any in that FTLB access instruction The TLBWI is normally us wired-down TLB entry. existing software. affect required for a is feature invalidate TLB entry EHINV The particular FTLB index can be used value the FTLB array. downwiredto a pageusing be the FTLB page-size is If TLB entry byusing a predefined addre MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: 360Vo For Programmers Architecture MIPS® Alternative MMU Organizations Alternative

, IntCtl, PageGrain, chitecture. Changes Changes chitecture. pseudo pseudo code to deal ft Reset Exceptions. ft Reset acknowledge the fact acknowledge the ng and virtual tags. location discussion. location show an example of the need need of the example an show ve been updated ve to reflect the documentation. Release 2 of the Ar of the Release 2 ed: Cause, Config, Config2, Config3, Config3, Config2, ed: Cause, Config, the list of exceptions that do not go through the list of exceptions that do not go through both virtual both virtual indexi rewritten to reflect the Release 2 changes. Release the to reflect rewritten chitecture added: EBase, HWREna s between Reset and So neral exception processing exception neral e TLB lookup process to , PerfCnt, Status, WatchHi, WatchLo. WatchHi, , PerfCnt, Status, note that both BadVPN2 and R fields are UNPRE- fields and R note that both BadVPN2 Description B entries to be 3, not 2, and entries to be 3, not 2, and B supported with a Fixed Mapping MMU. supported with a Fixed Mapping gisters were modifi gisters were mory, exceptions, and hazards ha exceptions, and mory, may support all page sizes. all page may support implementation-dependent. organized and updated ar and updated organized for external review release ation with the changes introduced in the changes introduced with ation to denote an instruction cache with cache instruction an to denote VI sed on review feedback: sed me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 361 with extended MIPS16e instructions. with extended MIPS16e SRSCtl, SRSMap. the general exception processing mechanism. error after an address exception. DICTABLE EntryHi, EntryLo0, EntryLo1, PageMask 2. Release in changes that not all implementations for 3. for • Config Add in this revision include: • new Coprocessor 0 registers following were The • Coprocessor 0 following The re • me descriptions of Virtual The •adjustment in ge offset incorrect branch Fix • description to register XContext Correct • that Note Supervisor Mode is not • bits 4..3 as Define TagLo • Describe the intended usage model difference •added. shadow registers has been GPR chapter on A • chapter on has been The CP0 hazards completely • vector Debug entry the EJTAG in Change ProbEn to ProbeTrap • exceptions Debug to error and EJTAG cache Add •of TL Correct the minimum number • Modify the description of PageMask and th 0.9512, 2001 March document Clean up 1.0029, 2002 August ba Update 0.92 January 200120, copy of re Internal review 1.90 September 1, 2002 specific Update the Revision Date MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For Revision History Revision Appendix B Appendix

to the Fixed Mapping Mapping Fixed to the red in certain combinations of red in certain combinations the time that the processor that the the time be gated by be gated by enable. 1K page ference for the purposes of the purposes the for ference d that software which preserves d that software which preserves Config registers should be field and a RDPGPR and WRP- register should be a R/W bit, not a register rrupt via an ERET. bit to indicate that bit the controls PSS and ged Resource Architecture, Rev. 6.03 registers. PCI IP1 0 Status to zero in all bit positions less than or equal equal or than less positions bit all in zero to set to 0b11 on a Release 2 chip in ker- which set to 0b11 Status definition as a pointer definition as rnal Interrupt Controller Interrupt Mode to rnal Controller Interrupt Interrupt note that the SRSCtl register is not updated at ange hazards for writes ange hazards to interrupt-related Cause the software interrupt handler runs. interrupt Software the software table, and document that DERET, ERET, and and ERET, table, and document that DERET, PS MT and MIPS® DSP present bits in the in the bits DSP present MIPS® PS MT and PerfCnt ility of triggering a triggering ility of the probab ich reduced = 1. 15 12 nges. These include: nges. These BEV , and Description en using VI modes. or EIC Interrupt able to Operating Modes chapter. Modes to Operating able mply dismiss the inte register as access enablesimplementation-depen-for the the registerscorrectly. willalso run Status upt being deasserted between deasserted between upt being ve reference load is a data re ll hazards before the instruction fetch at the target instruction. target at the fetch the instruction before ll hazards lease 2 cha lease 2 sk register power up zero and up zero register power sk e e vector offset. This is only e vector requi offset. Compare vs. an execution hazard. dependent bits in the the bits in dependent HWREna clude R ftware must set EBase Cause, , going to the EIC, rather than Status than rather EIC, the to going Status IP1 0 registers. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Watch Config3 register. detects the interrupt request and the time that that time the and request the interrupt detects si and case this for prepared be must a clear exceptions and interrupts R bit. This eliminates the This eliminates of problem having these bits support. page enabled 1K not has software nel 0xBFC0.0300,. not 0xBFC0.0200. in which the end of an exception GPR and instruction hazard GPR and change that introduced EBase. that introduced change the in fields dent hardware registers 31 and 30. and registers 31 hardware dent will run, an standard boot software such a way that defined in the value of the field when writing MMU appendix. allowed. are the performance counter, not the timer interrupt. timer not the counter, performance the show Cause to the most significant in th bit most significant to the vector number and vector spacing wh machine check. • a hardware interr note about Add • list Add of MIPS® MT CP0 registers and MI • that so restriction Add • hazards the CP0 of organization Improve the • PageMa of the bits 12..11 Make • cache be address of the error vector when the the is It should Correct BEV bit 1. • to shadow registers to introduction the Correct • 2 Release the reflect to description exception error cache the in pseudo-code the Correct • Document that EHB clears instruction state ch • Clarify thatPC-relati a MIPS16e • Update allfiles to FrameMaker 7.1. •requirements. reset 2 Release missing reflect to list exception reset Update • bits 31..30 in the Define • that Note implementation- • in the FR bit the Architecture 2 of the Release With • for Coprocessor definition Add 0 En • K23 Add and KU fields to main Config register • specific note about Add all shadow sets between the need to implement 0 and HSS - no holes • SRSCtl the to write software a from hazard the Change • Interrupt the figure Generation Correct for Exte • suggested software Add TLB init routine wh • the encoding table description for Correct the 2.00 9, 2003 June Complete the update to in 2.50 July 1, 2005 Changes in this revision: Revision Date 362Vo For Programmers Architecture MIPS® Revision History

and and , FDCI bit bit , FDCI Config4 register for C0_Config3 C0_PageMask EIC an explicit vec- EIC driving MT was incorrect in saying only saying incorrect in was ion Vector. Changed to Changed ion Vector. Config tion description. tion Exception Type table. Type Exception register. register. register affected. C options - RIPL=VectorNum, Explicit Vector- Explicit - RIPL=VectorNum, C options IntCtl ’t have a fixed reset value. ’t iguration to Appendix A iguration to Appendix and TLB; just can’t be used for mapping. be used for TLB; just can’t selected debug selected debug except HWENA cess is allowed to CDMM region. Description COP0 Register, CDMM bit in CDMM bit COP0 Register, nal meanings for CCA values. values. CCA for meanings nal ation pseudo-code for EIC Option_3 (EIC sends entire vec- sends entire (EIC Option_3 EIC for pseudo-code ation COPUnusable Excep COPUnusable ProbEn larger than 256MB are supported. larger . CDMMBase COP0 register ng EJTAG & PDTrace Registers & PDTrace ng EJTAG Config4. denoted by 0x4 in configuration CDMMBase release for internal review: release release for internal review: release for internal review: release release for internal review: release release for internal review: release release for internal review: release

a bunch of missing ones missing of bunch a register and access to it viathe instruction. RDHWR C0_PerfCtl are actually R/W actually are e ERL behavior description behavior description register description, the ERL affected. affected. . accessed through $3 not $4 - UserLocal Status ProbTrap me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 363 C0_Cause register field in and IPFDC Add the Add C0_DataLo/Hi ECR tor). Num; Explicit VectorOffset. Num; Explicit VectorOffset. tor offset (not using VectorNumbers). VectorNumbers). using (not tor offset 29 bits of kuseg becomes 29 bits of kuseg becomes uncached and unmapped. C0_Config3 in these new MMU configurations • • fixed. typos Various • ksseg/sseg about - footnote Modes Operating • extensions customer for usable longer COP3 no •RIPL != VectorNum Mode allows EIC • - added missi CP0Regs Table • • table Hazards - added • - Added BigPages feature Pages • Added TLBP -> TLBWI hazard • in field KScrExist Added • Added statement that only uncached ac • traditio MIPS Technologies Added • to Added list of COP2 instruction •Oper Handling Exception Updated • • Fixedcomments for ASE. •Enable Bit in CDMM Added •used to init can be values Reserved CCA •doesn Field CDMMBase_Upper_Address • to C0_Cause Disabled Exception Added DSP State •ECR incorrectly saying was Table • Clarified the text and diagrams 3 for the EI • 2.70, was actually missing the option of - revision mode new EIC • to bit added PCTD • scratch registers. kernel as 2 & 3 31, Select Reg CP0 Added • conf optional MMU VTLB/FTLB Added • chapter, CDMM Added 2.60 June 25, 2008 Changes in this revision: 2.802009 July 20, •VTLB MMU and FTLB 2.61 August 01, 2008 • In the 2.702009 January 22, MIPS Technologies-only 2.732.742009 April 22, MIPS Technologies-only 03, 2009 June MIPS Technologies-only 2.7512, 2009 June MIPS Technologies-only 2.722009 April 20, MIPS Technologies-only 2.712009 January 28, MIPS Technologies-only 2.62 2,009 January • CCRes is Revision Date MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ended, but additional r future debugger use. r future correct. PTEVld bit is only PTEVld correct. ontext registers and the rela- and registers ontext go into the BadVPN2 field was BadVPN2 field go into the able if Config3.CTXTC=1 and Config3.CTXTC=1 able if ged Resource Architecture, Rev. 6.03 lect 1 is reserved fo - selects 2&3 are recomm are 2&3 - selects width to be more compatible to MIPS32. MIPS32. to compatible more be to width for RI & XI bits. & XI RI for onControl/EVA. onControl/EVA. Description ContextConfig and registers. and XContextConfig ContextConfig s - be more explicit of the SEGBITS limitations. limitations. of the SEGBITS s explicit - be more t. Config5 register added. updated for RI & XI bits. RI & XI for updated evious description wasn’t fully description wasn’t evious for internal review: for internal PN2 field within Context and XC within PN2 field pdated for SmartMIPS behavior. SmartMIPS behavior. pdated for ption codes instead of exception using own their to use programmed gister allowed to be write- in EntryHi and WatchHi. in EntryHi and WatchHi. r Segmentati d for RIE and XIE bits. XIE RIE and d for description added. description Table Walking Feature Walking Table release for internal review: release release release for internal review: release for internal review: release for internal review: release release for internal review: release to C0 Register list. list. to C0 Register

fg1, SegCfg2 registers fg1, SegCfg2 scriptions updated scriptions updated e moved from e moved SmartMIPS ASE. se register added. se register dInstr & BadInstrP registers. lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: used for Directory PTE entries as leaf PTE entries are always loaded from memory. from memory. loaded always are entries PTE leaf as entries PTE Directory for used scratch registers are scratch allowed. 31:31- are bits VA correct The is used. register when the ContextConfig case the for incorrect for MIPS64. ((X-Y)-1) for 63:63-((X-Y)-1) MIPS32, TLBL code. Only. Config3.SM=0. within bits writable the with tionships • - pr Walker Hardware Page Table • Added TLB init routine fo •in ContextConfig Register is only 32-bits • register updated Config3 for CTXTC and RXI bits. • C0_Status. and ASE bits in C0_Cause Reserve MCU • Clean up description for KScratch registers • register. Debug2 Added • bit. Status.FR of change after UNPREDICTABLE are registers FPR • not support CCA=0 did 1004K • - Registers, Config4 KScratch mention that se • bits Context Register - the bit VA subscripts describing which • MIPS32 compatibility location for RI/XI EntryLo bits. • suppor Exception handling Nested •register update PageMask • Hardware Page Added • description and pseudo-code TLB •added: scheme Control, EVA Segmentation a) Adds SegCfg0, SegC • extended ASID field Added • ContextConfig Register b) SegCtl - Modifies EBase, Config3. • Invalidate TLB feature. • u description Context Register • register de EntryLo* • features added microMIPS • ASE MCU features added. • and RI exceptions can XI be • to be Read- allowed are RIE bits as and RI can XIE XI and be independently implemented • added Register TCOpt •BadV the the limits of Explain •cache way. one (0x7) for 32 sets for Added encoding • bits of C0_Context Lower re 3.112011 April 24, Technologies-only MIPS 3.51 October 2, 2012 MIPS Technologies-only 3.1417, 2012 February Technologies-only MIPS 2.8122, 2009 September Technologies-only MIPS 3.132011 November 10, Technologies-only MIPS 3.002010 March 8, • RI/XI featur 2.822010 January 19, MIPS Technologies-only 3.12 2011 April 28, •register XContext & XContextConfig 3.50 201220, September • Ba Added 3.10 2010 July 27, • register. XContextConfig Add 3.052010 July 07, • CMGCRBa Revision Date 364Vo For Programmers Architecture MIPS® Revision History

in Register table. in Register s the largest value sup- largest s the eld Descriptions, FR r zeroing out read-only read-only out zeroing r if is sup- floating-point oldest in machine. Meaning- machine. oldest in in Cause exception types. Cause in riptions, AR bit (Architecture revision extension bits (of EntryLo,TagLo) if extension bits (of EntryLo,TagLo) write of all 1s return all of write Release 5. Like Release 3, all features intro- features all 3, Release Like 5. Release sufficient for their purpose. Less testing. sufficient t to 0, but the current POR solution is for 9.41 Status Register Register Fi Status 9.41 Directory PTE entries can represent power-of- represent PTE entries can Directory registers and control bits and registers le. HW is responsible fo e, not supported in MIPS32, in MIPS64 only Registers match on 2nd half Registers match of microMIPS odel required is required, is required, odel required not mean mthc0/mfhc0 are implemented. implemented. are mthc0/mfhc0 mean not from list of extensions. COP0 registers requiring Description to initialize the Watch , TagLo, CDMMBase, CMGCRBase CDMMBase, , TagLo, d to record different types of Machine Check Exceptions. Check Exceptions. types of Machine d to record different Register Field Desc Field Register e available in kernelmode. Re-iterate that. that. Re-iterate in kernelmode. e available hould not contain comment about nd Virtualization exceptions nd Virtualization r a ig3.LPA, Config5.MVH ig3.LPA, DSP ASEs -> Modules now deprecated. ng Dual Page Method. ng Dual ent change: ude MSA and Virtualization ude MSA and Virtualization t me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 365 ported. Section 3.5.2 64-bit FPR Enable. Table Section 3.5.2 64-bit ported. FPR Table Enable. (floating-point register mode) bit. register mode) (floating-point level). AR=1 indicates Release 2 or Release 3 or 3 or Release 2 level). AR=1 indicates Release duced in Release 5 are optional. instruction. region, usi memory 4 ful to Speculate=0. Moved outside sub-table. ful outside to Moved Speculate=0. PageGrain.ELPA=0. HW had been asked to rese to been asked HW had PageGrain.ELPA=0. mtc0 to 0 out the extension bits that are writab that are bits the extension 0 out to mtc0 ported. bits on operation that updates the bits. which is up to 36b The two registers support PA Fur- of multiple. instead one bit to query for software it is easier in the future, of XPA dently on 64-bit HW need ther Config3.LPA=1 AAR initial version AAR initial •- MT and changes R5 •MDMX - changes R5 • by hardware” -> “Preset “Preset” •logos cover Update •text copyright Update •- include R5 changes MSA a • 9.57 Config Table R5 extension: •featur Pages Big BPG, 9.59 Table Correction: • FTLB/VTLB - if PageMask set to FTLB size, allowed to modify VTLB. • whether implementation-dependent • - added option so Walker Hardware Page Table • PageGrain.MCCause fiel Optional •- MAARI.Index to sw write of condition a Added • MAAR, MAARI and Config5.MRP Add •s 1.1 typo. Speculate=1 Table • extended EntryLo0/1, LLAddr Add • Conf PageGrain.ELPA, •having about SW comment Remove • Remove CDMMBaseCMGCRBase and •0. Since mth/mfhc0 may be used indepen- for mth/mfhc Config5.MVH, bit, a config Add 5.01 December 16, 2012 • technical cont No 5.02 2012 April • m FPU register changes: FR=1 R5 64-bit 3.52 12, 2012 November • segment(s) Overlay SegCtl 5.00 December 14, 2012 • - incl changes R5 5.04 September 29, 2013 M 5.03 September 9, 2013 • Update documen 5.04 November 12, 2013Version. initial XPA Revision Date MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

). Table 9.2 field. n bits now are required. ). register. SW must now must must now must SW register. Mask ged Resource Architecture, Rev. 6.03 Table 9.2 : no longer required : required to no longer write specified values while s/w can only set to 1. only s/w can while d significantly. required, all other values are optional all optional and required, other values are must be 1. must P register leaves it unmodified. it leaves register

does not modify register. ported values to the Wired field. Wired ported values to the ULRI EntryHi Index , : hardware unsupported values to the C : hardware ignores writes of C n encoding 2 has changed. before changing a value in this changing before Config3 bit field. d if an value d if an unsupported is written. CFG

, : now required. : must now be 1. PageMask n tionality has change , : HW ignores a write of 1; ; now R/W0 (see R/W0 ; now of 1; write a : HW ignores Limit BI RXI explicitly using TLBWI. NMI bit. bit. register. SegCtl , RP TS Cofig3 and KScratch BadInstrP, BidInstr, UserLocal, PTEI Config3 KU Status / : now required. : write of unsupported value : new field. : write of 0 value is ignored. EntryLo0/1 andom , : HW ignores writes of unsupported values to the to values unsupported writes of : HW ignores and and : now required. : now will be unchange and : now required, and required, now : : HW ignores a write of the value. the of a write : HW ignores : HW ignores a write of 1; R/W0 (see now K23 R Status Status n upported values of this field. values of unsupported of ignore writes : HW must : now required. Also, now required. : : in field size. change and / : FR= 1 now mandatory; FR = 0 now obsolete. ULR : writing unsupported values to this : now required. : now PTW PTEI BP SBRI C : HW ignores writes of values. reserved WP AR ULRI K0 bit 28: new name and changed functionality. and name new bit 28: changed functionality. and name new bit 27: CU FR SR KSU bit 25 and bit 21: now reserved. 21: and bit bit 25 lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: PWField : added a required : hardware ignores writes of unsup ignores writes : hardware : If value greater than, or equal to, the number of TLB entries is written, HW leaves this this leaves HW is written, entries TLB of number the to, or equal than, greater value : If Reset value changed to 2. is 2 illegal, are values 0,1 that Clarified implementation-specific. PTEI VS Config5 Wired RDHWR Wired Cause Config3 Cofig3 Config4format and func : field. Index register unchanged. EntryLo BadInstr required. BadInstrP: now Status Status Status Status Coprocessor 0 Coprocessor UserLocal Status IntCtl KScratch PageMask Status Status PWSize Config PWField PWSize invalidate TLB entries entries TLB invalidate to certain fields and flush TLB TLB flush and fields certain to Config PageGrain • • • • • • • Removed • Removed • • • COP0Index: Clarification - h/w clears • • • • • • • • • • • •COP0 •COP0 • • • • • • • • • • • 6.00 March 31, 2014 • Removed Revision Date Description 366Vo For Programmers Architecture MIPS® Revision History

requirements for requirements for l page support. Addr and LLB fields are are LLB fields Addr and table describing the prioriti- the table describing . . ; added clarifications to ; added clarifications ng compatibility in MIPS64. compatibility ng MAAR behavior and new COP0 . . PWField dded optional smal dded optional UFE/FRE PTW to indicated both the LL ching capability. Description range cannot speculate. range LLB e-width e-width - both Dir and Leaf Table Config5 PWSize for Release 6 handling; added handling; 6 Release for to account for double-width reads double-width account for to MAAR tr, XNP capabilities (new) XNP capabilities tr, written as a single field Config5 quirements for 32-bit addressi with clarifications of legacy . XK/XS/XU all 0, then no tablewalk - fix typo KX/SX/UX for endian swit for register for R6 multi-threading R6 multi-threading register for support. and to eliminate 1 kB pages; a kB 1 eliminate to . to detect presence of L2 Config2 in to detect presence for R6 multi-threading for R6 multi-threading support. Status : in Release 6 with multi-threading, this is replaced by VPNum. by VPNum. is replaced this 6 with multi-threading, : in Release tionally required KX/SX/UX KX/SX/UX/PX DEC/CES VP L2c MAAR . bal Number PageMask PTEI Status CP0.MAAR description for MIPS64 for CP0.MAAR description Status Glo Config5 Config5 Config5 Default is not to speculate not to speculate is Default by be specified it must to speculate, If an address is Addresses outside of the me III: MIPS64® / microMIPS64™ Privileged6.03Resource / microMIPS64™ Architecture, Rev. III: MIPS64® me 367 32-bit addressing compatibility addressing in 32-bit MIPS64. EBaseCPUNum zation of mandatory for R6. for mandatory PWField • COP0 LLAddr Updated • Added • MIPS64 Updated •minor Made changes reset to state in allfieldsof • offsets and Leaf table Dir Adjust • for Adjust appropriately doubl DSize • R0 is is R0 is PWCtl.PWDirExt PWField.BDI • is R0 R0 is is PWSize.BDW PWCtl.PWDirExt • is or R0. R/W if PWSize.PTEW it is imp-dep then If PWSize.PS=1, changes: pseudo-code MIPS64 HTW • If PWSize=1 and PWCtl. • and descriptions MAAR formats 64-bit Added • Misc.clarifications see change - bars changes: COP0 MIPS64 HTW • may be R0 in PWCtl.PWDirExt R6 • PWCtl.XK/XS/XU to be are •added XNP. CES and - rm Config5 Updated • VH is only condi •(new) MT for VPControl CP0 Added •PerfC HWREna with Updated • support: Added Modeless Evil Twin • Made minor change to reset state of • Modified • • CP0 Updated • Updated • Added • new re - 4.11 Section Added • Added 6.01 17, 2014 October • Added 6.03 December 22, 2015 Changes to 6.022015 July 10, • (new) DebugContextID BEVVA, CP0 Added Revision Date MIPS® Architecture For Programmers Volu Programmers MIPS® Architecture For

ged Resource Architecture, Rev. 6.03 reserved. rights All Inc. Computing, www.wavecomp.ai Wave © lume III: MIPS64® / microMIPS64™ Privile / MIPS64® lume III: Copyright 368Vo For Programmers Architecture MIPS® Revision History