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MIPS® Architecture for Programmers Volume III: MIPS64® / Micromips64

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MIPS® Architecture for Programmers Volume III: MIPS64® / Micromips64 MIPS® Architecture For Programmers Volume III: MIPS64® / microMIPS64™ Privileged Resource Architecture Document Number: MD00091 Revision 6.03 December 22, 2015 Public. This publication contains proprietary information which is subject to change without notice and is supplied ‘as is’, without any warranty of any kind. MIPS® Architecture For Programmers Volume III: MIPS64® / microMIPS64™ Privileged Resource Architecture, Rev. 6.03 Table of Contents Chapter 1: About This Book ................................................................................................................ 15 1.1: Typographical Conventions ....................................................................................................................... 16 1.1.1: Italic Text.......................................................................................................................................... 16 1.1.2: Bold Text.......................................................................................................................................... 16 1.1.3: Courier Text ..................................................................................................................................... 16 1.2: UNPREDICTABLE and UNDEFINED ....................................................................................................... 16 1.2.1: UNPREDICTABLE........................................................................................................................... 16 1.2.2: UNDEFINED .................................................................................................................................... 17 1.2.3: UNSTABLE ...................................................................................................................................... 17 1.3: Special Symbols in Pseudocode Notation................................................................................................. 17 1.4: For More Information ................................................................................................................................. 20 Chapter 2: The MIPS64 and microMIPS64 Privileged Resource Architecture ................................ 21 2.1: Introduction................................................................................................................................................ 21 2.2: The MIPS Coprocessor Model .................................................................................................................. 21 2.2.1: CP0 - The System Coprocessor ...................................................................................................... 21 2.2.2: CP0 Registers.................................................................................................................................. 21 Chapter 3: MIPS64 and microMIPS64 Operating Modes................................................................... 23 3.1: Debug Mode ............................................................................................................................................. 23 3.2: Kernel Mode .............................................................................................................................................. 23 3.3: Supervisor Mode ....................................................................................................................................... 24 3.4: User Mode ................................................................................................................................................. 24 3.5: Other Modes.............................................................................................................................................. 24 3.5.1: 64-bit Address Enable...................................................................................................................... 24 3.5.2: 64-bit Operations Enable ................................................................................................................. 24 3.5.3: 64-bit Floating-Point Operations Enable .......................................................................................... 25 3.5.4: 64-bit FPR Enable............................................................................................................................ 25 3.5.5: Coprocessor 0 Enable...................................................................................................................... 25 3.5.6: ISA Mode ......................................................................................................................................... 26 Chapter 4: Virtual Memory ................................................................................................................... 27 4.1: Differences between Releases of the Architecture.................................................................................... 27 4.1.1: Virtual Memory................................................................................................................................. 27 4.1.2: Physical Memory.............................................................................................................................. 27 4.1.3: Protection of Virtual Memory Pages................................................................................................. 27 4.1.4: Context Register .............................................................................................................................. 28 4.1.5: Segmentation Control ...................................................................................................................... 28 4.1.6: Enhanced Virtual Addressing........................................................................................................... 28 4.2: Terminology............................................................................................................................................... 28 4.2.1: Address Space................................................................................................................................. 28 4.2.2: Segment and Segment Size (SEGBITS) ......................................................................................... 28 4.2.3: Physical Address Size (PABITS) ..................................................................................................... 29 4.3: Virtual Address Spaces ............................................................................................................................. 29 4.4: Compliance................................................................................................................................................ 32 4.5: Access Control as a Function of Address and Operating Mode................................................................ 32 MIPS® Architecture For Programmers Volume III: MIPS64® / microMIPS64™ Privileged Resource Architecture, Rev. 6.03 3 4.6: Address Translation and Cacheability and Coherency Attributes for the kseg0 and kseg1 Segments..... 34 4.7: Address Translation and Cacheability-and-Coherency Attributes for the xkphys Segment ...................... 35 4.8: Address Translation for the kuseg Segment when StatusERL = 1............................................................. 37 4.9: Special Behavior for the kseg3 Segment when DebugDM = 1................................................................... 38 4.10: Special Behavior for Data References in User Mode with StatusUX = 0 ................................................. 38 4.11: 32-bit Compatibility Addressing for Release 5 EVA, and Release 6 ....................................................... 39 4.11.1: Use Cases for Effective_Address Generation Function................................................................. 42 4.12: TLB-Based Virtual Address Translation .................................................................................................. 42 4.12.1: Address Space Identifiers (ASID) .................................................................................................. 42 4.12.2: TLB Organization ........................................................................................................................... 42 4.12.3: TLB Initialization............................................................................................................................. 43 4.12.4: Address Translation ....................................................................................................................... 46 4.13: Segmentation Control ............................................................................................................................. 52 4.13.1: Exception Behavior under Segmentation Control .......................................................................... 56 4.14: Enhanced Virtual Addressing .................................................................................................................. 61 4.14.1: EVA Segmentation Control Configuration...................................................................................... 61 4.14.2: Enhanced Virtual Address (EVA) Instructions................................................................................ 63 4.15: Hardware Page Table Walker ................................................................................................................. 65 4.15.1: Multi-Level Page Table support ....................................................................................................
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