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Intel® Quartus® Prime Pro Edition User Guide Debug Tools

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Intel® Quartus® Prime Pro Edition User Guide Debug Tools Intel® Quartus® Prime Pro Edition User Guide Debug Tools Updated for Intel® Quartus® Prime Design Suite: 18.0 Subscribe UG-20139 | 2018.07.03 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. System Debugging Tools Overview................................................................................. 7 1.1. System Debugging Tools Portfolio............................................................................ 7 1.1.1. System Debugging Tools Comparison........................................................... 7 1.1.2. Suggested Tools for Common Debugging Requirements.................................. 8 1.1.3. Debugging Ecosystem................................................................................ 9 1.2. Tools for Monitoring RTL Nodes.............................................................................. 10 1.2.1. Resource Usage....................................................................................... 10 1.2.2. Pin Usage............................................................................................... 12 1.2.3. Usability Enhancements............................................................................ 12 1.3. Stimulus-Capable Tools.........................................................................................13 1.3.1. In-System Sources and Probes.................................................................. 13 1.3.2. In-System Memory Content Editor..............................................................14 1.3.3. System Console.......................................................................................14 1.4. Virtual JTAG Interface Intel FPGA IP....................................................................... 15 1.5. System-Level Debug Fabric................................................................................... 15 1.6. Partial Reconfiguration Design Debugging................................................................16 1.6.1. Debug Fabric for Partial Reconfiguration Designs.......................................... 16 1.7. System Debugging Tools Overview Revision History.................................................. 20 2. Design Debugging with the Signal Tap Logic Analyzer.................................................. 22 2.1. The Signal Tap Logic Analyzer................................................................................22 2.1.1. Hardware and Software Requirements........................................................ 23 2.1.2. Signal Tap Logic Analyzer Features and Benefits .......................................... 23 2.1.3. Backward Compatibility with Previous Versions of Intel Quartus Prime Software.................................................................................................24 2.2. Signal Tap Logic Analyzer Task Flow Overview..........................................................24 2.2.1. Add the Signal Tap Logic Analyzer to Your Design......................................... 25 2.2.2. Configure the Signal Tap Logic Analyzer...................................................... 25 2.2.3. Define Trigger Conditions.......................................................................... 26 2.2.4. Compile the Design.................................................................................. 26 2.2.5. Program the Target Device or Devices.........................................................26 2.2.6. Run the Signal Tap Logic Analyzer.............................................................. 26 2.2.7. View, Analyze, and Use Captured Data........................................................27 2.3. Configuring the Signal Tap Logic Analyzer............................................................... 27 2.3.1. Assigning an Acquisition Clock................................................................... 27 2.3.2. Adding Signals to the Signal Tap File...........................................................28 2.3.3. Adding Signals with a Plug-In.................................................................... 31 2.3.4. Specifying Sample Depth.......................................................................... 31 2.3.5. Capture Data to a Specific RAM Type.......................................................... 32 2.3.6. Select the Buffer Acquisition Mode..............................................................32 2.3.7. Specifying Pipeline Settings.......................................................................34 2.3.8. Filtering Relevant Samples........................................................................ 35 2.3.9. Manage Multiple Signal Tap Files and Configurations..................................... 42 2.4. Defining Triggers................................................................................................. 44 2.4.1. Basic Trigger Conditions............................................................................44 2.4.2. Comparison Trigger Conditions...................................................................45 2.4.3. Advanced Trigger Conditions......................................................................47 Intel® Quartus® Prime Pro Edition User Guide Debug Tools 2 Contents 2.4.4. Custom Trigger HDL Object....................................................................... 50 2.4.5. Trigger Condition Flow Control................................................................... 53 2.4.6. Specify Trigger Position.............................................................................64 2.4.7. Power-Up Triggers....................................................................................65 2.4.8. External Triggers......................................................................................67 2.5. Compiling the Design........................................................................................... 67 2.5.1. Prevent Changes Requiring Recompilation................................................... 67 2.5.2. Verify Whether You Need to Recompile Your Project...................................... 68 2.5.3. Incremental Route with Rapid Recompile.....................................................68 2.5.4. Timing Preservation with the Signal Tap Logic Analyzer................................. 70 2.5.5. Performance and Resource Considerations...................................................70 2.6. Program the Target Device or Devices.....................................................................71 2.6.1. Ensure Setting Compatibility Between .stp and .sof Files............................... 72 2.7. Running the Signal Tap Logic Analyzer.................................................................... 72 2.7.1. Runtime Reconfigurable Options.................................................................73 2.7.2. Signal Tap Status Messages.......................................................................75 2.8. View, Analyze, and Use Captured Data....................................................................76 2.8.1. Capturing Data Using Segmented Buffers.................................................... 76 2.8.2. Differences in Pre-fill Write Behavior Between Different Acquisition Modes....... 78 2.8.3. Creating Mnemonics for Bit Patterns........................................................... 79 2.8.4. Automatic Mnemonics with a Plug-In.......................................................... 79 2.8.5. Locating a Node in the Design................................................................... 80 2.8.6. Saving Captured Data...............................................................................80 2.8.7. Exporting Captured Data to Other File Formats............................................ 81 2.8.8. Creating a Signal Tap List File.................................................................... 81 2.9. Debugging Partial Reconfiguration Designs Using Signal Tap Logic Analyzer................. 81 2.9.1. Recommendations when Debugging PR Designs........................................... 81 2.9.2. Setting Up a Partial Reconfiguration Design for Debug...................................82 2.9.3. Performing Data Acquisition in a PR design.................................................. 83 2.10. Other Features...................................................................................................84 2.10.1. Creating Signal Tap File from Design Instances...........................................84 2.10.2. Using the Signal Tap MATLAB MEX Function to Capture Data........................ 86 2.10.3. Using Signal Tap in a Lab Environment...................................................... 88 2.10.4. Remote Debugging Using the Signal Tap Logic Analyzer...............................88 2.10.5. Using the Signal Tap Logic Analyzer in Devices with Configuration Bitstream Security................................................................................... 89 2.10.6. Monitor FPGA Resources Used by the Signal Tap Logic Analyzer.................... 89 2.11. Design Example: Using Signal Tap Logic Analyzers..................................................89 2.12. Custom Triggering Flow Application Examples........................................................ 90 2.12.1. Design Example 1: Specifying a Custom Trigger Position..............................90 2.12.2. Design Example 2: Trigger When triggercond1 Occurs Ten Times between triggercond2 and triggercond3...................................................................91 2.13. Signal Tap Scripting Support................................................................................91
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